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1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
D42/D43 MLB_TOP_AVUS: CRB
LAST_MODIFICATION=Fri May 3 22:17:26 2019
PAGE CSA CONTENTS SYNC DATE PAGE CSA CONTENTS SYNC DATE
1 1 TABLE OF CONTENTS MLB_TOP 07/19/2018 41 73 B2B: Camera Tele [MT] mlb_top 10/02/2018
D 2 2 SYSTEM:BOM Tables MLB_TOP 07/19/2018 42 74 B2B: Camera SWide (MB) mlb_top 10/02/2018
D
3 3 SYSTEM: FF BOM Specific & Mechanical MLB_TOP 08/01/2018 43 76 B2B: Camera Fcam mlb_top 10/02/2018
4 5 SYSTEM: Constraints MLB_TOP 08/01/2018 44 77 B2B: Strobe + Side Button mlb_top 10/02/2018
5 6 SYSTEM: Probe Points (Top) mlb_top 09/05/2018 45 78 B2B: Pearl Romeo + Juliet mlb_top 10/02/2018
6 9 BOOTSTRAPPING MLB_TOP 08/01/2018 46 79 B2B: Pearl Rosaline + Sensor mlb_top 10/02/2018
7 10 SOC: NAND & USB & Misc MLB_TOP 07/19/2018 47 80 B2B: CG Display mlb_top 09/07/2018
8 11 SOC: PCIE MLB_TOP 08/06/2018 48 81 B2B: CG Touch mlb_top 10/02/2018
9 12 SOC: ISP mlb_top 10/02/2018 49 82 B2B: Dock mlb_top 10/02/2018
10 13 SOC: Display mlb_top 10/02/2018 50 100 ALIASES: Power (Top) MLB_TOP 08/02/2018
11 14 SOC: SERIAL mlb_top 10/02/2018 51 110 ALIASES: FF ISP mlb_top 10/02/2018
12 15 SOC: GPIO mlb_top 10/02/2018 52 111 ALIASES: FF GPIO MLB_TOP 08/02/2018
13 16 SOC: AOP & SMC & NUB MLB_TOP 07/19/2018 53 120 ALIASES: I2C - AP mlb_top 10/02/2018
14 17 SOC: POWER (CPU/GPU/SOC) MLB_TOP 07/19/2018 54 121 ALIASES: I2C - AOP/SMC MLB_TOP 08/06/2018
15 18 SOC: POWER (Fixed/1V2) MLB_TOP 07/19/2018 55 130 ALIASES: I2C - Camera mlb_top 10/02/2018
16 19 SOC: POWER (AOP/AVE/DISP/USB/DDR) MLB_TOP 07/19/2018 56 140 ALIASES: GPIO MLB_TOP 08/02/2018
17 20 SOC: POWER (GND) mlb_top 10/02/2018 57 150 ALIASES: Dev Platform MLB_TOP 08/02/2018
18 26 NAND mlb_top 10/02/2018 58 200 Radios MLB_TOP 07/19/2018
19 27 SYSTEM POWER: PMU Bucks (1/4) MLB_TOP 08/01/2018 59 1 SCH,RADIO_MLB_ICE_LOFT
C C
20 28 SYSTEM POWER: PMU Bucks (2/4) MLB_TOP 08/01/2018 60 2 HB SPAD 05/01/2018
21 29 SYSTEM POWER: PMU LDOS (3/4) MLB_TOP 07/19/2018 61 3 UHB MLB SPAD 05/01/2018
22 30 SYSTEM POWER: PMU (4/4) MLB_TOP 07/19/2018 62 4 LOWER COUPLER 05/01/2018
23 31 SYSTEM POWER: Boost mlb_top 10/02/2018 63 5 LOWER ANTENNA FEEDS 05/01/2018
24 37 CAMERA: PMU1 (1/2) mlb_top 10/02/2018 64 6 ANTENNA SYSTEM 05/01/2018
25 38 CAMERA: PMU1 (2/2) mlb_top 10/02/2018 65 1 FRONT PAGE
26 39 CAMERA: DISCRETE (DIGITAL) mlb_top 10/02/2018 66 2 MODULE
27 41 CAMERA: DISCRETE (ANALOG) mlb_top 10/02/2018 67 3 FILTERS MATCHING
28 44 PEARL: Power rigel 10/03/2018 68 1 FEM MODULES
29 45 SENSORS: Top mlb_top 10/02/2018 69 2 FEM MODULES 05/08/2018
30 47 AUDIO: CODEC (1/2) mlb_top 10/02/2018
31 48 AUDIO: CODEC (2/2) mlb_top 10/02/2018
32 55 CG POWER: Touch mlb_top 10/02/2018
33 59 I/O: VDDM Comparators mlb_top 10/02/2018
34 61 I/O: Gecko mlb_top 10/02/2018
35 62 I/O: USB PD mlb_top 10/02/2018
36 63 I/O: Hydra mlb_top 10/02/2018
B 37 65 Interposer: Top mlb_top 10/02/2018 B
38 66 Interposer: Aliases mlb_top 09/05/2018
39 69 B2B: Battery (North) mlb_top 10/02/2018
40 72 B2B: Camera Wide (ON) mlb_top 10/02/2018
MCO: 056-08495 EEEE Codes Sub Designs TABLE_HIERARCHY_CONFIG_HEAD
BOM: 639-07383 (ULTIMATE,ROW,D42)

TABLE_5_HEAD
HARD/
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION SOURCE PROJECT SUB-DESIGN NAME VERSION SOFT
SYNC_DATE/TIME
TABLE_HIERARCHY_CONFIG_ITEM
TABLE_5_ITEM
825-7691 1 LNCH CRITICAL ULTIMATE_ROW_D42 D43 RADIO_MLB_ICE_LOFT 0.83.0 S 2019_04_30_16:40:16

BOM: 639-07386 (ULTIMATE,NA+CH,D42) 825-7691 1
EEEE FOR (MLB_TOP,639-06878,ULTIMATE,ROW,D42)
EEEE FOR (MLB_TOP,639-06907,ULTIMATE,US+CH,D42) LNDJ CRITICAL ULTIMATE_USCH_D42

TABLE_5_ITEM
D42 ROSE_MLB 0.56.0 S 2019_05_02_11:27:27

BOM: 639-07384 (EXTREME,ROW,D42) 825-7691 1 EEEE FOR (MLB_TOP,639-06879,EXTREME,ROW,D42) LNCR CRITICAL EXTREME_ROW_D42
TABLE_5_ITEM
D42 LAA_MLB 0.28.0 S 2019_04_26_11:43:12

BOM: 639-07387 (EXTREME.NA+CH,D42)

TABLE_5_ITEM
825-7691 1 EEEE FOR (MLB_TOP,639-06908,EXTREME,US+CH,D42) LNDX CRITICAL EXTREME_USCH_D42

TABLE_5_ITEM
825-7691 1 LND4 CRITICAL MAX_ROW_D42

BOM: 639-07385 (MAX,ROW,D42) 825-7691 1
EEEE FOR (MLB_TOP,639-06880,MAX,ROW,D42)
EEEE FOR (MLB_TOP,639-06909,MAX,US+CH,D42) LNF8 CRITICAL MAX_USCH_D42

TABLE_5_ITEM
BOM: 639-07388 (MAX,NA+CH,D42) 825-7691 1 EEEE FOR (MLB_TOP,639-06878,ULTIMATE,ROW,D43) L1W2 CRITICAL ULTIMATE_ROW_D43
TABLE_5_ITEM
TABLE_5_ITEM
825-7691 1 EEEE FOR (MLB_TOP,639-06907,ULTIMATE,US+CH,D43) L38J CRITICAL ULTIMATE_USCH_D43
A BOM: 639-06878 (ULTIMATE,ROW,D43)

TABLE_5_ITEM
825-7691 1 EEEE FOR (MLB_TOP,639-06879,EXTREME,ROW,D43) L1WF CRITICAL EXTREME_ROW_D43

TABLE_5_ITEM
A
825-7691 1 L38W CRITICAL EXTREME_USCH_D43
BOM: 639-06907 (ULTIMATE,NA+CH,D43) 825-7691 1
EEEE FOR (MLB_TOP,639-06908,EXTREME,US+CH,D43)
EEEE FOR (MLB_TOP,639-06880,MAX,ROW,D43) L1WR CRITICAL MAX_ROW_D43

TABLE_5_ITEM
BOM: 639-06879 (EXTREME,ROW,D43) 825-7691 1 EEEE FOR (MLB_TOP,639-06909,MAX,US+CH,D43) L397 CRITICAL MAX_USCH_D43
TABLE_5_ITEM
BOM: 639-06908 (EXTREME.NA+CH,D43) PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD
BOM: 639-06880 (MAX,ROW,D43) 051-04448 1 SCH,MLB_TOP,D43 SCH CRITICAL ?

TABLE_5_ITEM
BOM: 639-06909 (MAX,NA+CH,D43)

TABLE_5_ITEM
820-01682 1 PCB,MLB_TOP,D43 PCB CRITICAL ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NAND Global Alternates TABLE_CRITICAL_HEAD
TABLE_ALT_HEAD TABLE_ALT_HEAD
CRITICAL PART# COMMENT

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
Ultimate 377S00070
PART NUMBER
377S00001 ALT_PARTS ALL TVS,BIDIR,5.8V,6PF,01005

TABLE_ALT_ITEM
138S00284
PART NUMBER
138S00136 ALT_PARTS ALL CAP,X5R,2.2UF,20%,10V.KYO,0201

TABLE_ALT_ITEM 377S00001 TVS,BIDIR,5.8V,6PF,01005
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_5_HEAD
TABLE_ALT_ITEM TABLE_ALT_ITEM 377S0183 TVS,BIDIR,5.8V,0201

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
377S00140 377S00001 ALT_PARTS ALL TVS,BIDIR,5V,6PF,01005,SEMTECH 138S00049 138S0831 ALT_PARTS ALL CAP,CER,X5R,2.2UF,20%,6.3V,0201 TABLE_CRITICAL_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM TABLE_ALT_ITEM 377S00129 SUPRESS,TRANS,6.8V,100PF,01005

335S00360 1 TOSHIBA, 3Dv4,256Gb, Ultimate U2600 CRITICAL ULTIMATE 377S00061 377S0183 ALT_PARTS ALL TVS,BIDIR,5.8V,0201 138S00138 138S00164 ALT_PARTS ALL CAP,X5R,4UF,20%,4V.KYO,0201 TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM TABLE_ALT_ITEM 155S00200 FERR BD,150OHM,25%,200MA,0.7OHM DCR,01005

377S00080 377S0183 ALT_PARTS ALL TVS,BIDIR,5V,5PF,0201,SEMTECH 138S00139 138S00164 ALT_PARTS ALL CAP,X5R,4UF,20%,4V.MURATA,0201 TABLE_CRITICAL_ITEM
D Extreme 377S00173 377S0183 ALT_PARTS ALL TVS,BIDIR,5V,6.5PF,0201,SEMTECH

TABLE_ALT_ITEM 155S00402 FERR BD,33OHM,25%,1.5A,55MOHM DCR,0201
TABLE_CRITICAL_ITEM
D
TABLE_ALT_ITEM 152S00402 IND,PWR,1.0UH,20%,1.8A,160MOHM,1608
TABLE_5_HEAD 377S0168 377S00129 ALT_PARTS ALL SUPPRESS,TRANS,6.8V,100PF,AMOTECH,01005 TABLE_CRITICAL_ITEM
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_ITEM 118S00144 RES,MF,24KOHM,1%,200PPM,1/32W,01005
TABLE_5_ITEM 155S00400 155S00200 ALT_PARTS ALL FERR BD,150OHM,25%,200MA,0.7OHM DCR,01005 TABLE_CRITICAL_ITEM
335S00342 1 HYNIX, 3Dv4,512Gb, Extreme U2600 CRITICAL EXTREME TABLE_ALT_ITEM 131S00025 CAP,C0G,1000PF,2%,25V,0201
155S00194 155S00200 ALT_PARTS ALL FERR BD,150OHM,25%,280MA,0.69OHM DCR,01005 TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM 132S0316 CAP,X5R,0.1UF,20%,6.3V,01005

155S0755 155S00341 ALT_PARTS ALL
Max 155S00437 155S00402 ALT_PARTS ALL
FERR BD,240OHM,25%,200MA,1ohm DCR,01005
FERR BD,33OHM,25%,1.5A,55MOHM DCR,0201

TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_5_HEAD TABLE_ALT_ITEM 132S0639 CAP,CER,X5R,0.47UF,20%,25V,0201

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 152S00366 152S00402 ALT_PARTS ALL IND,PWR,1.0UH,20%,1.8A,160MOHM,TAIYO.1608 TABLE_CRITICAL_ITEM
TABLE_5_ITEM TABLE_ALT_ITEM 138S0706 CAP,X5R,1UF,20%,10V,0201

335S00343 1 HYNIX, 3Dv4, 512Gb, Max U2600 CRITICAL MAX 131S00329 131S00025 ALT_PARTS ALL CAP,C0G,1000PF,2%,25V,TAIYO,0201 TABLE_CRITICAL_ITEM

132S00185 132S0316 ALT_PARTS ALL CAP,CER,X5R,0.1UF,20%,6.3V,01005 TABLE_CRITICAL_ITEM

132S00232 132S00014 ALT_PARTS ALL CAP,X5R,0.22UF,10%,6.3V,TAIYO,01005 TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM 138S0831 CAP,CER,X5R,2.2UF,20%,6.3V,0201
Global Capacitors
132S00233 132S00014 ALT_PARTS ALL CAP,X5R,0.22UF,10%,6.3V,TAIYO,01005 TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM 138S00284 CAP,CER,X5R,2.2UF,20%,10V,0201

132S00088 132S0639 ALT_PARTS ALL CAP,X5R,0.47uF,20%,25V,0201,TAIYO TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM 138S00164 CAP,X5R,4UF,20%,4V,0201
TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
138S0739 138S0706 ALT_PARTS ALL CAP,CER,X5R,1UF,20%,10V,0201,SAMSUNG
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
TABLE_ALT_ITEM
PART NUMBER
TABLE_CRITICAL_ITEM
138S0945 138S0706 ALT_PARTS ALL CAP,CER,X5R,1UF,20%,10V,0201,KYOCERA
TABLE_ALT_ITEM
138S00149 0402-3T,10.5uF@1V TABLE_ALT_ITEM
138S00148 138S00149 ALT_PARTS ALL 0402-3T,10.5uF@1V, Kyocera 138S00264 138S00008 ALT_PARTS ALL CAP,X5R,1.5UF,20%,6.3V.TAIYO,0201
TABLE_ALT_ITEM
138S00150 138S00149 ALT_PARTS ALL 0402-3T,10.5uF@1V, SEMCO

TABLE_ALT_ITEM
138S00151 138S00149 ALT_PARTS ALL 0402-3T,10.5uF@1V, TY
C PART NUMBER ALTERNATE FOR

PART NUMBER
BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
CRITICAL PART#
138S00139
COMMENT
0201,3uF@1V
TABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
AVUS INDUCTORS TABLE_ALT_HEAD
Display CMC's C
138S00138 138S00139 ALT_PARTS ALL 0201,3uF@1V, Kyocera PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_CRITICAL_HEAD TABLE_ALT_HEAD
PART NUMBER CRITICAL PART# COMMENT PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
TABLE_ALT_ITEM
138S00164 138S00139 ALT_PARTS ALL 0201,3uF@1V, TY

TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
152S00721 152S00876 ALT_PARTS ALL Taiyo,IND,MLD,1UH,3.6A,60MO,2016 152S00876 Cyntec,IND TABLE_ALT_ITEM
TABLE_ALT_ITEM
155S00415 155S00524 ALT_PARTS ALL CMC,35O_OHM,7GHZ,TDK

138S00280 138S00139 ALT_PARTS ALL 0201,3uF@1V,SAM
152S00930 152S00897 ALT_PARTS ALL Cyntec,IND,CPLD,0.1UH,6.1A,27MO,2016 152S00897 Taiyo,IND

TABLE_CRITICAL_HEAD
TABLE_ALT_HEAD
TABLE_CRITICAL_HEAD
152S00826 152S00821 ALT_PARTS ALL Taiyo,IND,MLD,1UH,2.2A,60MO,2012 152S00821 Cyntec,IND CRITICAL PART# COMMENT
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
152S00831 152S00818 ALT_PARTS ALL Taiyo,IND,MLD,0.22UH,5.3A,40MO,1608 152S00818 Cyntec,IND 155S00524 FLT,NOISE,350_OHM,7GHZ,50MA,0403,MURATA
TABLE_ALT_ITEM
138S00221 138S00146 ALT_PARTS ALL 0402,5.1uF@3V, Kyocera

138S00146 0402,5.1uF@3V TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
152S00994 152S00987 ALT_PARTS ALL Taiyo,IND,MLD,1UH,1.5A,67MO,2012 152S00987 Cyntec,IND

TABLE_ALT_HEAD
152S00991 152S00984 ALT_PARTS ALL Taiyo,IND,MLD,0.47UH,3.5A,34MO,1614 152S00984 Cyntec.IND
TABLE_CRITICAL_HEAD


PART NUMBER 152S00992 152S00985 ALT_PARTS ALL Taiyo,IND,MLD,0.47UH,4.0A,45MO,2012 152S00985 Cyntec,IND
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
138S00003 138S00048 ALT_PARTS ALL 0402,15uF,6.3V, MURATA

138S00048 0402,15uF,6.3 152S00989 152S00982 ALT_PARTS ALL Taiyo,IND,MULT,0.47UH,2.8A,70MO,1608 152S00982 Cyntec,IND
TABLE_ALT_HEAD
TABLE_CRITICAL_HEAD

PART NUMBER
Multi-Vendor Criticals XTAL Alternate

TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
138S00140 138S00141 ALT_PARTS ALL 0201,1.1uF@3V, Kyocera

138S00141 0201,1.1uF@3V
TABLE_ALT_ITEM
138S00268 138S00141 ALT_PARTS ALL 0201,1.1uF@3V, SEMCO

TABLE_CRITICAL_HEAD TABLE_CRITICAL_HEAD TABLE_CRITICAL_HEAD TABLE_ALT_HEAD
CRITICAL PART# COMMENT CRITICAL PART# COMMENT CRITICAL PART# COMMENT PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
TABLE_ALT_HEAD

TABLE_CRITICAL_HEAD TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
PART NUMBER CRITICAL PART# COMMENT 197S0446 XTAL,24MHZ,30PPM,9.5PF,60 OHM MAX,1612 131S00353 CAP,CER,NPO/COG,10PF,5%,16V,01005 132S0245 CAP,CER,X5R,0.01UF,10%,6.3V,01005 TABLE_ALT_ITEM
TABLE_ALT_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

197S0612 197S00118 ALT_PARTS Y1000 XTAL, 24M, 1612
138S00116 138S00071 ALT_PARTS ALL CAP,CER,X5R,4UF,20%,6.3V,0201,H=0.55,TY 138S00071 CAP,CER,X5R,4UF,20%,6.3V,0201,H=0.55 155S00168 FLTR,NOISE,65 OHMZ,3.4OHM,0.7-2GHZ,0605 131S0220 CAP,CER,NP0/C0G,12PF,5%,16V,01005 132S00093 CAP,CER,X5R,0.022UF,20%,6.3V,01005 TABLE_ALT_ITEM
197S00120 197S00118 ALT_PARTS Y1000 XTAL, 24M, 1612
B 138S00117 138S00071 ALT_PARTS ALL CAP,CER,X5R,4UF,20%,6.3V,0201,H=0.55,KYO

TABLE_ALT_ITEM
377S0106 SUPPR,TRANS,VARISTOR,12V,33PF,01005
TABLE_CRITICAL_ITEM
131S00293 CAP,CER,NPO/COG,12PF,5%,16V,01005
TABLE_CRITICAL_ITEM
132S00025 CAP,CER,X5R,0.047UF,20%,6.3V,01005
TABLE_CRITICAL_ITEM
B
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
155S0576 FERR BD,10 OHM,50%,750MA,0.07 DCR,01005 131S0225 CAP,CER,NP0/C0G,15PF,5%,16V,01005 132S0664 CAP,CER,0.047UF,10%,25V,X5R,0201

TABLE_ALT_HEAD TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEAD
155S00341 FERR BD,240 OHM,25%,200MA,0.9 DCR,01005 131S00290 CAP,CER,NPO/COG,15PF,5%,16V,01005 132S0316 CAP,CER,X5R,0.1UF,20%,6.3V,01005

PART NUMBER CRITICAL PART# COMMENT
107S0257 THERMISTOR,NTC,10K OHM,1%,B=3435,01005 131S00378 CAP,CER,NP0/C0G,22PF,5%,16V,01005 132S00185 CAP,CER,X5R,0.1UF,20%,6.3V,01005

138S00128 138S00133 ALT_PARTS ALL 01005,0.47uF,6.3V,Murata 138S00133 01005,0.47uF, 6.3V TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
118S0608 RES,MF,1KOHM,1/32W,1%,01005 131S0223 CAP,CER,NP0/C0G,27PF,5%,16V,01005 132S0288 CAP,CER,X5R,0.1UF,10%,16V,0201

138S00269 138S00133 ALT_PARTS ALL 01005,0.47uF,6.3V,Taiyo
118S00064 RES,MF,11KOHM,1/32W,1%,01005 131S0804 CAP,CER,NP0/C0G.27PF,5%,25V,0201 132S0534 CAP,CER,X5R,0.1UF,10%,25V,0201

118S00022 RES,MF,41.2KOHM,1%,1/32W,01005 131S00291 CAP,CER,NP0/C0G,27PF,5%,16V,01005 132S00008 CAP,CER,X7R,0.1UF,10%,50V,0402

118S0637 RES,MF,82OHM,1%,1/32W,01005 131S00023 CAP,CER,NP0/C0G,39PF,5%,25V,01005 132S0304 CAP,CER,X5R,0.22UF,20%,6.3V,0201
20uF/26uF Dual Source 118S00068 RES,MF,1.3 MOHM,1%,200PPM,1/20W,0201

TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
131S0216 CAP,CER,NP0/C0G,47PF,5%,16V,01005
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
138S00014 CAP,CER,1UF,20%,16V,X5R,0201,H=0.39MM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_5_HEAD
117S0055 RES,MF,2MOHM,1/20W,5%,0201,SMD 131S00323 CAP,CER,NPO/COG,56PF,5%,25V,01005 138S0692 CAP,CER,X5R,1UF,20%,6.3V,0201

TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
TABLE_5_ITEM
131S0643 CAP,CER,NP0/C0G,56PF,5%,25V,01005 138S0683 CAP,CER,X5R,1UF,10%,25V,0402

138S00279 7 CAP,20UF,4V,0402,SEMCO C1708,C1709,C1733,C1736,C1970,C2711,C2712 CRITICAL CAP_20UF_SAMCO_ALT TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
TABLE_5_ITEM
131S0635 CAP,CER,NP0/C0G,68PF,5%,16V,01005 138S00070 CAP,X5R,4.7UF,20%,25V,0402

138S00279 7 CAP,20UF,4V,0402,SEMCO C2721,C2722,C2751,C2752,C3700,C3701,C3925 CRITICAL CAP_20UF_SAMCO_ALT TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
131S00303 CAP,CER,NPO/COG,100PF,5%,16V,01005 138S0652 CAP,CER,X5R,4.7UF,20%,6.3V,H=0.65MM,0402

TABLE_ALT_HEAD TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 131S0307 CAP,CER,NP0/C0G,100PF,5%,16V,01005 138S0979 CAP,CER,X5R,10UF,20%,10V,0402,H=0.65MM
PART NUMBER
TABLE_CRITICAL_ITEM
0402,20uF,4V,SEMCO
TABLE_ALT_ITEM
131S00053 CAP,CER,NP0/C0G,220PF,5%,10V,01005
138S00144 138S00279 CAP_20UF_SAMCO_ALT
C1708,C1709,C1733,C1736,C1970,C2711,C2712 TABLE_CRITICAL_ITEM
0402,20uF,4V,SEMCO
TABLE_ALT_ITEM
132S0249 CAP,CER,X7R,220PF,10%,10V,01005
138S00144 138S00279 CAP_20UF_SAMCO_ALT
C2721,C2722,C2751,C2752,C3700,C3701,C3925 TABLE_CRITICAL_ITEM
131S00170 CAP,CER,NP0/C0G,220PF,5%,25V,01005
A
TABLE_CRITICAL_ITEM
131S0883 CAP,CER,NP0/C0G,220PF,2%,50V,0201
TABLE_CRITICAL_ITEM
A
132S00258
15uF Single Source 132S0275
CAP,CER,X7R,330PF,10%,16V,01005
CAP,CER,X5R,470PF,10%,10V,01005
TABLE_CRITICAL_ITEM
TABLE_5_HEAD TABLE_CRITICAL_ITEM
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 132S0318 CAP,CER,X5R,820PF,10%,10V,01005
TABLE_5_ITEM TABLE_CRITICAL_ITEM
138S00003 9 CAP,15UF,6.3V,0402,MURATA C1734,C1735,C2723,C2734,C2753,C2801,C2811,C2813,C2731 CRITICAL CAP_15UF_SINGLE_SOURCE 132S0296 CAP,CER,X5R,1000PF,10%,6.3V,01005

TABLE_CRITICAL_ITEM
138S00003 8 CAP,15UF,6.3V,0402,MURATA C1762,C1763,C1764,C1925,C1926,C1927,C1927,C2823 CRITICAL CAP_15UF_SINGLE_SOURCE 132S0396 CAP,CER,X5R,1000PF,10%,10V,01005
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Cebu FIDUCIALS
TABLE_ALT_HEAD
PART NUMBER
TABLE_ALT_ITEM
339S00592 339S00591 ALT_PARTS U1000 CEBU,4GB,16NM,M
TABLE_ALT_ITEM
339S00593 339S00591 ALT_PARTS U1000 CEBU,4GB,18NM,H
TABLE_ALT_ITEM CRITICAL FD0402
339S00594 339S00591 ALT_PARTS U1000 CEBU,4GB,16NM,S
FID
1 0P5SQ-CROSS-NSP
1 D
SH0302 ROOM=ASSEMBLY
o
D SM
806-21704 FD0404
FID
SHLD-MLB-TOP-ADAMS-D4X 0P5SQ-CROSS-NSP
1
Crosses ROOM=ASSEMBLY
FD0407
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY
FD0413
FID
SB0303 0P5SQ-CROSS-NSP
1
2.9OD-0.92H-SM
o o o
ROOM=ASSEMBLY
1
O
FD0414
FID
0P5SQ-CROSS-NSP
1
Q
ROOM=ASSEMBLY
AC Return Steering - 50x FD0415
FID
0P5SQ-CROSS-NSP
SB0302 1
ROOM=ASSEMBLY
9
38 33 21 20 3
PP_VDD_MAIN 2.9OD-0.92H-SM
50 39
1
1 C03A3 CRITICAL
0.47UF
20% 1
6.3V
2 X5R
C 01005-1
SH0300 FD0403 C
SM
FID
806-17540 0P5SQ-SMP3SQ-NSP
1
SHLD-TTS-MLB-D4X ROOM=ASSEMBLY
O
FD0406
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY
Q
SB0304 FD0405
2.9OD-0.92H-SM Squares FID
1 0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY
o.
Q
FD0408
FID
39 38 33 21 20 3 PP_VDD_MAIN 0P5SQ-SMP3SQ-NSP
50 1
ROOM=ASSEMBLY
P
1 C03D4 1 C03D5
220PF 220PF
5% 5%
25V
2 COG 25V
2 COG FD0410
01005 01005 FID
——
0P5SQ-SMP3SQ-NSP
II I"
1
ROOM=ASSEMBLY
p
39 38 33 21 20 3
50
PP_VDD_MAIN
1 1
FD0412
C03E3 C03E5 FID
220PF 220PF 0P5SQ-SMP3SQ-NSP
5% 5% 1
25V 25V ROOM=ASSEMBLY
p
2 COG 2 COG
01005 01005
B 50 39 38 33 21 20 3 PP_VDD_MAIN B
39 38 33 21 20 3
PP_VDD_MAIN 1 C03L2 1 C03L3 1 C03L4
50
220PF 220PF 220PF CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED
1 C03F1 1 C03F2 1 C03F3 1 C03F5 5% 5% 5%
25V
2 COG 2 25V 25V
220PF 220PF 220PF 220PF COG 2 COG R0300 R0301 R0302 R0303 R0304 R0305
5% 5% 5% 5% 01005 01005 01005 0.00 0.00 0.00 0.00 0.00 0.00
25V
2 COG 25V
2 COG 25V
2 COG 2 25V 1 2 1 2 1 2 1 2 1 2 1 2
COG
01005 01005 01005 01005 0% 0% 0% 0% 0% 0%
1/32W 1/32W 1/32W 1/32W 1/32W 1/32W
—IH" HH"
50 39 38 33 21 20 3 PP_VDD_MAIN
|i >
MF MF MF MF MF MF
|l'
ll '
ll'
ii'
I 1'
ll‘
01005 01005 01005 01005 01005 01005
1 C03M1 1 C03M2 1 C03M3 1 C03M4
39 38 33 21 20 3
50
PP_VDD_MAIN
220PF 220PF 220PF 220PF
1 C03G1 1 C03G2 1 C03G4 1 C03G5 5% 5% 5% 5%
2 25V 25V 25V 25V
220PF 220PF 220PF 220PF COG 2 COG 2 COG 2 COG CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED
5% 5% 5% 5% 01005 01005 01005 01005
25V
2 COG 25V
2 COG 25V
2 COG 25V
2 COG R0306 R0307 R0308
01005 01005 01005 01005 0.00 0.00 0.00
1 2 1 2 1 2
50 39 38 33 21 20 3 PP_VDD_MAIN
0% 0% 0%
1 1 1 1/32W 1/32W 1/32W
39 38 33 21 20 3 PP_VDD_MAIN C03N1 C03N3 C03N4 MF MF MF
I1'
50 220PF 220PF 220PF 01005 01005 01005
1 C03H1 1 C03H2 1 C03H3 1 C03H4 1 C03H5 5% 5% 5%
2 25V 25V 2 25V
220PF 220PF 220PF 220PF 220PF COG 2 COG COG
5% 5% 5% 5% 5% 01005 01005 01005 CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED CKPLUS_WAIVE=TERMSHORTED
25V
2 COG 25V
2 COG 2 25V 2 25V 25V
COG COG 2 COG
SB0305 R0310 R0311 R0320 R0321 R0322
01005 01005 01005 01005 01005
2.9OD-0.92H-SM 1
0 2 1
0 2 1
0.00 2 1
0.00 2 1
0.00 2
Hi’
Hi'
1 5% 5% 0% 0% 0%
o
PP_VDD_MAIN 1/20W 1/20W 1/32W 1/32W 1/32W
39 38 33 21 20 3
li >
11
50 MF MF MF MF MF
0201 0201 01005 01005 01005
1 C03J2 1 C03J3 1 C03J4 1 C03J5
—
220PF 220PF 220PF 220PF SB0301
5% 5% 5% 5%
25V
2 COG 25V
2 COG 25V
2 COG 25V
2 COG 2.9OD-0.92H-SM
01005 01005 01005 01005
—
A 1
I
A
11 I"
—1|— "
p
ll '
39 38 33 21 20 3
50
PP_VDD_MAIN
1 C03K1 1 C03K2 1 C03K5
220PF 220PF 220PF TABLE_5_HEAD
5% 5% 5%
2 25V 25V 25V PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
COG 2 COG 2 COG
TABLE_5_ITEM
01005 01005 01005
870-03604 25 SPACER,INTERPOSER,SMALL,X891 MP0400-MP0424 CRITICAL COMMON
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RADIOS
DIELECTRIC BASED SPACING RULES HYBRID IMPEDANCE RULE
RULE DEFINITION LIST OF VALUES TRACE REFERENCE REQUIRED TRACE WIDTH

EXAMPLE: 1,3-5,7L,8L-10L
LAYER LAYER(s) IMPEDANCE (OPTIONAL)
A_DIELECTRIC_(N)X
Calculates dielectric distance from stackup, 1.5,2,3
shortest distance is used unless 'L'is defined
EXAMPLE: 2,1DL,3D-5D,7V,8VL-10VL
RULE NAME= 50_THIN ZONE NAME= PRIMARY
A_DIELECTRIC_(N)XD XV,XVL,X
Calculates dielectric distance from Hybrid Table and
stackup, shortest distance is used unless 'L' defined
2,2D,4D,4V TOP ISL2 50 0.062
EXAMPLE: 2_4,3L_5L
A_DIELECTRIC_(N)XIN_(N)XOUT
Calculates dielectric distance from stackup,
shortest distance is used unless 'L' is defined
? ISL6 ISL5,ISL7 50 0.038
D ISL8 ISL7,ISL9 50 0.029 D

CLEAR
BOTTOM ISL9 50 0.062
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* OVERRIDE CLEAR
DOMAIN CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* OVERRIDE
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N DOMAIN
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
90_OHM P A_90_OHM_DIFF DP:DP_*90* ?
DEFAULT_THICK P DEFAULT_THICK *MIC*BIAS* ?
GENERIC_DP P GENERIC_DP DP:DP_MIC*,DP_PENROSE*,DP_NTC_*,DP_MTR_RREF* ? HYBRID IMPEDANCE RULE
GENERIC_DP P GENERIC_DP DP:DP_ANALOG*SENSE* ? SYSTEM WIDE
NC_GENERIC_DP P GENERIC_DP DP:DP_NC* ? CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR TRACE REFERENCE REQUIRED TRACE WIDTH
OVERRIDE
DOMAIN LAYER LAYER(s) IMPEDANCE (OPTIONAL)
PWR_DP P PWR_DP DP:DP_CODEC_AOUT* ? CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
PWR_DEFAULT P PWR_DEFAULT PP_CPU_PCORE_LVCC,PP_GPU_LVCC ? RULE NAME= 50_WIDE ZONE NAME= PRIMARY

PWR_80UM P PWR_80UM PP1V8_ALWAYS,PP3V3_USB_DEBUG*,PP3V3_USB ? TOP ISL3 50 0.174
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR PWR_100UM P PWR_100UM PP1V2_S2 ?
OVERRIDE ISL3 TOP,ISL5 50 0.091
CLASS NAME
DOMAIN
E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
PWR_200UM P PWR_200UM PP1V8_S2,PP3V0_S2,PP1V8_IO ?
GND S MSAP_YIELD GND ? PWR_300UM P PWR_300UM PP1V8_NFC_S2 ? ISL5 ISL3,ISL7 50 0.104
LPDP_WIDE S A_DIELECTRIC_3X DP:DP_*90_LPDP*_WIDE* ? PWR_SHAPE P PWR_SHAPE LX*_BUCK* ?
ISL7 ISL5,ISL9 50 0.098
LPDP_SWIDE S A_DIELECTRIC_3X DP:DP_*90_LPDP*_SWIDE* ? PWR_SHAPE P PWR_SHAPE PP_VDD_MAIN,PP_VDD_BOOST ?
LPDP_TELE S A_DIELECTRIC_3X DP:DP_*90_LPDP*_TELE* ? PWR_SHAPE P PWR_SHAPE PP1V1_S2 ? ISL8 ISL7,ISL9 50 0.029
LPDP_FCAM S A_DIELECTRIC_3X DP:DP_*90_LPDP*_FCAM* ? PWR_SHAPE P PWR_SHAPE PP1V2_S4 ?
BOTTOM ISL8 50 0.174
MIPI_DISPLAY S A_DIELECTRIC_3X DP:DP_*90_MIPI*DISPLAY* ? S_PWR_100UM S 100UM-249UM_SPACING PP1V2_S2 ?
MIPI_IRCAM S A_DIELECTRIC_3X DP:DP_*90_MIPI*_IRCAM* ? S_PWR_200UM S 100UM-249UM_SPACING PP1V8_S2,PP3V0_S2,PP1V8_IO ?
PCIE_NAND S A_DIELECTRIC_3X DP:DP_*90_PCIE*_NAND* ? S_PWR_300UM S 250UM+_SPACING PP1V8_NFC_S2 ?
PCIE_WLAN S A_DIELECTRIC_3X DP:DP_*90_PCIE*_WLAN* ? S_PWR_SHAPE S 250UM+_SPACING PP_VDD_MAIN,PP_VDD_BOOST ?
HYBRID IMPEDANCE RULE
PCIE_BB S A_DIELECTRIC_3X DP:DP_*90_PCIE*_BB* ? S_PWR_SHAPE S 250UM+_SPACING PP1V1_S2 ?
HYDRA_DP S A_DIELECTRIC_3X DP:DP_*90_*HYDRA* ? S_PWR_SHAPE S 250UM+_SPACING PP1V2_S4 ? TRACE REFERENCE REQUIRED TRACE WIDTH
LAYER LAYER(s) IMPEDANCE (OPTIONAL)
MIKEYBUS_DP S A_DIELECTRIC_3X DP:DP_*90_*MIKEYBUS* ? SOC
USB_DP S A_DIELECTRIC_3X DP:DP_*90_*USB* ? CLEAR
RULE NAME= 50_WIDE_L1_THIN ZONE NAME= PRIMARY
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR*
C CLK
CLK_PMU_XTAL
S
S
A_DIELECTRIC_1.5X
A_DIELECTRIC_1.5X
CLK_AP*,CLK_BBPMU*,CLK_CAM*,CLK_GPIO*,CLK_ISP*,CLK_PMU_TO*
CLK_PMU_XTAL*
?
?
CLASS NAME
DOMAIN
E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:)
OVERRIDE
Y/N
TOP ISL2 50 0.062 C
PWR_80UM P PWR_80UM PP0V8_SOC_FIXED_PCIE_REFBUF,PP0V8_USB_DEBUG,PP_VDD_LOW_USB_DEBUG ? ISL5 ISL3,ISL7 50 0.104
CLK_SPMI S A_DIELECTRIC_1.5X SPMI*CLK* ?
PWR_80UM P PWR_80UM PP1V2_SOC_PCIE_REFBUF,PP1V8_XTAL ?
ANALOG_FB S A_DIELECTRIC_1.5X ANALOG_FB* ? ISL6 ISL5,ISL7 50 0.038
PWR_100UM P PWR_100UM PP_VDDIO12_GRP5 ?
SWITCHING S A_DIELECTRIC_1.5X LX*_BUCK* ?
PWR_200UM P PWR_200UM PP1V2_SOC,PP0V6_VDDQL_S1,PP1V8_FMON_R,PP1V8_ULPPLL_R ? ISL7 ISL5,ISL9 50 0.098
MIC1_DP S A_DIELECTRIC_1.5X DP:DP_*MIC1* ?
PWR_SHAPE P PWR_SHAPE PP_CPU_ECORE,PP_CPU_PCORE,PP_DCS_S1 ?
MIC2_DP S A_DIELECTRIC_1.5X DP:DP_*MIC2* ? ISL8 ISL7,ISL9 50 0.029
PWR_SHAPE P PWR_SHAPE PP_GPU,PP_SOC_S1,PP0V8_SOC_FIXED_S1 ?
PWR_SHAPE P PWR_SHAPE PP0V7_VDD_LOW_FLPPLL_R,PP0V7_VDD_LOW_S2 ? BOTTOM ISL9 50 0.062
PWR_SHAPE P PWR_SHAPE PP0V7_VDD_LOW_ULPPLL_R,PP_AVE_S1,PP_DISP_S1,PP_SRAM_S1 ?
MIC1 S DEFAULT PP_*MIC1*,*MIC1*FILT_RET* ?
S_PWR_100UM S 100UM-249UM_SPACING PP_VDDIO12_GRP5 ?
S_PWR_200UM S 100UM-249UM_SPACING PP1V2_SOC,PP0V6_VDDQL_S1,PP1V8_FMON_R,PP1V8_ULPPLL_R ?
MIC3 S DEFAULT PP_*MIC3*,*MIC3*FILT_RET* ? HYBRID IMPEDANCE RULE
S_PWR_SHAPE S 250UM+_SPACING PP_CPU_ECORE,PP_CPU_PCORE,PP_DCS_S1 ?
S_PWR_SHAPE S 250UM+_SPACING PP_GPU,PP_SOC_S1,PP0V8_SOC_FIXED_S1 ? TRACE REFERENCE REQUIRED TRACE WIDTH
PENROSE_DP S A_DIELECTRIC_1.5X DP:DP_*PENROSE* ?
S_PWR_SHAPE S 250UM+_SPACING PP0V7_VDD_LOW_FLPPLL_R,PP0V7_VDD_LOW_S2 ? LAYER LAYER(s) IMPEDANCE (OPTIONAL)
VSS_PMU_RTC S DEFAULT VSS_PMU_RTC ?
S_PWR_SHAPE S 250UM+_SPACING PP0V7_VDD_LOW_ULPPLL_R,PP_AVE_S1,PP_DISP_S1,PP_SRAM_S1 ?
RULE NAME= 50_THIN_L10 ZONE NAME= PRIMARY
NAND
TOP ISL2 50 0.062
CLEAR
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* OVERRIDE
CLASS TO CLASS SPACING CLASS NAME

DOMAIN
E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N ISL5_WIDE -> ISL5 ISL3,ISL7 50 0.104
CLASS NAME CLASS NAME CONSTRAINT SET PWR_80UM P PWR_80UM PP1V8_IO_NAND_* ? ISL6 ISL5,ISL7 50 0.038
SWITCHING GND DEFAULT PWR_100UM P PWR_100UM ANALOG_NAND_ZQ*,ANALOG_PCIE_NAND_RESREF ?
S_PWR_200UM GND DEFAULT PWR_SHAPE P PWR_SHAPE PP0V9_NAND*,PP2V63_NAND,PP1V2_IO_NAND,PP_VDDIO_2_NAND_R ? ISL8 ISL7,ISL9 50 0.029
S_PWR_SHAPE GND DEFAULT S_PWR_100UM S 100UM-249UM_SPACING ANALOG_NAND_ZQ*,ANALOG_PCIE_NAND_RESREF ?
S_PWR_100UM S_PWR_100UM 100UM-249UM_SPACING S_PWR_SHAPE S 250UM+_SPACING PP0V9_NAND*,PP2V63_NAND,PP1V2_IO_NAND,PP_VDDIO_2_NAND_R ?
S_PWR_200UM S_PWR_200UM 100UM-249UM_SPACING
PMU CAPPED RULE LAYER RULE NAME(S)
S_PWR_SHAPE S_PWR_SHAPE 250UM+_SPACING CLEAR VALUE (MM)
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* EXAMPLE:SMD2ALL,SMD_TO_SMD,MVIA2ALL,SHAPE2ALL
EX:ALL,EXT,INT
BOT,ISL2 EXAMPLE: 2D,2V,3DL-5DL,3VL
LPDP_WIDE LPDP_WIDE A_DIELECTRIC_2X DOMAIN
OVERRIDE
LINE2SMD ? 0.070 2,2D,4D,4V

B LPDP_SWIDE LPDP_SWIDE A_DIELECTRIC_2X
CLASS NAME
PWR_SHAPE
E,P,S
P
CONSTRAINT SET
PWR_SHAPE
DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:)
PP0V9_S1
Y/N
? MVIA2MVIA ? =0.065 2D,4D,4V B

LPDP_TELE LPDP_TELE A_DIELECTRIC_2X
S_PWR_SHAPE S 250UM+_SPACING PP0V9_S1 ? MVIA2SMD ? =0.070 2,2D,4D,4V
LPDP_FCAM LPDP_FCAM A_DIELECTRIC_2X
MVIA2SHAPE ? =0.070 2,2D,4D,4V
MIPI_DISPLAY MIPI_DISPLAY A_DIELECTRIC_2X
SMD2SMD ? 0.070 2,2D,4D,4V
MIPI_IRCAM MIPI_IRCAM A_DIELECTRIC_2X
SMD2SHAPE ? 0.070 2,2D,4D,4V
PCIE_NAND PCIE_NAND A_DIELECTRIC_2X
LINE2LINE ALL 0.290 4V
PCIE_WLAN PCIE_WLAN A_DIELECTRIC_2X RADIO_MLB_ICE_LOFT
LINE2MVIA EXT 0.150 4V
PCIE_BB PCIE_BB A_DIELECTRIC_2X NET RULE ASSIGNMENT
DOMAIN
LINE2MVIA INT 0.279 4V
HYDRA_DP HYDRA_DP A_DIELECTRIC_2X (E,P,S)
CONSTRAINT SET COMMA SEPARATED NET NAMES (WILDCARD SUPPORT EX: DDR* ) LINE2LINE TOP 0.160 2
USB_DP USB_DP A_DIELECTRIC_2X P A_50_THIN_L10_SE 50_LAA_TO_ANT_LAT LINE2MVIA EXT 0.075 2
MIC1_DP MIC1 DEFAULT P A_50_THIN_L10_SE 50_ANT5_LAA LINE2MVIA INT 0.120 2
MIC2_DP MIC2 DEFAULT
MVIA2MVIA EXT 0.080 2
MIC3_DP MIC3 DEFAULT CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
OVERRIDE MVIA2MVIA INT 0.060 2

MIC4_DP MIC4 DEFAULT CLASS NAME
DOMAIN
PENROSE_DP PENROSE_DP DEFAULT 50_WIDE S A_DIELECTRIC_2X_50_WIDE_SE 50_ANT1_CPLR_IN Y
CLK_PMU_XTAL VSS_PMU_RTC DEFAULT 50_THIN_L10 S A_DIELECTRIC_2X_50_THIN_L10_SE 50_ANT5_LAA,50_LAA_TO_ANT_LAT Y
LAA_MLB
CLEAR
CLEAR
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* OVERRIDE CLASS NAME
DOMAIN
DOMAIN
50_THIN_L10 S A_DIELECTRIC_2X_50_THIN_L10_SE 50_LAA_TO_ANT_LAT,50_WLAN_A* ?
E_LPDP_WIDE E DIFF_PAIR DP:DP_*90_LPDP*_WIDE* ?
E_LPDP_SWIDE E DIFF_PAIR DP:DP_*90_LPDP*_SWIDE* ?
E_LPDP_TELE E DIFF_PAIR DP:DP_*90_LPDP*_TELE* ? DOMAIN NET RULE ASSIGNMENT
E_LPDP_FCAM E DIFF_PAIR DP:DP_*90_LPDP*_FCAM* ? (E,P,S)

CONSTRAINT SET COMMA SEPARATED NET NAMES (WILDCARD SUPPORT EX: DDR* )
E_MIPI_DISPLAY E DIFF_PAIR DP:DP_*90_MIPI*DISPLAY* ? P A_50_THIN_SE 50_LAA_TO_XCVR*

A E_MIPI_IRCAM E DIFF_PAIR DP:DP_*90_MIPI*_IRCAM* ? P A_50_THIN_L10_SE 50_LAA_TO_ANT_LAT,50_WLAN_A_* A
E_PCIE_NAND E DIFF_PAIR DP:DP_*90_PCIE*_NAND* ?
E_PCIE_WLAN E DIFF_PAIR DP:DP_*90_PCIE*_WLAN* ?
E_PCIE_BB E DIFF_PAIR DP:DP_*90_PCIE*_BB* ?
E_USB_DP E DIFF_PAIR DP:DP_*90_*USB*,DP_90*HYDRA* ?
E_MIKEY_DP E DIFF_PAIR DP:DP_*90_*MIKEY* ?
E_PWR_DP E GENERIC_DP DP:DP_CODEC_AOUT* ?
E_GENERIC E GENERIC_DP DP:DP_MIC*,DP_PENROSE*,DP_NTC_*,DP_*MTR*,DP_ANALOG*SENSE* ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Probe Points - TOP

METROLOGY LVCC
PP_GPU_LVCC: ProbePoint removed, Access through MLB_BOT
XW0510
SHORT-10L-0.05MM-SM
PP_GPU 1 2
PP_GPU_LVCC
50 19 38
Removed: PAD_MTR_ANALOG_TEST_P PP_CPU_Pcore: ProbePoint removed,Access through MLB_BOT

XW0511 D
D SHORT-10L-0.05MM-SM
PP_CPU_PCORE_LVCC
Removed: PAD_MTR_ANALOG_TEST_N 50 19
PP_CPU_PCORE 1
-
<57> 2 38
BUMP SENSE PMU Sensors VALIDATION PP's

PP0653
P2MM-NSM PP0620 PP0644 PP0690
SM P2MM-NSM P2MM-NSM P2MM-NSM
O
1
PP PROBE_AOP_TO_DDR_SLEEP1 1
O
SM
GPIO_AOP_FROM_IMU_DATARDY 1
O
SM
GPIO_NUB_FROM_GECKO_IRQ_L
o
1
SM
=
13 IN PP 56 29 IN PP 34 13 IN PP
17[IN > ANALOG_GPU_SENSEN ROOM=TEST ROOM=TEST ROOM=TEST ROOM=TEST
14 ANALOG_GPU_SENSEP PP0613
P2MM-NSM PP0622 PP0667
IN
o
1
SM
PP
ROOM=TEST
36 22 7 IN
IO_PMU_TO_AP_HYDRA_ACTIVE_READY
P2MM-NSM
1
o SM
PP
ROOM=TEST
35 13 IN
GPIO_NUB_FROM_CCG2_INT_L
P2MM-NSM
o 1
SM
PP
ROOM=TEST
PP0651 PP0694
P2MM-NSM
o
1
SM PP0623
P2MM-NSM Rigel CLK_PMU_TO_AOP_32K
P2MM-NSM
o1
SM
=
PP 22 13 IN PP
IO_AP_TO_PMU_RESET
C 17 IN ANALOG_CPU_PCORE_SENSEN ROOM=TEST
PP0612
22 13 [IN > 1
o SM
PP
ROOM=TEST PP0680
ROOM=TEST
PP0696
C
14
=
c > ANALOG_CPU_PCORE_SENSEP
IN P2MM-NSM
o
1
SM
PP
IO_AP_TO_PMU_SOCHOT_L
PP0624
P2MM-NSM
28
=
[IN > PP_RIGEL_BUCK_BOOST_A
P2MM-NSM
o
1
SM
PP
ROOM=TEST 36 11 IN
UART7_AP_FROM_ACCESSORY_RXD
P2MM-NSM
o 1
SM
PP
ROOM=TEST
ROOM=TEST
PP0616
22 7 IN
1
o SM
PP
ROOM=TEST
PP0681
P2MM-NSM
PP0697
P2MM-NSM
P2MM-NSM
o
1
SM
PP
ROOM=TEST
PP0691
P2MM-NSM
28 IN
PP_RIGEL_BUCK_BOOST_B
o
1
SM
PP
ROOM=TEST
31 11 IN
SPI3_AP_FROM_CODEC_MISO
o
1
SM
PP
ROOM=TEST
ANALOG_SOC_SENSE_N SWD_NUB_BI_PMU_SWDIO
17 IN
PP0614
1
o SM
PP0698
=
56 13 IN PP
ANALOG_SOC_SENSE_P P2MM-NSM
14 ( IN> P2MM-NSM
o
1
SM
ROOM=TEST
31 11 IN
SPI3_AP_TO_CODEC_MOSI
o 1
SM
PP
PP
ROOM=TEST
PP0617
CCG SWD ROOM=TEST
PP0699
P2MM-NSM
P2MM-NSM
o
1
SM
PP
31 11 IN
SPI3_AP_TO_CODEC_CS_L
o1
SM
PP
ROOM=TEST
ANALOG_DCS_SENSEP ROOM=TEST PP0670

P2MM-NSM
=
16 IN
PP0652
P2MM-NSM
NAND PP0640
P2MM-NSM
(IN >
56 31 GPIO_AOP_TO_CODEC_CLP_EN
o1
SM
PP
ROOM=TEST
17 IN
ANALOG_VDDQL_DCS_SENSEN
o
1
SM
PP 56 35 IN
GPIO_AP_TO_CCG2_SWCLK
o
1
SM
PP PP0671
P2MM-NSM
ROOM=TEST
PP0618
PP0660
P2MM-NSM
ROOM=TEST
56 31 IN
GPIO_AOP_TO_CODEC_RESET_L
o1
SM
PP
16 IN
ANALOG_VDDQL_SENSEP
P2MM-NSM
o
1
SM
PP
18 7
=
(IN > SWD_AP_BI_NAND_SWDIO 1
o SM
PP
ROOM=TEST
ROOM=TEST
PP0672
P2MM-NSM
B
ROOM=TEST
18 11 6 IN
SPI0_AP_FROM_S4E_MISO_BOOT_CONFIG2
PP0662
P2MM-NSM
1
o SM
PP
ROOM=TEST
ADAMS =
[IN > GPIO_AP_FROM_CODEC_INT_L
56 31
o
1
SM
PP
ROOM=TEST
PP0673
B
PP0665 PP0645 P2MM-NSM
SOC Debug P2MM-NSM

P2MM-NSM
o SM UART7_AP_TO_ACCESSORY_TXD
o
1
SM
=
36 11 IN
SPMI_ISP_TO_CAM_PMU1_CLK 1 PP
18 7[IN >
IO_AP_TO_NAND_RESET_L 1
o SM
PP
ROOM=TEST
25 9 IN PP
ROOM=TEST
ROOM=TEST
PP0674
PP0600 PP0646 P2MM-NSM
22 7 IN
CLK_AP_TO_PMU_TST_CLKOUT
P2MM-NSM
o1
SM
PP
ROOM=TEST
PP0601
25 9 BI
SPMI_ISP_BI_CAM_PMU1_DATA
P2MM-NSM
o
1
SM
PP
ROOM=TEST
28 25
=
[ IN > GPIO_CAM_PMU1_TO_RIGEL_ENABLE o
1
SM
PP
ROOM=TEST
PP0675
GPIO_BOARD_ID0 P2MM-NSM PP0642 P2MM-NSM
7 6 IN
o1
SM
PP
ROOM=TEST
PCIE 27 26 25 IN
GPIO_CAM_PMU1_TO_SWIDE_LDO_EN
P2MM-NSM
o
1
SM
PP
ROOM=TEST
28 25 22 IN
GPIO_CAM_PMU1_FROM_RIGEL_INT -o
1
SM
PP
ROOM=TEST
PP0602
P2MM-NSM
PP0643
47 9
-
CIN3GPIO_ISP_TO_DISPLAY_FLASH_INT o1
SM
PP
90_PCIE0_AP_TO_NAND_REFCLK_P
PP0630
P2MM-NSM
GPIO_CAM_PMU1_TO_WIDE_LDO_EN
P2MM-NSM
o
1
SM
ROOM=TEST
18 8 IN
o1
SM
PP
ROOM=TEST
27 26 25 IN PP
ROOM=TEST
PP0647
Removed: PROBE_SOC_DEBUG3. Repurposed GPIO PP0631
P2MM-NSM P2MM-NSM
18 8
c
^-
IN
90_PCIE0_AP_TO_NAND_REFCLK_N
o1
SM
PP
ROOM=TEST
27 26 25 IN
GPIO_CAM_PMU1_TO_FCAM_LDO_EN
o
1
SM
PP
ROOM=TEST
Removed PP0604: PROBE_DFU_STATUS.: Add for Proto1

PP0648
P2MM-NSM
PP0605
P2MM-NSM
27 25
=-
[ IN > GPIO_CAM_PMU1_TO_TELE_LDO_EN
o
1
SM
PP
ROOM=TEST
A 22 7 IN
IO_PMU_TO_AP_PRE_UVLO_L
o
1
SM
PP
ROOM=TEST
A
*-
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TOP BOARD ONLY CONFIGURATION IS D42/D43 MLB

BOTTOM BOARD SELECTS ICE/MAV
D D
BOOTSTRAPPING:BOARD REV Board Rev[3 :0]
BOARD ID Float=Low I PU=High

3 2 1 0
BOOT CONFIG PreProlo 1 1 1
Prolo 1 1 1 0
(Spare) 1 0 1
R0923
GPIO_BOARD_REV3 1.00K NOSTUFF PP1V8_IO Prolo 2 1 0 0
1
AA5% -2
^
56 8 50 53
1/32W
MF (Spare) 0 1 1
01005
ROOM=SOC
R0922 EVT 0 1 0
GPIO_BOARD_REV2 1
1.00K 2
56 OUT AA/V (Spare) 0 1 1 1
5%
1/32W
MF
01005
ROOM=SOC SELECTED --> Carrier 0 1 1 0
R0921 (Spare) 0 0 1 1
GPIO_BOARD_REV1 1
1.00K 2
56 OUT
C 5%
1/32W DVT 0 0 1 0 C
MF
01005
ROOM=SOC
(Spare) 0 0 0 1
R0920
GPIO_BOARD_REV0 1
1.00K NOSTUFF
56 OUT A/5%W2 PVT 0 0 0 0
1/32W
MF
01005
ROOM=SOC Board ID[ 4:0]
TABLE_5_HEAD
Float=Low I PlbHigh
117S0156 1 RES,1.00KOHM, 01005 R0912 CRITICAL D421_BOARD_ID

TABLE_5_ITEM
4 3 2 1 0
BoardlD[ 4:0] Unused 0 = ICE. 1 = MAV 00 = None 01 = X1367/911 = X1364/810 = X1403 0 = MLB, 1 = DEV
NC_GPIO_BOARD_ID4 NC_GPIO_BOARD_ID4
7 OUT
CKPLUS_WAIVE=SINGLE_NODENET MAKE_BASE=TRUE
NO_TEST=1
MLB N104 5 ' b00100 0 0 0 0
DEVN104 5 ' b00101 0 0 0 1

R0913 MLB D42 5'b 01110 0 1 0
GPIO_BOARD_ID3 GPIO_BOARD_ID3 1
1.00K 2 NOSTUFF
7 OUT
MAKE_BASE=TRUE AAA
5% '
1/32W DEV D42 5'b01111 0 1 1
MF
01005
ROOM=SOC
R0912
DEFAULT --> MLB D421 5'bOOHO 0 0 0
B 7 OUT
GPIO_BOARD_ID2 GPIO_BOARD_ID2
MAKE_BASE=TRUE
1
1.00K 2
wv NOSTUFF DEV D421 5'b00111 0 0 1 B
5%
1/32W
MF
01005
ROOM=SOC
MLB D43 5 ' b01010 0 1 0 0
DEV D43 5'b 01011 0 1 0 1
7 OUT
PP1V8_IO
MLB D431 5 ' b00010 0 0 0 0
DEV D431 5’bOOOH 0 0 0 1

7 5
GPIO_BOARD_ID0 GPIO_BOARD_ID0
OUT
CKPLUS_WAIVE=SINGLE_NODENET MAKE_BASE=TRUE Boot Config[2:0]
No connect
Float=Low I PU=High
Usage MHz Test 2 1 0
SPIO NOR 12 0 0 0
SPIO NOR 12 Test 0 0 1

18 11 5 OUT
SPI0_AP_FROM_S4E_MISO_BOOT_CONFIG2 No connect
POR --> SPIO NAND POR 12 0 1 0
Proto Builds --> SPIO NAND Proto 12 Test 0 1 1
A R0901 A
SPI0_AP_TO_S4E_MOSI_BOOT_CONFIG1 1
4.7K SPIO NOR 40 1 0 0
18 11 OUT A /1%W2
1/32W
MF SPIO NOR 40 Test 1 0 1
01005
ROOM=SOC
R0900 SPIO NOR 6 1 1 0

SPI0_AP_TO_S4E_SCLK_BOOT_CONFIG0 1
4.7K
18 11 OUT A/W2 <-------Removed at EVT
SPIO NOR 6 Test 1 1 1
1%
1/32W
MF
01005
ROOM=SOC
NOSTUFF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: Misc 339S00623
U1000
D CEBU-4GB-18NM-H D
CSP
SYM 1 OF 21
TMKF89B0-C5
GPIO_BOARD_ID0 AD66 ROOM=SOC CD66
6 5 IN BOARD_ID0/SOC_DEBUG1 CPU_TRIGGER0 IO_AP_FROM_PMU_COMP_CPU_TRIGGER0_L IN 22
33
CPU_TRIGGER0: Internal Pull-Up
6
PP1V8_IO AP66 BOARD_ID1 CPU_TRIGGER1 CB64 IO_AP_FROM_PMU_CPU_TRIGGER1_L 22 CPU_TRIGGER1: Internal Pull-Up
DC
IN IN
GPIO_BOARD_ID2 BOARD ID
6 L65 BOARD_ID2 GPU_TRIGGER0 CF66 IO_AP_FROM_PMU_GPU_TRIGGER0_L 22 GPU_TRIGGER0: Internal Pull-Up
IN IN
6 IN
GPIO_BOARD_ID3 L64 BOARD_ID3/SPI0_SSIN GPU_TRIGGER1 CD64 IO_AP_FROM_PMU_GPU_TRIGGER1_L IN 22 GPU_TRIGGER1: Internal Pull-Up
6 IN
NC_GPIO_BOARD_ID4 J66 BOARD_ID4
DC m
THROTTLERS DROOP CB66 IO_PMU_TO_AP_PRE_UVLO_L 5 22 DROOP: Internal Pull-up
IN
22
IO_PMU_TO_AP_SIDE_L CF64 REQUEST_DFU1
IN CB65
SOCHOT1 IO_AP_TO_PMU_SOCHOT_L OUT 5 22
]0
22 IN
IO_PMU_TO_AP_VOL_DOWN_L CF65 REQUEST_DFU2
DFU SWD_TMS2 AK66 SWD_AP_BI_NAND_SWDIO 5 18
IO_HYDRA_TO_AP_FORCE_DFU AH64 BI
38 36 IN FORCE_DFU
SWD_TMS3 AK64 SWD_AP_BI_BB_SWDIO 38
NC_PROBE_DFU_STATUS AF66 BI
NO_TEST=1 DFU_STATUS
PROBE_DFU_STATUS: PP removed due to space constraints AM66
Y66 TST_CLKOUT/CTM_TRIGGER CLK_AP_TO_PMU_TST_CLKOUT OUT 5 22
57 NC_AP_TMR32_PWM0 TMR32_PWM0
57 NC_AP_TMR32_PWM1 Y65 TMR32_PWM1 ANALOGMUX_OUT BW3 AMUX_PMU_FROM_AP_ANALOGMUX_OUT 22
OUT
TMR32/PWM MISC
57 NC_AP_TMR32_PWM2 Y64 TMR32_PWM2
CFSB BW2 IO_PMU_TO_AP_HYDRA_ACTIVE_READY 5 22 36
IN
00 Q P P
NC_PAD_MTR_ANALOG_TEST_POS NO_TEST=1 CF2 PAD_MTR_ANALOG_TEST_P

HOLD_RESET A40
NC_PAD_MTR_ANALOG_TEST_NEG NO_TEST=1 CF3 PAD_MTR_ANALOG_TEST_N
R1001 1 TESTMODE B40 50 16
PP0V6_VDDQL_S1
39.2K MTR_RREF_P CB2 PAD_MTR_RREF_P
1%
MV
1/32W MTR_RREF_N CB3 PAD_MTR_RREF_N MTR 1 1 1 1 1 1
MF R1060 R1061 R1062 R1063 R1070 R1071
01005 2
NC_PAD_MTR_VREF_POS CD3
240 240 240 240 240 240
57 PAD_MTR_VREF_P 1% 1% 1% 1% 1% 1%
ROOM=SOC 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W
57 NC_PAD_MTR_VREF_NEG CD4 PAD_MTR_VREF_N MF MF MF MF MF MF
01005
2ROOM=SOC 01005
2 ROOM=SOC 01005
2ROOM=SOC 01005
2ROOM=SOC 01005
2ROOM=SOC 01005
2ROOM=SOC
DDR0_RREF CK3 ANALOG_DDR0_RREF
C DDR0_ZQ BU2 ANALOG_DDR0_ZQ C
DDR DDR1_RREF CJ65 ANALOG_DDR1_RREF
DDR2_RREF C3 ANALOG_DDR2_RREF
DDR3_RREF D63 ANALOG_DDR3_RREF
DDR3_ZQ AB66 ANALOG_DDR3_ZQ
XIO CP21 CLK_AP_XTAL_24M_IN
XO0 CR21 CLK_AP_XTAL_24M_OUT NOSTUFF
1
R1010 CRITICAL
511K ROOM=SOC_XTAL
1% Y1000
1/32W 1.60X1.20MM-SM
MF R1011
01005 24MHZ-30PPM-9.5PF-60OHM
i
2ROOM=SOC_XTAL
1
1.00K 2 CLK_AP_XTAL_24M_OUT_R 1 3
NO_XNET_CONNECTION=1
5% NC GND
1/32W
4
2
MF 1 C1010 C1011 1
01005
ROOM=SOC_XTAL
12PF 12PF
5% 5%
16V 16V
=dH"
2 NP0-C0G NP0-C0G 2
01005-1
ROOM=SOC_XTAL
01005-1
ROOM=SOC_XTAL
CRITICAL CRITICAL
SOC: NAND + USB 339S00623
U1000
CEBU-4GB-18NM-H
CSP
SYM 2 OF 21
B R1080 TMKF89B0-C5 B
CLK_AP_TO_NAND_24M 2
0.00 1 CLK_AP_TO_NAND_24M_R AU4 CR44
18 OUT NAND_SYS_CLK USB_DP 90_USB_AP_DATA_P BI 36
0% USB_DM CP44 90_USB_AP_DATA_N BI 36
00
1/32W 18 5 OUT
IO_AP_TO_NAND_RESET_L V64 SSD_RESET* NAND - IOS USB
MF USB_ID CL49 NC_USB_ID_AP 57
01005 18 OUT
IO_AP_TO_NAND_FW_STRAP V66 SSD_BFH
DO
ROOM=SOC USB_REXT CL47 ANALOG_AP_USB_REXT
USB_VBUS CM49 IO_AP_FROM_CHARGER_VBUS_DETECT IN 49
1
R1000
200
1%
1/32W
MF
01005
2ROOM=SOC
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
SOC: PCIe
U1000
L
CEBU-4GB-18NM-H
CSP
SYM 3 OF 21
18 8 BI
PCIE0_AP_BI_NAND_CLKREQ_L BJ65 PCIE_CLKREQ0* TMKF89B0-C5 1.2V PCIE_CLKREQ3* E2 PCIE3_AP_BI_WLAN_CLKREQ_1V2_L BI 8 38
339S00623
18 5 OUT
90_PCIE0_AP_TO_NAND_REFCLK_P CP32 PCIE_REF_CLK0_P PCIE_REF_CLK3_P CR26 90_PCIE3_AP_TO_WLAN_REFCLK_P OUT 38
18 5 OUT
90_PCIE0_AP_TO_NAND_REFCLK_N CR32 PCIE_REF_CLK0_N PCIE_REF_CLK3_N CP26 90_PCIE3_AP_TO_WLAN_REFCLK_N OUT 38
POO
OOP
C1100 1 2 0.22UF
10% 6.3V GND_VOID=TRUE
18 IN
90_PCIE0_AP_FROM_NAND_RX_P CER-X5R 01005 90_PCIE0_AP_FROM_NAND_C_RX_P CR17 PCIE_RX0_P PCIE_RX3_P CR6 90_PCIE3_AP_FROM_WLAN_C_RX_P IN 38
ROOM=SOC
18 90_PCIE0_AP_FROM_NAND_RX_N 90_PCIE0_AP_FROM_NAND_C_RX_N CP17 PCIE_RX0_N PCIE_RX3_N CP6 90_PCIE3_AP_FROM_WLAN_C_RX_N 38
uc
QC
LINK3
IN IN
C1101 1 2 0.22UF
NAND LINK
10% 6.3V GND_VOID=TRUE
CER-X5R 01005
ROOM=SOC
C1102 1 2 0.22UF
PCIE Gen2 - LINK 3
10% 6.3V GND_VOID=TRUE C

C 18 OUT
90_PCIE0_AP_TO_NAND_TX_P CER-X5R 01005 90_PCIE0_AP_TO_NAND_C_TX_P CM19 PCIE_TX0_P PCIE_TX3_P CM7 90_PCIE3_AP_TO_WLAN_C_TX_P OUT 38
ROOM=SOC
18 OUT
90_PCIE0_AP_TO_NAND_TX_N 90_PCIE0_AP_TO_NAND_C_TX_N CN19 PCIE_TX0_N PCIE_TX3_N CN7 90_PCIE3_AP_TO_WLAN_C_TX_N OUT 38
DO
PCIE Gen3 - LINK 0
C1103 1 2 0.22UF
10% 6.3V GND_VOID=TRUE 18 8 PCIE0_AP_TO_NAND_PERST_L BE64 PCIE_PERST0* 1.2V PCIE_PERST3* G4 PCIE3_AP_TO_WLAN_PERST_1V2_L 8 38
OUT
OOP
CER-X5R 01005
ROOM=SOC
J
57 NC_PCIE1_AP_CLKREQ_L BJ66 PCIE_CLKREQ1* PCIE_CLKREQ2* BG64 NC_PCIE2_CLKREQ_L 57
57 NC_PCIE1_AP_REF_CLK_P CP30 PCIE_REF_CLK1_P PCIE_REF_CLK2_P CP28 NC_PCIE2_AP_REF_CLK_P 57
57 NC_PCIE1_AP_REF_CLK_N CR30 PCIE_REF_CLK1_N PCIE_REF_CLK2_N CR28 NC_PCIE2_AP_REF_CLK_N 57
LINK1
LINK2
57
NC_PCIE1_AP_RX_P CR13 PCIE_RX1_P PCIE_RX2_P CR9 NC_PCIE2_AP_RX_P 57
57 NC_PCIE1_AP_RX_N CP13 PCIE_RX1_N PCIE_RX2_N CP9 NC_PCIE2_AP_RX_N 57
57
NC_PCIE1_AP_TX_P CM15 PCIE_TX1_P PCIE_TX2_P CM11 NC_PCIE2_AP_TX_P 57
57 NC_PCIE1_AP_TX_N CN15 PCIE_TX1_N PCIE_TX2_N CN11 NC_PCIE2_AP_TX_N 57
57 NC_PCIE1_AP_RESET_L BG66 PCIE_PERST1* PCIE_PERST2* BE65 NC_PCIE2_AP_RESET_L 57
B B
PCIE_RCAL_POS CK13 PCIE_RCAL_P 1.2V PCIE_CLKREQ4* E3 PCIE4_AP_BI_BB_CLKREQ_1V2_L 38
BI
1 PCIE_REF_CLK4_P CR24 90_PCIE4_AP_TO_BB_REFCLK_P 38
R1140 OUT
200 PCIE_REF_CLK4_N CP24 90_PCIE4_AP_TO_BB_REFCLK_N OUT 38
OOP
1%
1/32W
MF
01005
2 ROOM=SOC
PCIE_RCAL_NEG CL13 PCIE_RCAL_N
PCIE_RX4_P CR4 90_PCIE4_AP_FROM_BB_C_RX_P 38
LINK4
1 IN
C1140 PCIE_RX4_N CP4 90_PCIE4_AP_FROM_BB_C_RX_N 38
10PF IN
PCIe BB CLKREQ PU on BB domain 5%
PCIe Clock Request Pull-Ups 16V
2 NP0/C0G
01005
ROOM=SOC
50 15
PP1V2_SOC
53 50 6
PP1V8_IO PCIE_TX4_P CM5 90_PCIE4_AP_TO_BB_C_TX_P OUT 38
PCIE Gen2 - LINK 4

PCIE_TX4_N CN5 90_PCIE4_AP_TO_BB_C_TX_N OUT 38
R1100 1 R1130 1 PCIE4_AP_TO_BB_PERST_1V2_L
100K 100K 1.2V PCIE_PERST4* G3 OUT 8 38
ppp
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
18 8 PCIE0_AP_BI_NAND_CLKREQ_L
38 8 PCIE3_AP_BI_WLAN_CLKREQ_1V2_L
A A
PCIe Reset Pull-Downs
38 8 PCIE3_AP_TO_WLAN_PERST_1V2_L
38 8 PCIE4_AP_TO_BB_PERST_1V2_L
18 8 PCIE0_AP_TO_NAND_PERST_L
R1101 1 R1121 1 R1131 1
100K 100K 100K
5% 5% 5%
1/32W 1/32W 1/32W
MF MF MF
01005 2 01005 2 01005 2
ROOM=SOC ROOM=SOC ROOM=SOC
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
SOC: ISP
U1000
CEBU-4GB-18NM-H
CSP
SYM 4 OF 21
TMKF89B0-C5
51 90_LPDP_ISP_FROM_FCAM_RX_D0_N A32 LPDPRX_RX_D0_P 339S00623 MIPI0C_DPCLK A57 90_MIPI_ISP_FROM_IRCAM_CLK_P 45
IN
Polarity Swapped B32 B57
51 90_LPDP_ISP_FROM_FCAM_RX_D0_P LPDPRX_RX_D0_N MIPI0C_DNCLK 90_MIPI_ISP_FROM_IRCAM_CLK_N IN 45
51 90_LPDP_ISP_FROM_FCAM_RX_D1_N B30 LPDPRX_RX_D1_P MIPI0C_DPDATA0 A55 90_MIPI_ISP_FROM_IRCAM_D0_P 45
Polarity Swapped BI
51 90_LPDP_ISP_FROM_FCAM_RX_D1_P C30 LPDPRX_RX_D1_N MIPI0C_DNDATA0 B55 90_MIPI_ISP_FROM_IRCAM_D0_N 45
BI
MIPI-C
51 90_LPDP_ISP_FROM_WIDE_RX_D0_P A28 LPDPRX_RX_D2_P MIPI0C_DPDATA1 B59 90_MIPI_ISP_FROM_IRCAM_D1_P 45
IN
51 90_LPDP_ISP_FROM_WIDE_RX_D0_N B28 LPDPRX_RX_D2_N MIPI0C_DNDATA1 A59 90_MIPI_ISP_FROM_IRCAM_D1_N 45
IN
51 90_LPDP_ISP_FROM_WIDE_RX_D2_P B26 LPDPRX_RX_D3_P MIPI0C_REXT D55 ANALOG_MIPI_ISP_REXT
51 90_LPDP_ISP_FROM_WIDE_RX_D2_N C26 LPDPRX_RX_D3_N 1
ISP_I2C0_SCL/ISP_GPIO_15 C40 I2C0_ISP_SCL OUT 55
R1250
51 90_LPDP_ISP_FROM_WIDE_RX_D1_N B23 LPDPRX_RX_D4_P 200
Polarity Swapped ISP_I2C0_SDA/ISP_GPIO_14 A44 I2C0_ISP_SDA 55 1%
C23 BI
51 90_LPDP_ISP_FROM_WIDE_RX_D1_P LPDPRX_RX_D4_N 1/32W
C A42 MF C
A21 ISP_I2C1_SCL/ISP_GPIO_13 NC_I2C1_ISP_SCL OUT 57 01005
Polarity Swapped 51 90_LPDP_ISP_FROM_SWIDE_RX_D2_N LPDPRX_RX_D5_P D40
2 ROOM=SOC
B21 ISP_I2C1_SDA/ISP_GPIO_12 NC_I2C1_ISP_SDA BI 57
51 90_LPDP_ISP_FROM_SWIDE_RX_D2_P LPDPRX_RX_D5_N
I2C
ISP_I2C2_SCL/ISP_GPIO_11 B44 I2C2_ISP_SCL OUT 55
51 90_LPDP_ISP_FROM_SWIDE_RX_D1_N A17 LPDPRX_RX_D6_P
Polarity Swapped ISP_I2C2_SDA/ISP_GPIO_10 A45 I2C2_ISP_SDA 55
B17 BI
ISP_I2C3_SCL/ISP_GPIO_9 C42 GPIO_ISP_TO_TELE_SHDN_L OUT 41
51 90_LPDP_ISP_FROM_SWIDE_RX_D0_N B15 LPDPRX_RX_D7_P
Polarity Swapped ISP_I2C3_SDA/ISP_GPIO_8 A49 GPIO_ISP_TO_FCAM_SHDN_L 43
C15 OUT
LPDP-RX
51 NC_LPDP_ISP_RX_D8_P A13 LPDPRX_RX_D8_P ISP_GPIO0/SIO_LEAP_MADI_IN/AOP_LEAP_MADI_IN C47 GPIO_ISP_TO_CAM_PMU1_RESET_L 25
Polarity Swapped OUT
51 NC_LPDP_ISP_RX_D8_N B13 LPDPRX_RX_D8_N ISP_GPIO1/ISIO_LEAP_MADI_OUT/AOP_LEAP_MADI_OUT D47 GPIO_ISP_TO_IRCAM_SHDN_L 45
OUT
ISP_GPIO2/SOC_DEBUG2/MTR_ADC_DOUT D44 GPIO_ISP_TO_DISPLAY_FLASH_INT 5 47
B11 OUT
51 90_LPDP_ISP_FROM_TELE_RX_D1_P LPDPRX_RX_D9_P C45 ISP_GPIO3: External flash trigger
C11 ISP_GPIO3/SOC_DEBUG3 GPIO_ISP_RCAM_TO_STROBE_TRIGGER BI 36
38 40 41 42
51 90_LPDP_ISP_FROM_TELE_RX_D1_N LPDPRX_RX_D9_N AB4
ISP_GPIO4/ISP_SPMI_SDATA/MTR_ADC_CLKOUT SPMI_ISP_BI_CAM_PMU1_DATA BI 5 25
GPIO
CKPLUS_WAIVE=CLK_DATA_CON
51 90_LPDP_ISP_FROM_TELE_RX_D0_N B7 LPDPRX_RX_D10_P ISP_GPIO5/ISP_SPMI_SCLK AB2 SPMI_ISP_TO_CAM_PMU1_CLK OUT 5 25
Polarity Swapped
no pp pp DO DO Q9 QQ OQppQO
51 90_LPDP_ISP_FROM_TELE_RX_D0_P C7 LPDPRX_RX_D10_N ISP_GPIO6/ISP_FCAM_SPMI_SDATA/PLL_DIGOBS_0 AB3 NC_ISP_GPIO6 57

ISP_GPIO7/ISP_FCAM_SPMI_SCLK/PLL_DIGOBS_1 AD3 NC_ISP_GPIO7 57
51 90_LPDP_ISP_FROM_TELE_RX_D2_P A6 LPDPRX_RX_D11_P
51 90_LPDP_ISP_FROM_TELE_RX_D2_N B6 LPDPRX_RX_D11_N R1240
T2 CLK_ISP_TO_CAM_PMU1_24M_R 1
33.2 2 CLK_ISP_TO_CAM_PMU1_24M
SENSOR0_CLK OUT 25
A24
0
LPDP_ISP_RX0_RCAL_POS LPDPRX0_RCAL_P
1%
B24 LPDPRX0_RCAL_N 1/32W
1 MF
R1200 A9
01005
200 LPDPRX1_RCAL_P ROOM=SOC
1% B9
1/32W LPDPRX1_RCAL_N
MF
2 01005
ROOM=SOC R1241
LPDP_ISP_RX0_RCAL_NEG V3 CLK_ISP_TO_FCAM_12M_R 0.00 CLK_ISP_TO_FCAM_12M
SENSOR1_CLK 1 2 OUT 43
P
1 C1200 51 LPDP_ISP_BI_FCAM_AUX_RX_D0P D34 LPDPRX_AUX_D0_P 0%

B 1/32W B
10PF 57
NC_LPDP_ISP_AUX_RX_D1P C34 LPDPRX_AUX_D1_P MF
5% 01005
16V 51 LPDP_ISP_BI_SWIDE_AUX_RX_D2P D32 ROOM=SOC
2 NP0/C0G LPDPRX_AUX_D2_P
01005 57
NC_LPDP_ISP_AUX_RX_D3P D28
ROOM=SOC LPDPRX_AUX_D3_P
SENSOR CLK
57
NC_LPDP_ISP_AUX_RX_D4P D24 LPDPRX_AUX_D4_P
51 LPDP_ISP_BI_TELE_AUX_RX_D5P D21 LPDPRX_AUX_D5_P R1242
NC_LPDP_ISP_AUX_RX_D6P D19 V4 CLK_ISP_TO_IRCAM_12M_R 1
0.00 2 CLK_ISP_TO_IRCAM_12M
57 LPDPRX_AUX_D6_P SENSOR2_CLK OUT 45
LPDP_ISP_RX1_RCAL_POS
I
57
NC_LPDP_ISP_AUX_RX_D7P C19 LPDPRX_AUX_D7_P 0%
1/32W
1 57 NC_LPDP_ISP_AUX_RX_D8P D17 LPDPRX_AUX_D8_P MF
R1210 D13
01005
200 51 LPDP_ISP_BI_WIDE_AUX_RX_D9P LPDPRX_AUX_D9_P ROOM=SOC
1% NC_LPDP_ISP_AUX_RX_D10P D9
1/32W 57 LPDPRX_AUX_D10_P
MF NC_LPDP_ISP_AUX_RX_D11P
57 D6 LPDPRX_AUX_D11_P
2 01005
ROOM=SOC R1243
LPDP_ISP_RX1_RCAL_NEG 0.00
SENSOR3_CLK V2 CLK_ISP_TO_RIGEL_12M_R 1 2 CLK_ISP_TO_RIGEL_12M 28
1 OUT
f
C1210 0%
10PF 1/32W
5% MF
16V
2 NP0/C0G 01005
01005 ROOM=SOC
ROOM=SOC
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
SOC: Display
339S00623
U1000
CEBU-4GB-18NM-H
CSP
C SYM 5 OF 21 C
TMKF89B0-C5
90_MIPI_AP_TO_DISPLAY_CLK_N CP62 MIPID_DPCLK DISP_I2C_SCL/DISP_SPMI_SCLK Y4 NC_I2C_DISP_SCL
on on no GO no
47 OUT 57
DISP_I2C
Polarity Swapped CR62 Y2
47 OUT
90_MIPI_AP_TO_DISPLAY_CLK_P MIPID_DNCLK DISP_I2C_SDA/DISP_SPMI_SDATA NC_I2C_DISP_SDA 57
47 90_MIPI_AP_TO_DISPLAY_D0_P CR59 MIPID_DPDATA0

47 90_MIPI_AP_TO_DISPLAY_D0_N CP59 MIPID_DNDATA0
BI
DWI_CLK T65 NC_DWI_PMGR_TO_BACKLIGHT_CLK
90_MIPI_AP_TO_DISPLAY_D2_P CR61
DWI
47 OUT MIPID_DPDATA1 T66
Lane Swapped CP61 DWI_DO NC_DWI_PMGR_TO_BACKLIGHT_DATA
47 OUT
90_MIPI_AP_TO_DISPLAY_D2_N MIPID_DNDATA1
MIPI-D
47 90_MIPI_AP_TO_DISPLAY_D1_N CP64 MIPID_DPDATA2 DISP_TOUCH_BSYNC0 G64 NC_TOUCH_BSYNC0_DISP 57
OUT
Lane/Polarity Swapped CR64 E65
47 OUT
90_MIPI_AP_TO_DISPLAY_D1_P MIPID_DNDATA2 DISP_TOUCH_BSYNC1 NC_TOUCH_BSYNC1_DISP 57
DISP_TOUCH_EB E64
47 90_MIPI_AP_TO_DISPLAY_D3_N CP63 MIPID_DPDATA3
Polarity Swapped OUT
DISP_POL J64 NC_POL_DISP 57
47 90_MIPI_AP_TO_DISPLAY_D3_P CR63 MIPID_DNDATA3 DISPLAY_TE to provide WDG
OUT BW64
DISP_TE IO_AP_FROM_DISPLAY_TE IN 47
ANALOG_MIPI_AP_REXT CK59 MIPID_REXT

DP_WAKEUP G66 NC_WAKEUP_DP_DISP 57
GPIOS
EDP_HPD J65 NC_EDP_HPD_DISP 57
1
R1300 57 NC_LPDP_AP_TX0P CR47 LPDP_TX0P
200 NC_LPDP_AP_TX0N CP47
1% 57 LPDP_TX0N
1/32W
MF
LPDP-TX
01005 2 57 NC_LPDP_AP_TX1P CR49 LPDP_TX1P
ROOM=SOC
57 NC_LPDP_AP_TX1N CP49 LPDP_TX1N
'I
57 NC_LPDP_AP_TX2P CR51 LPDP_TX2P

57 NC_LPDP_AP_TX2N CP51 LPDP_TX2N
57 NC_LPDP_AP_TX3P CR53 LPDP_TX3P

NC_LPDP_AP_TX3N CP53
B 57 LPDP_TX3N
B
57 NC_LPDP_AP_AUXP CR55 LPDP_AUX_P
57 NC_LPDP_AP_AUXN CP55 LPDP_AUX_N
57 NC_LPDP_AP_RCALP CL57 LPDP_RCAL_P

57 NC_LPDP_AP_RCALN CM57 LPDP_RCAL_N
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: AP Serial
339S00623
U1000
CEBU-4GB-18NM-H
CSP
SYM 7 OF 21
D TMKF89B0-C5 D
36 IN
UART0_AP_DEBUG_RXD BE66 UART0_RXD I2C0_SCL AF64 NC_I2C0_AP_SCL 53
36 OUT
UART0_AP_DEBUG_TXD BC64 UART0_TXD I2C0_SDA AF65 NC_I2C0_AP_SDA 53
qq
57 NC_UART1_AP_CTS_1V2_L L4 UART1_CTS* I2C1_SCL N66 I2C1_AP_SCL 53
OUT
57 NC_UART1_AP_RTS_1V2_L J4 UART1_RTS* I2C1_SDA T64 I2C1_AP_SDA 53
BI
1.2V
I2C
57 NC_UART1_AP_RXD_1V2 J2 UART1_RXD
I2C2_SCL AW65 I2C2_AP_SCL 38 53
G2 OUT
57 NC_UART1_AP_TXD_1V2 UART1_TXD BA66
I2C2_SDA I2C2_AP_SDA BI 38 53
57 NC_UART2_AP_CTS_L BJ64 UART2_CTS*
I2C3_SCL L66 I2C3_AP_SCL 53
BL66 OUT
57 NC_UART2_AP_RTS_L UART2_RTS* N64
BL65 I2C3_SDA I2C3_AP_SDA BI 53
57 NC_UART2_AP_RXD UART2_RXD
57 NC_UART2_AP_TXD BL64 UART2_TXD I2S0_DIN BL3 I2S0_AP_FROM_CODEC_ASP3_DIN 31
IN
I2S0_DOUT BL2 I2S0_AP_TO_CODEC_ASP3_DOUT 31
A47 OUT
57 NC_UART3_AP_CTS_L UART3_CTS* BG4
UART
B49 I2S0_BCLK I2S0_AP_FROM_CODEC_ASP3_BCLK IN 31
57 NC_UART3_AP_RTS_L UART3_RTS* BJ4 R1410
C44 I2S0_LRCK I2S0_AP_FROM_CODEC_ASP3_LRCLK IN 31
57 NC_UART3_AP_RXD UART3_RXD BJ2 1
33.2 2
C49 I2S0_MCK I2S0_AP_TO_SPKAMP_TOP_MCLK_R I2S0_AP_TO_SPKAMP_TOP_MCLK OUT 38
57 NC_UART3_AP_TXD UART3_TXD
1%
I2S1_DIN AT4 I2S1_AP_FROM_CODEC_ASP4_DIN 31 1/32W
UART4_AP_FROM_NFC_CTS_L BN66 IN
38 IN UART4_CTS* MF
I2S1_DOUT AW2 I2S1_AP_TO_CODEC_ASP4_DOUT 31 01005
UART4_AP_TO_NFC_RTS_L BN64 OUT ROOM=SOC
38 OUT UART4_RTS*
I2S1_BCLK AT3 I2S1_AP_FROM_CODEC_ASP4_BCLK 31
UART4_AP_FROM_NFC_RXD BR66 IN
38 IN UART4_RXD
I2S1_LRCK AU2 I2S1_AP_FROM_CODEC_ASP4_LRCLK 31
UART4_AP_TO_NFC_TXD BR65 IN
I2S
38 OUT UART4_TXD AP4
qqqq
I2S1_MCK NC_I2S1_AP_MCLK 57
57 NC_UART6_AP_RXD AH65 UART6_RXD
I2S2_DIN BA3 I2S2_AP_FROM_BB_DIN 38
AH66 IN
57 NC_UART6_AP_TXD UART6_TXD BC4
I2S2_DOUT I2S2_AP_TO_BB_DOUT OUT 38
36 5 IN
UART7_AP_FROM_ACCESSORY_RXD BA64 UART7_RXD I2S2_BCLK BA2 I2S2_AP_FROM_BB_BCLK IN 38
UART7_AP_TO_ACCESSORY_TXD BC65 AW4 I2S2_AP_FROM_BB_LRCLK
no no no TO gngr gogc
36 5 OUT UART7_TXD I2S2_LRCK IN 38

I2S2_MCK AW3 NC_I2S2_AP_MCLK 57
C 18 6 5 IN
SPI0_AP_FROM_S4E_MISO_BOOT_CONFIG2 BN4 SPI0_MISO C
R1401 18 6 OUT
SPI0_AP_TO_S4E_MOSI_BOOT_CONFIG1 BN3 SPI0_MOSI I2S3_DIN/AP_PDM_IN1_DAT BG3 NC_I2S3_AP_DIN 57
SPI0_AP_TO_S4E_SCLK_BOOT_CONFIG0 1
0.00 2 SPI0_AP_TO_S4E_SCLK_BOOT_CONFIG0_R BN2 BE3 NC_I2S3_AP_DOUT
18 6 OUT SPI0_SCLK I2S3_DOUT/AP_PDM_IN1_CLK 57
q
0% I2S3_BCLK/AP_PDM_IN2_CLK BE2 NC_I2S3_AP_BCLK 57
SPI
1/32W 48 IN
SPI1_AP_FROM_TOUCH_MISO BU3 SPI1_MISO
MF I2S3_LRCK/AP_PDM_IN2_DAT BG2 NC_I2S3_AP_LRCLK 57
R1402 01005 48 OUT
SPI1_AP_TO_TOUCH_MOSI BR4 SPI1_MOSI
qqqq qq
0.00 ROOM=SOC I2S3_MCK/AP_PDM_OUT0_CLK BA4 NC_I2S3_AP_MCK 57
48
SPI1_AP_TO_TOUCH_SCLK 1 2 SPI1_AP_TO_TOUCH_SCLK_R BR2 SPI1_SCLK
OUT
0% 48 OUT
SPI1_AP_TO_TOUCH_CS_L BU4 SPI1_SSIN
1/32W
MF
01005 NC_SPI2_AP_MISO AF2 SPI2_MISO
ROOM=SOC
NC_SPI2_AP_MOSI AD2 SPI2_MOSI
NC_SPI2_AP_SCLK AD4 SPI2_SCLK
NC_SPI2_AP_CS_L AF4 SPI2_SSIN AP_PDM_OUT0_DAT BL4 NC_PDM_AP_OUT_DAT 57
31 5 IN
SPI3_AP_FROM_CODEC_MISO AP2 SPI3_MISO
R1404 31 5 OUT
SPI3_AP_TO_CODEC_MOSI AM2 SPI3_MOSI
qq
SPI3_AP_TO_CODEC_SCLK 1
0.00 2 SPI3_AP_TO_CODEC_SCLK_R AH3
31 OUT SPI3_SCLK
0% 31 5 SPI3_AP_TO_CODEC_CS_L AP3 SPI3_SSIN
OUT
1/32W
MF
01005
ROOM=SOC
339S00623
SPI: Route as Daisy-Chain. No T's Allowed U1000
Place series terminations close to SoC Pins CEBU-4GB-18NM-H
CSP
SYM 8 OF 21
TMKF89B0-C5
53 OUT
I2C4_AP_SCL AK4 I2C4_SCL SPI4_MISO AM4 NC_SPI4_MISO_AP 57
I2C SPI
53 BI
I2C4_AP_SDA AH2 I2C4_SDA SPI4_MOSI AK2 GPIO_PMU_TO_AP_DOUBLE_CLICK_DET_L IN 22
oq
SPI4_SCLK AK3 NC_SPI4_SCLK_AP 57
B B
PP1V8_IO 50
1 C1490
2.2UF
20%
6.3V
2 X5R-CERM
0201
ROOM=SOC_AUX
A1
VCC
U1401
STLNXA1L9YZ2S
WLCSP
53
I2C4_AP_SDA B1 SDA CRITICAL NC A3 NC
ROOM=SOC_AUX
53
I2C4_AP_SCL A2 SCL NC C1 NC
n
A VSS
A
B2
B3
C2
C3
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
D D
SOC: AP GPIO
339S00623
U1000
C CEBU-4GB-18NM-H
CSP
C
SYM 6 OF 21
TMKF89B0-C5
56 NC_AP_GPIO0 L3 GPIO0/I2C5_SCL GPIO GPIO16 AU64 GPIO_AP_TO_CCG2_SWCLK 56
56 NC_AP_GPIO1 L2 GPIO1/I2C5_SDA GPIO17 AU65 NC_AP_GPIO17 56
56 NC_AP_GPIO2 N4 GPIO2 GPIO18 BY66 GPIO_AP_FROM_DISPLAY_PANEL_ID 56

GPIO[0-8]: 1.2V
56 GPIO_AP_FROM_WLAN_TIME_SYNC_1V2 N3 GPIO3 GPIO19 AD64 PP1V8_IO PMU_ID: AVUS=1, WHITNEY = NC
56 GPIO_AP_TO_BB_COREDUMP_1V2 N2 GPIO4 GPIO20 AB65 NC_AP_GPIO20 56
56 GPIO_AP_FROM_BB_RESET_DETECT_1V2_L P4 GPIO5 GPIO21 BY64 NC_AP_GPIO21 56
56 NC_AP_GPIO6 P2 GPIO6 GPIO22 BY65 GPIO_AP_TO_NFC_DEV_WAKE 56
56 NC_AP_GPIO7 T4 GPIO7 GPIO23 AU66 NC_AP_GPIO23 56
56 NC_AP_GPIO8 T3 GPIO8 GPIO24 AT64 GPIO_AP_FROM_CODEC_INT_L 56
56 GPIO_BOARD_REV3 P64 GPIO9 GPIO25 BW66 GPIO_AP_FROM_SPKRAMP_TOP_INT_L 56
56 GPIO_BOARD_REV2 AP65 GPIO10 GPIO26 BU64 GPIO_AP_TO_SPKRAMP_TOP_RESET_L 56
56 GPIO_BOARD_REV1 AP64 GPIO11 GPIO27 BU65 GPIO_AP_FROM_BT_AUDIO_SYNC 56
56 GPIO_BOARD_REV0 B47 GPIO12 GPIO28 BU66 GPIO_AP_TO_AMUX_PMU_SYNC 56
56 GPIO_AP_CANARY1 AW64 GPIO13 GPIO29 P66 GPIO_AP_TO_TOUCH_RESET_L 56
56 GPIO_AP_CANARY2 AW66 GPIO14 GPIO30 P65 NC_AP_GPIO30 56
56 GPIO_AP_BI_CCG2_SWDIO AM65 GPIO15 GPIO31 AM64 NC_AP_GPIO31 56
B B
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: AOP 339S00623

U1000
CEBU-4GB-18NM-H
CSP
SYM 9 OF 21
TMKF89B0-C5
I2C0_AOP_SCL CP36 AOP_I2CM0_SCL
oo no 00
54 OUT
AOP_FUNC0 CL62 GPIO_AOP_FROM_IMU_DATARDY
54
I2C0_AOP_SDA CJ32 AOP_I2CM0_SDA
56
BI
AOP_FUNC1 CL34 GPIO_AOP_TO_IMU_SPI_CS_L 56
I2C
54
I2C1_AOP_SCL CM34 AOP_I2CM1_SCL AOP_FUNC2 CM63 GPIO_AOP_FROM_PEARL_B2B_DETECT 56
OUT
D 54 BI
I2C1_AOP_SDA CM26 AOP_I2CM1_SDA AOP_FUNC3 CJ34 GPIO_AOP_TO_R1_SPI_CS_L 56 D
AOP_FUNC4 CK34 GPIO_AOP_FROM_R1_INT
58 29
SPI0_AOP_FROM_IMU_R1_MISO CJ30 AOP_SPI0_MISO
56
IN CM55 GPIO_AOP_TO_R1_COREDUMP_TRIGGER
R1601 58 29 OUT
SPI0_AOP_TO_IMU_R1_MOSI CK23 AOP_SPI0_MOSI
AOP_FUNC5
CR38
56
SPI0_AOP_TO_IMU_R1_SCLK 1
33.2 2 SPI0_AOP_TO_IMU_R1_SCLK_R CK30 AOP_FUNC6 GPIO_AOP_TO_R1_TIME_SYNC 56
58 29 OUT AOP_SPI0_SCLK CM53
AOP_FUNC7 GPIO_AOP_TO_CODEC_RESET_L 56
SPI
1%
1/32W 57 NC_SPI1_AOP_MISO CJ42 AOP_SPI1_MISO AOP_FUNC8 CP38 GPIO_AOP_TO_CODEC_CLP_EN 56
MF
01005 57 NC_SPI1_AOP_MOSI CL42 AOP_SPI1_MOSI AOP_FUNC9/AOP_LPPLL CM51 GPIO_AOP_FROM_IRCAM_B2B_DETECT 56
ROOM=SOC
57 NC_SPI1_AOP_SCLK CL55 AOP_SPI1_SCLK AOP_FUNC10 CM36 GPIO_AOP_FROM_NFC_HOST_WAKE 56
GPIO
AOP_FUNC11 CM47 GPIO_AOP_FROM_SPKAMP_BOT_ARC_INT_L
I2S0_AOP_FROM_CODEC_ASP1_DIN CK53 AOP_I2S0_DIN
56
00 gc 00
31 IN
AOP_FUNC12 CL36 GPIO_AOP_TO_WLAN_CONTEXT_A 56
31 I2S0_AOP_TO_CODEC_ASP1_DOUT CL53 AOP_I2S0_DOUT
OUT
AOP_FUNC13 CL64 GPIO_AOP_TO_WLAN_CONTEXT_B 56
31 I2S0_AOP_FROM_CODEC_ASP1_BCLK CK40 AOP_I2S0_BCLK
IN
AOP_FUNC14 CJ36 GPIO_AOP_FROM_TOUCH_CTS 56
31 I2S0_AOP_FROM_CODEC_ASP1_LRCLK CK51 AOP_I2S0_LRCK
IN
AOP_FUNC15/AOP_PDM_CLK4 CK57 GPIO_AOP_BI_PROX_INT_L 56
I2S0_AOP_TO_CODEC_MCLK1_R CM42 AOP_I2S0_MCK/AOP_PDM_CLK2
AOP_FUNC16/AOP_PDM_CLK3 CK36 GPIO_AOP_FROM_ALS_INT_L
I2S
56
49 38 31 I2S1_AOP_FROM_AMPS_CODEC_ASP2_DIN CL40 AOP_I2S1_DIN AOP_FUNC17 CM64 GPIO_AOP_FROM_K2_INT_L 56

IN
R1603 49 38 31 OUT
I2S1_AOP_TO_AMPS_CODEC_ASP2_DOUT CM61 A0P_I2S1_DOUT/AOP_PDM_IN2_DAT AOP_FUNC18 CM38 GPIO_AOP_FROM_COMPASS_INT 56
I2S0_AOP_TO_CODEC_MCLK1 1
33.2 2 I2S1_AOP_AMPS_FROM_CODEC_ASP2_BCLK_R CM40 CM59 GPIO_AOP_FROM_HALL_CASE_INT_L
31 OUT AOP_I2S1_BCLK/AOP_PDM_IN1_CLK AOP_FUNC19 56
1% I2S1_AOP_AMPS_FROM_CODEC_ASP2_LRCLK_R CM62 AOP_I2S1_LRCK/AOP_PDM_IN2_CLK AOP_FUNC20 CL38 GPIO_AOP_FROM_HALL_FLAP_INT_L 56

1/32W
MF I2S1_AOP_TO_SPKRAMP_BOT_ARC_MCLK CJ40 AOP_I2S1_MCK AOP_FUNC21 CJ61 GPIO_AOP_FROM_TOUCH_INT_L
oc POP
49 OUT 56
01005
ROOM=SOC AOP_FUNC22 CJ38 GPIO_AOP_TOUCH_FROM_DISPLAY_BSYNC1 56
38 SPMI1_AOP_BI_RF_DATA CM24 AOP_UART0_RXD/NUB_SPMI1_SDATA
BI
R1604 38 OUT
SPMI1_AOP_TO_RF_CLK CM32 AOP_UARTO_TXD/NUB_SPMI1_SCLK
I2S1_AOP_AMPS_FROM_CODEC_ASP2_BCLK 1
49.9 2
49 38 31 IN
48
UART1_AOP_FROM_TOUCH_RXD CK7 AOP_UART1_RXD/NUB_SPMI2_SDATA
IN
1%
1/32W 48 UART1_AOP_TO_TOUCH_TXD CL32 AOP_UART1_TXD/NUB_SPMI2_SCLK
OUT
MF
UART
01005
ROOM=SOC
38 UART2_AOP_FROM_BB_RXD CL61 AOP_UART2_RXD
IN
OC
38 UART2_AOP_TO_BB_TXD CR36 AOP_UART2_TXD
OUT
C R1605 C
I2S1_AOP_AMPS_FROM_CODEC_ASP2_LRCLK 1
49.9 2
49 38 31 IN
1% C1607 1
1/32W
MF
01005
ROOM=SOC
15PF
5%
16V 2
NP0-C0G
01005-1
ROOM=B2B_INTERPOSER
SOC: SMC
339S00623
NOSTUFF
U1000
CEBU-4GB-18NM-H
CSP
SYM 10 OF 21
TMKF89B0-C5
I2C0_SMC_SCL CL23 SMC_I2CM0_SCL SMC_UART0_RXD/SMC_I2CM2_SDA CJ28 I2C2_SMC_SDA
00 00
00
54 OUT 54
I2C
54 I2C0_SMC_SDA CM30 SMC_I2CM0_SDA SMC_UART0_TXD/SMC_I2CM2_SCL CL24 I2C2_SMC_SCL 54
BI BI
54 I2C1_SMC_SCL CL30 SMC_I2CM1_SCL/SMC_UART1_TXD UART

OUT
54 I2C1_SMC_SDA CJ6 SMC_I2CM1_SDA/SMC_UART1_RXD
BI
49 22 OUT
SPMI0_NUB_TO_PMU_DOTARA_CLK
R1610
2
0.00 1
SOC: NUB
0% 339S00623
1/32W
MF
01005
U1000
ROOM=SOC CEBU-4GB-18NM-H
CSP
B SYM 11 OF 21 B
TMKF89B0-C5
R1611 SPMI0_NUB_TO_PMU_DOTARA_CLK_R CJ9 NUB_SPMI0_SCLK SPMI
SPMI0_NUB_BI_PMU_DOTARA_DATA 2
61.9 1 SPMI0_NUB_BI_PMU_DOTARA_DATA_R CL26
49 22 BI NUB_SPMI0_SDATA
1%
1/32W 58 38 22 18 SWD_NUB_TO_MANY_SWCLK CJ21 NUB_SWD_TCK_OUT
OUT
MF
01005 56 5 SWD_NUB_BI_PMU_SWDIO CJ24 NUB_SWD_TMS0 SWD
ROOM=SOC
SWD_NUB_BI_R1_SWDIO CJ19 NUB_SWD_TMS1
nnr pc 0
58 BI
118S0755
36 22 IO_HYDRA_TO_NUB_PMU_DOCK_CONNECT CK24 NUB_DOCK_CONNECT DOCK
IN
36 IO_HYDRA_TO_NUB_DOCK_ATTENTION CJ15 NUB_DOCK_ATTENTION/NUB_PDM_CLK1
IN
35 5 GPIO_NUB_FROM_CCG2_INT_L CJ26 NUB_GPIO_0/AOP_PDM_CLK0

IN
34 5 GPIO_NUB_FROM_GECKO_IRQ_L CK9 NUB_GPIO_1/AOP_PDM_DATA0
IN
34 GPIO_NUB_TO_GECKO_RESET_L CM28 NUB_GPIO_2/AOP_FUNC_23
OUT
NC_NUB_GPIO3_AP CJ7 NUB_GPIO_3 GPIO
38 GPIO_NUB_TO_BBPMU_CLK_EN CLK_DATA_CON CL28 NUB_GPIO_4/AOP_PDM_DATA1
OUT
NC_NUB_GPIO5_AP NO_TEST=1 CJ11 NUB_GPIO_5/AOP_PDM_DATAOUT
NC_NUB_GPIO6_AP NO_TEST=1 CK28 NUB_GPIO_6/AOP_PDM_OUT0_CLK
36 SWD_DOCK_TO_AP_SWCLK CJ55 JTAG_TCK

On
OUT
36 SWD_DOCK_BI_AP_SWDIO CJ44 JTAG_TMS
BI
CL44 JTAG_SEL
JTAG
CJ62
1 ill
NC JTAG_TDI
CK62 JTAG_TDO
NC
CL51 JTAG_TRST*
NC
90_USB_DBG_DATA_N CR42 DBG_USB_DM
00
36 BI
A 36 BI
90_USB_DBG_DATA_P CP42
CK45
DBG_USB_DP
A
NC DBG_USB_ID DEBUG USB
ANALOG_DBG_USB_VBUS_REXT CM45 DBG_USB_REXT
16 PP3V3_USB_DEBUG_FILT CL45 DBG_USB_VBUS
1
R1620 57 NC_CLK_CLK24M_OUT CJ23 CLK24M_OUT
200 IO_PMU_TO_SYSTEM_RESET_L CK42
1% 38 22 IN COLD_RESET*
1/32W CJ57
MF CFSB_AON
01005 2 CL63
ROOM=SOC 22 5 IN
CLK_PMU_TO_AOP_32K RT_CLK32768 MISC
onr
22 5 OUT
IO_AP_TO_PMU_RESET CL59 WDOG
5 OUT
PROBE_AOP_TO_DDR_SLEEP1 CM44 AON_SLEEP1_RESET*
CJ3 LP4_IN_RESET*
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: SOC 0.770V @ 4.9A MAX

0.651V @ 3.4A MAX
0.590V @ 2.7A MAX
PP_SOC_S1 50
1 C1760 1 C1761 1 C1765

2.2UF 2.2UF 4UF
20% 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
4V
2 X5R
0201 0201 0201
D SOC: CPU/GPU 339S00623

ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
D
U1000 1 C1762 1 C1763 1 C1764

CEBU-4GB-18NM-H 15UF 15UF 15UF
1.029V @ 15.2A MAX 0.985V @ 12.6A MAX 20% 20% 20%
CSP 6.3V
2 X5R-CERM 2 6.3V 2 6.3V
0.909V @ 15.2A MAX SYM 12 OF 21 0.686V @ 5.80A MAX X5R-CERM X5R-CERM
0.540V @ 3.8A MAX 0.562V @ 3.20A MAX 0402-0.1MM
ROOM=SOC_FILT
0402-0.1MM
ROOM=SOC_FILT
0402-0.1MM
ROOM=SOC_FILT
TMKF89B0-C5 OMIT_TABLE OMIT_TABLE
PP_CPU_PCORE AN46 AA29 PP_GPU OMIT_TABLE
50 VDD_PCPU CPU/GPU VDD_GPU 50
AN50 VDD_PCPU VDD_GPU AA37
1 C1702 1 C1703 ROOM=SOC_FILT
C1704
ROOM=SOC_FILT
C1705
ROOM=SOC_FILT
C1706
ROOM=SOC_FILT
C1707 AN54 VDD_PCPU VDD_GPU AA46
1 C1730 1 C1731 1 C1733 1 C1734 1 C1735 1 C1736
2.2UF 2.2UF 2.2UF 2.2UF 26UF 15UF 15UF 26UF
20% 20% 14UF 14UF 14UF 14UF AN58 VDD_PCPU VDD_GPU AA54 20% 20% 20% 20% 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 20% 20% 20% 20% AR43 AC27 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
4V
2 X5R 6.3V
2 X5R-CERM 2 6.3V
X5R-CERM
4V
2 X5R
0201 0201 4V 4V 4V 4V VDD_PCPU VDD_GPU 0201 0201 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM
ROOM=SOC_FILT ROOM=SOC_FILT X5R X5R X5R X5R AR48 AC31 ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
0402-D2X-1 0402-D2X-1 0402-D2X-1 0402-D2X-1 VDD_PCPU VDD_GPU
1 3 1 3 1 3 1 3 AR56 AC35 OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
VDD_PCPU VDD_GPU
AV41 W56
i i i 5
VDD_PCPU VDD_GPU 339S00623
2 4 2 4 2 4 2 4 AV58 VDD_PCPU VDD_GPU AC39 U1000
BB58 VDD_PCPU VDD_GPU F27 CEBU-4GB-18NM-H
BF41 VDD_PCPU VDD_GPU F31 CSP
F35 SYM 13 OF 21
BK41 VDD_PCPU VDD_GPU
BK54 F48 TMKF89B0-C5
VDD_PCPU VDD_GPU AA41 H25
BK58 F52 VDD_SOC SOC VDD_SOC
VDD_PCPU VDD_GPU AC43 BH25
BM43 H33 VDD_SOC VDD_SOC
VDD_PCPU VDD_GPU
1 C1708 1 C1709 BM48 VDD_PCPU VDD_GPU H41
AC52 VDD_SOC VDD_SOC BH39
26UF 26UF AC56 VDD_SOC VDD_SOC BK10
20% 20% BM52 VDD_PCPU VDD_GPU H50
2 4V 2 4V AE8 VDD_SOC VDD_SOC BK14
X5R X5R BM56 VDD_PCPU VDD_GPU K27
0402-0.1MM 0402-0.1MM AE22 VDD_SOC VDD_SOC BK22
ROOM=SOC_FILT ROOM=SOC_FILT BP46 VDD_PCPU VDD_GPU K31
AE33 VDD_SOC VDD_SOC BM16
C OMIT_TABLE OMIT_TABLE BP50
BT56
VDD_PCPU VDD_GPU K35
K39
AE37 VDD_SOC VDD_SOC BM20 C
VDD_PCPU VDD_GPU AE46 BM27
CC46 K43 VDD_SOC VDD_SOC
VDD_PCPU VDD_GPU AE50 BM31
CC50 K48 VDD_SOC VDD_SOC
VDD_PCPU VDD_GPU
0.970V @ 3.6A MAX
0.650V @ 2.1A MAX
0.530V @ 1.2A MAX
PP_CPU_ECORE
5 ANALOG_CPU_PCORE_SENSEP
CC56
BM39
AN29
VDD_PCPU
VDD_PCPU_SENSE
VDD_GPU
VDD_GPU
VDD_GPU
K52
K56
M29
SOC: SRAM AE58
AG20
AG27
AG31
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
BP14
BP22
BP33
BP37
50 VDD_ECPU M46 VDD_SOC VDD_SOC
AN33 VDD_GPU AG39 BT16
VDD_ECPU VDD_SOC VDD_SOC
ROOM=SOC_FILT
C1791
ROOM=SOC_FILT
C1792
1 C1794 AN37 VDD_ECPU
VDD_GPU M54
339S00623 AG43 VDD_SOC VDD_SOC BT20
2.2UF VDD_GPU R27
14UF
20%
14UF
20%
20%
2 6.3V
AR27 VDD_ECPU
VDD_GPU R31 U1000 AG52 VDD_SOC VDD_SOC BT27
4V 4V X5R-CERM AR31 VDD_ECPU CEBU-4GB-18NM-H AG56 VDD_SOC VDD_SOC BT31
X5R X5R 0201
ROOM=SOC_FILT VDD_GPU R35
0402-D2X-1 0402-D2X-1 AR35 VDD_ECPU CSP AJ22 VDD_SOC VDD_SOC BT39
1 3 1 3 VDD_GPU R48 SYM 14 OF 21
AR39 VDD_ECPU AJ33 VDD_SOC VDD_SOC BT43
VDD_GPU R52 TMKF89B0-C5
AV33 VDD_ECPU AJ37 VDD_SOC VDD_SOC M56
2 4 2 4 VDD_GPU R56 AR52 VDD_SRAM_PCPU SRAM VDD_SRAM_SOC AA18
AV37 VDD_ECPU AJ50 VDD_SOC VDD_SOC BV14
VDD_GPU U33 BB41 VDD_SRAM_PCPU VDD_SRAM_SOC AA58
AY27 VDD_ECPU AJ58 VDD_SOC VDD_SOC BV22
VDD_GPU U50 BF58 VDD_SRAM_PCPU VDD_SRAM_SOC AC12
AY39 VDD_ECPU AL20 VDD_SOC VDD_SOC BV33
VDD_GPU W27 BK46 VDD_SRAM_PCPU VDD_SRAM_SOC AC48
BB29 VDD_ECPU AL27 VDD_SOC VDD_SOC BV37
VDD_GPU W31 VDD_SRAM_SOC AE18
BD27 VDD_ECPU AL31 VDD_SOC VDD_SOC BV56
VDD_GPU W35 AV29 VDD_SRAM_ECPU VDD_SRAM_SOC AE41
BF29 VDD_ECPU AL39 VDD_SOC VDD_SOC CA16
VDD_GPU W39 BB37 VDD_SRAM_ECPU VDD_SRAM_SOC AE54
BF37 VDD_ECPU AC20 VDD_SOC VDD_SOC CA20
VDD_GPU W43 BH31 VDD_SRAM_ECPU VDD_SRAM_SOC AG12
BH27 VDD_ECPU AL43 VDD_SOC VDD_SOC CA27
VDD_GPU W48 VDD_SRAM_SOC AG25
BH35 VDD_ECPU AL52 VDD_SOC VDD_SOC CA31
VDD_GPU W52 VDD_SRAM_SOC AG35
BK29 VDD_ECPU AL56 VDD_SOC VDD_SOC CA39
VDD_GPU_SENSE AE27 ANALOG_GPU_SENSEP 5 AA33 VDD_SRAM_GPU VDD_SRAM_SOC AG48
BK33 VDD_ECPU
OUT AN10 VDD_SOC VDD_SOC CA43
AA50 VDD_SRAM_GPU VDD_SRAM_SOC AJ18
BK37 VDD_ECPU AN14 VDD_SOC VDD_SOC CC14
H29 AJ29
B H37
VDD_SRAM_GPU
VDD_SRAM_GPU
VDD_SRAM_SOC
VDD_SRAM_SOC AJ41
AN22 VDD_SOC VDD_SOC CC22 B
AR16 VDD_SOC VDD_SOC CE20
H46 VDD_SRAM_GPU VDD_SRAM_SOC AJ54
AR20 VDD_SOC VDD_SOC CE27
H54 VDD_SRAM_GPU VDD_SRAM_SOC AL12
AV10 VDD_SOC VDD_SOC AY16
M33 VDD_SRAM_GPU VDD_SRAM_SOC AL25
AV14 VDD_SOC VDD_SOC CE52
M50 VDD_SRAM_GPU VDD_SRAM_SOC AL35
AV22 VDD_SOC VDD_SOC CG22
U29 VDD_SRAM_GPU VDD_SRAM_SOC AN18
BB10 VDD_SOC VDD_SOC F41
U46 VDD_SRAM_GPU VDD_SRAM_SOC AR12
BB14 VDD_SOC VDD_SOC U12
U54 VDD_SRAM_GPU VDD_SRAM_SOC AR25
BB22 VDD_SOC
VDD_SRAM_SOC AV18 VDD_SOC_SENSE AY20 ANALOG_SOC_SENSE_P 5
BB60 VDD_SOC
OUT
VDD_SRAM_SOC AY12
BD16 VDD_SOC
VDD_SRAM_SOC AY25
BD20 VDD_SOC
VDD_SRAM_SOC BB18
BD39 VDD_SOC
BP54 VDD_SRAM_ANE VDD_SRAM_SOC BD25
BF22 VDD_SOC
0.752V @ 2.7A MAX BV46 VDD_SRAM_ANE VDD_SRAM_SOC BF18
BF8 VDD_SOC
50
PP_SRAM_S1 CC54 VDD_SRAM_ANE VDD_SRAM_SOC BK18
BF14 VDD_SOC
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT VDD_SRAM_SOC BM12
BH16 VDD_SOC
C1772 C1773 C1774 VDD_SRAM_SOC BM25
BH20 VDD_SOC
14UF 14UF 14UF VDD_SRAM_SOC BM35
20% 20% 20% BP18
4V 4V 4V VDD_SRAM_SOC
X5R X5R X5R BP29
0402-D2X-1 0402-D2X-1 0402-D2X-1 VDD_SRAM_SOC
1 3 1 3 BP41
1 3 VDD_SRAM_SOC
BT12
U
2 4 ,
t IT
2 4
IT
2 4
VDD_SRAM_SOC
VDD_SRAM_SOC
VDD_SRAM_SOC
VDD_SRAM_SOC
BT25
BT35
BV18
A VDD_SRAM_SOC BV29
BV41
A
VDD_SRAM_SOC
VDD_SRAM_SOC CA35
VDD_SRAM_SOC CE25
VDD_SRAM_SOC CE56
VDD_SRAM_SOC K20
VDD_SRAM_SOC R12
VDD_SRAM_SOC W20
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: FIXED 339S00623

U1000
CEBU-4GB-18NM-H
CSP
SYM 17 OF 21
VDD_FIXED: 0.8V @ 15mA MAX TMKF89B0-C5 R1840 VDD_FIXED_PCIE_REFBUF:0.8V @ 50mA MAX
PP0V8_SOC_FIXED_S1 CC16 CG18 PP0V8_SOC_FIXED_PCIE_REFBUF 0.00 PP0V8_SOC_FIXED_S1 15
D
50
AC10
VDD_FIXED
VDD_FIXED
VDD_FIXED_PCIE_REFBUF 1
0%
2 50
D
1 C1801 AC58 VDD_FIXED FIXED
C1840 1 1/32W
MF
0.1UF 01005
4UF BD8 VDD_FIXED 20%
6.3V 2 ROOM=SOC_FILT
20%
2 4V AR60 VDD_FIXED X5R-CERM
X5R 01005
0201 M12 VDD_FIXED ROOM=SOC_FILT
ROOM=SOC_FILT
BD60 VDD_FIXED VDD_FIXED_PLL_DDR0 CA12 PP0V8_SOC_FIXED_S1 50
CG56 VDD_FIXED VDD_FIXED_PLL_DDR1 BM60
(Analog) F37 VDD_FIXED VDD_FIXED_PLL_DDR2 W12 C1841 1 C1842 1 VDD_FIXED_PLL_DDR0:
VDD_FIXED_PLL_DDR1:
0.8V
0.8V
@
@
8mA
8mA
VDD_FIXED_MIPID: 0.8V @ 40mA MAX 0.1UF 0.1UF
VDD_FIXED_MIPIC: 0.8V @ 15mA MAX F56 VDD_FIXED VDD_FIXED_PLL_DDR3 D59 20% 20% VDD_FIXED_PLL_DDR2: 0.8V @ 8mA
6.3V 6.3V VDD_FIXED_PLL_DDR3: 0.8V @ 8mA
VDD_FIXED_MIPID_PLL: 0.8V @ 10mA MAX X5R-CERM 2 X5R-CERM 2
01005 01005 VDD_FIXED_PLL_LPDP: 0.8V @ 3mA
50 15
PP0V8_SOC_FIXED_S1 CG60 VDD_FIXED_MIPID ROOM=SOC_FILT ROOM=SOC_FILT VDD_FIXED_PLL_SOC: 0.8V @ 9mA
VDD_FIXED_PLL_ANE: 0.8V @ 5mA
1 C1806 1 C1805 VDD_FIXED_PLL_LPDP CG50 VDD_FIXED_PLL_GPU: 0.8V @ 5mA
2.2UF 0.1UF VDD_FIXED_PCPU: 0.8V @ 5mA
20% 20% F60 VDD_FIXED_MIPIC VDD_FIXED_ECPU: 0.8V @ 5mA
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
VDD_FIXED_PLL_SOC BH12
CJ59 VDD_FIXED_MIPID_PLL
(Analog)
VDD_FIXED_USB: 0.8V @ 5mA MAX R1810 VDD_FIXED_PLL_ANE BD10
PP0V8_SOC_FIXED_S1 0.00 2 PP0V8_USB_DEBUG
50 15 1
-A/W
0%
CG48 VDD_FIXED_USB
1/32W
MF
1 C1810 VDD_FIXED_PLL_GPU BF12
01005 0.1UF
ROOM=SOC_FILT
20%
2 6.3V
X5R-CERM
01005
ROOM=SOC_FILT
NOSTUFF
CG54 VDD_FIXED_LPDP_TX VDD_FIXED_PCPU AL48
(Analog)
C VDD_FIXED_LPDP_RX: 0.8V @ 80mA MAX C
PP0V8_SOC_FIXED_S1 H10 AN41
50 15 VDD_FIXED_LPDP_RX VDD_FIXED_ECPU
1 C1817
0.1UF
20%
2 6.3V
X5R-CERM
01005
ROOM=SOC_FILT
1 C1816
2.2UF
20%
2 6.3V
X5R-CERM
0201
ROOM=SOC_FILT
1 C1815
20%
2 6.3V
2.2UF
X5R-CERM
0201
ROOM=SOC_FILT
1H14
H18
H22
VDD_FIXED_LPDP_RX
VDD_FIXED_LPDP_RX
VDD_FIXED_LPDP_RX VDD_FIXED_MTR BH8
VDD_FIXED_MTR 0.8V @ 5mA
PP0V8_SOC_FIXED_S1 15 50
VDD_FIXED_PCIE:0.8V @ 105mA MAX

50 15
PP0V8_SOC_FIXED_S1 CE12 VDD_FIXED_PCIE0
CE8 VDD_FIXED_PCIE1
1 C1821 1 C1820
4UF 0.1UF
20% 20%
2 4V
X5R 2 6.3V
X5R-CERM
0201 01005
ROOM=SOC_FILT ROOM=SOC_FILT
SOC: VDD12 339S00623

VDD12_PLL_SOC: 1.2V @ 8mA MAX U1000
VDD12_PLL_PCPU: 1.2V @ 7mA MAX CEBU-4GB-18NM-H
VDD12_PLL_ECPU: 1.2V @ 7mA MAX CSP
VDD12_PLL_GPU: 1.2V @ 7mA MAX SYM 18 OF 21 XW1801
VDD12_PLL_ANE: 1.2V @ 7mA MAX OMIT
TMKF89B0-C5 SHORT-20L-0.05MM-SM VDDIO12_GRP5:1.2V @ 15mA MAX
PP1V2_SOC
50 15 BF10 VDD12_PLL_SOC VDD12 VDDIO12_GRP5 AC8 PP_VDDIO12_GRP5
<S1>- PP1V2_SOC 8 50
1
VDDIO12_GRP5 AG8 ROOM=SOC_FILT
1 C1828 1 C1827 1 C1826 1 C1825 1 C1845 CONTROL INDUCTANCE
B 0.1UF
20%
0.1UF
20% 20%
0.1UF
20%
4UF
20%
4UF B
2 6.3V
X5R-CERM
6.3V
2 X5R-CERM 2 6.3V
X5R-CERM 2 4V
X5R 2 4V
X5R
01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
0201
ROOM=SOC_FILT
0201
AJ46 VDD12_PLL_PCPU ROOM=SOC_FILT
VDD12_PCIE:1.2V @ 95mA MAX
VDD12_PCIE_REFBUF:1.2V @ 20mA MAX
VDD12_PCIE0 CG14 PP1V2_SOC 15 50
VDD12_PCIE1 CG8
AN39 VDD12_PLL_ECPU 1 C1850
4UF
20%
2 4V
X5R
0201
ROOM=SOC_FILT
BD12 VDD12_PLL_GPU
R1855
CC18PP1V2_SOC_PCIE_REFBUF 0.00
VDD12_PCIE_REFBUF
VDD12_PCIE_REFBUF CE18
2
wv
0%
1
BD14 VDD12_PLL_ANE
1 C1855 1/32W
MF
0.1UF 01005
20% ROOM=SOC_FILT
2 6.3V
X5R-CERM
01005
ROOM=SOC_FILT
VDD12_LPDP_TX CG52
VDD12_LPDP_RX: 1.2V @ 9mA MAX

VDD12_LPDP_RX: 1.2V @ 200mA MAX
VDD12_PLL_LPDP CE48 PP1V2_SOC
VDDIO12_PLL_DDRx: 1.2V @ 8mA MAX 15 50
A 50 15
PP1V2_SOC CC12 VDDIO12_PLL_DDR0 VDD12_LPDP_RX F25 1 C1830 1 C1831 1 C1832 1 C1833 1 C1834 A
BK60 VDDIO12_PLL_DDR1 VDD12_LPDP_RX F8 15PF 0.01UF 0.1UF 4UF 4UF
5% 10% 20% 20% 20%
AA12 VDDIO12_PLL_DDR2 VDD12_LPDP_RX F12 2 16V 2 6.3V 2 6.3V 2 4V 2 4V
NP0-C0G X5R X5R-CERM X5R X5R
D61 VDDIO12_PLL_DDR3 VDD12_LPDP_RX F16 01005-1 01005 01005 0201 0201
ROOM=SOC_FILT ROOM=SOC_FILT
VDD12_LPDP_RX F20
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: DDR 339S00623

U1000
CEBU-4GB-18NM-H
0.895V @ 910mA MAX CSP
0.735V @ 550mA MAX SYM 16 OF 21
0.614V @ 300mA MAX TMKF89B0-C5 VDD2_DDR*: 1.06V - 1.17V @ 2.2A MAX
50
PP_DCS_S1 BP10 VDD_DCS_DDR0 DDR VDD2_DDR0 BC2 PP1V1_S2 16 50
CC10 VDD_DCS_DDR0 VDD2_DDR0 BU1
1 C1989 1 C1988 1 C1987 1 C1986 1 C1985 VDD2_DDR0 BY1
1 C1980 1 C1981 1 C1982 1 C1983
15UF 4UF 4UF 4UF 4UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% BP58 VDD_DCS_DDR1 VDD2_DDR0 CD1 20% 20% 20% 20%
2 6.3V 2 4V 2 4V 2 4V 2 4V 6.3V 6.3V 6.3V 6.3V
D X5R-CERM
0402-0.1MM
X5R
0201
X5R
0201
X5R
0201
X5R
0201
CC58 VDD_DCS_DDR1 VDD2_DDR0 CM3 2 X5R-CERM
0201
ROOM=SOC_FILT
2 X5R-CERM
0201
ROOM=SOC_FILT
2 X5R-CERM
0201
ROOM=SOC_FILT
2 X5R-CERM
0201
ROOM=SOC_FILT
D
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
AA10 VDD_DCS_DDR2 VDD2_DDR1 BC66

Place caps on SoC Corners K10 VDD_DCS_DDR2 VDD2_DDR1 BU67
VDD2_DDR1 BY67
H58 VDD_DCS_DDR3 VDD2_DDR1 CD67 Added C1982, C1983 (2.2uF for each VDD2_DDRx Channel)
W58 VDD_DCS_DDR3 VDD2_DDR1 CM65
5 ANALOG_DCS_SENSEP A62 VDD_DCS_SENSE

OUT
VDD2_DDR2 AB1
BG1 VDDQL_DDR0 VDD2_DDR2 AT2
VDDQL* TOTAL: 0.573V - 0.63V @ 620mA MAX
Place caps on SoC Corners BL1 VDDQL_DDR0 VDD2_DDR2 D3
50 7
PP0V6_VDDQL_S1
BM8 VDDQL_DDR0 VDD2_DDR2 P1
1 C1994 1 C1993 1 C1992 1 C1991 1 C1990 BR1 VDDQL_DDR0 VDD2_DDR2 V1
15UF 4UF 4UF 4UF 4UF CC8 VDDQL_DDR0
SOC: AOP/AVE/ISP/USB 339S00623

20%
2 6.3V
X5R-CERM
0402-0.1MM
ROOM=SOC_FILT
20%
2 4V
X5R
0201
ROOM=SOC_FILT
20%
2 4V
X5R
0201
ROOM=SOC_FILT
20%
2 4V
X5R
0201
ROOM=SOC_FILT
2 4V
20%
X5R
0201
ROOM=SOC_FILT
CH1
CK1
CM1
VDDQL_DDR0
VDDQL_DDR0
VDDQL_DDR0
VDD2_DDR3
VDD2_DDR3
VDD2_DDR3
AB67
AT66
D65
U1000 VDD2_DDR3 P67
VDD_LOW: 0.71V @ 220mA MAX CEBU-4GB-18NM-H BE67 VDDQL_DDR1 VDD2_DDR3 V67
VDD_LOW_FLPPLL: 0.71V @ 0.3mA MAX CSP BJ67 VDDQL_DDR1
VDD_LOW_ULPPLL: 0.71V @ 0.03mA MAX SYM 15 OF 21
BN67
VDD_LOW_USB_DEBUGL: 0.71V @ 5mA MAX VDDQL_DDR1
TMKF89B0-C5 BP60
CC29 BP25 VDDQL_DDR1
PP0V7_VDD_LOW_S2 VDD_LOW VDD18_TSADC_SOC0 VDD18_TSADC_SOC: 1.8V @ 3mA MAX CE60 CJ4 PP1V1_S2 16
50
CC33 CJ51 VDD18_TSADC_CPU: 1.8V @ 5mA MAX VDDQL_DDR1 VDDIO11_RET_DDR0 50
VDD_LOW VDD18_TSADC_SOC1 CF67 CJ64 Current included in VDD2
VDD18_TSADC_CPU: 1.8V @ 3mA MAX VDDQL_DDR1 VDDIO11_RET_DDR1
1 C1900 CC37 VDD_LOW VDD18_TSADC_SOC2 C4
VDD18_AMUX: 1.8V @ 0.3mA MAX CJ67 VDDQL_DDR1 VDDIO11_RET_DDR2 D4
4UF CC41 VDD_LOW
20% AOP/AVE/DISP/USB PP1V8_IO 16 50 CL67 VDDQL_DDR1 VDDIO11_RET_DDR3 D62
2 4V CE35 VDD_LOW
X5R
C 0201
ROOM=SOC_FILT CE39
CE43
VDD_LOW
AV39
AF1 VDDQL_DDR2 VDD1_DDR*: 1.70V - 1.95V @ 220mA MAX C
VDD_LOW VDD18_TSADC_CPU0 AK1 BC1 PP1V8_S2 50
CG25 AR41 VDDQL_DDR2 VDD1_DDR0
VDD_LOW VDD18_TSADC_CPU1 AP1 CN2
VDDQL_DDR2 VDD1_DDR0
VDD18_TSADC_CPU2 BK50
E1 VDDQL_DDR2
1 C1996 1 C1997 1 C1998 1 C1999
VDD18_TSADC_CPU3 BK52 0.47UF 0.47UF 0.47UF 0.47UF
J1 BC67 20% 20% 20% 20%
R1905 VDD18_TSADC_CPU4 AL46
K8
CN66
6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 2 6.3V
X5R
1
10 2 PP0V7_VDD_LOW_FLPPLL_R CE33 F46 VDD18_USB: 1.8V @ 20mA MAX VDDQL_DDR2 VDD1_DDR1 01005-1 01005-1 01005-1 01005-1
VDD_LOW_FLPPLL VDD18_TSADC_GPU0 N1
5%
VDD18_XTAL: 1.8V @ 1mA MAX VDDQL_DDR2 ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
1/32W
MF
1 C1905 PP1V8_IO 16 50
W8 VDDQL_DDR2 VDD1_DDR2 AT1
01005 0.47UF VDD18_AMUX BW4 VDD1_DDR2 C2
ROOM=SOC_FILT
20%
2 6.3V VDD18_USB CJ49 FL1950 AD67 VDDQL_DDR3
X5R 240OHM-25%-0.2A-0.9OHM
01005-1 AH67 AT67
R1910 ROOM=SOC_FILT
VDD18_XTAL CJ17 PP1V8_XTAL 2 1
AM67
C66
1
100 2 PP0V7_VDD_LOW_ULPPLL_R CE31 01005
VDD_LOW_ULPPLL
5%
1 C1945 1 C1950 ROOM=SOC_FILT 1 C1946 D67 VDDQL_DDR3
1/32W
MF
1 C1910 0.1UF
20%
0.1UF
20%
4UF
20%
G67 VDDQL_DDR3
01005 4UF 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 2 4V
X5R
K60 VDDQL_DDR3
ROOM=SOC_FILT
20%
2 4V 01005 01005 0201
ROOM=SOC_FILT L67 VDDQL_DDR3
X5R ROOM=SOC_FILT ROOM=SOC_FILT
0201 W60
R1920 ROOM=SOC_FILT VDDQL_DDR3
1
0.00 2 PP_VDD_LOW_USB_DEBUG CG46 VDDIO18_AOP: 1.8 @ 20mA MAX A64
VDD_LOW_USB_DEBUG CG29 PP1V8_S2 VDDQL_SENSE
VDDIO18_AOP 16 29 46 49 50 54
0%
1/32W
MF
1 C1920 VDDIO18_AOP CG33
1 C1960 1 C1961
01005 0.1UF VDDIO18_AOP CG37
ROOM=SOC_FILT
20% 4UF 0.1UF ANALOG_VDDQL_SENSEP OUT 5
6.3V
2 X5R-CERM VDDIO18_AOP CG39 20% 20%
2 4V 6.3V
2 X5R-CERM
01005 VDDIO18_AOP CG41 X5R
ROOM=SOC_FILT
0201
ROOM=SOC_FILT
01005 VDD18_MIPIC:1.8 @ 2mA MAX
ROOM=SOC_FILT
AA22 VDD_AVE VDD18_MIPID:1.8 @ 20mA MAX
50 PP_AVE_S1 AC25 VDD_AVE F58 PP1V8_IO
VDD18_MIPIC
B 1 C1927 1 C1926 1 C1925 K12 VDD_AVE
50
B
15UF
20%
15UF
20%
15UF
20%
K16 VDD_AVE 1 C1965 1 C1966
2 6.3V 2 6.3V 6.3V
2 X5R-CERM K25 VDD_AVE 0.1UF 2.2UF
X5R-CERM X5R-CERM VDD18_MIPID CG58 20% 20%
0402-0.1MM 0402-0.1MM 0402-0.1MM M14 VDD_AVE 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM
OMIT_TABLE OMIT_TABLE OMIT_TABLE R25 VDD_AVE 01005 0201
ROOM=SOC_FILT
ROOM=SOC_FILT
U14 VDD_AVE
VDD18_EFUSE1 AC60
W16 VDD_AVE
VDD18_EFUSE2 CA25
W25 VDD_AVE
VDDIO18_GPR*: 1.8V @ 75mA MAX
VDD_AVE: 0.59V - 0.801V @ 3.2A MAX VDDIO18_MTR: 1.8V @ 28mA MAX
AL8 PP1V8_IO
VDD_DISP: 0.56V - 0.718V @ 1.5A MAX VDDIO18_GRP1 50
VDDIO18_GRP1 AR8
50 PP_DISP_S1 AA14 VDD_DISP
VDDIO18_GRP1 AY8
1 C1970 1 C1971 1 C1972 1 C1973
AC16 VDD_DISP 26UF 4UF 4UF 4UF
1 C1931 1 C1930 AE10 VDD_DISP
20%
2 4V
20%
2 4V
20%
2 4V 2 4V
20%
15UF 15UF X5R X5R X5R X5R
20% 20% AE14 VDD_DISP 0402-0.1MM 0201
ROOM=SOC_FILT
0201
ROOM=SOC_FILT
0201
ROOM=SOC_FILT
6.3V
2 X5R-CERM 6.3V
2 X5R-CERM VDDIO18_GRP3 AG60 ROOM=SOC_FILT
AG16 VDD_DISP OMIT_TABLE
0402-0.1MM 0402-0.1MM VDDIO18_GRP3 AL60
ROOM=SOC_FILT ROOM=SOC_FILT AJ10 VDD_DISP
VDDIO18_GRP3 AN60
AJ14 VDD_DISP
VDDIO18_GRP3 AY60
AL16 VDD_DISP
VDDIO18_GRP3 BH60
VDDIO18_GRP4 F39
VDD33_USB*: 3.3V @ 15mA MAX F43
CK47 VDDIO18_GRP4
50 PP3V3_USB VDD33_USB
BK8
R1940 VDDIO18_MTR
R1975
PP3V3_USB_DEBUG 1
0.00 2
VDDIO18_ULPLL: 1.8V @ 0.03mA MAX
21
CE29 PP1V8_ULPPLL_R 1
100 2 PP1V8_S2 16
VDD18_ULPPLL
A 0%
1/32W 5%
29 46 49 50 54
A
MF
01005
1 C1975 1/32W
MF
13 PP3V3_USB_DEBUG_FILT ROOM=SOC_FILT CJ47 VDD33_USB_DEBUG 4UF 01005
20% ROOM=SOC_FILT
2 4V
1 C1935 1 C1940 X5R
0201
ROOM=SOC_FILT
0.1UF
20%
0.1UF
20%
ROOM=SOC_FILT R1976 VDDIO18_FMON: 1.8V @ 0.1mA MAX
6.3V 6.3V BV25 PP1V8_FMON_R 1
49.9 2 PP1V8_IO 16
2 X5R-CERM 2 X5R-CERM VDD18_FMON 50
01005 01005 1%
ROOM=SOC_FILT ROOM=SOC_FILT 1 C1976 1/32W
MF
2.2UF 01005
20%
6.3V
2 X5R-CERM
0201
ROOM=SOC_FILT
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
339S00623 339S00623 339S00623
U1000 U1000 U1000
SOC: GND CEBU-4GB-18NM-H
CSP
SYM 19 OF 21
CEBU-4GB-18NM-H
CSP
SYM 20 OF 21
CEBU-4GB-18NM-H
CSP
SYM 21 OF 21
TMKF89B0-C5 TMKF89B0-C5 TMKF89B0-C5
A11 VSS VSS AL54 BH14 VSS VSS CA29 CM67 VSS VSS F10
A15 VSS VSS AL58 BH18 VSS VSS CA33 CM9 VSS VSS F14
A19 VSS VSS AM1 BH22 VSS VSS CA37 CN1 VSS VSS F18
A2 VSS VSS AM3 BH29 VSS VSS CA41 CN13 VSS VSS F22
A23 VSS VSS AN12 BH33 VSS VSS CA46 CN17 VSS VSS F29
A26 VSS VSS AN16 BH37 VSS VSS CA56 CN21 VSS VSS F33
A3 VSS VSS AN20 BH41 VSS VSS CB1 CN23 VSS VSS F50
D A30 VSS VSS AN25 BH58 VSS VSS CB4 CN24 VSS VSS F54 D
A34 VSS VSS AN27 BJ1 VSS VSS CB67 CN26 VSS VSS G1
A36 VSS VSS AN31 BJ3 VSS VSS CC20 CN28 VSS VSS G65
A38 VSS VSS AN35 BK12 VSS VSS CC25 CN3 VSS VSS H12
A65 VSS VSS AP67 BK35 VSS VSS CC48 CN4 VSS VSS H39
A66 VSS VSS AR10 BK39 VSS VSS CC52 CN40 VSS VSS H43
A7 VSS VSS AR14 BK43 VSS VSS CC60 CN42 VSS VSS H48
AA16 VSS VSS AR18 BK48 VSS VSS CD2 CN44 VSS VSS H52
AA20 VSS VSS AR22 BK56 VSS VSS CD65 CN45 VSS VSS H56
AA25 VSS VSS AR29 BL67 VSS VSS CE10 CN47 VSS VSS H60
AA27 VSS VSS AR33 BM10 VSS VSS CE14 CN49 VSS VSS H8
AA31 VSS VSS AR37 BM14 VSS VSS CE22 CN51 VSS VSS J3
AA35 VSS VSS AR46 BM18 VSS VSS CE37 CN53 VSS VSS J67
AA39 VSS VSS AR50 BM22 VSS VSS CE41 CN55 VSS VSS K14
AA52 VSS VSS AT65 BM37 VSS VSS CE54 CN6 VSS VSS K29
AA56 VSS VSS AU1 BM41 VSS VSS CE58 CN61 VSS VSS K33
AA60 VSS VSS AU3 BM46 VSS VSS CF1 CN62 VSS VSS K37
AA8 VSS VSS AU67 BM50 VSS VSS CF4 CN63 VSS VSS K41
AB64 VSS VSS AV12 BM54 VSS VSS CG12 CN64 VSS VSS K46
AC14 VSS VSS AV16 BM58 VSS VSS CG16 CN65 VSS VSS K50
C AC18 VSS VSS AV20 BN1 VSS VSS CG20 CN67 VSS VSS K54 C
AC22 VSS VSS AV25 BN65 VSS VSS CG27 CN9 VSS VSS K58
AC29 VSS VSS AV27 BP12 VSS VSS CG31 CP1 VSS VSS L1
AC33 VSS VSS AV31 BP16 VSS VSS CG35 CP11 VSS VSS M25
AC37 VSS VSS AV35 BP20 VSS VSS CG43 CP15 VSS VSS M27
AC41 VSS VSS AV60 BP27 VSS VSS CH2 CP19 VSS VSS M31
AC46 VSS VSS AV8 BP31 VSS VSS CH3 CP2 VSS VSS M35
AC50 VSS VSS AW1 BP35 VSS VSS CH4 CP23 VSS VSS M48
AC54 VSS VSS AW67 BP43 VSS VSS CH64 CP3 VSS VSS M52
AD1 VSS VSS AY10 BP48 VSS VSS CH65 CP34 VSS VSS N65
AD65 VSS VSS AY14 BP52 VSS VSS CH66 CP40 VSS VSS N67
AE12 VSS VSS AY22 BP56 VSS VSS CH67 CP45 VSS VSS P3
AE16 VSS VSS AY29 BP8 VSS VSS CJ1 CP5 VSS VSS R14
AE20 VSS VSS AY37 BR3 VSS VSS CJ13 CP57 VSS VSS R29
AE35 VSS VSS B1 BT14 VSS VSS CJ5 CP67 VSS VSS R50
AE39 VSS VSS B19 BT18 VSS VSS CJ53 CP7 VSS VSS R54
AE43 VSS VSS B2 BT22 VSS VSS CJ63 CR11 VSS VSS T1
AE48 VSS VSS B3 BT29 VSS VSS CJ66 CR15 VSS VSS T67
AE52 VSS VSS B34 BT33 VSS VSS CK11 CR19 VSS VSS U25
AF3 VSS VSS B4 BT46 VSS VSS CK19 CR3 VSS VSS U35
AF67 VSS VSS B42 BV12 VSS VSS CK2 CR34 VSS VSS U48
AG10 VSS VSS B45 BV16 VSS VSS CK21 CR40 VSS VSS U52
B AG14 VSS VSS B5 BV20 VSS VSS CK26 CR45 VSS VSS U56 B
AG18 VSS VSS B51 BV27 VSS VSS CK32 CR5 VSS VSS V65
AG22 VSS VSS B53 BV31 VSS VSS CK38 CR57 VSS VSS W10
AG41 VSS VSS B64 BW1 VSS VSS CK5 D1 VSS VSS W29
AG54 VSS VSS B67 BY2 VSS VSS CK61 D2 VSS VSS W41
AG58 VSS VSS BA1 BY3 VSS VSS CK63 D23 VSS VSS W46
AH1 VSS VSS BA65 BY4 VSS VSS CK64 D26 VSS VSS W50
AH4 VSS VSS BA67 C1 VSS VSS CK65 D30 VSS VSS W54
AJ12 VSS VSS BB12 C13 VSS VSS CK66 D36 VSS VSS Y1
AJ16 VSS VSS BB16 C17 VSS VSS CK67 D38 VSS VSS Y3
AJ20 VSS VSS BB20 C21 VSS VSS CL1 D42 VSS VSS Y67
AJ25 VSS VSS BB25 C24 VSS VSS CL11 D45 VSS
VSS_1 CR1
AJ31 VSS VSS BB39 C32 VSS VSS CL17 D5 VSS <-- Corner Ball Test Pins. System connects to GND.
VSS_2 CR67
VSS_3 A1
AJ39 VSS VSS BC3 C38 VSS VSS CL2 D53 VSS
VSS_4 A67
AJ43 VSS VSS BD18 C5 VSS VSS CL21 D57 VSS
VSS_DDR_SENSE A63 ANALOG_VDDQL_DCS_SENSEN 5
OUT
AJ56 VSS VSS BD37 C55 VSS VSS CL5 D7 VSS VSS_GPU_SENSE AE29 ANALOG_GPU_SENSEN 5
OUT
AJ60 VSS VSS BD41 C57 VSS VSS CL6 E4 VSS
A AJ8 VSS VSS BD58 C59 VSS VSS CL65 E66 VSS
VSS_PCPU_SENSE BP39 ANALOG_CPU_PCORE_SENSEN OUT 5
A
AK65 VSS VSS BE1 C6 VSS VSS CL66 E67 VSS VSS_SENSE AY18 ANALOG_SOC_SENSE_N 5
OUT
AK67 VSS VSS BE4 C61 VSS VSS CL7
AL10 VSS VSS BF16 C62 VSS VSS CL9
AL14 VSS VSS BF20 C63 VSS VSS CM13
AL37 VSS VSS BG65 CA14 VSS VSS CM4
AL41 VSS VSS BG67 CA18 VSS VSS CM6
AL50 VSS VSS BH10 CA22 VSS VSS CM66
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FUTURE COMPATABILITY: R2602 50mohm Max

S4E NAND
Default R2602: NO STUFF
196mA MAX R2602

PP1V2_IO_NAND 1
0 2 18 PP_VDDIO_2_NAND_R
19
D
5%
1/20W
MF
1 C2630 1 C2629 1 C2643 1 C2645 1 C2647 1 C2612 1 C2618 1 C2614 1 C2615 1 C2617 D
0201 15UF 15UF 2.2UF 2.2UF 2.2UF 220PF 100PF 68PF 47PF
ROOM=NAND
20% 20% 20% 20% 20% 5% 5% 5% 5% 22PF
2 6.3V
X5R-CERM
6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 25V
2 COG 16V
2 NP0-C0G 2 16V
NP0-C0G
16V
2 NP0-C0G 2%
NOSTUFF 0402-0.1MM 0402-0.1MM 0201 0201 0201 01005 01005-1 01005 01005 2 16V
C0G
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND 01005 1150mA MAX (1us peak power)
ROOM=NAND
PP2V63_NAND 21
2
R2603 1 C2613 1 C2616 1 C2619 1 C2621
0 15UF 15UF 15UF 15UF
5% 20% 20% 20% 20%
1/20W 6.3V
2 X5R-CERM 2 6.3V 2 6.3V 2 6.3V
1
MF X5R-CERM X5R-CERM X5R-CERM
0201 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM
267mA MAX S4E (8 dies) ROOM=NAND
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
50mA MAX S4E COMPATABILITY MODE
50
PP1V8_IO
1 C2641 1 C2624 1 C2626 1 C2610 1 C2611
20%
2.2UF
20%
2.2UF 2.2UF
20%
0.1UF
20% 5%
220PF 1 C2649 1 C2650 1 C2651 1 C2652
6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 2 25V
COG
2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20%
0201 0201 0201
ROOM=NAND
01005
ROOM=NAND
01005 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM
ROOM=NAND ROOM=NAND ROOM=NAND
0201
ROOM=NAND
0201
ROOM=NAND
0201
ROOM=NAND
0201
ROOM=NAND
700mA
578mA
MAX S4E
MAX S4E COMPATABILITY MODE
1 C2638 1 C2639 1 C2634 1 C2635 1 C2636 1 C2637
100PF
19 18
PP0V9_NAND 5%
16V
68PF 47PF 22PF 220PF 100PF
FUTURE COMPATABILITY 2 NP0-C0G 5% 5% 2% 5% 5%
16V
2 NP0-C0G 16V
2 NP0-C0G 2 16V 25V
2 COG 16V
2 NP0-C0G
1 C2602 1 C2605 1 C2600 1 C2601 R2625 -> Ferrite Bead (APN: 155S00340) 01005-1
01005 01005
C0G
01005 01005 01005-1
20%
26UF
20%
26UF
20%
2.2UF
20%
2.2UF R2625 ROOM=NAND
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
4V 4V 6.3V 6.3V PP1V8_IO_NAND_F 1
0.00 2
2 X5R 2 X5R 2 X5R-CERM 2 X5R-CERM
0402-0.1MM 0402-0.1MM 0201 0201 0%
C ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
C2625
4UF
1
1/32W
MF C
01005
20% ROOM=NAND
4V
X5R 2
0201
ROOM=NAND
1 C2622 1 C2627 1 C2640 1 C2642 1 C2644 1 C2646 FUTURE COMPATABILITY:

FUTURE COMPATABILITY
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF R2623 -> Ferrite Bead (APN: 155S00340)
20% 20% 20% 20% 20% 20% R2663 -> 2 Ohm
6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM
0201 0201 0201 0201 0201 0201 R2663 R2623
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
PP1V8_IO_NAND_R 1
0.00 2 PP0V9_NAND_F 1
0.00 2 PP0V9_NAND 18 19
0% 0%
1 C2663 1/32W
MF
1/32W
MF
1 C2623
01005 01005 2.2UF
1 C2603 1 C2606 1 C2609 1 C2607 1 C2608 1 C2604 20%
2.2UF ROOM=NAND ROOM=NAND
20%
6.3V
2 X5R-CERM
220PF 220PF 100PF 68PF 47PF 22PF 6.3V
2 X5R-CERM 0201
5% 5% 5% 5% 5% 2%
2 25V
COG 2 25V
COG
16V
2 NP0-C0G 16V
2 NP0-C0G 16V
2 NP0-C0G 2 16V
C0G
0201
ROOM=NAND
ROOM=NAND
01005 01005 01005-1 01005 01005 01005

ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
NC
NC
NC
G12
E10
E12
L12
M9
G6
G8
G4
N6
N8
R6
R8
N2
D3
R2
R4
K9
E2
P9
T5
F3
L2
L6
L8
J6
J8
J4
J2
PCI_AVDD_CLK_1
PCI_VDD_1
PCI_AVDD_CLK_2
PCI_AVDD_H
PCI_VDD_2
AVDD18_PLL
ANI0_VREF
ANI1_VREF
VDD_PLL
VPP
VDD
VDDIO_1/GPIO
VDDIO_2/NAND
VCC
B B
ROOM=NAND
7
CLK_AP_TO_NAND_24M M3 CLK_IN
U2600 EXT_D0/BOOT0 B3 GPIO_PMU_TO_NAND_LOW_BATT_BOOT_L 56
IN IN
NAND-S4E-S5E-MCP-STUDY C4 IO_AP_TO_NAND_FW_STRAP
90_PCIE0_AP_TO_NAND_REFCLK_P K11 LGA EXT_D1/BOOT1 IN 7
8 5 IN GND_VOID PCIE_REFCLK_P B5 SPI0_AP_TO_S4E_SCLK_BOOT_CONFIG0
90_PCIE0_AP_TO_NAND_REFCLK_N EXT_D2/BOOT2/SPINAND_SCLK 6 11
GND_VOID J12
IN
8 5 IN PCIE_REFCLK_M OMIT_TABLE C6 SPI0_AP_FROM_S4E_MISO_BOOT_CONFIG2
EXT_D3/SWD_UID0/SPINAND_MISO OUT 5 6 11
Default C2620: No Stuff 8

PCIE0_AP_BI_NAND_CLKREQ_L P5 PCIE_CLKREQ_N EXT_D4/UART_RX B7
BI NC
EXT_D5/SWD_UID1/SPINAND_MOSI C8 SPI0_AP_TO_S4E_MOSI_BOOT_CONFIG1 6 11
ANALOG_PCIE_NAND_RESREF H7 PCI_RESREF
IN
FUTURE COMPATABILITY: EXT_D6/UART_TX B9
NC
R2604 -> 200 Ohm 1
R2604 8 IN
90_PCIE0_AP_TO_NAND_TX_P GND_VOID M11 PCIE_RX0_P EXT_D7/SPF B11 IO_PMU_TO_MANY_SYSTEM_ALIVE IN 22
1
C2620 -> 10pF C2620 3.01K 8 IN
90_PCIE0_AP_TO_NAND_TX_N GND_VOID N12 PCIE_RX0_M E8 PCIE0_AP_TO_NAND_PERST_L
10PF 1% EXT_NCE/PERST* IN 8
5% 1/32W
2 16V MF D7 SWD_AP_BI_NAND_SWDIO
NP0/C0G 01005
2 ROOM=NAND EXT_NRE/JTAG_TMS BI 5 7
01005
ROOM=NAND
NOSTUFF EXT_NWE/JTAG_TCK E6 SWD_NUB_TO_MANY_SWCLK
8 OUT
90_PCIE0_AP_FROM_NAND_RX_P GND_VOID R12 PCIE_TX0_P
IN 13 22 38 58
8 OUT
90_PCIE0_AP_FROM_NAND_RX_N GND_VOID T11 PCIE_TX0_M EXT_RNB/JTAG_TDO E4
EXT_CLE/JTAG_TDI D5
NC
EXT_ALE/JTAG_SEL D9
DROOP_N T3
7 5
IO_AP_TO_NAND_RESET_L L4 RESET*
IN
WP_N G2 PP_VDDIO_2_NAND_R 18
G10 TRST*
Board trace <= 0.2Ohm FUTURE COMPATABILITY
A ANALOG_NAND_ZQ_C
ANALOG_NAND_ZQ_NEG
K3
C10
ZQ_C
A
ZQ_N
1 1
R2600 R2601
100 300
0.1% 0.1%
VSS
1/32W 1/32
MF MF
01005
2ROOM=NAND 01005
2ROOM=NAND
A2
A4
A6
A8
A10
A12
B1
B13
C2
C12
D1
D11
D13
F1
F5
F7
F9
F11
F13
H1
H3
H5
H9
H11
H13
J10
K1
K5
K7
K13
L10
M1
M5
M7
M13
N4
N10
P1
P3
P7
P11
P13
R10
T1
T7
T9
T13
U2
U4
U6
U8
U10
U12
FUTURE COMPATABILITY: R2600 -> 300 Ohm
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BUCK0-9/SWITCHES
343S00333
U2700
TMLF49B0-CPZ
L2740 WLCSP L2700 0.4V - 1.15V
1.0UH-20%-1.55A-0.063OHM SYM 2 OF 5
1UH-20%-3.6A-0.062OHM
50
PP1V1_S2 1 2 LX0_BUCK4 A4 BUCK4_LX0 BUCK0_LX0 F18 LX0_BUCK0 1 2 PP_CPU_PCORE 5 50
mm mm
PIJD2012-SM PIWE20160H-SM
1 C2744 1 C2743 1 C2742 1 C2741 1 C2740 ROOM=PMU ROOM=PMU 1 C2700 1 C2701 1 C2702
26UF 26UF 26UF 26UF 220PF 220PF 15UF 15UF
20% 20% 20% 20% 5% L2741 5% 20% 20%
4V 4V 4V 4V 25V L2701 25V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 COG 0.22UH-20%-5.8A-0.04OHM 2 COG 2 X5R-CERM 2 X5R-CERM
0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 01005 B17 0.1UH-20%-6.1A-0.019OHM 01005 0402-0.1MM 0402-0.1MM
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 1 2 LX1_BUCK4 A2 BUCK0_LX1 MTFE2016-2SM ROOM=PMU ROOM=PMU ROOM=PMU
B18
mm
1608 B2 BUCK4_LX1
:
ROOM=PMU D
D 1 3
BUCK4
LX1_BUCK0
BUCK4
L
UPPER_COIL_IN UPPER_COIL_OUT
mam
2.7A MAX
V_BUCK4_Default = 1.0625V OMIT
XW2740
SHORT-20L-0.05MM-SM
D17 LX3_BUCK0 2 4
BUCK0_LX3 LOWER_COIL_IN LOWER_COIL_OUT
mam
2 1 ANALOG_FB_BUCK4 D4 BUCK4_FB D18
:
ROOM=PMU
yy
ROOM=PMU C4 BUCK4_VSS_FB
NO_XNET_CONNECTION
BUCK0
L2702
H17 0.1UH-20%-6.1A-0.019OHM
BUCK0
BUCK0_LX2 MTFE2016-2SM
15.2A MAX
H18
:
LX2_BUCK0 1 3
L
mm
L2750
1.0UH-20%-1.55A-0.063OHM K17 LX4_BUCK0 2 4
LOWER_COIL_IN LOWER_COIL_OUT
mam
PP_AVE_S1 1 2 Y9 BUCK0_LX4 K18
50 LX0_BUCK5 BUCK5_LX0
:
ROOM=PMU
um
PIJD2012-SM
1 C2753 1 C2752 1 C2751 1 C2750 ROOM=PMU
15UF 26UF 26UF 220PF
20% 20% 20% 5% L2751 R2700
6.3V 4V 4V 25V XW2700
2 X5R-CERM 2 X5R 2 X5R 2 COG 0.22UH-20%-5.8A-0.04OHM 0.00 SHORT-10L-0.05MM-SM
0402-0.1MM 0402-0.1MM 0402-0.1MM 01005 BUCK0_FB H15 ANALOG_FB_BUCK0 1 2 ANALOG_FB_BUCK0_R 1 2
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 1 2 W11
A/W
LX1_BUCK5
yy
ROOM=SOC
OMIT_TABLE OMIT_TABLE OMIT_TABLE BUCK5_LX1 0% MF
um
1608 Y11 1/32W NO_XNET_CONNECTION
ROOM=PMU
01005
BUCK5
ROOM=SOC
NO_XNET_CONNECTION
3.2A MAX
OMIT J16
BUCK5
BUCK0_VSS_FB
XW2750
SHORT-10L-0.05MM-SM
2 1 ANALOG_FB_BUCK5 U9 BUCK5_FB
C 0.4V - 1.06V C
yy
ROOM=SOC V9 BUCK5_VSS_FB
L2710 1.03V for overdrive only
NO_XNET_CONNECTION
1UH-20%-3.6A-0.062OHM
BUCK1_LX0 Y13 LX0_BUCK1 1 2 PP_GPU 5 50
um
PIWE20160H-SM
ROOM=PMU 1 C2710 1 C2711 1 C2712
220PF 26UF 26UF
5% 20% 20%
L2711 25V
2 COG 4V
2 X5R 4V
2 X5R
W17 0.1UH-20%-6.1A-0.019OHM 01005 0402-0.1MM 0402-0.1MM
BUCK1_LX1 MTFE2016-2SM ROOM=PMU ROOM=PMU ROOM=PMU
Y17
OMIT_TABLE OMIT_TABLE
:
L2760
0.47UH-3.7A-0.034OHM LX1_BUCK1 1 3
1
mam
38 21
PP1V2_S4 1 2 LX0_BUCK6 Y7 BUCK6_LX
maa
PIJD16140H-SM
BUCK1
1 C2762 1 C2761 1 C2763 1 C2760 ROOM=PMU W15 LX2_BUCK1 2 4
BUCK1_LX2 LOWER_COIL_IN LOWER_COIL_OUT
mam
26UF 26UF 15UF 220PF OMIT Y15
20% 20% 20% 5%
:
ROOM=PMU
BUCK1
10A MAX
4V
2 X5R 4V
2 X5R 6.3V
2 X5R-CERM 25V
2 COG XW2760
SHORT-20L-0.05MM-SM
0402-0.1MM 0402-0.1MM 0402-0.1MM 01005 OMIT
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 2 yy 1 ANALOG_FB_BUCK6 V7 BUCK6_FB
BUCK6
ROOM=PMU W7 BUCK6_VSS_FB
XW2710
SHORT-20L-0.05MM-SM
1.5A MAX
NO_XNET_CONNECTION U13
BUCK1_FB ANALOG_FB_BUCK1 1 2
V_BUCK6_Default = 1.240625V ROOM=SOC
yy
BUCK6
NO_XNET_CONNECTION
BUCK1_VSS_FB V13
0.735V - 1.01V L2770 L2720
0.47UH-20%-4.0A-0.05OHM 1UH-20%-2.2A-0.06OHM 0.67V/0.80V
B 50
PP_SRAM_S1 1
mua 2 LX0_BUCK7 A14 BUCK2_LX0 A8 LX0_BUCK2 1 2 PP_SOC_S1 50
B
BUCK7_LX
am
PIJD2012-SM B14 PIJR20120H-SM
1 C2772 1 C2771 ROOM=PMU ROOM=PMU 1 C2723
1 C2770 1 C2720 1 C2721 1 C2722
15UF 26UF L2721 15UF
20% 20% 220PF 220PF 26UF 26UF 20%
6.3V 4V 5% OMIT 0.22UH-20%-5.8A-0.04OHM 5% 20% 20% 6.3V
BUCK7
2 X5R-CERM 2 X5R 25V 25V 2 X5R-CERM
2.2A MAX
0402-0.1MM 0402-0.1MM 2 COG A6 1 2 2 COG 2 4V
X5R 2 4V
X5R 0402-0.1MM
LX1_BUCK2
UOJ2/
ROOM=PMU ROOM=PMU 01005 XW2770 01005 0402-0.1MM 0402-0.1MM ROOM=PMU
ROOM=PMU SHORT-20L-0.05MM-SM BUCK2_LX1 B6 1608 ROOM=PMU ROOM=PMU ROOM=PMU
BUCK2
2 yy 1 ANALOG_FB_BUCK7 D14 BUCK7_FB ROOM=PMU OMIT_TABLE OMIT_TABLE OMIT_TABLE
ROOM=PMU C14 BUCK7_VSS_FB
BUCK2
4.9A MAX
NO_XNET_CONNECTION OMIT
BUCK7
XW2720
SHORT-20L-0.05MM-SM
BUCK2_FB D8 ANALOG_FB_BUCK2 1 yy 2
ROOM=SOC
C8 NO_XNET_CONNECTION
BUCK2_VSS_FB
L2730
1UH-20%-3.6A-0.062OHM
V3 LX0_BUCK3 1 2ROOM=PMU PP1V8_S4 21 38 58
lam
0.675V - 1.06V L2780
0.47UH-2.9A-0.072OHM W3 PIWE20160H-SM
BUCK3_LX
50
PP_DISP_S1 1 2 LX0_BUCK8 T18 BUCK8_LX Y3 XW2730 1 C2730 1 C2731 1 C2732 1 C2733 1 C2734
moa
PIJD1608FE-SM SHORT-20L-0.05MM-SM 220PF 15UF 26UF 26UF 15UF
2A MAX
BUCK3
1 C2781 1 C2782 1 C2780 ROOM=PMU BUCK3_FB W1 ANALOG_FB_BUCK3 1 2 5% 20% 20% 20% 20%
25V 4V 4V
BUCK3
2 6.3V 2 6.3V
yy
26UF 15UF 220PF OMIT 2 COG X5R-CERM 2 X5R 2 X5R X5R-CERM
20% 20% 5% OMIT V1 ROOM=PMU 01005 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM
BUCK3_VSS_FB NO_XNET_CONNECTION
BUCK8
4V 6.3V 25V ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
1.5A MAX
2 X5R 2 X5R-CERM 2 COG XW2780 OMIT_TABLE OMIT_TABLE
0402-0.1MM 0402-0.1MM 01005 SHORT-10L-0.05MM-SM
2 1 T16
BUCK8
ROOM=PMU ROOM=PMU ROOM=PMU ANALOG_FB_BUCK8 BUCK8_FB R3 PP1V8_S2 38 49 50
yy
ROOM=SOC T17 BUCK8_VSS_FB BUCK_SWI0
NO_XNET_CONNECTION R4 BUCK3_SW0
)
M2 PP1V8_IO 33 40 41 43 45 50 52 55
A L2790 BUCK_SWI1
: M3 BUCK3_SW1
A
0.600V - 0.875V 0.47UH-2.9A-0.072OHM
BUCK
BUCK_SWI2 R5 BUCK3_SW2 PP1V8_TOUCH_S2 48 53
50
PP_DCS_S1 1 2 LX0_BUCK9 A10
SWITCHES
BUCK9_LX
PIJD1608FE-SM M1 BUCK3_SW3
mm-
1 1 1 ROOM=PMU BUCK_SWI3 PP1V8_NFC_S2 38
C2791 C2792 C2790
26UF 26UF 220PF OMIT R1 PP1V2_IO_NAND 18
20% 20% 5% BUCK_SWI4
BUCK9
4V 4V 25V R2 BUCK6_SW0
)
2 X5R 2 X5R 2 COG XW2790
0402-0.1MM 0402-0.1MM 01005 SHORT-10L-0.05MM-SM
BUCK9
ROOM=PMU ROOM=PMU ROOM=PMU 2 1 ANALOG_FB_BUCK9 C10 BUCK9_FB M4 PP0V9_NAND 18
BUCK_SWI5
yy
1.3A MAX
B10 M5 BUCK12_SW0
)
ROOM=PMU BUCK9_VSS_FB
NO_XNET_CONNECTION
ROOM=PMU
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BUCK10-12/BUCK-ANALOG-DIGITAL VDD
343S00333
U2700
TMLF49B0-CPZ
WLCSP L2800
SYM 3 OF 5
0.47UH-2.9A-0.072OHM
50 39 38 33 21 20 3 PP_VDD_MAIN C17 BUCK10_LX Y5 LX0_BUCK10 1jsrm 2 PP0V6_VDDQL_S1 50
C18 PIJD1608FE-SM
1 C2852 1 C2851 1 C2850 1 C2855 1 C2854 1 C2853 G17
ROOM=PMU 1 C2800 1 C2802 1 C2801
220PF 26UF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF G18 5% 20% 15UF
20% 20% 20% 20% 20% 20%
L17 2 25V 4V
2 X5R 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM VDD_BUCK0_8_11 COG
01005 0402-0.1MM 2 6.3V
X5R-CERM
0201 0201 0201 0201 0201 0201 L18 ROOM=PMU ROOM=PMU
0402-0.1MM
D
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
R17 ROOM=PMU
OMIT_TABLE
D
R18
OMIT
XW2800
1.3A MAX
BUCK10
SHORT-20L-0.05MM-SM
C2858 C2857 C2856
1
2.2UF
20%
1
2.2UF
20%
1
2.2UF
20%
1 C2862
2.2UF
1 C2861
2.2UF
1 C2860
2.2UF
W8
BUCK10_FB V5 ANALOG_FB_BUCK10 2
- -
6T> 1
ROOM=PMU
NO_XNET_CONNECTION
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
20% 20% 20%
2 6.3V 2 6.3V 2 6.3V W12
BUCK10
0201 0201 0201 X5R-CERM X5R-CERM X5R-CERM
ROOM=PMU ROOM=PMU ROOM=PMU 0201 0201 0201
ROOM=PMU ROOM=PMU ROOM=PMU W16
Y8 VDD_BUCK1_5_6
Y12
1 C2867
2.2UF
20%
1 C2866
2.2UF
20% T
1 C2865
2.2UF
1 C2864
2.2UF
1 C2863
2.2UF
Y16
BUCK VDD
W5
2 6.3V
X5R-CERM
0201
ROOM=PMU
2 6.3V
X5R-CERM
0201
ROOM=PMU
T 20%
2 6.3V
X5R-CERM
0201
ROOM=PMU
20%
2 6.3V
X5R-CERM
0201
ROOM=PMU
20%
2 6.3V
X5R-CERM
0201
ROOM=PMU A1
A5
BUCK10_VSS_FB
A9
B1 VDD_BUCK2_4_9
B5
B9
L2810 0.415V - 1.06V
1UH-20%-2.2A-0.06OHM
BUCK11_LX0 M18 LX0_BUCK11 1 i?rrn.
PIJR20120H-SM
2 PP_CPU_ECORE 50
V4
ROOM=PMU 1 C2810 1 C2811 1 C2812 1 C2813
C W4
VDD_BUCK3_10
5%
220PF
20%
15UF 26UF
20% 20%
15UF C
Y4 2 25V
COG
6.3V
2 X5R-CERM 4V
2 X5R 2 6.3V
X5R-CERM
01005 0402-0.1MM 0402-0.1MM 0402-0.1MM
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
L2811
A13 0.22UH-20%-5.8A-0.04OHM
B13 VDD_BUCK12_7
BUCK11_LX1 (
P17
P18
LX1_BUCK11 1 ioTTT\
1608
2
3.6A MAX
BUCK11
ROOM=PMU
21 PP1V5_VLDOINT C1
C5
1 C2872 C9
220PF C13
BUCK11
5% OMIT
2 25V C16
COG
01005 E6 XW2810
SHORT-20L-0.05MM-SM
ROOM=PMU F6 M15
F7
BUCK11_FB ANALOG_FB_BUCK11 1
61> 2
ROOM=SOC
NO_XNET_CONNECTION
F17
G16
K6 VDD_ANA
L16
R16
ANALOG VDD
U2
B U4 B
V8
V12 BUCK11_VSS_FB M16
V16
W13
K11
50 39 38 33 21 20 3 PP_VDD_MAIN F9 VDD_MAIN L2820

0.47UH-2.9A-0.072OHM
1 C2830
0.47UF
BUCK12_LX A12 LX0_BUCK12 1izcm
PIJD1608FE-SM
2 PP0V9_S1 21
20%
6.3V ROOM=PMU 1 C2820 1 C2823 1 C2822 1 C2821
1.5A MAX
BUCK12
2 X5R 220PF 15UF
01005-1 5% 20% 4UF 26UF
20% 20%
ROOM=PMU 2 25V
COG
6.3V
2 X5R-CERM 4V
2 X5R 4V
2 X5R
01005 0402-0.1MM 0201 0402-0.1MM
OMIT_TABLE
D6 OMIT
E15 XW2820
SHORT-20L-0.05MM-SM
C12
T6 VDD_DIG
<57>
BUCK12
BUCK12_FB ANALOG_FB_BUCK12 2 1
T11 ROOM=PMU
NO_XNET_CONNECTION
DIGITAL VDD
A A
50 PP1V2_S2 N6 VDDIO1V2
BUCK12_VSS_FB B12
ROOM=PMU
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
50 39 38 33 20 3
PP_VDD_MAIN
OMIT
XW2990 1 C2990 1 C2991 1 C2992 1 C2993
SHORT-20L-0.05MM-SM 15UF 15UF 15UF 15UF
22 OUT
VDD_MAIN_SNS 2 1 20%
6.3V
20%
6.3V
20% 20%
2 X5R-CERM 2 X5R-CERM 2 6.3V 6.3V
2 X5R-CERM
D
ROOM=PMU
NO_XNET_CONNECTION
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
X5R-CERM
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
PMU - LDOs D
50 27 23 21 PP_VDD_BOOST
1 C2970 1 C2971
2.2UF 2.2UF
20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201 0201
ROOM=CAM_PMU ROOM=CAM_PMU
VSS
LDOS
U2700
TMLF49B0-CPZ U2700
WLCSP TMLF49B0-CPZ
SYM 5 OF 5
B4 A16 WLCSP
343S00333 SYM 1 OF 5
B8 A17 PP_VDD_BOOST F5 VLDO1 G4 PP3V3_USB LDO1 200 MA MAX
C B16 A18
50 27 23 21
G5 Vin:
343S00333
VLDO2 K5 PP1V8_CODEC_VA_S2
50
31 LDO2 50 mA MAX C
C2 E17 H5 LDO1 E1
LDO2 VLDO3 PP1V2_SOC 50 LDO3 400 mA MAX
C3 VSS_BUCK0 E18 J2 LDO5 H2
VDD_BOOST_LDO LDO10 VLDO4 PP0V7_VDD_LOW_S2 50 LDO4 300 MA MAX
C6 J17 J3 LDO13
VDD_BOOST_SNS K2
C7 J18 J4 PP2V63_NAND 18 LDO5 1200 MA MAX
C11
C15
D1
V18
W14
W18
J5
Vin:
VLDO5
VLDO6
3
K3
K4
H1 PP1VX_DISPLAY_VDD 47 LDO6 250 MA MAX

D2 VSS_BUCK1 L4 LDO9
Y14 50 PP_VDD_MAIN VDD_MAIN_LDO LDO_INT L1 PP3V0_S2
D3 VLDO7 50 LDO7 250 MA MAX
Y18
LDO VOUT
LDO VDD
D5 58 38 19 PP1V8_S4 N1 VLDO8 E5 PP1V0_S4 58 LDO8 400 MA MAX
D13 N2
Vin:
XW2996
D15 N3 BUCK3_SW0
SHORT-10L-0.1MM-SM
D16 A7 P3 VDD_B3 BUCK3_SW1 2 1 PP1V0_R1_ANA_S4 58
BUCK3_SW2 NO_XNET_CONNECTION=1
ROOM=PMU
E16 VSS_BUCK2 B7 P4 BUCK3_SW3 OMIT
F3 VLDO9 L5 PP1V8_ALWAYS 49 LDO9 10 MA MAX
P5
V2 VLDO10 H4 PP3V0_DISPLAY LDO10 250 MA MAX
F11 47
W2 PP1V1_S2 G2 Vin: VLDO11 H3 PP1VX_DISPLAY_VDD LDO11 250 MA MAX
F15 VSS_BUCK3
50
VDD_B4 LDO4
47
Y1 G3 LDO11 VLDO12 F1 PP0V8_SOC_FIXED_S1 LDO12 400 MA MAX
F16 50
Y2 VLDO13 F4 PP3V3_USB_DEBUG LDO13 50 MA MAX
G6 1 C2916 PP1V2_S4 P1
VDD_B6
Vin:
BUCK6_SW0 VLDO14 K1 PP1V2_S2
16
LDO14 50 MA MAX
G7 A3 2.2UF P2 38 50
20%
G15 VSS_BUCK4 B3 2 6.3V
X5R-CERM 38
PP1V2_S4 E2 VMBX E8 PP_VMBX_PMU
H6 0201 19
21 Vin: 4.5V
W10 ROOM=PMU E3 VDD_B6_LDO LDO3
H7 PP1V5_VLDOINT
VMAX/INT LDO/
PLACE_NEAR=U2700.G2:3MM
LDO8 VLDOINT L3
VSS_BUCK5 Y10 E4 20
CHG PUMP
H16
J6 W6 PP0V9_S1 N4 Vin: 1 C2919 C2917 C2902 C2904 C2908
E
20
1 1 1 1
B J7 VSS_BUCK6_10 Y6 N5 VDD_B12 BUCK12_SW0 15UF
20% 0.1UF 4UF 4UF 15UF
1 C2912 1 C2980 1 C2914 1 C2982 B
J10
A15 Vin: VCP_OUT P6 PP_VPUMP_PMU 2 6.3V 20% 20% 20% 20% 4UF 4UF 4UF 2.2UF
F2 VDD_B12_LDO LDO12
X5R-CERM 2 6.3V 4V
2 X5R 4V
2 X5R 2 6.3V 20% 20% 20% 20%
J15 5.22V 0402-0.1MM X5R X5R-CERM 4V
2 X5R 4V
2 X5R 4V
2 X5R 2 6.3V
VSS VSS_BUCK7 B15 ROOM=PMU 01005-2 0201 0201 0402-0.1MM X5R-CERM
K7 38 21 19 PP1V2_S4 G1 VDD_LDO6 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 0201 0201 0201 0201
M6 U17 50 27 23 21 PP_VDD_BOOST L2 VDD_LDO7
K15 VSS_BUCK8 U18 38 21 19 PP1V2_S4 J1 VDD_LDO14
K16
N17
1 C2918 1 C2901 1 C2903 1 C2907 1 C2909 1 C2913 1 C2981
L6 PP_VDD_BOOST E7 VDD_BOOST Vin: Maximizer 0.1UF 2.2UF 15UF 15UF 4UF
L7
VSS_BUCK11 N18 50 27 23 21
20% 20% 20% 20% 20% 2.2UF 2.2UF
U5 2 6.3V 2 6.3V 6.3V 2 6.3V 4V 20% 20%
AUX VDD
VDD_BOOST1BUCK3/6/10 X5R 2 X5R-CERM 2 X5R

L15 A11 T15 01005-2
X5R-CERM
0201 0402-0.1MM
X5R-CERM
0402-0.1MM 0201 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
VDD_BOOST2BUCK8 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 0201 0201
M7 VSS_BUCK12_9 B11 D12 VDD_BOOST3BUCK7/9/12 ROOM=PMU ROOM=PMU
M17
VSS_DFT_2 T2
N7 1 C2921 1 C2922 1 C2923
N15 2.2UF 4UF 15UF
J13 VPP 20% 20% 20%
N16 2 6.3V 4V
2 X5R 2 6.3V
X5R-CERM X5R-CERM
P7 ROOM=PMU
0201 0201 0402-0.1MM
ROOM=PMU ROOM=PMU ROOM=PMU
P15 PP_VMBX_PMU: Continuous bias at VDD_MAIN or VDD_BOOST
P16 PP_VPUMP_PMU: Biased at 5V in all states except OFF state
R6
T5
U3
U15
U14
U16
V6
V10
A V11 A
V14
V15
V17
W9
CLEAR
DOMAIN
ROOM=PMU CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
PWR_100UM P PWR_100UM PP1V5_VLDOINT ?

PWR_DEFAULT P PWR_DEFAULT PP_VMBX_PMU,PP_VPUMP_PMU ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONTROL PIN NOTES:
PMU - GPIOs NOTE

NOTE
(1):INPUT PULL-DOWN 100-300k
(2):INPUT PULL-DOWN 1M
NOTE (3):INPUT PULL-UP OR DOWN 100k-300k
AMUX CAPS NOTE (4):OUTPUT OPEN-DRAIN, REQUIRES PULL-UP
D AMUX_PMU_FROM_CAM_PMU 22 25 AMUX_PMU_FROM_GECKO 22 34 D
1 C3071 1 C3072 SYSTEM INTERFACE/AUX R3010
1000PF 1000PF 200K
10% 10% 343S00333 1 2
10V
2 X5R
10V
2 X5R
01005 01005 U2700 1%
1/32W
ROOM=PMU ROOM=PMU
TMLF49B0-CPZ MF
01005
WLCSP ROOM=PMU
SYM 4 OF 5 OMIT
AMUX_RCAM_PVDD IO_AP_TO_PMU_RESET L12 RESET_IN1 IREF F8 ANALOG_PMU_IREF C3010 XW3046
REFERENCES
22 26 13 5 IN
0 t qc
IO_HYDRA_TO_PMU_RESET M12 1.5UF SHORT-20L-0.05MM-SM
RESET_IN2
1 C3073 36 IN
IO_AP_TO_PMU_SOCHOT_L K13 RESET_IN3
VREF E9 ANALOG_PMU_VREF 1 2 1 2
RESETS
1000PF 7 5 IN 6.3V 20% ROOM=PMU
10% 38 22 13 IO_PMU_TO_SYSTEM_RESET_L L10 RESET* VSS_REF D9 ANALOG_PMU_VSS_REF CER-X5R 0201
10V
2 X5R
OUT
N11
i
01005 NC SHDN J12
ROOM=PMU
VREF_ADC ANALOG_PMU_VREF_ADC
1 C2899
IO_PMU_TO_AP_HYDRA_ACTIVE_READY K10 0.1UF
COLD_RESET & SYSTEM_ALIVE ACTIVE_READY
0 C 0 00 0
36 7 5 OUT
VDD_MAIN_SNS D7 VDD_MAIN_SNS 21
20%
IN
2 6.3V
0000 ot
13 5 OUT
CLK_PMU_TO_AOP_32K R7 SLEEP_32K UVWARN* N10 IO_PMU_TO_AP_PRE_UVLO_L OUT 5 7
X5R
Only has DS control when powered by VBUCK3 01005-2
PP1V8_S2 46 50 48
CLK_PMU_TO_TOUCH_32K P8 OUT_32K VDD_BOOST_UVLO_L U6 ROOM=PMU
OUT NC
X
CPU_TRIGGER0* P14 IO_AP_FROM_PMU_COMP_CPU_TRIGGER0_L
THROTTLERS
7 33
1 1 IO_PMU_TO_MANY_SYSTEM_ALIVE L11 OUT
R3061 R3062 SYS_ALIVE
SYSTEM I/F
22 18 OUT
CPU_TRIGGER1* R15 IO_AP_FROM_PMU_CPU_TRIGGER1_L 7
100K 100K 49 48 38 25 23 GPIO_TOUCH_TO_MANY_SCAN_ACTIVE P13 FORCE_SYNC OUT
5% 5%
IN
GPU_TRIGGER0* R14 IO_AP_FROM_PMU_GPU_TRIGGER0_L 7
1/32W 1/32W 11 GPIO_PMU_TO_AP_DOUBLE_CLICK_DET_L N14 DBLCLICK_DET OUT
MF MF
OUT
GPU_TRIGGER1* T14 IO_AP_FROM_PMU_GPU_TRIGGER1_L 7
M11 OUT
I
2 01005 01005
2 ROOM=PMU NC CRASH*
ROOM=PMU
49 33 IO_PMU_TO_DOTARA_RESET_L K12 FAULT_OUT*
OUT
IO_PMU_TO_MANY_SYSTEM_ALIVE 18 22
M9
36 13 IN
IO_HYDRA_TO_NUB_PMU_DOCK_CONNECT LDO13_EN
IO_PMU_TO_SYSTEM_RESET_L 13 22 38
BRICK_ID1 J8 IO_HYDRA_TO_PMU_USB_BRICK_ID_TIA
C C
0
22 30 36
SPMI0_NUB_TO_PMU_DOTARA_CLK M8 SPMI_SCLK IN
SPMI I/F
0?
49 13 IN
BRICK_ID2 J9 ANALOG_PMU_VDD_MAIN_SENSE_FILT 22
49 13 SPMI0_NUB_BI_PMU_DOTARA_DATA N8 SPMI_SDATA
BI
ADC_IN J11 AMUX_PMU_TO_ADC_IN
ADC
22
IBAT F10 ANALOG_PMU_VDD_MAIN_ISENSE 39

IN
7 AMUX_PMU_FROM_AP_ANALOGMUX_OUT G13 AMUX_A<0>
IN
VBAT E10 ANALOG_PMU_VDD_MAIN_VSENSE_2
00 c 100 0
39
CKPLUS_WAIVE=SINGLE_COMP_NET
E13 AMUX_A<1> IN
Amux pins A1, A6 and A7 are used for ADC offset cal F13 M14
AMUX_PMU_TO_ADC_IN
22 AMUX_A<2> BUTTON1 IO_BUTTON_VOL_DOWN_L IN 49
Do not change without contacting FCT team E12 M13
34 22 IN
AMUX_PMU_FROM_GECKO AMUX_A<3> BUTTON2 IO_BUTTON_SIDE_L IN 44
E14 L13
BUTTONS
26 22 IN
AMUX_RCAM_PVDD AMUX_A<4> BUTTON3 IO_BUTTON_VOL_UP_L IN 49
36 30 22 IO_HYDRA_TO_PMU_USB_BRICK_ID_TIA F14 AMUX_A<5> BUTTON4 K14 IO_BUTTON_RINGER_A 49

IN IN
G14 AMUX_A<6> L14 IO_PMU_TO_AP_VOL_DOWN_L
TEST MUX
H14 BUTTONO1 OUT 7
AMUX_A<7> N13
E11 BUTTONO2 IO_PMU_TO_AP_SIDE_L OUT 7
38 OUT
AMUX_PMU_AY AMUX_AY N12
BUTTONO3 NC
I
1 GPIO_AP_TO_AMUX_PMU_SYNC F12
R3011 56 IN AMUX_B<0>
qqc qc M
200K 39 ANALOG_BMU_DIFF_AMP_ISENSE D10 AMUX_B<1> GPIO1 L8 GPIO_PMU_TO_CCG2_RESET_L 56
IN
1% G8 R13
1/32W 47 IN
AMUX_PMU_FROM_DISPLAY AMUX_B<2> GPIO2 NC_PMU_GPIO_2 56
MF G9 T13
2 01005 25 22 IN
AMUX_PMU_FROM_CAM_PMU AMUX_B<3> GPIO3 SWD_NUB_BI_PMU_SWDIO 56
1
ROOM=PMU 28 25 5 IN
GPIO_CAM_PMU1_FROM_RIGEL_INT G10 AMUX_B<4> GPIO4 T12 GPIO_PMU_FROM_WLAN_HOST_WAKE 56
R3090 REQUIRED TO PREVENT
NOSTUFF GPIO_PMU_TO_AMUX_PMU_SUPER_TP H8 R12 200K STARTUP GLITCH
NTCs 56
7 5
IN
IN
CLK_AP_TO_PMU_TST_CLKOUT H9
AMUX_B<5>
AMUX_B<6>
GPIO5
GPIO6 P12
GPIO_PMU_NFC_TO_ARC_TRIG
GPIO_PMU_NFC_TO_ARC_RESET_L
56
56
1%
1/32W
MF
H10 U12 01005
58 56 38 IN
CLK_GPIO_PMU_TO_WLAN_R1_32K AMUX_B<7> GPIO7 NC_PMU_GPIO_7 56
2 ROOM=PMU
FOREHEAD NTC 38 36 AMUX_PMU_BY D11 AMUX_BY GPIO8 U11 NC_PMU_GPIO_8 56

OUT
GPIO9 R11 GPIO_PMU_FROM_BB_PCIE_HOST_WAKE_1V2_L 56
GPIOS
22 NTC_FOREHEAD_P H12 TDEV1 GPIO10 U10 NC_PMU_GPIO_10 56
1
38 IN
NTC_RADIO_BB_P H13 TDEV2 GPIO11 P11 GPIO_PMU_FROM_CHARGER_INT_L 56
OMIT NTC_RADIO_PA_P J14 T10 GPIO_PMU_FROM_CODEC_WAKE_L
R3041
NTCS
TDEV3 GPIO12
B C3041 1 NTC_FOREHEAD_P 22 XW3041
SHORT-20L-0.05MM-SM
58
NTC_AP_P G12 TDEV4 GPIO13 P10 GPIO_PMU_TO_AMUX_PMU_SUPER_TP
56
B
100PF 10KOHM-1% 22
GPIO_PMU_TO_R1_RESET_L
56
5% NTC_FOREHEAD_N 1 2 22 NTC_BATTERY_P H11 TDEV5 GPIO14 R10 56
16V 01005
NP0-C0G 2 ROOM=PMU ROOM=PMU ANALOG_PMU_TCAL G11 TCAL GPIO15 K9 GPIO_PMU_TO_NAND_LOW_BATT_BOOT_L 56
01005-1 2 NO_XNET_CONNECTION
ROOM=PMU
GPIO16 M10 CLK_GPIO_PMU_TO_DISPLAY_32K
1 C3020 1
R3020 GPIO17 T9 GPIO_PMU_TO_WLAN_REG_ON
56
100PF 3.92K CLK_PMU_XTAL1_32K T1 XIN

56
OSCILLATOR
5% 0.1% GPIO18 R9 CLK_GPIO_PMU_TO_WLAN_R1_32K 56
2 16V 1/32W CLK_PMU_XTAL2_32K U1 XOUT
NP0-C0G TK GPIO19 U8 GPIO_PMU_TO_SPKAMP_BOT_RESET_L 56
01005-1
ROOM=PMU
2 01005
ROOM=PMU Y3000 22 VSS_PMU_RTC T4 VSS GPIO20 P9 GPIO_PMU_TO_DOTARA_EN_EXT_1V8 56
32.768KHZ-20PPM-12.5PF T8
SEQUENCED
1 2 T3 GPIO21 GPIO_PMU_TO_BBPMU_RESET_L 56
a
NXTAL_MEMS R8
GPIO22 GPIO_PMU_TO_NFC_EN 56
RADIO BB NTC ON MLB_BOT C3051 1 1.60X1.00-SM

CRITICAL
1 C3052 L9 DFT_CTRL<0>
GPIO23 U7 GPIO_PMU_TO_BOOST_EN 56
22PF 22PF GPIO24 T7 GPIO_PMU_TO_DISPLAY_PANICB
TEST I/F
ROOM=PMU 56
2% 2% 58 38 18 13 SWD_NUB_TO_MANY_SWCLK N9 DFT_CTRL<1>
16V 2 16V
IN
GPIO25 K8 GPIO_PMU_TO_DISPLAY_RESET_L
C0G 2 C0G 56
01005 01005
ROOM=PMU ROOM=PMU
OMIT CRITICAL CRITICAL 1
XW3042 22 VSS_PMU_RTC
ROOM=PMU PULL-DOWN REQUIRED TO PREVENT R3091
SHORT-20L-0.05MM-SM STARTUP GLITCH 200K
1 2 1%
38 NTC_RADIO_BB_N R3091: NOSTUFF 1/32W
1 ROOM=PMU MF
ROOM=PMU R8010: 100K Pull-down 01005
2 ROOM=PMU
NO_XNET_CONNECTION SHORT-20L-0.05MM-SM
XW3000 PMU_VDD_RTC_DIG cap tracker rdar#: 29938782 NOSTUFF
2 OMIT
NO_XNET_CONNECTION CRITICAL
R3003
RADIO PA NTC ON RADIOS PAGE 39 ANALOG_PMU_VDD_MAIN_SENSE 1
9.53K 2 ANALOG_PMU_VDD_MAIN_SENSE_FILT 22
1%
1/32W
MF
A AP NTC
BATTERY NTC
01005
ROOM=PMU
1 C3003
0.1UF A
20%
1 2 6.3V
X5R
1 01005-2
OMIT OMIT ROOM=PMU
C3044 1
R3044 NTC_AP_P XW3044 C3045 1 XW3045
100PF
5% 10KOHM-1%
22
SHORT-20L-0.05MM-SM 100PF
R3045 NTC_BATTERY_P 22
SHORT-20L-0.05MM-SM
16V
NP0-C0G 2 01005
NTC_AP_N 1 2 5%
16V
10KOHM-1% NTC_BATTERY_N 1 2
01005-1 ROOM=PMU ROOM=PMU
NP0-C0G 2 01005 ROOM=PMU
ROOM=PMU 2 NO_XNET_CONNECTION
01005-1 ROOM=PMU
ROOM=PMU 2
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Boost Enable Pull

56 23
GPIO_PMU_TO_BOOST_EN
1
R3100
511K
1%
1/32W
MF
2 01005
ROOM=BOOST
BOOST
C C
50
PP_VDD_MAIN
1 C3190 1
15UF When VDD_MAIN < 3.4, boosts to 3.4
20% Otherwise tracks VDD_MAIN
2 6.3V
X5R-CERM L3100
0402-0.1MM 0.47UH-20%-3.8A-0.039OHM A3 VIN VOUT B3 PP_VDD_BOOST 21 27 50
ROOM=BOOST MCFE2016-SM
A4 VIN U3100 VOUT B4
ROOM=BOOST
CRITICAL SN61280E
1 C3110 1 C3111 1 C3112 1 C3113 1 C3114 1 C3115
2 C3 SW 15UF 15UF 15UF 15UF 15UF 220PF
CSP 20% 20% 20% 20% 20% 5%
LX_SYS_BOOST C4 SW 353S01124 2 6.3V
X5R-CERM
6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 2 6.3V
X5R-CERM
6.3V
2 X5R-CERM 2 25V
COG
ROOM=BOOST 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 01005
56 23 IN
GPIO_PMU_TO_BOOST_EN A1 EN CRITICAL ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST
I2C0_SMC_SDA 1
R3110
39.2 2
VW
54
=> I2C0_SMC_SDA_BOOST
[ IN
I2C0_SMC_SCL B2
C2
SCL
SDA
54 BI
' 1%
1/32W B1 VSEL
MF
01005
ROOM=BOOST C1 BYP*
49 48 38 25 22 IN
GPIO_TOUCH_TO_MANY_SCAN_ACTIVE A2 GPIO
PGND
AGND Tie directly to GND plane
D2
D3
D4
D1
XW3100 OMIT
SHORT-20L-0.05MM-SM
AGND_BOOST 2 1
ROOM=BOOST
B B
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
152S00871 152S00869 ALT_PARTS ALL IND,PWR,0.47UH,20%,4A,50MOHM,TAIYO,2016
TABLE_ALT_ITEM
152S00873 152S00869 ALT_PARTS ALL IND,PWR,0.47UH,20%,3.8A,55MOHM,TDK,2016
A A
CLEAR CLEAR
DOMAIN DOMAIN
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
PWR_SHAPE P PWR_SHAPE LX_SYS_BOOST ? SWITCHING S A_DIELECTRIC_1.5X LX_SYS_BOOST ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CAMERA PMU1
D D
50 PP_VDD_MAIN
1 C3792 1 C3791 1 C3790 U3700
220PF 0.47UF 2.2UF D2657B0N0VNAVAG
5% 20% 20%
2 25V
COG 2 6.3V
X5R 2 6.3V
X5R-CERM WLCSP L3700
01005 01005-1 0201 SYM 1 OF 4
0.47UH-20%-4.0A-0.05OHM
ROOM=CAM_PMU1 ROOM=CAM_PMU1 ROOM=CAM_PMU1
A3
B3
VDD_BUCK0_0
ROOM=CAM_PMU1
CRITICAL BUCK0_LX0_0 A2
B2
LX_CAM_PMU1_BUCK0 isrm.
1
PIJD2012-SM
2 PP_CAM_PMU1_VDDL_BUCK0 24 26 BUCK0: Total I_Load = 1300mA
VDD_BUCK0_1 338S00510 BUCK0_LX0_1
BUCK0_FB D1 ROOM=CAM_PMU1
1 C3700 1 C3701 1 C3702 1 C3703
26UF 26UF 330PF 56PF
20% 20% 10% 5%
XW3700
SHORT-20L-0.05MM-SM
2 4V
X5R 2 4V
X5R 2 16V
X7R 2 25V
NP0/C0G
VCC MAIN BUCKS
0402-0.1MM 0402-0.1MM 01005 01005
ANALOG_FB_CAM_PMU1_BUCK0 1 2 ROOM=CAM_PMU1 ROOM=CAM_PMU1
ROOM=CAM_PMU1 ROOM=CAM_PMU1
ROOM=CAM_PMU1
OMIT
B6 VDD_MAIN_1
F5 VDD_MAIN_2
U3700
D2657B0N0VNAVAG
WLCSP Vout (Typical) I Load (Max)
C 50 24
PP_VDD_BOOST H8 VDD_LDO1_2
SYM 2 OF 4
ROOM=CAM_PMU1 VLDO1 H7 PP2V85_IRCAM_AVDD 45 VLDO1: 2.85V (Imax = 50mA) VLDO1: I_Load = 18mA
C
CRITICAL G7
VLDO2 PP3V0_PENROSE_SVDD VLDO2: 3V (Imax = 50mA) VLDO2: I_Load = XmA
1 C3795 338S00510
44
2.2UF
20%
1 C3711 1 C3721 1 C3712 1 C3722
6.3V
2 X5R-CERM 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20%
0201 6.3V
2 X5R-CERM 2 6.3V 2 6.3V 2 6.3V
ROOM=CAM_PMU1
X5R-CERM X5R-CERM X5R-CERM
0201 0201 0201 0201
ROOM=CAM_PMU1 ROOM=CAM_PMU1 ROOM=CAM_PMU1 ROOM=CAM_PMU1
F8 VDD_LDO3_4 VLDO3 G8 PP3V3_MAMABEAR 45 VLDO3: 3.3V (Imax = 50mA) VLDO3: I_Load = XmA
VLDO4 F7 PPVAR_TELE_AVDD2 41 VLDO4: 1.9V/2.6V (Imax = 150mA) VLDO4: I_Load = 80mA
1 C3713 1 C3723 1 C3714 1 C3724
2.2UF 2.2UF 2.2UF 2.2UF
LDO INPUT LDO OUTPUT 20% 20% 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
6.3V
2 X5R-CERM 2 6.3V
X5R-CERM
0201
ROOM=CAM_PMU1
0201 0201 0201
ROOM=CAM_PMU1 ROOM=CAM_PMU1 ROOM=CAM_PMU1
D8 VDD_LDO5_6_7 VLDO5 E8 PPVAR_SWIDE_AVDD2 42 VLDO5: 1.9V/2.6V (Imax = 150mA) VLDO5: I_Load = 80mA
VLDO6 E7 PP3V3_RCAM_SVDD 26 40 41 VLDO6: 2.85V (Imax = 150mA) VLDO6: I_Load = 80mA
VLDO7 D7 PPVAR_WIDE_AVDD2 40 VLDO7: 1.9V/2.3V (Imax = 150mA) VLDO7: I_Load = 80mA
1 C3715 1 C3725
1 C3716 1 C3726 1 C3717 1 C3727
2.2UF 2.2UF 2.2UF 2.2UF
2.2UF 2.2UF 20% 20% 20% 20%
20% 20% 2 6.3V 2 6.3V 2 6.3V 2 6.3V
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
X5R-CERM
0201
X5R-CERM
0201
X5R-CERM
0201
X5R-CERM
0201
0201 0201 ROOM=CAM_PMU1 ROOM=CAM_PMU1 ROOM=CAM_PMU1 ROOM=CAM_PMU1
26 24
PP_CAM_PMU1_VDDL_BUCK0 B8 VDD_LDO8_9 VLDO8 C8 PP1V15_TELE_DVDD 41 VLDO8: 1.15V (Imax = 400mA) VLDO8: I_Load = 270mA
B VLDO9 C7 PP1V2_IRCAM_DVDD 45 VLDO9: 1.2V (Imax = 400mA) VLDO9: I_Load = 110mA B
1 C3718 1 C3719
4UF 4UF
20% 20%
2 4V
X5R 2 4V
X5R
0201 0201
VLDO10 E5
NC
VDD_HI:SW charge pump replacement

PP_VDD_BOOST A7 SW INPUT SW OUTPUT
50 24 VDD_HI
50 25
PP1V8_IO
r A5
G3
VPP_1V8_1
VPP_1V8_2
PP_1V8_SW
VDD_MAX
VDD_RTC
VDD_RTC_DIG
A4
A6
E4
F4
PP_VDD_MAX_CAM_PMU1
PP_VDD_RTC_CAM_PMU1
PP1V8_CAM_PMU1_IO_SW 42
VDD_MAX: Intetrnal supply. Power-Or of VDD_HI or VDD_MAIN

55
PP_1V8_SW: I_Load = 50mA
C3730 1 C3720
1
0.1UF 1.0UF
X5R-CERM 20%
2 10V
2
6.3V X5R-CERM
01005 0201-1
20% ROOM=CAM_PMU1
ROOM=CAM_PMU1
A CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
A
OVERRIDE OVERRIDE
DOMAIN DOMAIN
PWR_50UM P PWR_50UM PP_VDD_MAX_CAM_PMU1,PP_VDD_RTC_CAM_PMU1 ? S_PWR_100UM S 100UM-249UM_SPACING PP1V8_CAM_PMU1_IO_SW ?

PWR_80UM P PWR_80UM PP1V8_IRCAM_VDDIO*,PP3V3_MAMABEAR* ? S_PWR_100UM S 100UM-249UM_SPACING PP2V85_IRCAM_AVDD* ?
PWR_100UM P PWR_100UM PP1V8_CAM_PMU1_IO_SW ? S_PWR_200UM S 100UM-249UM_SPACING PPVAR_WIDE_AVDD2,PPVAR_SWIDE_AVDD2 ?
PWR_100UM P PWR_100UM PP2V85_IRCAM_AVDD ? S_PWR_200UM S 100UM-249UM_SPACING PP1V2_FCAM_DVDD ?
PWR_200UM P PWR_200UM PPVAR_WIDE_AVDD2,PPVAR_SWIDE_AVDD2 ? S_PWR_SHAPE S 250UM+_SPACING PP_CAM_PMU1_VDDL_BUCK0 ?
PWR_200UM P PWR_200UM PP1V2_FCAM_DVDD ? S_PWR_SHAPE S 250UM+_SPACING PP1V2_IRCAM_DVDD ?
PWR_SHAPE P PWR_SHAPE LX_CAM_PMU1_*,PP_CAM_PMU1_VDDL_BUCK0 ? S_PWR_SHAPE S 250UM+_SPACING PP1V15_TELE_DVDD ?
PWR_SHAPE P PWR_SHAPE PP1V2_IRCAM_DVDD ? SWITCHING S A_DIELECTRIC_1.5X LX_CAM_PMU1_* ?
PWR_SHAPE P PWR_SHAPE PP1V15_TELE_DVDD ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CAMERA PMU1
D D
U3700
D2657B0N0VNAVAG
WLCSP
G5 SYM 3 OF 4
ROOM=CAM_PMU1 E1
55 OUT
I2C1_CAM_PMU1_SCL SCL_1 GPIO1 GPIO_CAM_PMU1_TO_FCAM_LDO_EN OUT 5 26 27
I2C1: WIDE G6 CRITICAL C2
55 BI
I2C1_CAM_PMU1_SDA SDA_1 GPIO2 GPIO_CAM_PMU1_TO_TELE_LDO_EN OUT 5 27
338S00510 D2
J4 GPIO3 GPIO_CAM_PMU1_TO_RIGEL_ENABLE OUT 5 28
55 38 OUT
I2C2_CAM_PMU1_SCL SCL_2 E2
I2C2: SWIDE/LEX/STROBE J5 GPIO4 GPIO_CAM_PMU1_FROM_RIGEL_INT IN 5 22 28
55 38 BI
I2C2_CAM_PMU1_SDA SDA_2 I2C GPIO F2
GPIO5 GPIO_CAM_PMU1_TO_WIDE_LDO_EN OUT 5 26 27
55 I2C3_CAM_PMU1_SCL H4 SCL_3 GPIO6 C3 GPIO_CAM_PMU1_TO_WIDE_SHDN_L 40
OUT OUT
I2C3: TELE H5 D3
PP1V8_IO 55 BI
I2C3_CAM_PMU1_SDA SDA_3 GPIO7 GPIO_CAM_PMU1_TO_SWIDE_SHDN_L OUT 42
50 24
GPIO8/TCAL B4 GPIO_CAM_PMU1_TO_SWIDE_LDO_EN 5 26 27
H3 OUT
55 OUT
I2C4_CAM_PMU1_SCL SCL_4 D6
I2C4: IRCAM/ROMEO J3 GPIO9/TDEV1 GPIO_CAM_PMU1_TO_STROBE_DRIVER_HWEN OUT 38
55 BI
I2C4_CAM_PMU1_SDA SDA_4
00 up oo oo
R3802 1 GPIO10/TDEV2 F6 GPIO_CAM_PMU1_TO_PVDD_RESET_L 26
R3805
OUT
nnngnnnnnn
100K B5 GPIO_RIGEL_BI_YOGI_STATUS_R 1
11K 2 GPIO_RIGEL_BI_YOGI_STATUS
5% GPIO11/TDEV3 BI 28 46
1/32W 9 5 SPMI_ISP_TO_CAM_PMU1_CLK J6 SCLK
IN C4
MF GPIO12/TDEV4 GPIO_RIGEL_BI_MAMABEAR_STATUS_R 1% C
C 01005 2 SPMI 1/32W
9 5 SPMI_ISP_BI_CAM_PMU1_DATA H6 SDATA GPIO13/FORCE_SYNC E3 GPIO_TOUCH_TO_MANY_SCAN_ACTIVE 22 23 38 48 49 MF
BI IN
oo
ROOM=CAM_PMU1 01005
ROOM=CAM_PMU1
IO_CAM_PMU1_CRASH_L F3 CRASH*
G4 RESET R3806
9 IN
GPIO_ISP_TO_CAM_PMU1_RESET_L RESET* 1
10K 2 GPIO_RIGEL_BI_MAMABEAR_STATUS BI 28 45
5%
1 ANALOG_CAM_PMU1_VREF C5 VREF CLKI F1 CLK_ISP_TO_CAM_PMU1_24M 9 1/32W
R3801 IN
REFERENCE CLK EXPAND MF
100K 01005
5% ANALOG_CAM_PMU1_IREF D5 IREF CLKO_1 G2 CLK_CAM_PMU1_TO_WIDE_24M 40
1 ROOM=CAM_PMU1
OUT R3850
1/32W G1
MF CLKO_2 CLK_CAM_PMU1_TO_SWIDE_24M OUT 42 100K
2 01005 H2 5%
CLKO_3 CLK_CAM_PMU1_TO_TELE_24M OUT 41 1/32W
POO
ROOM=CAM_PMU1 1 MF
1 R3800 CLKO_4 H1
x
C3800 200K NC 2 01005
ROOM=CAM_PMU1
0.22UF 0.1%
10% 1/20W R3850: Place near F1
6.3V
2 CER-X5R TF
AMUX B7 AMUX_PMU_FROM_CAM_PMU 22
01005 2 0201 OUT
Precision 50ppm Resistor VPP_OTP J1
Advanced Test Mode (OTP rewrite)
U3700
D2657B0N0VNAVAG B
B WLCSP
SYM 4 OF 4
A8 ROOM=CAM_PMU1 A1
VSS VSS_BUCK0
C1 CRITICAL B1
VSS VSS_BUCK0
C6 338S00510
VSS
D4 VSS
E6 VSS
J2 VSS
J7 VSS
J8 VSS
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SWIDE VDDL LDO

D
U3900 50
PP_VDD_MAIN
Lex D
PPVAR_RCAM_PVDD: I_Load = 900mA (MAX)
SCY99247-1.20V
WLCSP PP1V2_SWIDE_DVDD: I_Load = 260mA
1 C3940
2.2UF
26 24 PP_CAM_PMU1_VDDL_BUCK0
A2 VIN
VER-1
VOUT A1 PP1V2_SWIDE_DVDD 42
20%
6.3V
2 X5R-CERM
L3940
GPIO_CAM_PMU1_TO_SWIDE_LDO_EN B2 353S01904 0201 U3940 0.47UH-2.9A-0.072OHM
-
EN
27 25 5
1 C3905 1 C3907 1 C3908 C3906 ROOM=RCAM_LEX D2685 PIJD1608FE-SM
XW3960
1
ROOM=RCAM_LDO ROOM=RCAM_LEX
PP3V3_RCAM_SVDD C2 B1 4UF 4UF 4UF 0.22UF CSP SHORT-0201
41 40 26 24 VBIAS SNS B3
<57
T
20% 20% 20% 10% C3 VIN 338S00463 LX LX_LEX 1 2 PPVAR_RCAM_PVDD_XW 1 2 PPVAR_RCAM_PVDD 40 41
2 4V 2 4V 2 4V
2
6.3V
C3900 1 1 C3901
GND X5R
0201
X5R
0201
X5R
0201 CER-X5R 25
=>GPIO_CAM_PMU1_TO_PVDD_RESET_L
[ IN
C2 RESET* VOUT A2
1 C3941 1 C3942 1 C3943 ROOM=RCAM_LEX
T
ROOM=RCAM_LEX
ROOM=RCAM_LDO ROOM=RCAM_LDO ROOM=RCAM_LDO
01005
C1
2.2UF 0.47UF ROOM=RCAM_LDO
I2C2_CAM_PMU1_SCL C1 SCL DMUX B2 15UF 15UF 330PF
20% 20% 55 IN
XW3940 20% 20% 10%
6.3V 2
X5R-CERM
0201
ROOM=RCAM_LDO T 2 6.3V
X5R
01005-1
ROOM=RCAM_LDO
55 BI
I2C2_CAM_PMU1_SDA B1 SDA
VSS
VPP A1
ANALOG_FB_LEX
SHORT-20L-0.05MM-SM
1
OMIT
2
2 6.3V
X5R-CERM
0402-0.1MM
ROOM=RCAM_LEX
2 6.3V
X5R-CERM
0402-0.1MM
ROOM=RCAM_LEX
2 16V
X7R
01005
ROOM=RCAM_LEX
A3
1 ROOM=RCAM_LEX
Enable operation: Assert EN after VIN and VBIAS rails reach nominal levels
R3940
100K
5%
1/32W
MF 2
01005
ROOM=RCAM_LEX
XW3950
SHORT-20L-0.05MM-SM
22 AMUX_RCAM_PVDD 1 2
OMIT
Wide VDDL LDO ROOM=RCAM_LEX
U3910
SCY99247-1.20V
C A2
WLCSP
VER-1
A1
PP1V2_WIDE_DVDD: I_Load = 660mA C
26 24 PP_CAM_PMU1_VDDL_BUCK0 VIN VOUT PP1V2_WIDE_DVDD 40
B2 353S01904
GPIO_CAM_PMU1_TO_WIDE_LDO_EN EN
27 25 5
1 C3913 1 C3914 1 C3915 1 C3917 C3916
1
ROOM=RCAM_LDO
41 40 26 24 PP3V3_RCAM_SVDD C2 VBIAS SNS B1 4UF 4UF 4UF 4UF 0.22UF

20% 20% 20% 20% 10%
2 4V 2 4V 2 4V 2 4V
2
GND X5R X5R X5R X5R 6.3V
CER-X5R
C3910 1 1 C3909 0201 0201 0201 0201 01005
C1
2.2UF 0.47UF ROOM=RCAM_LDO ROOM=RCAM_LDO ROOM=RCAM_LDO ROOM=RCAM_LDO ROOM=RCAM_LDO

20% 20%
6.3V 2 6.3V
X5R-CERM 2 X5R
0201 01005-1
ROOM=RCAM_LDO ROOM=RCAM_LDO
FCAM VDDL LDO

U3920
SCY99247-1.20V
WLCSP
B 26 24 PP_CAM_PMU1_VDDL_BUCK0 A2 VIN
VER-1
VOUT A1 PP1V2_FCAM_DVDD 43 B
B2 353S01904
GPIO_CAM_PMU1_TO_FCAM_LDO_EN EN
27 25 5
1 C3925 C3926
1
ROOM=FCAM_LDO
41 40 26 24 PP3V3_RCAM_SVDD C2 VBIAS SNS B1 26UF 0.22UF
T
20% 10%
2 4V
2
GND X5R 6.3V

CER-X5R
C3920 1 1 C3929 0402-0.1MM
I ROOM=FCAM_LDO
01005
C1
2.2UF 0.47UF OMIT_TABLE ROOM=FCAM_LDO

20% 20%
6.3V 2 6.3V
X5R-CERM 2 X5R
0201
ROOM=FCAM_LDO
01005-1
ROOM=FCAM_LDO
A A
CLEAR CLEAR
DOMAIN DOMAIN
PWR_SHAPE P PWR_SHAPE PPVAR_RCAM_PVDD,PPVAR_RCAM_PVDD_XW ? S_PWR_SHAPE S 250UM+_SPACING PPVAR_RCAM_PVDD,PPVAR_RCAM_PVDD_XW ?

PWR_SHAPE P PWR_SHAPE PP1V2_WIDE_DVDD,PP1V2_SWIDE_DVDD ? S_PWR_SHAPE S 250UM+_SPACING PP1V2_WIDE_DVDD,PP1V2_SWIDE_DVDD ?
PWR_SHAPE P PWR_SHAPE LX_LEX ? SWITCHING S A_DIELECTRIC_1.5X LX_LEX ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CAMERA VDDH LDOs

D D
U4100
LP5907UVX2.925-S
DSBGA PP2V925_FCAM_AVDD
50 27 23 21 PP_VDD_BOOST A1 VIN VOUT A2 43
353S00015 138S00122 138S00122 FCAM_AVDD1: I_Load = 76mA
ROOM=FCAM_LDO
26 25 5 GPIO_CAM_PMU1_TO_FCAM_LDO_EN B1 VEN CRITICAL

1 C4111 1 C4112 1 C4113 1 C4114 1 C4115 1 C4116
GND 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
I
1 C4190 2 6.3V 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 2 6.3V 2 6.3V
B2
X5R-CERM X5R X5R
2.2UF 0201 0201 0201 0201 0201-4 0201-4
20% ROOM=FCAM_LDO ROOM=FCAM_LDO ROOM=FCAM_LDO ROOM=FCAM_LDO ROOM=FCAM_LDO ROOM=FCAM_LDO
2 6.3V
X5R-CERM CRITICAL CRITICAL
0201
ROOM=FCAM_LDO
U4110
C LP5907UVX2.925-S C
DSBGA PP2V925_WIDE_AVDD1
50 27 23 21 PP_VDD_BOOST A1 VIN VOUT A2 40
353S00015 WIDE_AVDD1: I_Load = 100mA
ROOM=RCAM_LDO
26 25 5 GPIO_CAM_PMU1_TO_WIDE_LDO_EN B1 VEN CRITICAL 1 C4120 1 C4121 1 C4122 1 C4123 1 C4124

GND 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20%
C4191
T
1 6.3V 6.3V 6.3V 6.3V 6.3V
B2
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
2.2UF 0201 0201 0201 0201 0201
20%
6.3V
2 X5R-CERM
ROOM=RCAM_LDO ROOM=RCAM_LDO ROOM=RCAM_LDO ROOM=RCAM_LDO ROOM=RCAM_LDO
0201
ROOM=RCAM_LDO
U4120
LP5907UVX2.925-S
DSBGA
50 27 23 21 PP_VDD_BOOST A1 VIN VOUT A2 PP2V925_TELE_AVDD1 41
353S00015
ROOM=RCAM_LDO TELE_AVDD1: I_Load = 80mA
25 5 GPIO_CAM_PMU1_TO_TELE_LDO_EN B1 VEN CRITICAL 1 C4117 1 C4125 1 C4126 1 C4127 1 C4128
GND 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20%
C4192
T
1 6.3V 6.3V 6.3V 6.3V 6.3V
B2
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
2.2UF 0201 0201 0201 0201 0201
20% ROOM=RCAM_LDO ROOM=RCAM_LDO ROOM=RCAM_LDO ROOM=RCAM_LDO ROOM=RCAM_LDO
6.3V
2 X5R-CERM
0201
ROOM=RCAM_LDO
B B
U4130
LP5907UVX2.925-S
DSBGA
50 27 23 21 PP_VDD_BOOST A1 VIN VOUT A2 PP2V925_SWIDE_AVDD1 42
353S00015
ROOM=RCAM_LDO
26 25 5 GPIO_CAM_PMU1_TO_SWIDE_LDO_EN B1 VEN CRITICAL 1 C4118

GND 10UF
20%
1 C4193
2.2UF
20%
6.3V
2 X5R-CERM
0201
ROOM=RCAM_LDO
T
B2
2 10V
X5R-CERM
0402-0.1MM
ROOM=RCAM_LDO
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
353S01728 353S00015 ALT_PARTS ALL IC,LDO,REG,2.925V,250MA,ONSEMI
A A
CLEAR CLEAR
DOMAIN DOMAIN
PWR_100UM P PWR_100UM PP2V925_FCAM_AVDD ? S_PWR_100UM S 100UM-249UM_SPACING PP2V925_WIDE_AVDD*,PP2V925_FCAM_AVDD ?

PWR_200UM P PWR_200UM PP2V925_SWIDE_AVDD1 ? S_PWR_200UM S 100UM-249UM_SPACING PP2V925_SWIDE_AVDD1 ?
PWR_200UM P PWR_200UM PP2V925_WIDE_AVDD1 ? S_PWR_200UM S 100UM-249UM_SPACING PP2V925_TELE_AVDD1 ?
PWR_200UM P PWR_200UM PPVAR_TELE_AVDD2,PP2V925_TELE_AVDD1 ? S_PWR_200UM S 100UM-249UM_SPACING PP3V3_RCAM_SVDD ?
PWR_200UM P PWR_200UM PP3V3_RCAM_SVDD ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Rigel Driver 50
PP_VDD_MAIN
1 C4497 C4494 1
15UF 4UF
20% 20%
6.3V 6.3V
2 X5R-CERM CER-X5R 2
0402-0.1MM 0201
ROOM=RIGEL ROOM=RIGEL
C4493 1
4UF
20%
6.3V
CER-X5R 2
D 0201
ROOM=RIGEL
D
C4492 1
4UF
20%
6.3V
CER-X5R 2
0201
ROOM=RIGEL
C4491
m
1
4UF
Terminate @ Cap via on VDD_MAIN plane. 20%
6.3V
OMIT CER-X5R 2
0201
o
XW4400
SHORT-10L-0.1MM-SM
ROOM=RIGEL
2 1 PP_RIGEL_VINCORE
ROOM=RIGEL
C4490 1
c
1.0UF
20%
.
10V
X5R-CERM 2
0201-1
ROOM=RIGEL
C 50 PP1V8_IO
PP_VANA
c h C
e
50
PP_VDD_BOOST
1 C4495 1 C4496 1 C4498
T
2.2UF 1.0UF 2.2UF
20% 20% 20%
6.3V 10V
2 6.3V
VINSUA A10
VINSDA F10
2 X5R-CERM 2 X5R-CERM
VCC4 G9
VCC3 G2
VIN_LVT H8
VDDIO C5
VANA H4
VINVCORE2 H5
VINSDB E2
VINSUB A3
VINSUB A2
VINSUB A1
VINSUA A9
VINSUA A8
VINSDA E9
VINCORE F5
VINSDB F2
VINSDB F1
VINSDA F9
X5R-CERM
0201 0201-1 0201
ROOM=RIGEL ROOM=RIGEL ROOM=RIGEL
45 PP_ROMEO_CATHODE K4
K5
VK
VK
e 1 VBBOUTA
VBBOUTA
H10
J10
5 PP_RIGEL_BUCK_BOOST_A
L4400
1 C4400
4.7UF
1 C4401
220PF
li
20% 5%
K6 VK VBBOUTA K10 2 25V 2 25V
0.47UH-20%-4A-0.048OHM X5R COG
K7 0402-0P1MM 01005
K8
VK U4400 VLXA D10 LXA_RIGEL 1 2 ROOM=RIGEL ROOM=RIGEL
VK STB601A0N D9 PIWA20120H-SM
VLXA
NTC_PEARL_VSCEL_TO_RIGEL G4 NTC
WLCSP
VLXA E10
1 C4405 ROOM=RIGEL
45 IN
343S00315 4.7UF NO_XNET_CONNECTION=1
b
20% 152S00640
C4 OTPHV
ROOM=RIGEL
VCXA B10 25V
2 X5R 1 C4420
VCXA B9 CXA_RIGEL 0402-0P1MM 0.01UF
D4 TAMP ROOM=RIGEL
10%
CRITICAL BOOSTSDA E8 RIGEL_BOOSTSDA 2 6.3V
X5R
o
25 5 GPIO_CAM_PMU1_TO_RIGEL_ENABLE B3 ENA 01005
IN
BULKSDA D8 RIGEL_BULKSDA ROOM=RIGEL
46 25 GPIO_RIGEL_BI_YOGI_STATUS C8 XEF1
BI
45 25 GPIO_RIGEL_BI_MAMABEAR_STATUS C7 XEF0 BULKSDB D3 RIGEL_BULKSDB
B8 THROT BOOSTSDB E3 RIGEL_BOOSTSDB
IO_IRCAM_TO_RIGEL_STROBE A4 STROBE
1 C4421
45 IN B1 CXB_RIGEL 0.01UF
M
VCXB
B B7 TESTMODE VCXB B2 1 C4410
10%
2 6.3V
X5R B
.
4.7UF 01005
B5 TESTMODE2 VLXB D1 20%
2 25V
ROOM=RIGEL L4401
VLXB D2 X5R 0.47UH-20%-4A-0.048OHM
B6 TEST 0402-0P1MM
VLXB E1 LXB_RIGEL ROOM=RIGEL 1 2
CLK_ISP_TO_RIGEL_12M A7 MCLK PIWA20120H-SM
9
J1 C4411 C4412
w
IN ROOM=RIGEL 1 1
VBBOUTB
25 22 5 OUT
GPIO_CAM_PMU1_FROM_RIGEL_INT B4 INT VBBOUTB J2 NO_XNET_CONNECTION=1
4.7UF 220PF
152S00640 20% 5%
J3 5 PP_RIGEL_BUCK_BOOST_B 2 25V
R4400 55 IN I2C0_ISP_SCL A5 SCL
VBBOUTB X5R
0402-0P1MM
2 25V
COG
01005
I2C0_ISP_SDA 1
33.2 2 I2C0_ISP_SDA_R A6 H9 ROOM=RIGEL ROOM=RIGEL
55 BI SDA IOUT0
w
1% IOUT0 K9
1/32W G5 PD0
MF IOUT0 J9 PP_ROMEO_DENSE_ANODE 45
01005 G6 PD1
ROOM=RIGEL H1
H7 IOUT1
ANALOG_RIGEL_LSCP LSCP H2
IOUT1
C4422 PP_ROMEO_SPARSE_ANODE
w
1 IOUT1 H3 45
0.01UF
10% IOUT2 K1
6.3V
X5R 2 IOUT2 K2
01005
ROOM=RIGEL IOUT2 K3 PP_ROSALINE_ANODE 46
TABLE_ALT_HEAD
IOUT3 G1 PP_ROMEO_A_ANODE 45
PART NUMBER
TABLE_ALT_ITEM
IOUT4 G10 PP_ROMEO_B_ANODE 152S00965 152S00640 ALT_PARTS L4400,L4401 IND,MLD,0.47UH,4A,2010,Taiyo

GNDCORE4
GNDCORE3
GNDCORE2
45
GNDCORE
CLEAR
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR*
PGNDK
PGNDK
PGNDK
PGNDK
PGNDK
PGNDB
PGNDB
PGNDA
PGNDA
GNDD
OVERRIDE
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
DOMAIN
PWR_100UM P PWR_100UM PP_RIGEL_VINCORE,PP_VANA ?

PWR_100UM P PWR_100UM PP_ROMEO_A_ANODE,PP_ROMEO_B_ANODE ?
J8
J7
J6
J5
J4
G8
G3
H6
F6
C6
G7
E6
F8
E5
F3
D7
D6
D5
C3
C2
C1
C9
C10
A PWR_SHAPE P PWR_SHAPE CX*_RIGEL,LX*_RIGEL,PP_RIGEL_BUCK_BOOST_* ? A
PWR_SHAPE P PWR_SHAPE PP_ROSALINE_ANODE,PP_ROMEO_CATHODE ?
PWR_SHAPE P PWR_SHAPE PP_ROMEO_DENSE_ANODE,PP_ROMEO_SPARSE_ANODE ? XW4401
AGND_RIGEL 1 2
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR SHORT-10L-0.1MM-SM
OVERRIDE ROOM=CODEC
DOMAIN
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N PGNDK: Direct connect to GND plane PGNDA/PGNDB: Direct connect to GND plane
S_PWR_100UM S 100UM-249UM_SPACING PP_RIGEL_VINCORE,PP_VANA ?
S_PWR_100UM S 100UM-249UM_SPACING PP_ROMEO_A_ANODE,PP_ROMEO_B_ANODE ?
S_PWR_SHAPE S 250UM+_SPACING CX*_RIGEL,LX*_RIGEL,PP_RIGEL_BUCK_BOOST_* ? AGND: Connect together on non GND layer, then attach to GND plane at a single point
S_PWR_SHAPE S 250UM+_SPACING PP_ROSALINE_ANODE,PP_ROMEO_CATHODE ?
S_PWR_SHAPE S 250UM+_SPACING PP_ROMEO_DENSE_ANODE,PP_ROMEO_SPARSE_ANODE ?
CLK S A_DIELECTRIC_1.5X CLK*_RIGEL_12M* ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Kobol - Accel & Gyro
C C
PP1V8_S2 16 29 46 49 50 54
54 50 49 46 29 16
PP1V8_S2
1 C4500 1 C4501 1 C4502
0.1UF 0.1UF 2.2UF
20% 20% 20%
R4501 1 2 6.3V
X5R-CERM
01005
2 6.3V
X5R-CERM
01005
2 6.3V
X5R-CERM
0201
100K
5% ROOM=KOBOL ROOM=KOBOL ROOM=KOBOL
1/32W
MF
16
1
01005 2
ROOM=KOBOL
VDD VDDIO
338S00367
CRITICAL
U4500
BMI282AA
LGA
ROOM=KOBOL
56 GPIO_AOP_TO_IMU_SPI_CS_L 5 CS* SCLK 2
SPI0_AOP_TO_IMU_R1_SCLK 13 58
IN IN
15 SM
MOSI 3
SPI0_AOP_TO_IMU_R1_MOSI 13 58
IN
56 5 GPIO_AOP_FROM_IMU_DATARDY 6 INT MISO 4
SPI0_AOP_FROM_IMU_R1_MISO 13 58
OUT OUT
7 MOTION_INT
NC
GND
8
9
10
11
12
13
14
B B
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BRIGHTON AUDIO CODEC (ANALOG INPUTS & OUTPUTS)

U4700
CS42L77A1
WLCSP
SYM 1 OF 4
49
49 =
[ IN
IN
> MIC1_LOWER_TO_CODEC_AIN1_P
MIC1_LOWER_TO_CODEC_AIN1_N
M8
L8
AIN1+
AIN1-
338S00509
CRITICAL
ROOM=CODEC
AOUT+
AOUT-
F11
G11
CODEC_AOUT_TO_HAC_P
CODEC_AOUT_TO_HAC_N
46
46
D D
44 MIC2_REAR_TO_CODEC_AIN2_P M11 AIN2+
IN
44 MIC2_REAR_TO_CODEC_AIN2_N L11 AIN2-
IN
M9
46
o MIC3_FRONT_TO_CODEC_AIN3_P AIN3+
=
IN
MIC3_FRONT_TO_CODEC_AIN3_N L9
46 [ >
IN AIN3-
49
49 =
[ IN -
IN
> MIC4_LOWER_TO_CODEC_AIN4_P
MIC4_LOWER_TO_CODEC_AIN4_N
M10
L10
AIN4+
AIN4-
C4750 M3
0.22UF 44 PENROSE_IR_TO_CODEC_AIN5_P AIN5A+
=
IN
GND L3
44
c >
IN
2 1 PENROSE_IR_TO_CODEC_AIN5_N AIN5A-
10%
6.3V
CER-X5R
01005
ROOM=B2B_STROBE
J=
^ L4 AIN5B+
C |
| L5 AIN5B-
C
Place Near B2B
|
|
V
C4751 K5
0.22UF 44 IN
PENROSE_VIS_TO_CODEC_AIN6_P AIN6A+
44 IN
GND 2 1 PENROSE_VIS_TO_CODEC_AIN6_N K4 AIN6A- C4700
100PF
10% 1 2
6.3V
CER-X5R
01005
ROOM=B2B_STROBE
5%
16V
NP0-C0G
1
NO_XNET_CONNECTION=1 R4700 01005-1
=
L2 AIN6B+ 20.0 ROOM=CODEC
90_MIKEYBUS_DATA_P
F
1 2
M2 AIN6B-
5%
< >
BI 36
1/32W
MF
DP F1 90_MIKEYBUS_CODEC_DATA_P 01005
E1 ROOM=CODEC
DN 90_MIKEYBUS_CODEC_DATA_N
R4701
F
J2
K2
AIN7+
AIN7-
MBUS_REF E2 ANALOG_MIKEYBUS_REFERENCE
< = IN ) 49
1
20.0
5%
1/32W
MF
2
C4701
90_MIKEYBUS_DATA_N BI 36
1
R4710 1 C4711 01005
ROOM=CODEC 100PF
100 330PF
5% 10% 1 2
2 16V
J3 AIN8+
1/32W
MF
2 01005
X7R
01005 5% i
F
ROOM=CODEC ROOM=CODEC 16V
K3 AIN8- NP0-C0G
01005-1
ROOM=CODEC
B B
Can be placed near Dock Connector
H3 AIN9+
F H2 AIN9-
J4 AIN10+
F J5 AIN10-
LDCM
L6 AIN11+
F L7 AIN11-
HALOGEN_TIA_IOUT
1
C4720
220PF
5%
1
R4721
200K
1%
1/32W
MF
01005
2
25V ROOM=CODEC
COG NO_XNET_CONNECTION=1
K7 G4 01005
AIN12+ TIA_EXOUT NC 2 C4721
F
ROOM=CODEC
K6 AIN12- TIA_OUT G5 10UF
G1 HALOGEN_TIA_IN IO_HYDRA_TO_PMU_USB_BRICK_ID_TIA
2
TIA_SENSE -CD
IN 22 36
38 PDM_OUT1_CODEC_TO_SPKAMP_TOP_CLK A6 PDMOUT1_CLK
OUT 20%
PDM_OUT1_CODEC_TO_SPKRAMP_TOP_DATA D6 PDMOUT1_DATA 10V
A 38 OUT
B6
X5R-CERM
0402-0.1MM
ROOM=CODEC
A
PDMOUT2_CLK NO_XNET_CONNECTION=1
C6 PDMOUT2_DATA
CLEAR
CLEAR
CLASS NAME
DOMAIN
DOMAIN
PWR_80UM P PWR_80UM PP1V8_CODEC_VA_S2 ? CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
PWR_200UM P PWR_200UM AGND_CODEC,CODEC_FILTP,CODEC_LP_FILTN ? S_PWR_200UM S 100UM-249UM_SPACING AGND_CODEC,CODEC_FILTP,CODEC_LP_FILTN ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BRIGHTON AUDIO CODEC (POWER & I/O)
D 50 PP_VDD_BOOST D
C4810: Place near G12 1 C4810 1 C4811 1 C4812 U4700
C4810: Can reduce to 2.2uF if located near BOOST CS42L77A1
10UF 0.1UF 220PF WLCSP
20% 20% 5%
2 10V
6.3V
2 X5R-CERM 2 25V SYM 4 OF 4
X5R-CERM COG 338S00509
01005 01005
ROOM=CODEC
G12 VDD_P ROOM=CODEC GND_D0 A1
0402-0.1MM
ROOM=CODEC
ROOM=CODEC
F2 VDD_MBUS CRITICAL GND_D1 A12
GND_D2 A8
50 PP1V8_S2 H1 VDD_1P8
GND_D3 B4
E12 VIO_GPIO C12
1 C4801 1 C4802 1 C4803 1 C4804 1 C4805 D10 GND_D4
m
VIO_I2C D1
10UF 0.1UF 0.1UF 0.1UF 0.1UF A5 GND_D5
20% 20% 20% 20% VIO_SPI E6
20% 6.3V 6.3V 6.3V 6.3V E3 GND_D6
C4801: Place near H1 2 10V 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM VIO_MCLK J1 I2C ADDRESS: 1001 010x
X5R-CERM 01005 01005 01005 01005 A11 GND_D7
0402-0.1MM VIO_ASP M1
o
GND_D8
ROOM=CODEC
PLACE_NEAR=U4700.H1:2MM
ROOM=CODEC ROOM=CODEC ROOM=CODEC ROOM=CODEC
B3 VIO_SWIRE U4700
A7 VIO_PDM CS42L77A1
F12 WLCSP
PP1V2_S2 A4 GND_P0 SYM 3 OF 4
VDD_D0
c
50
GND_P1 M12 338S00509
D12 VDD_D1 GPIO_AOP_TO_CODEC_RESET_L H7 RESET* GPIO3_JTAG_TRST* E10
OqqqO 0 0 0
56 5 IN
.
GPIO4_JTAG_TDO D11
21 PP1V8_CODEC_VA_S2 M4 VDD_A 56 GPIO_PMU_FROM_CODEC_WAKE_L H8 WAKE*
OUT
GPIO5_JTAG_TMS F8
ROOM=CODEC
GPIO_AP_FROM_CODEC_INT_L E11 INT* GPIO2_JTAG_TDI F9
1 C4815 56 5 OUT
CRITICAL
GPIO1_JTAG_TCK F10
h
2.2UF E9 I2C_ADDR
20%
6.3V
2 X5R-CERM
1 C4820 I2C0_AOP_SCL C11 I2C_SCL
0201
1.0UF 54 IN
20% I2C0_AOP_SDA E8 I2C_SDA
31 AGND_CODEC ROOM=CODEC
2 10V C4840 1 54 BI
c
X5R-CERM
0201-1 15PF 11 IN
SPI3_AP_TO_CODEC_SCLK B5 SPI_SCK
ROOM=CODEC 5%
C PLACE_NEAR=U4700.A4:2MM 16V 2
NP0-C0G
01005-1
ROOM=CODEC
11 5
11 5
IN
SPI3_AP_TO_CODEC_CS_L
SPI3_AP_TO_CODEC_MOSI
E5
D5
SPI_SS*
SPI_MOSI
C
IN
e
C4820: Place near A4 C5
11 5 OUT
SPI3_AP_FROM_CODEC_MISO SPI_MISO
I2S0_AOP_TO_CODEC_MCLK1 C2 MCLK1_IN TSTI D2
0
13 IN
T
D3 MCLK2_IN TSTI J7
I
C1 MCLK_OUT TSTO H4
NC NC
1
I2S0_AOP_FROM_CODEC_ASP1_BCLK B7 ASP1_BCLK
oc 00
13 OUT
13 I2S0_AOP_FROM_CODEC_ASP1_LRCLK E7 ASP1_FSYNC
OUT
13 I2S0_AOP_TO_CODEC_ASP1_DOUT D7 ASP1_DIN
IN
I2S0_AOP_FROM_CODEC_ASP1_DIN C7
e
13 OUT ASP1_DOUT
li
I2S1_AOP_AMPS_FROM_CODEC_ASP2_BCLK A9 ASP2_BCLK
00
49 38 13 OUT
R4832 49 38 13 OUT
I2S1_AOP_AMPS_FROM_CODEC_ASP2_LRCLK D8 ASP2_FSYNC
I2S1_AOP_TO_AMPS_CODEC_ASP2_DOUT 1
49.9 2 I2S1_AOP_TO_AMPS_CODEC_ASP2_DOUT_R C8
49 38 13 IN ASP2_DIN
1% 49 38 13 I2S1_AOP_FROM_AMPS_CODEC_ASP2_DIN B8 ASP2_DOUT
OUT
1/32W
MF
b
01005
I2S0_AP_FROM_CODEC_ASP3_BCLK A10 ASP3_BCLK
ngnn ngnn
ROOM=CODEC 11 OUT
11 I2S0_AP_FROM_CODEC_ASP3_LRCLK D9 ASP3_FSYNC
OUT
11 I2S0_AP_TO_CODEC_ASP3_DOUT C9 ASP3_DIN
IN
I2S0_AP_FROM_CODEC_ASP3_DIN B9
o
ASP3_DOUT
U4700 11 OUT
CS42L77A1
WLCSP 11 I2S1_AP_FROM_CODEC_ASP4_BCLK B12 ASP4_BCLK
OUT
SYM 2 OF 4 11 I2S1_AP_FROM_CODEC_ASP4_LRCLK C10 ASP4_FSYNC
OUT
PP_CODEC_TO_MIC1_LOWER_BIAS K9 338S00509 H12 B10
49 MIC1_BIAS MIC_FILT+ CODEC_MIC_FILTP C4830 11 IN
I2S1_AP_TO_CODEC_ASP4_DOUT ASP4_DIN
CRITICAL
M
MIC1_LOWER_TO_CODEC_BIAS_FILT_RET J9 MIC1_BIAS_REF MIC_FILT- J12 31 AGND_CODEC 2.2UF I2S1_AP_FROM_CODEC_ASP4_DIN B11 ASP4_DOUT
B 49 IN ROOM=CODEC
1 20%
6.3V
11 OUT
C4
B
.
X5R-CERM SWIRE1_CLK0
0201
2 ROOM=CODEC A2 SWIRE1_CLK1
A3 SWIRE1_CLK2
PP_CODEC_TO_MIC2_REAR_BIAS
44
K11 MIC2_BIAS LP_FILT+ K1 CODEC_LP_FILTP
C3 SWIRE1_DATA0
w
MIC2_REAR_TO_CODEC_BIAS_FILT_RET J10 MIC2_BIAS_REF LP_FILT- L1 CODEC_LP_FILTN
q
44 IN D4 SWIRE1_DATA1
1 C4831 E4 SWIRE1_DATA2
0.1UF
20%
2 6.3V
X5R-CERM B1
01005 SWIRE2_CLK0
w
ROOM=CODEC
B2 SWIRE2_CLK1
PP_CODEC_TO_MIC3_FRONT_BIAS
46
L12 MIC3_BIAS
F4 SWIRE2_DATA0
46 MIC3_FRONT_TO_CODEC_BIAS_FILT_RET K10 MIC3_BIAS_REF
IN
56 5 GPIO_AOP_TO_CODEC_CLP_EN F7 CLP_EN
IN
w
FILT+ M7 CODEC_FILTP
FILT- M6 31 AGND_CODEC
PP_CODEC_TO_MIC4_LOWER_BIAS
49
K12 MIC4_BIAS 1 C4832
49 IN
MIC4_LOWER_TO_CODEC_BIAS_FILT_RET H9 MIC4_BIAS_REF 10UF
20%
2 10V
X5R-CERM
0402-0.1MM
1 C4827 1 C4825 GND_A0 F3
ROOM=CODEC
1.0UF 1.0UF
20% 20% GND_A1 F5
2 10V
X5R-CERM 2 10V
X5R-CERM H11 G7
0201-1 0201-1 NC MIC5_BIAS GND_A2
ROOM=CODEC ROOM=CODEC G9 MIC5_BIAS_REF GND_A3 G8
NC
GND_A4 H5
H6
A GND_A5
GND_A6 J6 A
1 C4828 1 C4826 GND_A7 J8
1.0UF 1.0UF
20% 20% J11 MIC6_BIAS GND_A8 K8
2 10V 2 10V NC
X5R-CERM X5R-CERM H10 MIC6_BIAS_REF GND_A9 M5
0201-1 0201-1 NC
ROOM=CODEC ROOM=CODEC GND_A10 F6
G10 MICBIAS_DIS
GND_A11 G2
GND_A12 G3
GND_A13 G6 XW4802
£
31 AGND_CODEC 1 2
H
SHORT-10L-0.1MM-SM
"
ROOM=CODEC
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
TOUCH Discrete
C C
L5500 U5500 U5501
1UH-20%-1.8A-0.16OHM
FAN4861 SCY99223
am
PIGA1608-SM
rr
TOUCH_BOOST_LX B1 WLCSP PP5V5_TOUCH_BOOST WLCSP
1 2 SW VOUT B2 A1 IN
ROOM=TOUCH_VDDH ROOM=TOUCH_VDDH
ROOM=TOUCH_VDDH
OUT A2 PP5V1_TOUCH_VDDH 48
PP_VDD_MAIN 353S01844
50
A1 VIN 353S01892 FB C2 1 C5500 1 C5501 B1 EN 1 C5502 1 C5503
10UF 220PF
C5506 C1 GND 2.2UF 2.2UF
GND
1 EN 20% 5%
2.2UF 2 10V
X5R-CERM 2 25V
COG
20% 20%
2 10V 2 10V
B2
20% 0402-0.1MM 01005 X5R X5R
6.3V ROOM=TOUCH_VDDH ROOM=TOUCH_VDDH 0201 0201
A2
X5R-CERM 2 ROOM=TOUCH_VDDH ROOM=TOUCH_VDDH
0201
ROOM=TOUCH_VDDH CRITICAL CRITICAL
XW5500
= IO_TOUCH_TO_VDDH_EN SHORT-10L-0.1MM-SM
> <5
[ PP5V1_TOUCH_VDDH_TEST 1
^ 2
48 38 IN 38
ROOM=TOUCH_VDDH
NO_XNET_CONNECTION
B B
A A
CLEAR CLEAR
DOMAIN DOMAIN
PWR_100UM P PWR_100UM PP5V1_TOUCH_VDDH_TEST ? S_PWR_100UM S 100UM-249UM_SPACING PP5V1_TOUCH_VDDH_TEST ?

PWR_200UM P PWR_200UM PP5V1_TOUCH_VDDH,PP5V5_TOUCH_BOOST ? S_PWR_200UM S 100UM-249UM_SPACING PP5V1_TOUCH_VDDH,PP5V5_TOUCH_BOOST ?
SWITCHING S A_DIELECTRIC_1.5X TOUCH_BOOST_LX ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VDD_MAIN COMPARATORS
D D
VDD_MAIN OV CUT-OFF CIRCUIT
38 PP_VDD_MAIN_OV_R
Place near Hydra

353S01398
ROOM=OV_COMP
OMIT
U5900 XW5900
R5901 TPS3720-S
BGA
SHORT-20L-0.05MM-SM
ROOM=OV_COMP
100
<57>- 1
1 A1 VDD OUTA A2 2
50 34 PP_VDD_MAIN
AA5%/V2 PP_HYDRA_ACC1_OV_COMP PP_HYDRA_ACC1 36 49
1/32W
MF
01005
TC5901
1
5%
220PF
CRITICAL
GND
OUTB B2 IO_PMU_TO_DOTARA_RESET_L 22 49
NO_XNET_CONNECTION
T
ROOM=OV_COMP
2 25V
COG
B1
01005
C ROOM=OV_COMP
C
Voltage Threshold = 5.2V
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
353S01375 353S01398 ALT_PARTS U5900 ON SEMI
VDD_MAIN PRE-UPO COMPARATOR

PP1V8_IO 19 40 41 43 45 50 52 55
IQ=2.5uA
B B
CRITICAL
U5901
TLV4021S5
B1
PP_VDD_MAIN A2 IN DSBGA
50 39 38 21 20 3
V+ 353S01976
I_IN=1.65uA @3.3V A1 IO_AP_FROM_PMU_COMP_CPU_TRIGGER0_L 7 22
V- OPEN-DRAIN Comparator Output

Comparator Threshold (V_TH): ROOM=UPO_COMP 50K OHM (typ) pull-up in U1000
V_TH(falling) = 3.2V If V_IN > V_TH, then Output= High-Z
B2
V_TH(raising) = 3.254V If V_IN < V_TH, then Output= LOW
+/- 1% accuracy from -40C to 85C
A A
CLEAR
DOMAIN
PWR_50UM P PWR_50UM PP_VDD_MAIN_OV_R,PP_HYDRA_ACC1_OV_COMP ?
8 7 6 5 4 3 2 CDS_LIB=apple
1
8 7 6 5 4 3 2 1
D D
Gecko
GECKO Reset Pull Down
34 13
GPIO_NUB_TO_GECKO_RESET_L
1
I2C ADDRESS: 0X52
R6100
100K
5%
1/32W
MF
2 01005
50 33
PP_VDD_MAIN PP_VDD_BOOST 50
ROOM=GECKO
C6161 1 C6162 1
C
C 2.2UF
20%
2.2UF
20%
6.3V 2 6.3V 2 PLACE_NEAR=U6150.D4:2MM
X5R-CERM X5R-CERM
VDD_BYPASS D3
VDD_LDO D4
VDD_BUCK A3
0201 0201
ROOM=GECKO ROOM=GECKO
PLACE_NEAR=U6150.A3:2MM
CRITICAL
U6150 L6150
FAN53740UCA1X 0.47UH-20%-2.8A-0.067OHM
CSP
22 AMUX_PMU_FROM_GECKO D2 AMUX LX A4 LX_GECKO 1 2
n Qg n
OUT
353S01650 1210
54
I2C1_SMC_SCL B2 SCL
ROOM=GECKO
C3 ROOM=GECKO
IN
A2 VOUT C4
54 BI
I2C1_SMC_SDA SDA PP_ACC_VAR 36
"Hh
13 5 OUT
GPIO_NUB_FROM_GECKO_IRQ_L B1 IRQ* CRITICAL 1 C6150 1 C6151 1 C6152
A1 220PF 15UF 0.1UF
34 13 GPIO_NUB_TO_GECKO_RESET_L C1 RESET* 5% 20% 20%
IN NC D1 2 25V 2 6.3V 6.3V
2 X5R-CERM
COG X5R-CERM
PGND
01005 0402-0.1MM 01005
ROOM=GECKO ROOM=GECKO ROOM=GECKO
AGND OMIT_TABLE
B3
C2
B4
B B
IND Alternate TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
152S00853 152S00854 ALT_PARTS L6150 IND,PWR,0.47UH,20%,2.7A,TY
15uF Single Source

TABLE_5_HEAD

TABLE_5_ITEM
138S00003 1 CAP,15UF,6.3V,0402,MURATA C6151 CRITICAL CAP_15UF_SINGLE_SOURCE
A A
CLEAR
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* OVERRIDE
OVERRIDE DOMAIN
CLASS NAME
DOMAIN
PWR_SHAPE P PWR_SHAPE LX_GECKO,PP_ACC_VAR ? S_PWR_SHAPE S 250UM+_SPACING PP_ACC_VAR ?

SWITCHING S A_DIELECTRIC_1.5X LX_GECKO ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
USB-PD
50
PP1V8_S2
50
PP3V0_S2
C 1 C6290 1 C6291
PP1V8_VCCD_CCG2 C
1.0UF 1.0UF
20% 20%
2 10V
X5R-CERM 2 10V
X5R-CERM
1 C6292
0201-1 0201-1 1.0UF
ROOM=USB_PD ROOM=USB_PD 20%
n
2 10V
X5R-CERM NCNC
0201-1
C4
E3
A1
E1
E4
ROOM=USB_PD
TBD: C6290,C6291 may be repaced by 0.1uF. Location dependant
PP_VAR_USB_RVP
VDDD
VCCD
VDDIO
VCONN2
VCONN1
49 36
1
R6210
499K
1%
1/20W
MF
201
2ROOM=USB_PD
13 5
=
<
OUT i
GPIO_NUB_FROM_CCG2_INT_L
PP5V0_USB_RVP_R
NC
C3
D3
C2
D2
GPIO_C3 CRITICAL
GPIO_D3 U6200
GPIO_C2 WLCSP
ROOM=USB_PD
CC1
CC2
RD1
B4
A4
B3
IO_CCG2_CC1_BI_HYDRA_CC0
1
5%
C6200
220PF
BI 36
1 NC GPIO_D2
R6211 2 25V
50K
1 C6210 NC
B2 GPIO_B2 COG
01005
1% 22NF CG8889ATT ROOM=USB_PD
1/32W 20% 54 IN
I2C0_SMC_SCL A3 I2C_0_SCL XRES B1 GPIO_PMU_TO_CCG2_RESET_L IN 56
MF 2 6.3V A2
2 01005
X5R-CERM
01005 54 BI
I2C0_SMC_SDA I2C_0_SDA
ROOM=USB_PD ROOM=USB_PD E2
56 BI
GPIO_AP_BI_CCG2_SWDIO SWD_IO
56 5 GPIO_AP_TO_CCG2_SWCLK D1 SWD_CLK
IN
VSS VSS
D4
C1
B B
A A
CLEAR
DOMAIN
PWR_80UM P PWR_80UM PP1V8_VCCD_CCG2, PP5V0_USB_RVP_R ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
Hydra
I2C Address: 0011010X
50
PP3V0_S2 PP_ACC_VAR 34
1 C6390 1 C6391
1.0UF 0.1UF 50
PP1V8_S2
20% 20%
2 10V 2 6.3V
X5R-CERM X5R-CERM 1 C6395 C
C 0201-1
ROOM=HYDRA
01005
ROOM=HYDRA
0.01UF
10%
2 6.3V
H4
H5
C6
D6
A6
B6
E6
X5R
01005
ROOM=HYDRA VDD1V8 VDD3V0
ACC_PWR
U6300 From Yangtze

90_MIKEYBUS_DATA_P C2 CBTL1612A1 G6 PP_VAR_USB_RVP
DIG_DP P_IN
00 00
30 BI 35 49
WLCSP
30 BI
90_MIKEYBUS_DATA_N D2 DIG_DN ACC1 A5 PP_HYDRA_ACC1 33 49
ROOM=HYDRA
Debug USB Tracker rdar: 29792849 90_USB_DBG_DATA_P D3 USB1_DP CRITICAL ACC1 B5 1 C6311 1 C6312
13 BI
ACC1 C5 0.47UF 0.47UF
13
90_USB_DBG_DATA_N D4 USB1_DN 20% 20%
BI
343S00204 ACC1 D5 2 25V 2 25V
CER-X5R CER-X5R
30 22 IO_HYDRA_TO_PMU_USB_BRICK_ID_TIA F3 BRICK_ID ACC1 E5 0201 0201
OUT
ACC2 A7 PP_HYDRA_ACC2 49
ROOM=HYDRA ROOM=HYDRA
90_USB_AP_DATA_L_P B3 USB0_DP
ACC2 B7
90_USB_AP_DATA_L_N B4 USB0_DN
ACC2 C7
UART7_AP_TO_ACCESSORY_TXD D1 UART0_TX ACC2 D7
DQDQD
11 5 IN
11 5 OUT
UART7_AP_FROM_ACCESSORY_RXD C1 UART0_RX ACC2 E7
UART0_AP_DEBUG_TXD F2 UART1_TX DP1 C3 90_HYDRA_DP1_CONN_P
000 00 0 00 00
11 IN BI 49
11 OUT
UART0_AP_DEBUG_RXD E2 UART1_RX DN1 C4 90_HYDRA_DP1_CONN_N BI 49
GPIO_ISP_RCAM_TO_STROBE_TRIGGER B1 UART2_TX DP2 A3 90_HYDRA_DP2_CONN_P

L6300 42 41 40 38 9 IN BI 49
I
15NH-250MA A1 UART2_RX DN2 A4 90_HYDRA_DP2_CONN_N 49
NC BI
90_USB_AP_DATA_P 1 2 SWD_DOCK_TO_AP_SWCLK E1 JTAG_CLK CON_DET_L G3 IO_E75_TO_HYDRA_CON_DETECT_L

non
7 BI 13 OUT IN 49
GND_VOID
0201 13
SWD_DOCK_BI_AP_SWDIO F1 JTAG_DIO IO_HYDRA_TO_CHARGER_VBUS1_VALID_L
ROOM=HYDRA
BI
POW_GATE_EN* H3 OUT 49
IO_HYDRA_TO_AP_FORCE_DFU H2 FORCE_DFU
B L6301 38 7 OUT
SWITCH_EN E4 IO_PMU_TO_AP_HYDRA_ACTIVE_READY IN 5 7 22
B
15NH-250MA G2 EXT_SW_EN HOST_RESET F6 IO_HYDRA_TO_PMU_RESET
I
22
NC OUT
90_USB_AP_DATA_N 1 2 IO_HYDRA_TO_NUB_PMU_DOCK_CONNECT G1 DOCK_CONNECT
On
7 BI
GND_VOID
22 13 OUT
SDA G5 I2C1_SMC_SDA BI 54
0201
ROOM=HYDRA 35 BI
IO_CCG2_CC1_BI_HYDRA_CC0 B2 CC0 SCL G4 I2C1_SMC_SCL IN 54
A2 CC1 INT F7 IO_HYDRA_TO_NUB_DOCK_ATTENTION OUT 13
BYPASS F5 ANALOG_HYDRA_BYPASS
R6310
0.00
38 22 BI
AMUX_PMU_BY 1 2 AMUX_PMU_BY_R DVSS
DVSS1
1 C6330
0% 1.0UF
1
R6311 20%
E3
G7
H1
H6
H7
F4
1/32W
MF 2 10V
X5R-CERM
01005 0.00 0201-1
ROOM=HYDRA 0% ROOM=HYDRA
NOSTUFF 1/32W
MF
2 01005
ROOM=HYDRA
A A
CLEAR
DOMAIN
CLEAR
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* OVERRIDE
DOMAIN
PWR_80UM P PWR_80UM PP_VAR_USB_RVP ? CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
PWR_SHAPE P PWR_SHAPE PP_HYDRA_ACC1,PP_HYDRA_ACC1_CONN,PP_HYDRA_ACC2* ? S_PWR_SHAPE S 250UM+_SPACING PP_HYDRA_ACC* ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
ROOM=B2B_INTERPOSER
998-18081 998-18081 998-18081
J_INT_BOT J_INT_BOT J_INT_BOT
SM SM SM
SYM 1 OF 3 SYM 2 OF 3 SYM 3 OF 3
GND 1 95 GND GND 189 IO189 IO283 283 PP_VDD_MAIN 50_ANT4 377 IO377 461 50_UHBPA_2G_LB_OUT
38 IO1 IO95 38 38 38 38 IO461 38
INTERPOSER-MLB-DR-BOT-D4X
GND 2 96 GND GND 190 IO190 IO284 284 PP_VDD_MAIN GND 378 IO378 462 GND
38 IO2 IO96 38 38 38 38 IO462 38
GND 3 97 90_PCIE4_AP_TO_BB_C_TX_N GND 191 IO191 IO285 285 PP_VDD_MAIN GND 379 IO379 463 GND
38 IO3 IO97 38 38 38 38 IO463 38
GND 4 98 GND_VOID
GND GND 192 IO192 IO286 286 PP_VDD_MAIN GND 380 IO380 IO464 464 50_WLAN_G_LAT
38 IO4 IO98 38 38 38 38 38
GND 5 99 90_PCIE4_AP_TO_BB_C_TX_P RFFE_XCVR_TO_LBTX_CLK 193 IO193 IO287 287PDM_OUT1_CODEC_TO_SPKAMP_TOP_CLK 50_ANT2 381 IO381 IO465 465 GND
38 IO5 IO99 38 38 38 38 38
GPIO_AP_CANARY2 6 100 GND_VOID

GND RFFE_XCVR_TO_LBTX_DATA 194 IO194 IO288 288 GND GND 382 IO382 IO466 466 GND
38 IO6 IO100 38 38 38 38 38
GND 7 101 GND GND 195 IO195 IO289 289

I2S1_AOP_AMPS_FROM_CODEC_ASP2_BCLK GND 383 IO383 IO467 467 GND
38 IO7 IO101 38 38 38 38 38
D 38 NFC_ANT 8
IO8 IO102 102 GND 38 38 GND 196 IO196 IO290 290 GPIO_AP_FROM_SPKRAMP_TOP_INT_L 38 38 GND 384 IO384 IO468 468 50_MMDSM_UHB_ANT 38 D
GND 9 103 GND GND 197 IO197 IO291 291
I2S1_AOP_FROM_AMPS_CODEC_ASP2_DIN 50_ANT6_UHB 385 IO385 IO469 469 GND
38 IO9 IO103 38 38 38 38 38
NFC_ANT 10 104 50_LAA_TO_XCVR_LAT GND 198 IO198 IO292 292 GND GND 386 IO386 IO470 470 50_LB_TX_ANT1
38 IO10 IO104 38 38 38 38 38
GND 11 105 GND RFA1_SW_CTRL2 199 IO199 293

IO293 I2S1_AOP_AMPS_FROM_CODEC_ASP2_LRCLK GND 387 IO387 IO471 471 GND
38 IO11 IO105 38 38 38 38 38
GND 12 106 GND VFE_LO_1V2 200 IO200 IO294 294 GPIO_AP_TO_SPKRAMP_TOP_RESET_L GND 388 IO388 IO472 472 GND
38 IO12 IO106 38 38 38 38 38
GND 13 107 50_WLAN_A_TX1 GND 201 IO201 295

IO295 PDM_OUT1_CODEC_TO_SPKRAMP_TOP_DATA GND 389 IO389 IO473 473 GND
38 IO13 IO107 38 38 38 38 38
PP_VDD_MAIN 14 108 50_XCVR_TX1_HB 50_XCVR_RX2_UHB_PRX 202 IO202 IO296 296 GND GND 390 IO390 IO474 474 LAT_SAWTOOTH_B
38 IO14 IO108 38 38 38 38 38
GND 15 109 GND GND 203 IO203 IO297 297 PP1V2_S2 GND 391 IO391 IO475 475 GND
38 IO15 IO109 38 38 38 38 38
PP_VDD_MAIN 16 110 GND GND 204 IO204 IO298 298 GPIO_AOP_TO_WLAN_CONTEXT_A GND 392 IO392 IO476 476 GND
38 IO16 IO110 38 38 38 38 38
GND 17 111 50_WLAN_A_RX1_LAA GND 205 IO205 IO299 299 PP1V8_S2 GND 393 IO393 IO477 477 GND
38 IO17 IO111 38 38 38 38 38
GND 18 112 50_XCVR_TX1_MB1 50_UHBPA_UHB 206 IO206 IO300 300 GND GND 394 IO394 IO478 478 GND
38 IO18 IO112 38 38 38 38 38
GND 19 113 GND GND 207 IO207 IO301 301 I2C2_AP_SDA GND 395 IO395 IO479 479 GND
38 IO19 IO113 38 38 38 38 38
PP_STROBE_DRIVER_COOL_LED 20 114 GND GND 208 IO208 IO302 302 GPIO_AOP_TO_WLAN_CONTEXT_B GND 396 IO396 IO480 480 GND
38 IO20 IO114 38 38 38 38 38
GND 21 115 GND GND 209 IO209 IO303 303 GPIO_TOUCH_TO_MANY_SCAN_ACTIVE PP1V2_S4 397 IO397 IO481 481 GND
38 IO21 IO115 38 38 38 38 38
PP_STROBE_DRIVER_WARM_LED 22 116 GND 5GHZ_C1_VDET 210 IO210 IO304 304 GND GND 398 IO398 IO482 482 50_XCVR_RX14_LB_MLB_PRX38
38 IO22 IO116 38 38 38 38
GND 23 117 50_XCVR_TX0_MB2 GND 211 IO211 IO305 305 I2C_R1_BI_NFC_SDA GND 399 IO399 IO483 483 GND
38 IO23 IO117 38 38 38 38 38
GND 24 118 GND RFA1_SW_CTRL1 212 IO212 IO306 306 GND GND 400 IO400 IO484 484 GND
38 IO24 IO118 38 38 38 38 38
GND 25 119 GND GND 213 IO213 IO307 307 GND GND 401 IO401 IO485 485 VIO_RFFE_XCVR_TO_RX_1V838
38 IO25 IO119 38 38 38 38
GND 26 120 GND GND 214 IO214 IO308 308 IO_BB_TO_R1_COEX GND 402 IO402 IO486 486 RFFE_XCVR_TO_FE_RX_DATA38
38 IO26 IO120 38 38 38 38
GND 27 121 GND IO_PMU_TO_SYSTEM_RESET_L 215 IO215 IO309 309 GND GND 403 IO403 IO487 487 RFFE_XCVR_TO_FE_RX_CLK 38
38 IO27 IO121 38 38 38 38
GND 28 122 VPA_2G I2S2_AP_TO_BB_DOUT 216 IO216 IO310 310 GND GND 404 IO404 IO488 488 VIO_RFFE_XCVR_TO_TX_1V838
38 IO28 IO122 38 38 38 38
GND 29 123 50_XCVR_TX1_UHB GND 217 IO217 IO311 311 IO_R1_TO_WLAN_COEX GND 405 IO405 IO489 489 RFFE_XCVR_TO_HBTX_DATA 38
38 IO29 IO123 38 38 38 38
GND 30 124 VPA_ET_UHB I2S2_AP_FROM_BB_DIN 218 IO218 IO312 312 I2C_R1_TO_NFC_SCL GPIO_PMU_TO_WLAN_REG_ON 406 IO406 IO490 490 RFFE_XCVR_TO_HBTX_CLK 38
38 IO30 IO124 38 38 38 38
GND 31 125 GND GPIO_NUB_TO_BBPMU_CLK_EN 219 IO219 IO313 313 GND GND 407 IO407 IO491 491 GND
38 IO31 IO125 38 38 38 38 38
GND 32 126 VPA_2G I2S2_AP_FROM_BB_BCLK 220 IO220 IO314 314 GND GND 408 IO408 IO492 492 VFE_HI_3V15
38 IO32 IO126 38 38 38 38 38
GPIO_AP_FROM_BT_AUDIO_SYNC 33 IO127 127 VPA_ET_UHB GND 221 IO221 IO315 315 GND GND 409 IO409 IO493 493 GND
38 IO33 38 38 38 38 38
UART4_AP_FROM_NFC_CTS_L 34 IO128 128 GND I2S2_AP_FROM_BB_LRCLK 222 IO222 IO316 316 GND 410 IO410
GPIO_PMU_FROM_BB_PCIE_HOST_WAKE_1V2_L IO494 494 GND
IO34
C 38
38 GPIO_AP_TO_NFC_DEV_WAKE 35
IO35 IO129 129 50_XCVR_TX0_MB3
38
38
38
38
223
GPIO_AP_FROM_BB_RESET_DETECT_1V2_L IO223 IO317 317 GND
38
38
38
38 I2C2_CAM_PMU1_SCL 411 IO411 IO495 495 50_HBPA_ANT3

38
38
C
38 UART4_AP_FROM_NFC_RXD 36 IO36 IO130 130 VPA_2G 38 38 I2S0_AP_TO_SPKAMP_TOP_MCLK 224 IO224 IO318 318 GND 38 38 GND 412 IO412 IO496 496 GND 38
GND 37 IO131 131 VPA_ET_UHB GND 225 IO225 IO319 319 GND I2C2_CAM_PMU1_SDA 413 IO413 IO497 497 GND
38 IO37 38 38 38 38 38
UART4_AP_TO_NFC_TXD 38 IO132 132 GND GPIO_AP_TO_BB_COREDUMP_1V2 226 IO226 IO320 320 IO_TOUCH_TO_VDDH_EN PP1V8_S4 414 IO414 IO498 498 50_XCVR_RX8_MLB_HB_PRX 38
38 IO38 38 38 38 38
GND 39 IO133 133 50_XCVR_TX0_HB PCIE4_AP_TO_BB_PERST_1V2_L 227 IO227 IO321 321 IO_WLAN_TO_R1_COEX PP1V8_NFC_S2 415 IO415 IO499 499 GND
38 IO39 38 38 38 38 38
SWD_AP_BI_BB_SWDIO 40 IO134 134 GND GND 228 IO228 IO322 322 PP5V1_TOUCH_VDDH_TEST GND 416 IO416 IO500 500 GND
38 IO40 38 38 38 38 38
GND 41 IO135 135 GND PCIE3_AP_BI_WLAN_CLKREQ_1V2_L 229 IO229 IO323 323 GPIO_BT_TO_R1_DEV_WAKE AMUX_PMU_AY 417 IO417 IO501 501 50_XCVR_RX9_MLB_HB_PRX 38
38 IO41 38 38 38 38
UART4_AP_TO_NFC_RTS_L 42 IO136 136 GND GPIO_AP_FROM_WLAN_TIME_SYNC_1V2 230 IO230 IO324 324 GND GPIO_PMU_FROM_WLAN_HOST_WAKE 418 IO418 IO502 502 GND
38 IO42 38 38 38 38 38
PP_GPU_LVCC 43 IO137 137 50_CPLL_CPLOUT2 PCIE3_AP_TO_WLAN_PERST_1V2_L 231 IO231 IO325 325 IO_BT_TO_R1_TIME_SYNC GPIO_ISP_RCAM_TO_STROBE_TRIGGER 419 IO419 IO503 503 GND
38 IO43 38 38 38 38 38
UART2_AOP_FROM_BB_RXD 44 IO138 138 GND GND 232 IO232 IO326 326 SPKRAMP_TOP_TO_COIL_OUT_POS GND 420 IO420 IO504 504 GND
38 IO44 38 38 38 38 38
GND 45 IO139 139 GND GND 233 IO233 IO327 327 GND GPIO_BB_TO_MANY_GSM_BURST_IND 421 IO421 IO505 505 GND
38 IO45 38 38 38 38 38
SWD_NUB_TO_MANY_SWCLK 46 IO140 140 50_CPLL_CPLOUT1 PCIE4_AP_BI_BB_CLKREQ_1V2_L 234 IO234 IO328 328 COIL_TO_SPKRAMP_TOP_VSENSE_POS GPIO_PMU_TO_BBPMU_RESET_L 422 IO422 IO506 506 GND
38 IO46 38 38 38 38 38
PP_CPU_PCORE_LVCC 47 IO141 141 VPA_ET_HB GND 235 IO235 IO329 329 SPKRAMP_TOP_TO_COIL_OUT_POS 423 IO423
GPIO_CAM_PMU1_TO_STROBE_DRIVER_HWEN
38 IO47 38 38 38 38
GPIO_AOP_FROM_HALL_CASE_INT_L 48 IO142 142 GND GND 236 IO236 IO330 330 COIL_TO_SPKRAMP_TOP_VSENSE_NEG GND 424 IO424
38 IO48 38 38 38 38
GND 49 IO143 143 GND CLK_BBPMU_TO_DOTARA_38M4_1V8 237 IO237 IO331 331 GND CLK_GPIO_PMU_TO_WLAN_R1_32K 425 IO425
38 IO49 38 38 38 38
GPIO_AOP_FROM_NFC_HOST_WAKE 50 IO144 144 GND GND 238 IO238 IO332 332 SPKRAMP_TOP_TO_COIL_OUT_NEG GPIO_PMU_TO_NFC_EN 426 IO426
38 IO50 38 38 38 38
I2C2_AP_SCL 51 IO145 145 GND IO_SPKAMP_TO_SPKAMP_SYNC 239 IO239 IO333 333 SPKRAMP_TOP_TO_COIL_OUT_NEG NTC_STROBE_MODULE 427 IO427
38 IO51 38 38 38 38
GND 52 IO146 146 GND GND 240 IO240 IO334 334 GND GND 428 IO428
38 IO52 38 38 38 38
UART2_AOP_TO_BB_TXD 53 IO147 147 VPA_ET_HB GND 241 IO241 IO335 335 GND GND 429 IO429
38 IO53 38 38 38 38
GND 54 IO148 148 GND IO_BT_TO_BOT_SPK_TRIG 242 IO242 IO336 336 RFFE_LAA_UAT_VIO AMUX_PMU_BY 430 IO430
38 IO54 38 38 38 38
GND 55 IO149 149 GND GND 243 IO243 IO337 337 RFFE_LAA_UAT_CLK GND 431 IO431
38 IO55 38 38 38 38
38 IO56 38 38 38 38
GND 57 IO151 151 GND GND 245 IO245 IO339 339 RFFE_LAA_UAT_DATA GND 433 IO433
38 IO57 38 38 38 38
GND 58 IO152 152 GND GND 246 IO246 IO340 340 5GHZ_C0_VDET GND 434 IO434
38 IO58 38 38 38 38
GND 59 IO153 153 VPA_ET_HB NTC_RADIO_BB_N 247 IO247 IO341 341 GND GND 435 IO435
38 IO59 38 38 38 38
38 GND 60 IO60 IO154 154 GND 38 38 GND 248 IO248 IO342 342 GND 38 38 GND 436 IO436
B 38 SPMI1_AOP_TO_RF_CLK 61 IO61 IO155 155 GND 38 38 NTC_RADIO_BB_P 249 IO249 IO343 343 50_WLAN_A_TX0 38 38 GND 437 IO437 B
38 IO62 38 38 38 38
SPMI1_AOP_BI_RF_DATA 63 IO157 157 GND GND 251 IO251 IO345 345 GND GND 439 IO439
38 IO63 38 38 38 38
38 GND 64 IO64 IO158 158 GND 38 38 GND 252 IO252 IO346 346 50_WLAN_A_RX0_LAA 38 38 GND 440 IO440
GND 65 IO159 159 GND PP_VDD_MAIN_OV_R 253 IO253 IO347 347 GND GND 441 IO441
38 IO65 38 38 38 38
38 IO66 38 38 38 38
90_PCIE3_AP_TO_WLAN_REFCLK_N 67 IO161 161 GND GND 255 IO255 IO349 349 50_LAA_TO_XCVR_UAT GND 443 IO443
38
GND_VOID
IO67 38 38 38 38
38 IO68 38 38 38 38
90_PCIE3_AP_TO_WLAN_REFCLK_P 69 IO163 163 GND IO_NFC_TO_ARC_RESET_L 257 IO257 IO351 351 GND GND 445 IO445
38
GND_VOID
IO69 38 38 38 38
GND 70 IO164 164 GND GND 258 IO258 IO352 352 GND 50_XCVR_TX0_LB2 446 IO446
38 IO70 38 38 38 38
GND 71 IO165 165 GND GND 259 IO259 IO353 353 RFA0_SW_CTRL2 GND 447 IO447
38 IO71 38 38 38 38
GND 72 IO166 166 GND IO_NFC_TO_ARC_TRIG 260 IO260 IO354 354 GND GND 448 IO448
38 IO72 38 38 38 38
90_PCIE4_AP_TO_BB_REFCLK_PGND_VOID 73 IO167 167 GND GPIO_PMU_FROM_CHARGER_INT_L 261 IO261 IO355 355 GND 50_XCVR_TX0_MB1 449 IO449
38 IO73 38 38 38 38
GND 74 IO168 168 GND I2S1_AOP_TO_AMPS_CODEC_ASP2_DOUT262 IO262 IO356 356 GND GND 450 IO450
38 IO74 38 38 38 38
90_PCIE4_AP_TO_BB_REFCLK_NGND_VOID 75 IO169 169 GPIO_AP_CANARY1 GND 263 IO263 IO357 357 IO_R1_TO_BB_LAA_SW_CTRL GND 451 IO451
38 IO75 38 38 38 38
GND 76 IO170 170 GND IO_HYDRA_TO_AP_FORCE_DFU 264 IO264 IO358 358 GND GND 452 IO452
38 IO76 38 38 38 38
GND 77 IO171 171 50_XCVR_RX6_MB_UHB_PRX GND 265 IO265 IO359 359 RFA0_SW_CTRL1 GND 453 IO453
38 IO77 38 38 38 38
38 IO78 38 38 38 38
90_PCIE3_AP_TO_WLAN_C_TX_PGND_VOID 79 IO173 173 GND GND 267 IO267 IO361 361 GND GND 455 IO455
38 IO79 38 38 38 38
GND 80 IO174 174 GND GND 268 IO268 IO362 362 RFA0_SW_CTRL0 GND 456 IO456
38 IO80 38 38 38 38
90_PCIE3_AP_TO_WLAN_C_TX_N 81 IO175 175 GND GND 269 IO269 IO363 363 GND GND 457 IO457
38 IO81 38 38 38 38
GND
GND_VOID 82 IO176 176 GND GND 270 IO270 IO364 364 GND GND 458 IO458
38 IO82 38 38 38 38
GND 83 IO177 177 50_XCVR_RX10_MLB_HB_PRX GND 271 IO271 IO365 365 GND GND 459 IO459
38 IO83 38 38 38 38
GND 84 IO178 178 LAT_SAWTOOTH_A GND 272 IO272 IO366 366 GND GND 460 IO460
38 IO84 38 38 38 38
90_PCIE3_AP_FROM_WLAN_C_RX_N 85 IO179 179 GND GND 273 IO273 IO367 367 GND
38
GND_VOID
IO85 38 38 38
GND 86 IO180 180 GND GND 274 IO274 IO368 368 GND
IO86
A 38
38 90_PCIE3_AP_FROM_WLAN_C_RX_P
GND_VOID
87
IO87 IO181 181 GND
38
38
38
38 GND 275 IO275 IO369 369 GND

38
38 A
38 IO88 38 38 38
GND 89 IO183 183 RFA1_SW_CTRL0 GND 277 IO277 IO371 371 UAT_SAWTOOTH_B
38 IO89 38 38 38
GND 90 IO184 184 50_HBPA_DRX_OUT GND 278 IO278 IO372 372 GND
38 IO90 38 38 38
90_PCIE4_AP_FROM_BB_C_RX_N 91 IO185 185 GND GND 279 IO279 IO373 373 UAT_SAWTOOTH_A
38
GND_VOID
IO91 38 38 38
38 IO92 38 38 38
90_PCIE4_AP_FROM_BB_C_RX_P 93 IO187 187 GND GND 281 IO281 IO375 375 GND
38
GND_VOID
IO93 38 38 38
GND 94 IO188 188 50_MMDSM_MHB_ANT PP_VDD_MAIN 282 IO282 IO376 376 GND
38 IO94 38 38 38
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 I2C2_AP_SDA MAKE_BASE=TRUE I2C2_AP_SDA 11 53 37 GND MAKE_BASE=TRUE GND 37 50_XCVR_RX9_MLB_HB_PRX MAKE_BASE=TRUE 50_XCVR_RX9_MLB_HB_PRX 58
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 50_XCVR_RX2_UHB_PRX MAKE_BASE=TRUE 50_XCVR_RX2_UHB_PRX 58 37 GPIO_AOP_TO_WLAN_CONTEXT_B MAKE_BASE=TRUE GPIO_AOP_TO_WLAN_CONTEXT_B 56 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GPIO_TOUCH_TO_MANY_SCAN_ACTIVE MAKE_BASE=TRUE GPIO_TOUCH_TO_MANY_SCAN_ACTIVE 22 23 25 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
48 49
37 GND MAKE_BASE=TRUE GND 37 50_LAA_TO_XCVR_LAT MAKE_BASE=TRUE 50_LAA_TO_XCVR_LAT 58 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 I2C_R1_BI_NFC_SDA MAKE_BASE=TRUE I2C_R1_BI_NFC_SDA 58 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 GPIO_AP_CANARY2 MAKE_BASE=TRUE GPIO_AP_CANARY2 56 37 GND MAKE_BASE=TRUE GND 37 50_UHBPA_UHB MAKE_BASE=TRUE 50_UHBPA_UHB 58 37 GND MAKE_BASE=TRUE GND 37 GPIO_PMU_TO_WLAN_REG_ON MAKE_BASE=TRUE GPIO_PMU_TO_WLAN_REG_ON 56 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 50_WLAN_A_TX1 MAKE_BASE=TRUE 50_WLAN_A_TX1 58 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 NFC_ANT MAKE_BASE=TRUE NFC_ANT 38 44 37 50_XCVR_TX1_HB MAKE_BASE=TRUE 50_XCVR_TX1_HB 58 37 GND MAKE_BASE=TRUE GND 37 IO_BB_TO_R1_COEX MAKE_BASE=TRUE IO_BB_TO_R1_COEX 58 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 NFC_ANT MAKE_BASE=TRUE NFC_ANT 38 44 37 GND MAKE_BASE=TRUE GND 37 5GHZ_C1_VDET MAKE_BASE=TRUE 5GHZ_C1_VDET 58 37 GND MAKE_BASE=TRUE GND 37 GPIO_PMU_FROM_BB_PCIE_HOST_WAKE_1V2_L MAKE_BASE=TRUE GPIO_PMU_FROM_BB_PCIE_HOST_WAKE_1V2_L 56
D 37 GND MAKE_BASE=TRUE GND 37 50_WLAN_A_RX1_LAA MAKE_BASE=TRUE 50_WLAN_A_RX1_LAA 58 37 GND MAKE_BASE=TRUE GND 37 IO_R1_TO_WLAN_COEX MAKE_BASE=TRUE IO_R1_TO_WLAN_COEX 58 37 I2C2_CAM_PMU1_SCL MAKE_BASE=TRUE I2C2_CAM_PMU1_SCL 25 55 D
37 GND MAKE_BASE=TRUE GND 37 50_XCVR_TX1_MB1 MAKE_BASE=TRUE 50_XCVR_TX1_MB1 58 37 RFA1_SW_CTRL1 MAKE_BASE=TRUE RFA1_SW_CTRL1 58 37 I2C_R1_TO_NFC_SCL MAKE_BASE=TRUE I2C_R1_TO_NFC_SCL 58 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 I2C2_CAM_PMU1_SDA MAKE_BASE=TRUE I2C2_CAM_PMU1_SDA 25 55
37 PP_VDD_MAIN MAKE_BASE=TRUE PP_VDD_MAIN 3 20 21 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 PP1V8_S4 MAKE_BASE=TRUE PP1V8_S4 19 21 58
33 38 39 50
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 IO_PMU_TO_SYSTEM_RESET_L MAKE_BASE=TRUE IO_PMU_TO_SYSTEM_RESET_L 13 22 37 GND MAKE_BASE=TRUE GND 37 PP1V8_NFC_S2 MAKE_BASE=TRUE PP1V8_NFC_S2 19
37 PP_VDD_MAIN MAKE_BASE=TRUE PP_VDD_MAIN 3 20 21 37 GND MAKE_BASE=TRUE GND 37 I2S2_AP_TO_BB_DOUT MAKE_BASE=TRUE I2S2_AP_TO_BB_DOUT 11 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
33 38 39 50
37 GND MAKE_BASE=TRUE GND 37 50_XCVR_TX0_MB2 MAKE_BASE=TRUE 50_XCVR_TX0_MB2 58 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 AMUX_PMU_AY MAKE_BASE=TRUE AMUX_PMU_AY 22
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 I2S2_AP_FROM_BB_DIN MAKE_BASE=TRUE I2S2_AP_FROM_BB_DIN 11 37 GND MAKE_BASE=TRUE GND 37 GPIO_PMU_FROM_WLAN_HOST_WAKE MAKE_BASE=TRUE GPIO_PMU_FROM_WLAN_HOST_WAKE 56
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GPIO_NUB_TO_BBPMU_CLK_EN MAKE_BASE=TRUE GPIO_NUB_TO_BBPMU_CLK_EN 13 37 GND MAKE_BASE=TRUE GND 37 GPIO_ISP_RCAM_TO_STROBE_TRIGGER MAKE_BASE=TRUE GPIO_ISP_RCAM_TO_STROBE_TRIGGER 9 36 40 41 42
37 PP_STROBE_DRIVER_COOL_LED MAKE_BASE=TRUE PP_STROBE_DRIVER_COOL_LED 44 37 GND MAKE_BASE=TRUE GND 37 I2S2_AP_FROM_BB_BCLK MAKE_BASE=TRUE I2S2_AP_FROM_BB_BCLK 11 37 IO_TOUCH_TO_VDDH_EN MAKE_BASE=TRUE IO_TOUCH_TO_VDDH_EN 32 48 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 IO_WLAN_TO_R1_COEX MAKE_BASE=TRUE IO_WLAN_TO_R1_COEX 58 37 GPIO_BB_TO_MANY_GSM_BURST_IND MAKE_BASE=TRUE GPIO_BB_TO_MANY_GSM_BURST_IND 46
37 PP_STROBE_DRIVER_WARM_LED MAKE_BASE=TRUE PP_STROBE_DRIVER_WARM_LED 44 37 VPA_2G MAKE_BASE=TRUE VPA_2G 38 37 I2S2_AP_FROM_BB_LRCLK MAKE_BASE=TRUE I2S2_AP_FROM_BB_LRCLK 11 37 PP5V1_TOUCH_VDDH_TEST MAKE_BASE=TRUE PP5V1_TOUCH_VDDH_TEST 32 37 GPIO_PMU_TO_BBPMU_RESET_L MAKE_BASE=TRUE GPIO_PMU_TO_BBPMU_RESET_L 56
58
37 GND MAKE_BASE=TRUE GND 37 50_XCVR_TX1_UHB MAKE_BASE=TRUE 50_XCVR_TX1_UHB 58 37 GPIO_AP_FROM_BB_RESET_DETECT_1V2_L MAKE_BASE=TRUE GPIO_AP_FROM_BB_RESET_DETECT_1V2_L 56 37 GPIO_BT_TO_R1_DEV_WAKE MAKE_BASE=TRUE GPIO_BT_TO_R1_DEV_WAKE 58 37 GPIO_CAM_PMU1_TO_STROBE_DRIVER_HWEN MAKE_BASE=TRUE GPIO_CAM_PMU1_TO_STROBE_DRIVER_HWEN 25
37 GND MAKE_BASE=TRUE GND 37 VPA_ET_UHB MAKE_BASE=TRUE VPA_ET_UHB 38 37 I2S0_AP_TO_SPKAMP_TOP_MCLK MAKE_BASE=TRUE I2S0_AP_TO_SPKAMP_TOP_MCLK 11 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
58
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 IO_BT_TO_R1_TIME_SYNC MAKE_BASE=TRUE IO_BT_TO_R1_TIME_SYNC 58 37 CLK_GPIO_PMU_TO_WLAN_R1_32K MAKE_BASE=TRUE CLK_GPIO_PMU_TO_WLAN_R1_32K 22 56 58
37 GND MAKE_BASE=TRUE GND 37 VPA_2G MAKE_BASE=TRUE VPA_2G 38 37 GPIO_AP_TO_BB_COREDUMP_1V2 MAKE_BASE=TRUE GPIO_AP_TO_BB_COREDUMP_1V2 56 37 SPKRAMP_TOP_TO_COIL_OUT_POS MAKE_BASE=TRUE SPKRAMP_TOP_TO_COIL_OUT_POS 38 46 37 GPIO_PMU_TO_NFC_EN MAKE_BASE=TRUE GPIO_PMU_TO_NFC_EN 56
58
37 GND MAKE_BASE=TRUE GND 37 VPA_ET_UHB MAKE_BASE=TRUE VPA_ET_UHB 38 37 PCIE4_AP_TO_BB_PERST_1V2_L MAKE_BASE=TRUE PCIE4_AP_TO_BB_PERST_1V2_L 8 37 GND MAKE_BASE=TRUE GND 37 NTC_STROBE_MODULE MAKE_BASE=TRUE NTC_STROBE_MODULE 44
58
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 COIL_TO_SPKRAMP_TOP_VSENSE_POS MAKE_BASE=TRUE COIL_TO_SPKRAMP_TOP_VSENSE_POS 46 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 50_XCVR_TX0_MB3 MAKE_BASE=TRUE 50_XCVR_TX0_MB3 58 37 PCIE3_AP_BI_WLAN_CLKREQ_1V2_L MAKE_BASE=TRUE PCIE3_AP_BI_WLAN_CLKREQ_1V2_L 8 37 SPKRAMP_TOP_TO_COIL_OUT_POS MAKE_BASE=TRUE SPKRAMP_TOP_TO_COIL_OUT_POS 38 46 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 VPA_2G MAKE_BASE=TRUE VPA_2G 38 37 GPIO_AP_FROM_WLAN_TIME_SYNC_1V2 MAKE_BASE=TRUE GPIO_AP_FROM_WLAN_TIME_SYNC_1V2 56 37 COIL_TO_SPKRAMP_TOP_VSENSE_NEG MAKE_BASE=TRUE COIL_TO_SPKRAMP_TOP_VSENSE_NEG 46 37 AMUX_PMU_BY MAKE_BASE=TRUE AMUX_PMU_BY 22 36
58
37 GND MAKE_BASE=TRUE GND 37 VPA_ET_UHB MAKE_BASE=TRUE VPA_ET_UHB 38 37 PCIE3_AP_TO_WLAN_PERST_1V2_L MAKE_BASE=TRUE PCIE3_AP_TO_WLAN_PERST_1V2_L 8 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
58
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 SPKRAMP_TOP_TO_COIL_OUT_NEG MAKE_BASE=TRUE SPKRAMP_TOP_TO_COIL_OUT_NEG 38 46 37 GND MAKE_BASE=TRUE GND
37 GPIO_AP_FROM_BT_AUDIO_SYNC MAKE_BASE=TRUE GPIO_AP_FROM_BT_AUDIO_SYNC 56 37 50_XCVR_TX0_HB MAKE_BASE=TRUE 50_XCVR_TX0_HB 58 37 GND MAKE_BASE=TRUE GND 37 SPKRAMP_TOP_TO_COIL_OUT_NEG MAKE_BASE=TRUE SPKRAMP_TOP_TO_COIL_OUT_NEG 38 46 37 GND MAKE_BASE=TRUE GND
37 UART4_AP_FROM_NFC_CTS_L MAKE_BASE=TRUE UART4_AP_FROM_NFC_CTS_L 11 37 GND MAKE_BASE=TRUE GND 37 PCIE4_AP_BI_BB_CLKREQ_1V2_L MAKE_BASE=TRUE PCIE4_AP_BI_BB_CLKREQ_1V2_L 8 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 GPIO_AP_TO_NFC_DEV_WAKE MAKE_BASE=TRUE GPIO_AP_TO_NFC_DEV_WAKE 56 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 UART4_AP_FROM_NFC_RXD MAKE_BASE=TRUE UART4_AP_FROM_NFC_RXD 11 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 RFFE_LAA_UAT_VIO MAKE_BASE=TRUE RFFE_LAA_UAT_VIO 58 37 GND MAKE_BASE=TRUE GND
C 37 GND
37 UART4_AP_TO_NFC_TXD
MAKE_BASE=TRUE
MAKE_BASE=TRUE
GND
UART4_AP_TO_NFC_TXD 11
37
37
50_CPLL_CPLOUT2
GND
MAKE_BASE=TRUE
MAKE_BASE=TRUE
50_CPLL_CPLOUT2
GND
58 37
37
CLK_BBPMU_TO_DOTARA_38M4_1V8
GND
MAKE_BASE=TRUE
MAKE_BASE=TRUE
CLK_BBPMU_TO_DOTARA_38M4_1V8
GND
49 37
37
RFFE_LAA_UAT_CLK
GND
MAKE_BASE=TRUE
MAKE_BASE=TRUE
RFFE_LAA_UAT_CLK
GND
58 37
37
GND
GND
MAKE_BASE=TRUE
MAKE_BASE=TRUE
GND
GND
C
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 IO_SPKAMP_TO_SPKAMP_SYNC MAKE_BASE=TRUE IO_SPKAMP_TO_SPKAMP_SYNC 49 37 RFFE_LAA_UAT_DATA MAKE_BASE=TRUE RFFE_LAA_UAT_DATA 58 37 GND MAKE_BASE=TRUE GND
37 SWD_AP_BI_BB_SWDIO MAKE_BASE=TRUE SWD_AP_BI_BB_SWDIO 7 37 50_CPLL_CPLOUT1 MAKE_BASE=TRUE 50_CPLL_CPLOUT1 58 37 GND MAKE_BASE=TRUE GND 37 5GHZ_C0_VDET MAKE_BASE=TRUE 5GHZ_C0_VDET 58 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 VPA_ET_HB MAKE_BASE=TRUE VPA_ET_HB 38 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
58
37 UART4_AP_TO_NFC_RTS_L MAKE_BASE=TRUE UART4_AP_TO_NFC_RTS_L 11 37 GND MAKE_BASE=TRUE GND 37 IO_BT_TO_BOT_SPK_TRIG MAKE_BASE=TRUE IO_BT_TO_BOT_SPK_TRIG 49 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 PP_GPU_LVCC MAKE_BASE=TRUE PP_GPU_LVCC 5 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 50_WLAN_A_TX0 MAKE_BASE=TRUE 50_WLAN_A_TX0 58 37 GND MAKE_BASE=TRUE GND
37 UART2_AOP_FROM_BB_RXD MAKE_BASE=TRUE UART2_AOP_FROM_BB_RXD 13 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 SWD_NUB_TO_MANY_SWCLK MAKE_BASE=TRUE SWD_NUB_TO_MANY_SWCLK 13 18 22 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 50_WLAN_A_RX0_LAA MAKE_BASE=TRUE 50_WLAN_A_RX0_LAA 58 37 50_XCVR_TX0_LB2 MAKE_BASE=TRUE 50_XCVR_TX0_LB2 58
58
37 PP_CPU_PCORE_LVCC MAKE_BASE=TRUE PP_CPU_PCORE_LVCC 5 37 VPA_ET_HB MAKE_BASE=TRUE VPA_ET_HB 38 37 NTC_RADIO_BB_N MAKE_BASE=TRUE NTC_RADIO_BB_N 22 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
58
37 GPIO_AOP_FROM_HALL_CASE_INT_L MAKE_BASE=TRUE GPIO_AOP_FROM_HALL_CASE_INT_L 56 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 NTC_RADIO_BB_P MAKE_BASE=TRUE NTC_RADIO_BB_P 22 37 50_LAA_TO_XCVR_UAT MAKE_BASE=TRUE 50_LAA_TO_XCVR_UAT 58 37 50_XCVR_TX0_MB1 MAKE_BASE=TRUE 50_XCVR_TX0_MB1 58
37 GPIO_AOP_FROM_NFC_HOST_WAKE MAKE_BASE=TRUE GPIO_AOP_FROM_NFC_HOST_WAKE 56 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 I2C2_AP_SCL MAKE_BASE=TRUE I2C2_AP_SCL 11 53 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 UART2_AOP_TO_BB_TXD MAKE_BASE=TRUE UART2_AOP_TO_BB_TXD 13 37 VPA_ET_HB MAKE_BASE=TRUE VPA_ET_HB 38 37 PP_VDD_MAIN_OV_R MAKE_BASE=TRUE PP_VDD_MAIN_OV_R 33 37 RFA0_SW_CTRL2 MAKE_BASE=TRUE RFA0_SW_CTRL2 58 37 GND MAKE_BASE=TRUE GND
58
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 IO_NFC_TO_ARC_RESET_L MAKE_BASE=TRUE IO_NFC_TO_ARC_RESET_L 49 37 IO_R1_TO_BB_LAA_SW_CTRL MAKE_BASE=TRUE IO_R1_TO_BB_LAA_SW_CTRL 58 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 RFA0_SW_CTRL1 MAKE_BASE=TRUE RFA0_SW_CTRL1 58 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 IO_NFC_TO_ARC_TRIG MAKE_BASE=TRUE IO_NFC_TO_ARC_TRIG 49 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 SPMI1_AOP_TO_RF_CLK MAKE_BASE=TRUE SPMI1_AOP_TO_RF_CLK 13 37 GND MAKE_BASE=TRUE GND 37 GPIO_PMU_FROM_CHARGER_INT_L MAKE_BASE=TRUE GPIO_PMU_FROM_CHARGER_INT_L 49 56 37 GND MAKE_BASE=TRUE GND 37 50_UHBPA_2G_LB_OUT MAKE_BASE=TRUE 50_UHBPA_2G_LB_OUT 58
49
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 I2S1_AOP_TO_AMPS_CODEC_ASP2_DOUT MAKE_BASE=TRUE I2S1_AOP_TO_AMPS_CODEC_ASP2_DOUT 13 37 RFA0_SW_CTRL0 MAKE_BASE=TRUE RFA0_SW_CTRL0 58 37 GND MAKE_BASE=TRUE GND
31
37 SPMI1_AOP_BI_RF_DATA MAKE_BASE=TRUE SPMI1_AOP_BI_RF_DATA 13 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
B 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 IO_HYDRA_TO_AP_FORCE_DFU MAKE_BASE=TRUE IO_HYDRA_TO_AP_FORCE_DFU 7 36 37 GND MAKE_BASE=TRUE GND 37 50_WLAN_G_LAT MAKE_BASE=TRUE 50_WLAN_G_LAT 58 B
37 90_PCIE3_AP_TO_WLAN_REFCLK_N MAKE_BASE=TRUE 90_PCIE3_AP_TO_WLAN_REFCLK_N 8 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 50_MMDSM_UHB_ANT MAKE_BASE=TRUE 50_MMDSM_UHB_ANT 58
37 90_PCIE3_AP_TO_WLAN_REFCLK_P MAKE_BASE=TRUE 90_PCIE3_AP_TO_WLAN_REFCLK_P 8 37 GPIO_AP_CANARY1 MAKE_BASE=TRUE GPIO_AP_CANARY1 56 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 50_LB_TX_ANT1 MAKE_BASE=TRUE 50_LB_TX_ANT1 58
37 GND MAKE_BASE=TRUE GND 37 50_XCVR_RX6_MB_UHB_PRX MAKE_BASE=TRUE 50_XCVR_RX6_MB_UHB_PRX 58 37 GND MAKE_BASE=TRUE GND 37 UAT_SAWTOOTH_B MAKE_BASE=TRUE UAT_SAWTOOTH_B 44 58 37 GND MAKE_BASE=TRUE GND
37 90_PCIE4_AP_TO_BB_REFCLK_P MAKE_BASE=TRUE 90_PCIE4_AP_TO_BB_REFCLK_P 8 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 UAT_SAWTOOTH_A MAKE_BASE=TRUE UAT_SAWTOOTH_A 58 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 LAT_SAWTOOTH_B MAKE_BASE=TRUE LAT_SAWTOOTH_B 58
37 90_PCIE4_AP_TO_BB_REFCLK_N MAKE_BASE=TRUE 90_PCIE4_AP_TO_BB_REFCLK_N 8 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 50_XCVR_RX10_MLB_HB_PRX MAKE_BASE=TRUE 50_XCVR_RX10_MLB_HB_PRX 58 37 GND MAKE_BASE=TRUE GND 37 50_ANT4 MAKE_BASE=TRUE 50_ANT4 58 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 LAT_SAWTOOTH_A MAKE_BASE=TRUE LAT_SAWTOOTH_A 58 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 90_PCIE3_AP_TO_WLAN_C_TX_P MAKE_BASE=TRUE 90_PCIE3_AP_TO_WLAN_C_TX_P 8 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 90_PCIE3_AP_TO_WLAN_C_TX_N MAKE_BASE=TRUE 90_PCIE3_AP_TO_WLAN_C_TX_N 8 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 50_ANT2 MAKE_BASE=TRUE 50_ANT2 58 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 PP_VDD_MAIN MAKE_BASE=TRUE PP_VDD_MAIN 3 20 21 37 GND MAKE_BASE=TRUE GND 37 50_XCVR_RX14_LB_MLB_PRX MAKE_BASE=TRUE 50_XCVR_RX14_LB_MLB_PRX 58
33 38 39 50
37 GND MAKE_BASE=TRUE GND 37 RFA1_SW_CTRL0 MAKE_BASE=TRUE RFA1_SW_CTRL0 58 37 PP_VDD_MAIN MAKE_BASE=TRUE PP_VDD_MAIN 3 20 21 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
33 38 39 50
37 GND MAKE_BASE=TRUE GND 37 50_HBPA_DRX_OUT MAKE_BASE=TRUE 50_HBPA_DRX_OUT 58 37 PP_VDD_MAIN MAKE_BASE=TRUE PP_VDD_MAIN 3 20 21 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
33 38 39 50
37 90_PCIE3_AP_FROM_WLAN_C_RX_N MAKE_BASE=TRUE 90_PCIE3_AP_FROM_WLAN_C_RX_N 8 37 GND MAKE_BASE=TRUE GND 37 PP_VDD_MAIN MAKE_BASE=TRUE PP_VDD_MAIN 3 20 21 37 50_ANT6_UHB MAKE_BASE=TRUE 50_ANT6_UHB 58 37 VIO_RFFE_XCVR_TO_RX_1V8 MAKE_BASE=TRUE VIO_RFFE_XCVR_TO_RX_1V8 58
33 38 39 50
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 PP_VDD_MAIN MAKE_BASE=TRUE PP_VDD_MAIN 3 20 21 37 GND MAKE_BASE=TRUE GND 37 RFFE_XCVR_TO_FE_RX_DATA MAKE_BASE=TRUE RFFE_XCVR_TO_FE_RX_DATA 58
33 38 39 50
37 90_PCIE3_AP_FROM_WLAN_C_RX_P MAKE_BASE=TRUE 90_PCIE3_AP_FROM_WLAN_C_RX_P 8 37 GND MAKE_BASE=TRUE GND 37 PDM_OUT1_CODEC_TO_SPKAMP_TOP_CLK MAKE_BASE=TRUE PDM_OUT1_CODEC_TO_SPKAMP_TOP_CLK 30 37 GND MAKE_BASE=TRUE GND 37 RFFE_XCVR_TO_FE_RX_CLK MAKE_BASE=TRUE RFFE_XCVR_TO_FE_RX_CLK 58
37 GND MAKE_BASE=TRUE GND 37 50_MMDSM_MHB_ANT MAKE_BASE=TRUE 50_MMDSM_MHB_ANT 58 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 VIO_RFFE_XCVR_TO_TX_1V8 MAKE_BASE=TRUE VIO_RFFE_XCVR_TO_TX_1V8 58
49
GND GND GND I2S1_AOP_AMPS_FROM_CODEC_ASP2_BCLK I2S1_AOP_AMPS_FROM_CODEC_ASP2_BCLK 13 GND GND RFFE_XCVR_TO_HBTX_DATA RFFE_XCVR_TO_HBTX_DATA
A 37 GND
37 GND
MAKE_BASE=TRUE
MAKE_BASE=TRUE GND
37
37 GND
MAKE_BASE=TRUE
MAKE_BASE=TRUE GND
37
37 GPIO_AP_FROM_SPKRAMP_TOP_INT_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE GPIO_AP_FROM_SPKRAMP_TOP_INT_L 56
31
37
37 GND
MAKE_BASE=TRUE
MAKE_BASE=TRUE GND
37
37 RFFE_XCVR_TO_HBTX_CLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE RFFE_XCVR_TO_HBTX_CLK
58
58 A
49
37 90_PCIE4_AP_FROM_BB_C_RX_N MAKE_BASE=TRUE 90_PCIE4_AP_FROM_BB_C_RX_N 8 37 GND MAKE_BASE=TRUE GND 37 I2S1_AOP_FROM_AMPS_CODEC_ASP2_DIN MAKE_BASE=TRUE I2S1_AOP_FROM_AMPS_CODEC_ASP2_DIN 13 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
31
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 VFE_HI_3V15 MAKE_BASE=TRUE VFE_HI_3V15 58
49
37 90_PCIE4_AP_FROM_BB_C_RX_P MAKE_BASE=TRUE 90_PCIE4_AP_FROM_BB_C_RX_P 8 37 RFFE_XCVR_TO_LBTX_CLK MAKE_BASE=TRUE RFFE_XCVR_TO_LBTX_CLK 58 37 I2S1_AOP_AMPS_FROM_CODEC_ASP2_LRCLK MAKE_BASE=TRUE I2S1_AOP_AMPS_FROM_CODEC_ASP2_LRCLK 13 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
31
37 GND MAKE_BASE=TRUE GND 37 RFFE_XCVR_TO_LBTX_DATA MAKE_BASE=TRUE RFFE_XCVR_TO_LBTX_DATA 58 37 GPIO_AP_TO_SPKRAMP_TOP_RESET_L MAKE_BASE=TRUE GPIO_AP_TO_SPKRAMP_TOP_RESET_L 56 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 PDM_OUT1_CODEC_TO_SPKRAMP_TOP_DATA MAKE_BASE=TRUE PDM_OUT1_CODEC_TO_SPKRAMP_TOP_DATA 30 37 GND MAKE_BASE=TRUE GND 37 50_HBPA_ANT3 MAKE_BASE=TRUE 50_HBPA_ANT3 58
37 90_PCIE4_AP_TO_BB_C_TX_N MAKE_BASE=TRUE 90_PCIE4_AP_TO_BB_C_TX_N 8 37 GND MAKE_BASE=TRUE GND 37 PP1V2_S2 MAKE_BASE=TRUE PP1V2_S2 21 50 37 PP1V2_S4 MAKE_BASE=TRUE PP1V2_S4 19 21 37 GND MAKE_BASE=TRUE GND
37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GPIO_AOP_TO_WLAN_CONTEXT_A MAKE_BASE=TRUE GPIO_AOP_TO_WLAN_CONTEXT_A 56 37 GND MAKE_BASE=TRUE GND 37 50_XCVR_RX8_MLB_HB_PRX MAKE_BASE=TRUE 50_XCVR_RX8_MLB_HB_PRX 58
37 90_PCIE4_AP_TO_BB_C_TX_P MAKE_BASE=TRUE 90_PCIE4_AP_TO_BB_C_TX_P 8 37 RFA1_SW_CTRL2 MAKE_BASE=TRUE RFA1_SW_CTRL2 58 37 PP1V8_S2 MAKE_BASE=TRUE PP1V8_S2 19 49 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
50
37 GND MAKE_BASE=TRUE GND 37 VFE_LO_1V2 MAKE_BASE=TRUE VFE_LO_1V2 58 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND 37 GND MAKE_BASE=TRUE GND
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
PLACE_NEAR=U2700:5MM
C7020
0.47UF
22 ANALOG_PMU_VDD_MAIN_ISENSE 1 2 ANALOG_PMU_VDD_MAIN_VSENSE_2 22
20%
R7021 1 1
499
1%
6.3V
X5R
01005-1
ROOM=PMU 1%
R7020
499 BATTERY CONNECTOR - NORTH
C 1/32W
MF
1/32W
MF C
ANALOG_PMU_VDD_MAIN_ISENSE_R
ANALOG_PMU_VDD_MAIN_VSENSE_2_R
01005 2 01005
2 ROOM=PMU Rcpt: 516S00505 <-- This one on MLB
ROOM=PMU
Plug: 516S00506
OMIT
2 2
XW7010
SHORT-20L-0.05MM-SM J7010
OMIT OMIT ANALOG_PMU_VDD_MAIN_SENSE B2B-BATT-HP-RCPT-2CP
22 1 2 F-ST-SM
XW7021 XW7020 ROOM=B2B_BATTERY_NORTH
9
SHORT-20L-0.05MM-SM SHORT-20L-0.05MM-SM 5 6
ROOM=PMU 1 1 ROOM=B2B_BATTERY_NORTH
NO_XNET_CONNECTION NO_XNET_CONNECTION
PLACE_NEAR=J7010.1:8MM XW3001
PP_VDD_MAIN
<T2>
1 3 DIFF_AMP_REF
50 38 33 21 20 3 1 -2
1 C7009
56PF
1 C7010
220PF
1 C7011
330PF
22 OUT
2
ANALOG_BMU_DIFF_AMP_ISENSE 2 4 Pin3: DIFF_AMP_GND SHORT-20L-0.05MM-SM
ROOM=PMU
OMIT 1
5%
2 25V
5%
2 25V
10%
2 16V
DZ7011 7 8 Placed near PMU
NP0/C0G
01005
COG
01005
X7R
01005
ESD202-B1-CSP01005 10
ROOM=B2B_BATTERY_NORTH ROOM=B2B_BATTERY_NORTH ROOM=B2B_BATTERY_NORTH SG-WLL-2-2
ROOM=B2B_BATTERY_NORTH ROOM=B2B_BATTERY_NORTH
B B
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Wide Camera
Rcpt: 516S00402
Connector
<-- This one on MLB
Power Filtering
Plug: 516S00403 FL7201
FERR-33OHM-25%-1.5A
ROOM=B2B_WIDE_RCAM
41 26
PPVAR_RCAM_PVDD 1 2 PPVAR_WIDE_PVDD_CONN 40
J7200 0201 VOLTAGE=3.0V
AA28DK-S026VA1 ROOM=B2B_WIDE_RCAM 1
F-ST-SM C7290
31 220PF
5%
27 28 25V
2 COG
01005
FL7295 ROOM=B2B_WIDE_RCAM D
D 40 PP1V8_CAM_WIDE_VDDIO_CONN 1 2 PPVAR_WIDE_AVDD2 24 40 10-OHM-750MA
40 25 GPIO_CAM_PMU1_TO_WIDE_SHDN_L 3 4 PP2V925_WIDE_AVDD1 27 40
55 52 50 45 43 41 33 19
PP1V8_IO 1 2 PP1V8_CAM_WIDE_VDDIO_CONN 40
5 6
01005-1
GPIO_ISP_RCAM_TO_STROBE_TRIGGER 7 8 PPVAR_WIDE_PVDD_CONN ROOM=B2B_WIDE_RCAM 1 1
42 41 40 38 36 9 40 C7295 C7296
42 41 RCAM_SYNC 9 10 I2C1_CAM_PMU1_SCL 40 55
0.1UF 220PF
20% 5%
55 40 I2C1_CAM_PMU1_SDA 11 12 PP3V3_RCAM_SVDD 24 26 40 41
6.3V
2 X5R-CERM 25V
2 COG
40 CLK_CAM_PMU1_TO_WIDE_24M_CONN 13 14 01005 01005
ROOM=B2B_WIDE_RCAM ROOM=B2B_WIDE_RCAM
15 16 GND_VOID 90_LPDP_ISP_FROM_WIDE_RX_D2_CONN_P 40
90_LPDP_ISP_FROM_WIDE_RX_D0_CONN_P GND_VOID 17 18 GND_VOID 90_LPDP_ISP_FROM_WIDE_RX_D2_CONN_N PP2V925_WIDE_AVDD1
40 40
27 40
90_LPDP_ISP_FROM_WIDE_RX_D0_CONN_N GND_VOID 19 20 PPVAR_WIDE_AVDD2
40
40 24
21 22 GND_VOID 90_LPDP_ISP_FROM_WIDE_RX_D1_CONN_P 40
23 24 GND_VOID 90_LPDP_ISP_FROM_WIDE_RX_D1_CONN_N
40 LPDP_ISP_BI_WIDE_AUX_RX_D9P_CONN 40
25 26 1 C7291 1 C7292
40 26 PP1V2_WIDE_DVDD
220PF 220PF
5% 5%
25V 25V
29 30 2 COG 2 COG
01005 01005
32 ROOM=B2B_WIDE_RCAM ROOM=B2B_WIDE_RCAM
PP1V2_WIDE_DVDD 26 40
1 C7293
Pin Assignments based on D42 (flex_rcam_on_l_0.5.0)
220PF
5%
25V
2 COG
01005
ROOM=B2B_WIDE_RCAM
PP3V3_RCAM_SVDD 24 26 40 41
C 1 C7294 C
220PF
5%
25V
2 COG
01005
ROOM=B2B_WIDE_RCAM
CAM_PMU1 I2C1
I2C1_CAM_PMU1_SCL
LPDP Filters C7230
55 40 IN 0.1UF
51
90_LPDP_ISP_FROM_WIDE_RX_D0_P 1 2 90_LPDP_ISP_FROM_WIDE_RX_D0_CONN_P 40
OUT
0
1 C7200 GND_VOID
ROOM=B2B_WIDE_RCAM
56PF 20%
5% 6.3V
25V
2 NP0/C0G X5R-CERM
01005
01005
ROOM=B2B_WIDE_RCAM
C7231
0.1UF
51
90_LPDP_ISP_FROM_WIDE_RX_D0_N 1 2 90_LPDP_ISP_FROM_WIDE_RX_D0_CONN_N 40
I2C1_CAM_PMU1_SDA OUT
55 40 BI GND_VOID
ROOM=B2B_WIDE_RCAM
20%
6.3V
1 C7201 X5R-CERM
01005
56PF
5%
25V
2 NP0/C0G C7240
01005 0.1UF
ROOM=B2B_WIDE_RCAM 90_LPDP_ISP_FROM_WIDE_RX_D1_P 1 2 90_LPDP_ISP_FROM_WIDE_RX_D1_CONN_P
51 OUT 40
GND_VOID
ROOM=B2B_WIDE_RCAM
20%
6.3V
X5R-CERM
01005
B C7241 B
0.1UF
51
OUT
0
GND_VOID
ROOM=B2B_WIDE_RCAM
IO Filters 20%
6.3V
X5R-CERM
R7205 01005
CLK_CAM_PMU1_TO_WIDE_24M 1
0.00 2 CLK_CAM_PMU1_TO_WIDE_24M_CONN
25 IN 40 C7250
0% 0.1UF
1/32W 1 C7206 90_LPDP_ISP_FROM_WIDE_RX_D2_P 1 2 90_LPDP_ISP_FROM_WIDE_RX_D2_CONN_P
MF 51 OUT 40
01005 56PF GND_VOID
ROOM=B2B_WIDE_RCAM
ROOM=B2B_WIDE_RCAM 5%
25V 20%
2 NP0/C0G 6.3V
01005 X5R-CERM
ROOM=B2B_WIDE_RCAM
01005
C7251
GPIO_CAM_PMU1_TO_WIDE_SHDN_L 0.1UF
40 25 IN
51
OUT
GND_VOID
1 ROOM=B2B_WIDE_RCAM
C7207 20%
220PF 6.3V
5% X5R-CERM
25V
2 COG 01005
01005
ROOM=B2B_WIDE_RCAM C7260
0.1UF
LPDP_ISP_BI_WIDE_AUX_RX_D9P 1 2 LPDP_ISP_BI_WIDE_AUX_RX_D9P_CONN
51 BI 40
GPIO_ISP_RCAM_TO_STROBE_TRIGGER ROOM=B2B_WIDE_RCAM
42 41 40 38 36 9 OUT
20% 1 C7261
1 6.3V
C7208 X5R-CERM 56PF
220PF 01005 5%
5% 25V
2 NP0/C0G
25V
2 COG 01005
01005 ROOM=B2B_WIDE_RCAM
ROOM=B2B_WIDE_RCAM
A A
CLEAR CLEAR
DOMAIN DOMAIN
PWR_100UM P PWR_100UM PP1V8_CAM_WIDE_VDDIO_CONN ? S_PWR_100UM S 100UM-249UM_SPACING PP1V8_CAM_WIDE_VDDIO_CONN ?
PWR_SHAPE P PWR_SHAPE PPVAR_WIDE_PVDD_CONN ? S_PWR_SHAPE S 250UM+_SPACING PPVAR_WIDE_PVDD_CONN ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Tele Camera Connector
Rcpt: 516S00402 <-- This one on MLB Power Filtering
Plug: 516S00403
FL7301
FERR-33OHM-25%-1.5A
40 26
PPVAR_RCAM_PVDD 1 2 PPVAR_TELE_PVDD_CONN 41
ROOM=B2B_TELE_RCAM
0201
J7300 ROOM=B2B_TELE_RCAM 1
AA28DK-S026VA1
C7390
F-ST-SM 220PF
5%
31 25V
2 COG
41 24 PP1V15_TELE_DVDD 27 28 01005
FL7395 ROOM=B2B_TELE_RCAM
D 10-OHM-750MA
D
1 2
3 4 55 52 50 45 43 40 33 19
PP1V8_IO 1 2 PP1V8_CAM_TELE_VDDIO_CONN 41
GND_VOID 90_LPDP_ISP_FROM_TELE_RX_D1_CONN_P 41
90_LPDP_ISP_FROM_TELE_RX_D2_CONN_P GND_VOID 5 6 01005-1
41 GND_VOID 90_LPDP_ISP_FROM_TELE_RX_D1_CONN_N 41 ROOM=B2B_TELE_RCAM 1 C7395 1 C7396
90_LPDP_ISP_FROM_TELE_RX_D2_CONN_N GND_VOID 7 8
41 0.1UF 220PF
9 10 GND_VOID
20% 5%
90_LPDP_ISP_FROM_TELE_RX_D0_CONN_P 41 6.3V
2 X5R-CERM 25V
2 COG
41
LPDP_ISP_BI_TELE_AUX_RX_D5P_CONN 11 12 GND_VOID 90_LPDP_ISP_FROM_TELE_RX_D0_CONN_N 41 01005 01005
ROOM=B2B_TELE_RCAM ROOM=B2B_TELE_RCAM
42 41 40 RCAM_SYNC 13 14
41 PPVAR_TELE_PVDD_CONN 15 16
41 40 26 24 PP3V3_RCAM_SVDD 17 18 PP1V8_CAM_TELE_VDDIO_CONN 41
19 20
PP2V925_TELE_AVDD1 27 41
41 9 GPIO_ISP_TO_TELE_SHDN_L GPIO_ISP_RCAM_TO_STROBE_TRIGGER 9 36 38 40 41 42
41
CLK_CAM_PMU1_TO_TELE_24M_CONN 21 22 41 24 PPVAR_TELE_AVDD2
55 41 I2C3_CAM_PMU1_SDA 23 24 PP2V925_TELE_AVDD1 27 41
55 41 I2C3_CAM_PMU1_SCL 25 26 PPVAR_TELE_AVDD2 24 41 1 1
C7391 C7392
220PF 220PF
29 30 5% 5%
25V
2 COG 25V
2 COG
32 01005 01005
ROOM=B2B_TELE_RCAM ROOM=B2B_TELE_RCAM
PP1V15_TELE_DVDD 24 41
Pin Assignments based on D42 (flex_rcam_ab_l_0.3.0)
1 C7393
220PF
5%
25V
2 COG
01005
ROOM=B2B_TELE_RCAM
PP3V3_RCAM_SVDD 24 26 40 41
C C
1 C7394
CAM_PMU1 I2C3 220PF
5%
25V
2 COG
55 41
I2C3_CAM_PMU1_SCL 01005
IN ROOM=B2B_TELE_RCAM
1 C7300
56PF
5%
25V
2 NP0/C0G
01005 LPDP Filters
ROOM=B2B_TELE_RCAM
C7330
0.1UF
51 90_LPDP_ISP_FROM_TELE_RX_D0_P 1 2 90_LPDP_ISP_FROM_TELE_RX_D0_CONN_P 41
I2C3_CAM_PMU1_SDA OUT
55 41 BI GND_VOID
ROOM=B2B_TELE_RCAM
20%
1 C7301 6.3V
X5R-CERM
56PF 01005
5%
25V
2 NP0/C0G
01005
C7331
ROOM=B2B_TELE_RCAM
0.1UF
51
90_LPDP_ISP_FROM_TELE_RX_D0_N 1 2 90_LPDP_ISP_FROM_TELE_RX_D0_CONN_N 41
OUT
0
ROOM=B2B_TELE_RCAM
GND_VOID
20%
6.3V
X5R-CERM
01005
IO Filters C7340
0.1UF
R7305 51
90_LPDP_ISP_FROM_TELE_RX_D1_P 1 2 90_LPDP_ISP_FROM_TELE_RX_D1_CONN_P 41
0.00 OUT
CLK_CAM_PMU1_TO_TELE_24M 1 2 CLK_CAM_PMU1_TO_TELE_24M_CONN ROOM=B2B_TELE_RCAM
25 IN 41
GND_VOID
20%
0% 6.3V
1/32W 1 C7306 X5R-CERM
MF 01005
B 01005 56PF B
ROOM=B2B_TELE_RCAM
5%
25V
2 NP0/C0G C7341
01005 0.1UF
ROOM=B2B_TELE_RCAM
51
OUT
ROOM=B2B_TELE_RCAM
GND_VOID
20%
41 9
GPIO_ISP_TO_TELE_SHDN_L 6.3V
IN X5R-CERM
01005
1 C7307
220PF C7350
5% 0.1UF
25V
2 COG
51
90_LPDP_ISP_FROM_TELE_RX_D2_P 1 2 90_LPDP_ISP_FROM_TELE_RX_D2_CONN_P 41
01005 OUT
0
ROOM=B2B_TELE_RCAM
ROOM=B2B_TELE_RCAM
GND_VOID
20%
6.3V
X5R-CERM
01005
42 41 40 38 36 9 OUT
GPIO_ISP_RCAM_TO_STROBE_TRIGGER
1
C7351
C7308 0.1UF
220PF 51
5% OUT
25V
2 COG ROOM=B2B_TELE_RCAM GND_VOID
20%
01005 6.3V
ROOM=B2B_TELE_RCAM X5R-CERM
01005
RCAM_SYNC
C7360
42 41 40 BI 0.1UF
51
LPDP_ISP_BI_TELE_AUX_RX_D5P 1 2 LPDP_ISP_BI_TELE_AUX_RX_D5P_CONN 41
1 OUT
C7310 ROOM=B2B_TELE_RCAM
220PF 20% 1 C7361
5% 6.3V
25V
2 COG X5R-CERM 56PF
01005 5%
01005 25V
2 NP0/C0G
ROOM=B2B_TELE_RCAM
01005
A ROOM=B2B_TELE_RCAM A
CLEAR CLEAR
DOMAIN DOMAIN
PWR_100UM P PWR_100UM PP1V8_CAM_TELE_VDDIO_CONN ? S_PWR_100UM S 100UM-249UM_SPACING PP1V8_CAM_TELE_VDDIO_CONN ?
PWR_SHAPE P PWR_SHAPE PPVAR_TELE_PVDD_CONN ? S_PWR_SHAPE S 250UM+_SPACING PPVAR_TELE_PVDD_CONN ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Super Wide Camera Connector Power Filtering
Rcpt: 516S00458 <-- This one on MLB
Plug: 516S00459
FL7495
10-OHM-750MA
J7400 55 24
PP1V8_CAM_PMU1_IO_SW 1 2 PP1V8_CAM_SWIDE_VDDIO_CONN 42
AA26DK-S22VA2
F-ST-SM 01005-1
ROOM=B2B_SWIDE_RCAM 1 1
27 C7495 C7496
23 24 0.1UF 220PF
20% 5%
6.3V 25V
c
ROOM=B2B_SWIDE_RCAM 2 X5R-CERM 2 COG
1 2 01005 01005
42 LPDP_ISP_BI_SWIDE_AUX_RX_D2P_CONN GND_VOID 90_LPDP_ISP_FROM_SWIDE_RX_D1_CONN_P 42 ROOM=B2B_SWIDE_RCAM ROOM=B2B_SWIDE_RCAM
O
D 3 4 GND_VOID 90_LPDP_ISP_FROM_SWIDE_RX_D1_CONN_N 42
D
90_LPDP_ISP_FROM_SWIDE_RX_D2_CONN_P GND_VOID 5 6
42
90_LPDP_ISP_FROM_SWIDE_RX_D2_CONN_N GND_VOID 7 8 90_LPDP_ISP_FROM_SWIDE_RX_D0_CONN_P PP2V925_SWIDE_AVDD1
42 GND_VOID 42
42 27
9 10 GND_VOID
90_LPDP_ISP_FROM_SWIDE_RX_D0_CONN_N 42 PPVAR_SWIDE_AVDD2
42 24
41 40 RCAM_SYNC 11 12
42 25 GPIO_CAM_PMU1_TO_SWIDE_SHDN_L 13 14 PP2V925_SWIDE_AVDD1 27 42
15 16 1 C7491 1 C7492
PPVAR_SWIDE_AVDD2 24 42
GPIO_ISP_RCAM_TO_STROBE_TRIGGER 17 18 220PF 220PF
42 41 40 38 36 9 5% 5%
I2C2_CAM_PMU1_SCL 19 20 25V
2 COG 2 25V
55 42 CLK_CAM_PMU1_TO_SWIDE_24M_CONN 42 COG
21 22 01005 01005
55 42 I2C2_CAM_PMU1_SDA PP1V8_CAM_SWIDE_VDDIO_CONN 42 ROOM=B2B_SWIDE_RCAM ROOM=B2B_SWIDE_RCAM
66666666666
0099999999
42 26 PP1V2_SWIDE_DVDD 25 26
28 PP1V2_SWIDE_DVDD
42 26
1 C7493
220PF
5%
25V
2 COG
01005
ROOM=B2B_SWIDE_RCAM
Pin Assignments based on (D42/flex_rcam_mb_l_0.1.0)
LPDP Filters
C CAM_PMU1 I2C2 C
C7430
0.1UF
55 42
I2C2_CAM_PMU1_SCL 51
90_LPDP_ISP_FROM_SWIDE_RX_D0_P 1 2 90_LPDP_ISP_FROM_SWIDE_RX_D0_CONN_P 42
IN OUT
GND_VOID
ROOM=B2B_SWIDE_RCAM
1 C7400 20%
6.3V
56PF X5R-CERM
5% 01005
25V
2 NP0/C0G
01005 C7431
ROOM=B2B_SWIDE_RCAM
0.1UF
51
90_LPDP_ISP_FROM_SWIDE_RX_D0_N 1 2 90_LPDP_ISP_FROM_SWIDE_RX_D0_CONN_N 42
OUT
GND_VOID
ROOM=B2B_SWIDE_RCAM
55 42
I2C2_CAM_PMU1_SDA 20%
BI 6.3V
X5R-CERM
01005
1 C7401
56PF C7440
5% 0.1UF
25V
2 NP0/C0G
51
01005 OUT
0
GND_VOID
ROOM=B2B_SWIDE_RCAM ROOM=B2B_SWIDE_RCAM
20%
6.3V
X5R-CERM
01005
C7441
IO Filters 0.1UF
51
90_LPDP_ISP_FROM_SWIDE_RX_D1_N 1 2 90_LPDP_ISP_FROM_SWIDE_RX_D1_CONN_N 42
OUT
GND_VOID
ROOM=B2B_SWIDE_RCAM
R7405 20%
0.00 6.3V
25
CLK_CAM_PMU1_TO_SWIDE_24M 1 2 CLK_CAM_PMU1_TO_SWIDE_24M_CONN 42
X5R-CERM
IN 01005
0%
1/32W 1 C7406
MF C7450
01005 56PF 0.1UF
B ROOM=B2B_SWIDE_RCAM 5% B
2 25V 51
NP0/C0G OUT
01005 GND_VOID
ROOM=B2B_SWIDE_RCAM
ROOM=B2B_SWIDE_RCAM 20%
6.3V
X5R-CERM
01005
42 25 IN
GPIO_CAM_PMU1_TO_SWIDE_SHDN_L C7451
0.1UF
1 C7407 90_LPDP_ISP_FROM_SWIDE_RX_D2_N 1 2 90_LPDP_ISP_FROM_SWIDE_RX_D2_CONN_N
51 OUT 42
0
220PF GND_VOID
ROOM=B2B_SWIDE_RCAM
5% 20%
25V
2 COG 6.3V
01005 X5R-CERM
ROOM=B2B_SWIDE_RCAM
01005
C7460
0.1UF
LPDP_ISP_BI_SWIDE_AUX_RX_D2P 1 2 LPDP_ISP_BI_SWIDE_AUX_RX_D2P_CONN
GPIO_ISP_RCAM_TO_STROBE_TRIGGER 51 BI 42
42 41 40 38 36 9 OUT
1 20% 1 C7461
C7408 6.3V
220PF X5R-CERM 56PF
5% 01005 5%
25V ROOM=B2B_SWIDE_RCAM 25V
2 NP0/C0G
2 COG
01005 01005
ROOM=B2B_SWIDE_RCAM
ROOM=B2B_SWIDE_RCAM
A A
CLEAR CLEAR
DOMAIN DOMAIN
PWR_100UM P PWR_100UM PP1V8_CAM_SWIDE_VDDIO_CONN ? S_PWR_100UM S 100UM-249UM_SPACING PP1V8_CAM_SWIDE_VDDIO_CONN ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power Filtering FCAM Connector
FL7600 Rcpt: 516S00244 <-- This one on MLB
10-OHM-750MA Plug: 516S00245
55 52 50 45 41 40 33 19
PP1V8_IO 1 2 PP1V8_FCAM_VDDIO_CONN 43
01005-1
ROOM=B2B_FCAM 1 1
C7600 C7601 J7600
0.1UF 220PF BB35K-RA18-3A D
D 20% 5% F-ST-SM
6.3V 2 25V
2 X5R-CERM COG
01005 01005 23
ROOM=B2B_FCAM
ROOM=B2B_FCAM
43 26 PP1V2_FCAM_DVDD 19 20
43 LPDP_ISP_BI_FCAM_AUX_RX_D0P_CONN 1 2 Sensor: VDDL2
3 4
43 26
PP1V2_FCAM_DVDD
43 90_LPDP_ISP_FROM_FCAM_RX_D0_CONN_N GND_VOID 5 6 CLK_ISP_TO_FCAM_12M_CONN 43
1 C7602 1 C7603 43 90_LPDP_ISP_FROM_FCAM_RX_D0_CONN_P GND_VOID 7 8
0.1UF 220PF 9 10 I2C2_ISP_SDA 43 55
20% 5%
6.3V
2 X5R-CERM 25V
2 COG 43 90_LPDP_ISP_FROM_FCAM_RX_D1_CONN_N GND_VOID 11 12 GPIO_ISP_TO_FCAM_SHDN_L 9 43
01005
ROOM=B2B_FCAM
01005 43 90_LPDP_ISP_FROM_FCAM_RX_D1_CONN_P GND_VOID 13 14 FCAM_TO_IRCAM_SYNC 43 45
ROOM=B2B_FCAM
15 16 PP1V8_FCAM_VDDIO_CONN 43
55 43 I2C2_ISP_SCL 17 18 Sensor: AGND
21 22 PP2V925_FCAM_AVDD 27 43
43 27
PP2V925_FCAM_AVDD
24
1 1 ROOM=B2B_FCAM
C7604 C7605
0.1UF 220PF
20% 5%
6.3V
2 X5R-CERM 25V
2 COG
01005 01005
ROOM=B2B_FCAM ROOM=B2B_FCAM
C C
FCAM I/O
LPDP FILTERS
R7610 ROOM=B2B_FCAM
CLK_ISP_TO_FCAM_12M 1
0.00 2 CLK_ISP_TO_FCAM_12M_CONN
9 IN 43
0
C7630
0% 0.1UF
1/32W 1 C7610 90_LPDP_ISP_FROM_FCAM_RX_D0_P
MF 51
1 2 90_LPDP_ISP_FROM_FCAM_RX_D0_CONN_P 43
56PF OUT
01005
ROOM=B2B_FCAM
5%
25V
2 NP0/C0G 20%
6.3V
01005 X5R-CERM
ROOM=B2B_FCAM
01005
C7631
90_LPDP_ISP_FROM_FCAM_RX_D0_N 0.1UF
43 9
GPIO_ISP_TO_FCAM_SHDN_L 51
1 2 90_LPDP_ISP_FROM_FCAM_RX_D0_CONN_N 43
IN OUT
1 C7611 20%
6.3V
220PF X5R-CERM
5% 01005
25V
2 COG ROOM=B2B_FCAM
01005 ROOM=B2B_FCAM
ROOM=B2B_FCAM
C7632
90_LPDP_ISP_FROM_FCAM_RX_D1_P 0.1UF
51
1 2 90_LPDP_ISP_FROM_FCAM_RX_D1_CONN_P 43
FCAM_TO_IRCAM_SYNC OUT
45 43 OUT
20%
1 C7612 6.3V
X5R-CERM
100PF 01005
B 5% B
16V
2 NP0-C0G
01005-1
C7633
0.1UF
ROOM=B2B_FCAM 90_LPDP_ISP_FROM_FCAM_RX_D1_N
51
1 2 90_LPDP_ISP_FROM_FCAM_RX_D1_CONN_N 43
OUT
20%
6.3V
X5R-CERM
01005
ROOM=B2B_FCAM
ISP I2C2
55 43 IN
I2C2_ISP_SCL
1
C7634
C7620 0.1UF
56PF 51
LPDP_ISP_BI_FCAM_AUX_RX_D0P 1 2 LPDP_ISP_BI_FCAM_AUX_RX_D0P_CONN 43
5% BI
25V
2 NP0/C0G 20% 1 C7635
01005 6.3V
ROOM=B2B_FCAM
X5R-CERM 56PF
01005 5%
NOSTUFF ROOM=B2B_FCAM 25V
2 NP0/C0G
01005
I2C2_ISP_SDA ROOM=B2B_FCAM
55 43 BI
1 C7621
56PF
5%
25V
2 NP0/C0G
01005
ROOM=B2B_FCAM
NOSTUFF
A A
CLEAR
DOMAIN
PWR_50UM P PWR_50UM PP1V8_FCAM_VDDIO_CONN ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Strobe Connector
PENROSE FL7703
Rcpt: 516S00557
Plug: 516S00558
<-- This one on MLB
150OHM-25%-200MA-0.7DCR
24 PP3V0_PENROSE_SVDD 1 rrm 01005-2
2 PP3V0_PENROSE_SVDD_CONN 44
Pin Assignement matched to d42_flex_strobe_fargo_smt_0.4.0
516S00557
ROOM=B2B_STROBE
1 C7704 J7700
220PF AA36DK-SVA1
5% F-ST-SM
2 25V
COG 21
01005 UAT_SAWTOOTH_B_FARGO: Used on D43, NC on D42
D
ROOM=B2B_STROBE
44 38 NFC_ANT 17
6 18
D
FL7701
150OHM-25%-200MA-0.7DCR
44 UAT_SAWTOOTH_B_FARGO 13
oo - 14
30 OUT
PENROSE_IR_TO_CODEC_AIN5_P 1 rrm 01005-2
2 PENROSE_IR_TO_CODEC_AIN5_CONN_POS 44
53 44
53
I2C1_AP_SDA
44 I2C1_AP_SCL
1
3
oo
o o-
2
4 PP_CODEC_TO_MIC2_REAR_BIAS_CONN 44
ROOM=B2B_STROBE
1 C7702 44
NTC_STROBE_MODULE_CONN 5
o o- 6 MIC2_REAR_TO_CODEC_BIAS_FILT_RET 31
56PF PP3V0_PENROSE_SVDD_CONN
o o-
44
7 8 MIC2_REAR_TO_CODEC_AIN2_CONN_P 44
5%
2 25V
NP0/C0G 44 PENROSE_VIS_TO_CODEC_AIN6_CONN_POS
9
11
o o- 10
12
MIC2_REAR_TO_CODEC_AIN2_CONN_N 44
44 PENROSE_IR_TO_CODEC_AIN5_CONN_POS IO_BUTTON_SIDE_CONN_L
01005
ROOM=B2B_STROBE oo 44
PP_STROBE_DRIVER_WARM_LED
44 38
15
o o- 16 PP_STROBE_DRIVER_COOL_LED 38 44
FL7732 19 20
150OHM-25%-200MA-0.7DCR
30 OUT
PENROSE_VIS_TO_CODEC_AIN6_P 1 rrm 2 PENROSE_VIS_TO_CODEC_AIN6_CONN_POS 44
22
01005-2
ROOM=B2B_STROBE
1 C7732 MAKE_BASE=TRUE GND
ROOM=B2B_STROBE
5%
56PF
2 25V
NP0/C0G
01005
ROOM=B2B_STROBE
I
30 GND MAKE_BASE=TRUE
MIC2 (ANC REF)

FL7705 30 GND
150OHM-25%-200MA-0.7DCR
C
31
PP_CODEC_TO_MIC2_REAR_BIAS 1 rrm 2 PP_CODEC_TO_MIC2_REAR_BIAS_CONN 44
53 44
o I2C1_AP_SCL
IN
C
01005-2
ROOM=B2B_STROBE 1 C7705 1 C7708 Deleted XWs for ease of placement and routing
220PF 56PF
5% 5%
2 25V 2 25V
NP0/C0G
COG 01005
01005
ROOM=B2B_STROBE ROOM=B2B_STROBE
FL7706
NFC
150OHM-25%-200MA-0.7DCR
MIC2_REAR_TO_CODEC_AIN2_P 1
rrm 2 MIC2_REAR_TO_CODEC_AIN2_CONN_P 53 44 BI
I2C1_AP_SDA NFC_ANT
T
38 44
30 OUT 44
01005-2
ROOM=B2B_STROBE 1 C7706
1 C7709 1 C7795 1 C7796 1 C7797
56PF
56PF 5% 1000PF 1000PF 27PF
5% 2 25V 2% 2% 2%
2 25V
NP0/C0G
01005
ROOM=B2B_STROBE
NP0/C0G
01005
ROOM=B2B_STROBE
T 2 25V
C0G-NP0
0201
ROOM=B2B_STROBE
CRITICAL
2 25V
C0G-NP0
0201
ROOM=B2B_STROBE
OMIT_TABLE
2 50V
NP0-C0G
0201
ROOM=B2B_STROBE
OMIT_TABLE
FL7707 TABLE_5_HEAD
150OHM-25%-200MA-0.7DCR PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
30 OUT
MIC2_REAR_TO_CODEC_AIN2_N 1
rrm 01005-2
2 MIC2_REAR_TO_CODEC_AIN2_CONN_N 44 131S00011 1 CAP,56pF,50V,01005 C7797 CRITICAL D421_NFC_MATCH
TABLE_5_ITEM
C7707
TABLE_5_ITEM
ROOM=B2B_STROBE 1 131S00026 1 CAP,820pF,25V,0201 C7796 CRITICAL D421_NFC_MATCH

56PF
5%
2 25V
NP0/C0G
01005 TABLE_5_HEAD

ROOM=B2B_STROBE
TABLE_5_ITEM
131S00116 1 CAP,27pF,50V,01005 C7797 CRITICAL D431_NFC_MATCH

TABLE_5_ITEM
131S00025 1 CAP,1000pF,25V,0201 C7796 CRITICAL D431_NFC_MATCH

B B
Strobe Filtering Side Button
R7710 R7790
0.00 2
PP_STROBE_DRIVER_WARM_LED 100 UAT_SAWTOOTH_B 1 UAT_SAWTOOTH_B_FARGO
C7720 1
38 44
22 OUT
IO_BUTTON_SIDE_L
1
1
AAAr
5%
2
1
IO_BUTTON_SIDE_CONN_L 44
58 38
'WV0%
1/32W
44
220PF C7710
27PF
1/32W
MF
MF
01005
1 C7790
5%
25V 2 5%
6.3V
01005
ROOM=B2B_STROBE
DZ7710 ROOM=B2B_STROBE
33PF
5%
COG
01005 NP0-C0G 2 5.5V-6.2PF 2 16V
NP0-C0G
ROOM=B2B_STROBE
0201 0201 01005-1
ROOM=B2B_STROBE ROOM=B2B_STROBE
ROOM=B2B_STROBE
2
PP_STROBE_DRIVER_COOL_LED 38 44
C7722 1
220PF
5%
25V
COG 2
01005
ROOM=B2B_STROBE
R7730
NTC_STROBE_MODULE 1
0.00 2 NTC_STROBE_MODULE_CONN
38 OUT AA0%/V 44
R7731 1 1/32W
MF 1 C7730
19.1K 01005
220PF
1%
A 1/32W
MF
ROOM=B2B_STROBE
5%
2 25V
COG
A
01005 2 01005
ROOM=B2B_STROBE
ROOM=B2B_STROBE
CLEAR
DOMAIN
CLEAR
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* OVERRIDE
DOMAIN
PWR_80UM P PWR_80UM PP3V0_PENROSE* ? CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
PWR_SHAPE P PWR_SHAPE PP_STROBE_DRIVER_WARM_LED,PP_STROBE_DRIVER_COOL_LED ? S_PWR_SHAPE S 250UM+_SPACING PP_STROBE_DRIVER_WARM_LED,PP_STROBE_DRIVER_COOL_LED ?

PWR_SHAPE P PWR_SHAPE NFC_ANT* ? S_PWR_SHAPE S 250UM+_SPACING NFC_ANT* ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Romeo Power Filtering
45 28
PP_ROMEO_B_ANODE Romeo Connector
45 28
PP_ROMEO_A_ANODE
PP_ROMEO_DENSE_ANODE Rcpt: 516S00479 <-- This one on MLB
45 28
PP_ROMEO_SPARSE_ANODE Plug: 516S00480
45 28
45 28
PP_ROMEO_CATHODE
PP3V3_MAMABEAR 24 45
J7800
AA38D-S10VA1
1 1 1 1 1 1 F-ST-SM D
D C7892 C7893 C7894 C7895 C7896 C7897 45 28
PP_ROMEO_SPARSE_ANODE 15 16 PP_ROMEO_SPARSE_ANODE 28 45
220PF 220PF 220PF 220PF 220PF 220PF PP_ROMEO_CATHODE PP_ROMEO_CATHODE
5% 5% 5% 5% 5% 5% 45 28
11 12 28 45
25V
2 COG 25V
2 COG 2 25V 25V 25V 25V
COG 2 COG 2 COG 2 COG
01005 01005 01005 01005 01005 01005
ROOM=B2B_ROMEO ROOM=B2B_ROMEO ROOM=B2B_ROMEO ROOM=B2B_ROMEO ROOM=B2B_ROMEO ROOM=B2B_ROMEO 1 2 I2C4_CAM_PMU1_SCL
55 45 I2C4_CAM_PMU1_SDA 45 55
45 NTC_PEARL_VCSEL_TO_RIGEL_CONN
3 4 PP3V3_MAMABEAR 24 45
45 IO_RIGEL_BI_MAMABEAR_STATUS_CONN 5 6
45 GPIO_AOP_FROM_PEARL_B2B_DETECT_CONN 7 8 PP_ROMEO_B_ANODE 28 45
Romeo I/O 9 10 PP_ROMEO_A_ANODE 28 45
ooooo
66 6 6 6
R7854
GPIO_AOP_FROM_PEARL_B2B_DETECT 1
0.00 2 GPIO_AOP_FROM_PEARL_B2B_DETECT_CONN 13 14 PP_ROMEO_CATHODE
56 OUT 45 45 28 PP_ROMEO_CATHODE 28 45
0
0% 45 28 PP_ROMEO_DENSE_ANODE 17 18 PP_ROMEO_DENSE_ANODE 28 45
1/32W 1 C7854
MF ROOM=B2B_ROMEO
01005 220PF
ROOM=B2B_ROMEO
5%
25V
2 COG
01005
ROOM=B2B_ROMEO
R7855
NTC_PEARL_VSCEL_TO_RIGEL 1
0.00 2 NTC_PEARL_VCSEL_TO_RIGEL_CONN
28 OUT 45 CAM_PMU1 I2C4
0%
1/32W 1 C7855
MF
01005 220PF
ROOM=B2B_ROMEO
5% 55 45
I2C4_CAM_PMU1_SCL
25V IN
2 COG
01005 1 C7852
ROOM=B2B_ROMEO
56PF
5%
25V
2 NP0/C0G
R7856 01005
0.00 ROOM=B2B_ROMEO
28 25
GPIO_RIGEL_BI_MAMABEAR_STATUS 1 2 IO_RIGEL_BI_MAMABEAR_STATUS_CONN 45 NOSTUFF C
C IN
0%
1/32W 1 C7856
MF
01005 220PF
ROOM=B2B_ROMEO
5% 55 45
I2C4_CAM_PMU1_SDA
25V BI
2 COG
01005 1 C7853
ROOM=B2B_ROMEO
5%
56PF Juliet Connector
25V
2 NP0/C0G Rcpt: 516S00395 <-- This one on MLB
R7865 01005 Plug: 516S00396
GPIO_AOP_FROM_IRCAM_B2B_DETECT 0.00 ROOM=B2B_ROMEO
56 OUT
1 2 GPIO_AOP_FROM_IRCAM_B2B_DETECT_CONN 45 Pin assignments matched to d42_flex_juliet_l_1.2.0
NOSTUFF
0%
1/32W 1 C7865 J7830
MF BB35AA-RA18-3A
01005 220PF F-ST-SM
ROOM=B2B_ROMEO
5%
25V
2 COG 23
01005 I2C4_CAM_PMU1_SDA 45 55
ROOM=B2B_ROMEO PP1V2_IRCAM_DVDD 19 20
45 24
C7880 1 1 2
45 GPIO_AOP_FROM_IRCAM_B2B_DETECT_CONN IO_IRCAM_TO_RIGEL_STROBE 28 45
56PF 90_MIPI_ISP_FROM_IRCAM_D0_P 3 4 FCAM_TO_IRCAM_SYNC
5% 9 43 45
25V 90_MIPI_ISP_FROM_IRCAM_D0_N 5 6
NP0/C0G 2 9 GND_VOID PP2V85_IRCAM_AVDD_CONN 45
01005 7 8 Sensor: AGND
ROOM=B2B_JULIET
Juliet Power and I/O 9
90_MIPI_ISP_FROM_IRCAM_CLK_P GND_VOID 9 10 PP1V8_IRCAM_VDDIO_CONN 45
9
90_MIPI_ISP_FROM_IRCAM_CLK_N GND_VOID 11 12 GPIO_ISP_TO_IRCAM_SHDN_L 9 45
45 24
PP1V2_IRCAM_DVDD I2C4_CAM_PMU1_SCL
55 45 13 14 I2C4_CAM_PMU1_SDA 45 55
1 C7870 1 C7871 9
90_MIPI_ISP_FROM_IRCAM_D1_P GND_VOID 15 16 I2C4_CAM_PMU1_SCL 45 55
0.1UF 220PF 1 9
90_MIPI_ISP_FROM_IRCAM_D1_N GND_VOID 17 18 CLK_ISP_TO_IRCAM_12M_CONN 45
20% 5% C7881
6.3V 25V
2 COG 56PF
2 X5R-CERM
01005 01005 5% 21 22
ROOM=B2B_JULIET ROOM=B2B_JULIET 25V
NP0/C0G 2
B FL7872 01005 24 B
10-OHM-750MA ROOM=B2B_JULIET
ROOM=B2B_JULIET
PP2V85_IRCAM_AVDD 1 2 PP2V85_IRCAM_AVDD_CONN
24 45
01005-1
ROOM=B2B_JULIET 1 1
C7872 C7873
0.1UF 220PF
20% 5%
6.3V 25V
2 COG
2 X5R-CERM
01005
ROOM=B2B_JULIET
01005
ROOM=B2B_JULIET
FL7874
10-OHM-750MA
55 52 50 43 41 40 33 19
PP1V8_IO 1 2 PP1V8_IRCAM_VDDIO_CONN 45
01005-1
ROOM=B2B_JULIET 1 1
C7874 C7875
0.1UF 220PF
20% 5%
6.3V 25V
2 COG
2 X5R-CERM
01005 01005
ROOM=B2B_JULIET ROOM=B2B_JULIET
45 9 IN GPIO_ISP_TO_IRCAM_SHDN_L 45 28 IO_IRCAM_TO_RIGEL_STROBE
OUT
1 C7860 1 C7863
220PF 220PF
5% 5%
25V
2 COG 25V
2 COG
01005 01005
ROOM=B2B_JULIET
ROOM=B2B_JULIET
R7861
CLK_ISP_TO_IRCAM_12M 1
0.00 2 CLK_ISP_TO_IRCAM_12M_CONN
A 9 IN 45
45 43 IN
FCAM_TO_IRCAM_SYNC A
0% 1
1/32W C7862
MF 56PF 1 C7864
01005 5%
25V 220PF
ROOM=B2B_JULIET 2 NP0/C0G 5%
01005 2 25V
COG
ROOM=B2B_JULIET 01005
ROOM=B2B_JULIET
CLEAR
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
OVERRIDE CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR*
DOMAIN OVERRIDE
DOMAIN
PWR_100UM P PWR_100UM PP2V85_IRCAM_AVDD_CONN ? S_PWR_100UM S 100UM-249UM_SPACING PP_ROMEO_A_ANODE,PP_ROMEO_B_ANODE ?
PWR_100UM P PWR_100UM PP_ROMEO_A_ANODE,PP_ROMEO_B_ANODE ? S_PWR_SHAPE S 250UM+_SPACING PP_ROMEO_CATHODE,PP_ROMEO_DENSE_ANODE,PP_ROMEO_SPARSE_ANODE ?
PWR_SHAPE P PWR_SHAPE PP_ROMEO_CATHODE,PP_ROMEO_DENSE_ANODE,PP_ROMEO_SPARSE_ANODE ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AOP I2C SPEAKER2 Rosaline + Sensor Connector

SPKRAMP_TOP_TO_COIL_OUT_POS Plug: 516S00394
46 38
54 46
I2C0_AOP_SCL IN
IN
1 C7900 1 C7930 1 C7931 J7900

1 AA28DK-S028VA1
56PF 220PF 470PF R7936 F-ST-SM
-
5% 5% 2%
'AAA
2 25V
NP0/C0G 2 25V
COG 2 25V
NP0-C0G
1.00K 33
1%
01005 01005 0201 1/32W 46 38 SPKRAMP_TOP_TO_COIL_OUT_POS 29 30
ROOM=B2B_SENSOR ROOM=B2B_SENSOR ROOM=B2B_SENSOR MF
2
D
01005
ROOM=B2B_SENSOR
NO_XNET_CONNECTION=1 46 38 SPKRAMP_TOP_TO_COIL_OUT_NEG 1 2 CODEC_AOUT_TO_HAC_CONN_N 46
D
R7901 R7933 3 4 CODEC_AOUT_TO_HAC_CONN_P 46
I2C0_AOP_SDA 1
0.00 2 I2C0_AOP_BI_PROX_ALS_YOGI_SDA_CONN COIL_TO_SPKRAMP_TOP_VSENSE_POS 1
100 2 COIL_TO_SPKRAMP_TOP_VSENSE_POS_CONN 5 6 COIL_TO_SPKRAMP_TOP_VSENSE_NEG_CONN
54 BI 46 38 OUT 46 46
0% 5% GPIO_AOP_FROM_ALS_INT_CONN_L 7 8 COIL_TO_SPKRAMP_TOP_VSENSE_POS_CONN
1 C7901 1/32W
MF
C7935 1 1/32W
MF
46
GPIO_BB_TO_MANY_GSM_BURST_IND_CONN 9 10 PP1V8_COMPASS_S2_CONN
46
56PF 01005 220PF 01005

46 46
5% ROOM=B2B_SENSOR
5% ROOM=B2B_SENSOR 46 ALS_HOLD 11 12 GPIO_AOP_FROM_COMPASS_INT 46 56
2 25V 25V 2
13 14
NP0/C0G
01005
COG
01005 46 28 PP_ROSALINE_ANODE
ROOM=B2B_SENSOR ROOM=B2B_SENSOR 15 16
17 18
19 20
54 46 I2C0_AOP_SCL 21 22 GPIO_RIGEL_BI_YOGI_STATUS 25 28 46
46 I2C0_AOP_BI_PROX_ALS_YOGI_SDA_CONN 23 24 GPIO_AOP_BI_PROX_INT_L 46 56
PP_CODEC_TO_MIC3_FRONT_BIAS_CONN 25 26 PP3V0_YOGI_PROX_ALS_CONN
46 38
SPKRAMP_TOP_TO_COIL_OUT_NEG 46 46
IN
46 MIC3_FRONT_TO_CODEC_AIN3_CONN_N 27 28 MIC3_FRONT_TO_CODEC_AIN3_CONN_P 46
1 C7932 1 C7933
220PF 470PF R7937 31 32
PROX & ALS POWER 5%
2 25V
2%
2 25V
1
1.00K ROOM=B2B_SENSOR
OMIT 34
-AAA-
COG NP0-C0G 1%
R7911 01005
ROOM=B2B_SENSOR
0201
ROOM=B2B_SENSOR
1/32W
MF XW7900
SHORT-20L-0.05MM-SM ROOM=B2B_SENSOR
PP3V0_S2 1
0.00 2 PP3V0_YOGI_PROX_ALS_CONN 46 01005
ROOM=B2B_SENSOR MIC3_FRONT_TO_CODEC_BIAS_FILT_RET 1 2
i
50 31
2 NO_XNET_CONNECTION=1
0%
1/32W
MF 1 C7914 R7934
01005
220PF COIL_TO_SPKRAMP_TOP_VSENSE_NEG 1
100 2 COIL_TO_SPKRAMP_TOP_VSENSE_NEG_CONN
ROOM=B2B_SENSOR 38 OUT 46
5%
2 25V 5%
COG
01005 C7934 1 1/32W
MF Pin Assignments matched to flex_sensor_1.4.0
ROOM=B2B_SENSOR
220PF 01005
5% ROOM=B2B_SENSOR
25V 2
COG
C 01005
ROOM=B2B_SENSOR C
50 46 22 PP1V8_S2
1
R7917
10K
PROX/ALS I/O 5%
1/32W
MF
01005
2 ROOM=B2B_SENSOR
56 46 BI
GPIO_AOP_BI_PROX_INT_L
1 C7917
220PF
5%
2 25V
COG
01005
MIC3 FL7940
150OHM-25%-200MA-0.7DCR
ROOM=B2B_SENSOR
31
PP_CODEC_TO_MIC3_FRONT_BIAS 1 2 PP_CODEC_TO_MIC3_FRONT_BIAS_CONN 46 46 28
PP_ROSALINE_ANODE
01005-2
ROOM=B2B_SENSOR 1 DZ7940 1 C7960
R7918 6.8V-100PF
01005-2 5%
220PF
GPIO_AOP_FROM_ALS_INT_L 0.00 GPIO_AOP_FROM_ALS_INT_CONN_L 46 ROOM=B2B_SENSOR
56 OUT
1 2 2 2 25V
COG
0% 01005
1/32W
MF
1 C7918 ROOM=B2B_SENSOR
220PF
01005
5% R7912
ROOM=B2B_SENSOR 2 25V
COG FL7941 PP1V8_S2 1
0.00 2 PP1V8_COMPASS_S2_CONN
01005 150OHM-25%-200MA-0.7DCR 54 50 49 29 16 46
ROOM=B2B_SENSOR 0%
30 OUT
MIC3_FRONT_TO_CODEC_AIN3_N 1 2 MIC3_FRONT_TO_CODEC_AIN3_CONN_N 46 1/32W
MF
1 C7902
01005-2 01005 220PF
ROOM=B2B_SENSOR 1 DZ7941 ROOM=B2B_SENSOR
5%
2 25V
B 6.8V-100PF
01005-2
ROOM=B2B_SENSOR
COG
01005 B
R7919 2 ROOM=B2B_SENSOR
GPIO_BB_TO_MANY_GSM_BURST_IND 1
0.00 2 GPIO_BB_TO_MANY_GSM_BURST_IND_CONN 46
38 IN
0% FL7942 GPIO_AOP_FROM_COMPASS_INT
1/32W
MF
1 C7919 150OHM-25%-200MA-0.7DCR
56 46 OUT
01005
5%
220PF
MIC3_FRONT_TO_CODEC_AIN3_P 1 2 MIC3_FRONT_TO_CODEC_AIN3_CONN_P
1 C7980
ROOM=B2B_SENSOR 2 25V
COG
30 OUT 46
220PF
01005-2 5%
01005
ROOM=B2B_SENSOR
ROOM=B2B_SENSOR 1 DZ7942 2 25V
COG
6.8V-100PF
01005-2
01005
ROOM=B2B_SENSOR
ROOM=B2B_SENSOR
2
46 28 25
GPIO_RIGEL_BI_YOGI_STATUS
BI
1 C7920
5%
220PF FL7990
2 25V
150OHM-25%-200MA-0.7DCR
COG
01005 30
CODEC_AOUT_TO_HAC_N 1 2 CODEC_AOUT_TO_HAC_CONN_N 46
ROOM=B2B_SENSOR
01005-2
ROOM=B2B_SENSOR 1 DZ7990
6.8V-100PF
01005-2
50 46 22 PP1V8_S2 2
ROOM=B2B_SENSOR
1
R7921
10K
5%
1/32W
MF FL7991
01005
2 ROOM=B2B_SENSOR
150OHM-25%-200MA-0.7DCR
ALS_HOLD CODEC_AOUT_TO_HAC_P
46
30
1 2 CODEC_AOUT_TO_HAC_CONN_P 46
A R7921: ALS Pull-down changed to pull-up in EVT

For RF coex mitigation
01005-2
ROOM=B2B_SENSOR 1 DZ7991 A
1 C7921 6.8V-100PF
01005-2
220PF ROOM=B2B_SENSOR
5% 2
2 25V
COG
01005
ROOM=B2B_SENSOR
CLEAR CLEAR
DOMAIN DOMAIN
PWR_80UM P PWR_80UM PP1V8_COMPASS_S2_CONN,PP3V0_YOGI_PROX_ALS_CONN ? S_PWR_SHAPE S 250UM+_SPACING PP_ROSALINE_ANODE ?

PWR_SHAPE P PWR_SHAPE PP_ROSALINE_ANODE ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Display Flex Connector
Display Power Rcpt: 516S00501 <-- This one on MLB
FL8080 Plug: 516S00502
FERR-33OHM-25%-1.5A
516S00501
50
PP1V8_IO 1 2 PP1V8_DISPLAY_DVDD_CONN 47
0201 PP1V8_DISPLAY_DVDD: Imax = 25mA J8000
ROOM=B2B_DISPLAY
1 C8081 245858036211829
220PF F-ST-SM
5% 47
PP_VDD_MAIN_DISPLAY_CONN 41
2 25V
COG 37 38 PP_VDD_MAIN_DISPLAY_CONN
01005 47
ROOM=B2B_DISPLAY
D
1 2
D
XW8083
SHORT-0201 Pin 5 on Flex:PP_VPP for vendor programming
3 4
5 6
1 2 NC
47
GPIO_AP_FROM_DISPLAY_PANEL_ID_CONN 7 8 AMUX_PMU_FROM_DISPLAY_CONN 47
ROOM=B2B_DISPLAY
9 10 GPIO_PMU_TO_DISPLAY_PANICB_CONN 47
NC
XW8082 NC
11 12 GPIO_PMU_TO_DISPLAY_RESET_CONN_L 47
SHORT-0201 13 14 PP1V8_DISPLAY_DVDD_CONN 47
PP1VX_DISPLAY_VDD PP1VX_DISPLAY_VDD 1 2 PP1VX_DISPLAY_VDD_CONN NC
21
MAKE_BASE=TRUE
47
47
GPIO_ISP_TO_DISPLAY_FLASH_INT_CONN 15 16 PP3V0_DISPLAY_VCI_CONN 47
PP1VX_DISPLAY_VDD: Imax = 120mA
21 PP1VX_DISPLAY_VDD C2911 1 C2931 1 ROOM=B2B_DISPLAY
1 C8082 47
CLK_GPIO_PMU_TO_DISPLAY_32K_CONN 17 18 PP1VX_DISPLAY_VDD_CONN 47
2.2UF 2.2UF 220PF 19 20
20% 20% 5%
6.3V 6.3V 2 25V
90_MIPI_AP_TO_DISPLAY_D2_CONN_P 21 22 GPIO_AOP_TOUCH_FROM_DISP_BSYNC1_CONN
X5R-CERM 2 X5R-CERM 2 COG 47 GND_VOID 47
0201 0201 01005 47
90_MIPI_AP_TO_DISPLAY_D2_CONN_N GND_VOID 23 24 IO_AP_FROM_DISPLAY_TE_CONN 47
ROOM=PMU ROOM=PMU ROOM=B2B_DISPLAY
25 26
90_MIPI_AP_TO_DISPLAY_CLK_CONN_P 27 28 90_MIPI_AP_TO_DISPLAY_D1_CONN_P
FL8083 47
90_MIPI_AP_TO_DISPLAY_CLK_CONN_N
GND_VOID
29 30
GND_VOID
90_MIPI_AP_TO_DISPLAY_D1_CONN_N
47
FERR-70OHM-25%-0.300A 47 GND_VOID GND_VOID 47

31 32
21
PP3V0_DISPLAY 1 2 PP3V0_DISPLAY_VCI_CONN 47 90_MIPI_AP_TO_DISPLAY_D3_CONN_P
01005 PP3V0_DISPLAY_VCI: Imax = 10mA 47 GND_VOID 33 34 GND_VOID 90_MIPI_AP_TO_DISPLAY_D0_CONN_P 47
C2910 1 ROOM=B2B_DISPLAY 1 C8083 47

90_MIPI_AP_TO_DISPLAY_D3_CONN_N GND_VOID 35 36 GND_VOID 90_MIPI_AP_TO_DISPLAY_D0_CONN_N 47
2.2UF 220PF
20% 5%
6.3V 2 2 25V
X5R-CERM COG 39 40
0201 01005
ROOM=PMU ROOM=B2B_DISPLAY 42
ROOM=B2B_DISPLAY
XW8084
SHORT-0201
50
PP_VDD_MAIN 1 2 PP_VDD_MAIN_DISPLAY_CONN 47
ROOM=B2B_DISPLAY
1 C8084 1 C8085 1 C8086
C XW8085 5%
220PF
5%
220PF
5%
220PF C
SHORT-0201 2 25V
COG 2 25V
COG 2 25V
COG
1 2 01005 01005 01005
ROOM=B2B_DISPLAY ROOM=B2B_DISPLAY ROOM=B2B_DISPLAY
ROOM=B2B_DISPLAY
ROOM=B2B_DISPLAY
Display Control Signals Display MIPI L8000

35OHM-3.0OHM-7GHZ
TAM0403S-SM
R8000 R8004 SYM_VER-1
155S00524
GPIO_PMU_TO_DISPLAY_RESET_L 1
0.00 2 GPIO_PMU_TO_DISPLAY_RESET_CONN_L 47 9 GPIO_ISP_TO_DISPLAY_FLASH_INT 1
0.00 2 GPIO_ISP_TO_DISPLAY_FLASH_INT_CONN 10 BI
90_MIPI_AP_TO_DISPLAY_D0_N 1 4 90_MIPI_AP_TO_DISPLAY_D0_CONN_N 47
56 IN 5 IN 47
0% 0%
PULL-DOWN REQUIRED TO PREVENT 1
R8010 1/32W
MF
1 C8000 1/32W
MF
1 C8004 90_MIPI_AP_TO_DISPLAY_D0_P 2 3 90_MIPI_AP_TO_DISPLAY_D0_CONN_P
220PF 220PF 10 47
-vw
STARTUP GLITCH BI
100K 01005
5%
01005
5% GND_VOID
R8010: 100K Pull-down 5% 25V
1/32W ROOM=B2B_DISPLAY
2 25V
COG
ROOM=B2B_DISPLAY
2 COG ROOM=B2B_DISPLAY
R3091: NOSTUFF MF 01005 01005
2 01005
ROOM=B2B_DISPLAY
ROOM=B2B_DISPLAY ROOM=B2B_DISPLAY L8010
35OHM-3.0OHM-7GHZ
TAM0403S-SM
SYM_VER-1
155S00524
R8001 R8009 90_MIPI_AP_TO_DISPLAY_D1_N 1 4 90_MIPI_AP_TO_DISPLAY_D1_CONN_N
p p
10 IN 47
GPIO_PMU_TO_DISPLAY_PANICB 1
10 2 GPIO_PMU_TO_DISPLAY_PANICB_CONN 47 CLK_GPIO_PMU_TO_DISPLAY_32K 1
0.00 2 CLK_GPIO_PMU_TO_DISPLAY_32K_CONN
56 IN 56 IN 47
5% 0%
1/32W
MF
1 C8001 1/32W
MF
1 C8009 10 IN
90_MIPI_AP_TO_DISPLAY_D1_P 2 3 90_MIPI_AP_TO_DISPLAY_D1_CONN_P 47
01005 220PF 01005 56PF GND_VOID

ROOM=B2B_DISPLAY
5% 5%
2 25V
COG
ROOM=B2B_DISPLAY
2 25V
NP0/C0G
ROOM=B2B_DISPLAY
01005
ROOM=B2B_DISPLAY
01005
ROOM=B2B_DISPLAY
L8020
35OHM-3.0OHM-7GHZ
TAM0403S-SM
B
SYM_VER-1
B R8005 R8003 90_MIPI_AP_TO_DISPLAY_D2_P 1

155S00524
4 90_MIPI_AP_TO_DISPLAY_D2_CONN_P
o
10 IN 47
1.00K 2 AMUX_PMU_FROM_DISPLAY 1
0.00 2 AMUX_PMU_FROM_DISPLAY_CONN
56 OUT
GPIO_AP_FROM_DISPLAY_PANEL_ID 1 GPIO_AP_FROM_DISPLAY_PANEL_ID_CONN 47 22 OUT 47
0%
5%
1/32W 1/32W
MF
1 C8003 10 IN
MF
01005 01005 56PF GND_VOID ROOM=B2B_DISPLAY
5%
ROOM=B2B_DISPLAY ROOM=B2B_DISPLAY
2 25V
NP0/C0G
L8030
35OHM-3.0OHM-7GHZ
01005 TAM0403S-SM
ROOM=B2B_DISPLAY SYM_VER-1
155S00524
R8006 90_MIPI_AP_TO_DISPLAY_D3_P 1 4 90_MIPI_AP_TO_DISPLAY_D3_CONN_P
IO_AP_FROM_DISPLAY_TE 1
0.00 2 IO_AP_FROM_DISPLAY_TE_CONN 47
10 IN 47
10 OUT
0%
1/32W
MF
1 C8006 10 IN
01005 56PF
5% GND_VOID ROOM=B2B_DISPLAY
ROOM=B2B_DISPLAY
2 25V
NP0/C0G
01005 L8040
35OHM-3.0OHM-7GHZ
ROOM=B2B_DISPLAY
TAM0403S-SM
SYM_VER-1
155S00524
90_MIPI_AP_TO_DISPLAY_CLK_P 1 4 90_MIPI_AP_TO_DISPLAY_CLK_CONN_P
R8007 10 IN 47
GPIO_AOP_TOUCH_FROM_DISPLAY_BSYNC1 1
0.00 2 GPIO_AOP_TOUCH_FROM_DISP_BSYNC1_CONN 47
0
56 48 OUT
0% 10 IN
90_MIPI_AP_TO_DISPLAY_CLK_N 2 3 90_MIPI_AP_TO_DISPLAY_CLK_CONN_N 47
1/32W GND_VOID
1
C8007 MF
01005
56PF ROOM=B2B_DISPLAY
5%
25V 2
NP0/C0G
01005
ROOM=B2B_DISPLAY
A A
CLEAR CLEAR
DOMAIN DOMAIN
PWR_100UM P PWR_100UM PP1V8_DISPLAY_DVDD_CONN ? S_PWR_100UM S 100UM-249UM_SPACING PP1V8_DISPLAY_DVDD_CONN,PP3V0_DISPLAY* ?

PWR_100UM P PWR_100UM PP3V0_DISPLAY* ? S_PWR_SHAPE S 250UM+_SPACING PP_VDD_MAIN_DISPLAY_CONN,PP1VX_DISPLAY_VDD* ?
PWR_SHAPE P PWR_SHAPE PP_VDD_MAIN_DISPLAY_CONN,PP1VX_DISPLAY_VDD* ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Touch Connector
Plug: 516S00516
Touch Power
XW8190 J8100
SHORT-0201 PP1V8_TOUCH_S2: IMAX = 73mA AA28DK-20VA1
PP1V8_TOUCH_S2_CONN 48 F-ST-SM
PP1V8_TOUCH_S2
1
53 48 19 1 2 25
21 22
ROOM=B2B_TOUCH
C8190 1 1 C8191
2.2UF 220PF
D
20%
6.3V
X5R-CERM 2 2 COG
5%
25V 48 GPIO_AOP_FROM_TOUCH_CTS_CONN 1 2 SPI1_AP_FROM_TOUCH_MISO_CONN 48 D
0201 01005 48 SPI1_AP_TO_TOUCH_CS_CONN_L 3 4 GPIO_AOP_TOUCH_FROM_DISPLAY_BSYNC_TOUCH_CONN 48
ROOM=B2B_TOUCH
ROOM=B2B_TOUCH
48 GPIO_AP_TO_TOUCH_RESET_CONN_L 5 6 UART1_AOP_TO_TOUCH_TXD_CONN 48
53 48 I2C3_AP_SCL 7 8 I2C3_AP_SDA_CONN 48
R8196 PP5V1_TOUCH_VDDH IMAX = 10mA 48 GPIO_AOP_FROM_TOUCH_INT_CONN_L 9 10 SPI1_AP_TO_TOUCH_MOSI_CONN 48
PP5V1_TOUCH_VDDH 1
0 2 PP5V1_TOUCH_VDDH_CONN 48 CLK_PMU_TO_TOUCH_32K_CONN 11 12 UART1_AOP_FROM_TOUCH_RXD_CONN 48
32 48
5% 48 I2C_TOUCH_SCL 13 14
1/20W
MF
C8149 1 1 C8196 48 SPI1_AP_TO_TOUCH_SCLK_CONN 15 16 I2C_TOUCH_SDA 48
0201 2.2UF 220PF IO_TOUCH_TO_VDDH_EN_CONN 17 18 GPIO_TOUCH_TO_MANY_SCAN_ACTIVE_CONN
ROOM=B2B_TOUCH
20% 5% 48 48
6.3V 2 25V
X5R-CERM 2 COG 48 PP5V1_TOUCH_VDDH_CONN 19 20 PP1V8_TOUCH_S2_CONN 48
0201 01005
ROOM=B2B_TOUCH ROOM=B2B_TOUCH
23 24
26
ROOM=B2B_TOUCH
Pin Assignments based on flex_grape_x1372_3.0.0
53 48 19 PP1V8_TOUCH_S2
Touch and Misc I/O R8116 1
100K
5%
1/32W
AP I2C Filters
MF
01005
C ROOM=B2B_TOUCH
2
R8106 R8120
C
R8101 SPI1_AP_TO_TOUCH_CS_L 1
0.00 2 SPI1_AP_TO_TOUCH_CS_CONN_L 0.00 I2C3_AP_SDA_CONN
CLK_PMU_TO_TOUCH_32K 1
0.00 2 CLK_PMU_TO_TOUCH_32K_CONN 11 IN 48
53 BI
I2C3_AP_SDA 1 2 48
22 IN 48 0%
0%
NOSTUFF 1/32W 1 C8106 1 C8120 0%
1/32W
1/32W
MF
1 C8101 MF
01005
5%
56PF 56PF MF
01005
01005 56PF ROOM=B2B_TOUCH 25V 5% ROOM=B2B_TOUCH
ROOM=B2B_TOUCH
5% 2 NP0/C0G 2 25V
25V
2 NP0/C0G 01005 NP0/C0G
ROOM=B2B_TOUCH
01005
01005 ROOM=B2B_TOUCH
ROOM=B2B_TOUCH
R8107
0.00 I2C3_AP_SCL
R8100 11
SPI1_AP_TO_TOUCH_SCLK 1 2 SPI1_AP_TO_TOUCH_SCLK_CONN 48
HH
IN 53 48 IN
GPIO_AP_TO_TOUCH_RESET_L 0.00 GPIO_AP_TO_TOUCH_RESET_CONN_L 0%
56 IN
1 2 48 1/32W
MF
1 C8107 1 C8121
0% 56PF
1/32W
MF
1 C8100 01005
ROOM=B2B_TOUCH
5%
25V 5%
56PF
01005 220PF 2 NP0/C0G 2 25V
ROOM=B2B_TOUCH
5% 01005 NP0/C0G
25V
2 COG ROOM=B2B_TOUCH
01005
ROOM=B2B_TOUCH
R8102 R8109
SPI1_AP_TO_TOUCH_MOSI 0.00 SPI1_AP_TO_TOUCH_MOSI_CONN
GPIO_AOP_FROM_TOUCH_INT_L 1
0.00 2 GPIO_AOP_FROM_TOUCH_INT_CONN_L 11 IN
1 2 48
56 OUT 48
0%
0%
1/32W 1 C8102 1/32W
MF
1 C8109
MF 01005 56PF
01005 220PF ROOM=B2B_TOUCH
5%
ROOM=B2B_TOUCH
5% 2 25V
2 25V
COG
NP0/C0G
01005
ROOM=B2B_TOUCH
R8110
33.2
B R8130
0.00
11 OUT
SPI1_AP_FROM_TOUCH_MISO 1 2 SPI1_AP_FROM_TOUCH_MISO_CONN 48 B
GPIO_AOP_TOUCH_FROM_DISPLAY_BSYNC_TOUCH_CONN 1%
56 47 IN
GPIO_AOP_TOUCH_FROM_DISPLAY_BSYNC1 1 2 48 1/32W
MF
1 C8110
0%
1/32W 01005 56PF
5%
MF
01005
1 C8130 ROOM=B2B_TOUCH
2 25V
NP0/C0G
ROOM=B2B_TOUCH
56PF 01005
5%
2 25V
NP0/C0G
ROOM=B2B_TOUCH
01005
ROOM=B2B_TOUCH
R8147 R8103
GPIO_TOUCH_TO_MANY_SCAN_ACTIVE 1
0.00 2 GPIO_TOUCH_TO_MANY_SCAN_ACTIVE_CONN 0.00
49 38 25 23 22 OUT 48
13 IN
UART1_AOP_TO_TOUCH_TXD 1 2 UART1_AOP_TO_TOUCH_TXD_CONN 48
0%
1/32W
MF
1 C8147 0%
1/32W 1 C8103
100PF MF
56PF
01005
ROOM=B2B_TOUCH
5%
2 16V
NP0-C0G
01005
ROOM=B2B_TOUCH
2 25V
5% I2C_TOUCH - UNUSED
01005-1 NP0/C0G
ROOM=B2B_TOUCH 01005
ROOM=B2B_TOUCH
48 I2C_TOUCH_SDA
CKPLUS_WAIVE=I2C_PULLUP
I2C_TOUCH_SCL
R8197 R8104 48
CKPLUS_WAIVE=I2C_PULLUP
IO_TOUCH_TO_VDDH_EN 1
0.00 2 IO_TOUCH_TO_VDDH_EN_CONN UART1_AOP_FROM_TOUCH_RXD 1
0.00 2 UART1_AOP_FROM_TOUCH_RXD_CONN 1 1
38 32 IN 48 13 OUT 48
R8150 R8151
vw-
0% 0% 1.00K 1.00K
1/32W
MF 1 C8197 1/32W
MF
1 C8104 5% 5%
01005 01005 56PF 1/32W 1/32W
ROOM=B2B_TOUCH
220PF ROOM=B2B_TOUCH
5% MF MF
5% 2 25V 2 01005 2 01005
2 25V
COG
NP0/C0G
01005
ROOM=B2B_TOUCH ROOM=B2B_TOUCH
01005
l|
ROOM=B2B_TOUCH
ROOM=B2B_TOUCH
R8105
A 56 OUT
GPIO_AOP_FROM_TOUCH_CTS 1
0.00 2 GPIO_AOP_FROM_TOUCH_CTS_CONN 48 A
0%
1/32W
MF
1 C8105
01005 220PF
ROOM=B2B_TOUCH
5%
2 25V
COG
01005
ROOM=B2B_TOUCH
CLEAR
DOMAIN
PWR_200UM P PWR_200UM PP1V8_TOUCH_S2* ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power Sensors R8200
PP1V8_S2 2
10K 1
54 50 46 29 16
5%
50 49 38 19 PP1V8_S2 1/32W
MF
01005
ROOM=B2B_DOCK
1 C8241 GPIO_AOP_FROM_K2_INT_L DOCK FLEX CONNECTOR
56 49 OUT
220PF Rcpt: 516S00554 <-- This one on MLB
5%
25V
2 COG Plug: 516S00555
56 49 OUT
GPIO_AOP_FROM_HALL_FLAP_INT_L
01005
ROOM=B2B_DOCK
1 C8200 1 C8201 J8200
PP1V8_ALWAYS 21 220PF 220PF BK13P0.8-56DS2-0.35V
5% 5% F-ST-SM
1 25V
2 COG 25V
2 COG ROOM=B2B_DOCK
R8235 01005 01005
100K ROOM=B2B_DOCK ROOM=B2B_DOCK
516S00554
5% 61
D
D 1/32W
MF
01005
2 ROOM=B2B_DOCK 57 58
56 49 38
GPIO_PMU_FROM_CHARGER_INT_L
OUT
1
ARC + Bottom Speaker 1 2
C8235 R8250 49 30 MIC1_LOWER_TO_CODEC_AIN1_N MIC1_LOWER_TO_CODEC_AIN1_P 30 49
220PF 82 31 MIC1_LOWER_TO_CODEC_BIAS_FILT_RET 3 4 PP_CODEC_TO_MIC1_LOWER_BIAS_CONN 49
5% 38 31 13 I2S1_AOP_AMPS_FROM_CODEC_ASP2_BCLK 1 2 I2S1_AOP_AMPS_FROM_CODEC_ASP2_BCLK_CONN 49
25V IN 5 6
2 COG 49 30 MIC4_LOWER_TO_CODEC_AIN4_N MIC4_LOWER_TO_CODEC_AIN4_P 30 49
01005 1%
1/32W 31 MIC4_LOWER_TO_CODEC_BIAS_FILT_RET 7 8 PP_CODEC_TO_MIC4_LOWER_BIAS_CONN 49
ROOM=B2B_DOCK MF
01005 50 49 38 19 PP1V8_S2 Pin 9 on DOCK_FLEX: PP1V8_DOTARA_S2 9 10 PP1V8_S2 Pin 10 on DOCK_FLEX: PP1V8_SENSORS_S2 19 38 49 50
ROOM=B2B_DOCK
R8251 11 12
49.9 I2S1_AOP_TO_SPKRAMP_BOT_ARC_MCLK_CONN 49
38 31 13 IN
I2S1_AOP_AMPS_FROM_CODEC_ASP2_LRCLK 1 2 I2S1_AOP_AMPS_FROM_CODEC_ASP2_LRCLK_CONN 49
49 36 35 PP_VAR_USB_RVP 13 14 I2S1_AOP_AMPS_FROM_CODEC_ASP2_BCLK_CONN 49
54 49
I2C2_SMC_SCL I2C Busses 1%
IN 15 16
1/32W SPMI0_NUB_TO_PMU_DOTARA_CLK_CONN 49
I2C2_SMC_SDA MF
54 49 01005 56 49 GPIO_AOP_FROM_SPKAMP_BOT_ARC_INT_L 17 18 I2S1_AOP_FROM_AMPS_CODEC_ASP2_DIN_CONN 49
BI R8252 ROOM=B2B_DOCK
49.9 49 36 IO_HYDRA_TO_CHARGER_VBUS1_VALID_L 19 20 I2S1_AOP_TO_AMPS_CODEC_ASP2_DOUT_CONN 49
38 31 13 I2S1_AOP_TO_AMPS_CODEC_ASP2_DOUT 1 2 I2S1_AOP_TO_AMPS_CODEC_ASP2_DOUT_CONN 49
BI 21 22
I2C1_AOP_SCL 54 49 I2C2_SMC_SDA GPIO_AOP_FROM_HALL_FLAP_INT_L 49 56
54 49 IN
1%
1/32W 54 49 I2C2_SMC_SCL
23 24
I2C1_AOP_SDA MF
54 49 01005 54 49 I2C1_AOP_SDA 25 26 CLK_BBPMU_TO_DOTARA_38M4_1V8_CONN 49
BI R8253
ROOM=B2B_DOCK
49.9 54 49 I2C1_AOP_SCL 27 28
1 C8210 1 C8211 1 C8212 1 C8213 38 31 13 I2S1_AOP_FROM_AMPS_CODEC_ASP2_DIN 1 2 I2S1_AOP_FROM_AMPS_CODEC_ASP2_DIN_CONN 49
OUT 29 30
56PF 56PF 56PF 56PF IO_SPKAMP_TO_SPKAMP_SYNC_CONN 49
1%
5% 5% 5% 5% 1/32W 56 49 GPIO_AOP_FROM_K2_INT_L 31 32 GPIO_PMU_NFC_TO_ARC_RESET_CONN_L 49
25V
2 NP0/C0G 25V
2 NP0/C0G 2 25V 25V MF
NP0/C0G 2 NP0/C0G
01005 56 GPIO_PMU_TO_SPKAMP_BOT_RESET_L 33 34 IO_PMU_TO_DOTARA_RESET_L 22 33 49
01005 01005 01005
ROOM=B2B_DOCK
01005 ROOM=B2B_DOCK
R8254 ROOM=B2B_DOCK
ROOM=B2B_DOCK ROOM=B2B_DOCK 35 36 GPIO_PMU_FROM_CHARGER_INT_L
49.9 38 49 56
13 IN
I2S1_AOP_TO_SPKRAMP_BOT_ARC_MCLK 1 2 I2S1_AOP_TO_SPKRAMP_BOT_ARC_MCLK_CONN 49
49 SPMI0_NUB_BI_PMU_DOTARA_DATA_CONN 37 38 GPIO_PMU_NFC_TO_ARC_TRIG_CONN 49
1%
C8265 1 1/32W 1 C8253 1 C8250 1 C8251 1 C8252 1 C8254 39 40 GPIO_PMU_TO_DOTARA_EN_EXT_1V8 49 56
MF
56PF 01005 56PF 56PF 56PF 56PF 56PF 49 IO_BUTTON_RINGER_A_CONN 41 42 IO_AP_FROM_CHARGER_VBUS_DETECT 7 49
5% ROOM=B2B_DOCK
5% 5% 5% 5% 5%
LOWER MIC1 + LOWER MIC4 25V 25V 25V 25V 25V 25V 30 ANALOG_MIKEYBUS_REFERENCE 43 44 IO_BUTTON_VOL_UP_CONN_L 49
NP0/C0G 2 2 NP0/C0G 2 NP0/C0G 2 NP0/C0G 2 NP0/C0G 2 NP0/C0G
01005 01005
ROOM=B2B_DOCK
01005 01005 01005 01005 45 46 I2S1_AOP_AMPS_FROM_CODEC_ASP2_LRCLK_CONN 49
MIC1_LOWER_TO_CODEC_AIN1_P ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK
49 30 OUT
C NOSTUFF R8255 36 90_HYDRA_DP2_CONN_P GND_VOID 47 48 IO_BT_TO_BOT_SPK_TRIG 38 49
C
MIC1_LOWER_TO_CODEC_AIN1_N IO_SPKAMP_TO_SPKAMP_SYNC 1
121 2 IO_SPKAMP_TO_SPKAMP_SYNC_CONN 90_HYDRA_DP2_CONN_N 49 50 GPIO_TOUCH_TO_MANY_SCAN_ACTIVE
49 30 OUT 38 IN 49 36 GND_VOID 22 23 25 38 48 49
1% 36 90_HYDRA_DP1_CONN_N GND_VOID 51 52 IO_E75_TO_HYDRA_CON_DETECT_CONN_L 49
1 C8220 1 C8221 1/32W
MF 36 90_HYDRA_DP1_CONN_P GND_VOID 53 54 IO_BUTTON_VOL_DOWN_CONN_L 49
56PF 56PF GPIO_AOP_FROM_SPKAMP_BOT_ARC_INT_L 01005 ROOM=B2B_DOCK
56 49 IN
5% 5% 55 56 PP_HYDRA_ACC1_CONN 49
25V
2 NP0/C0G 25V
2 NP0/C0G
01005 01005 49 38 IN
IO_BT_TO_BOT_SPK_TRIG
ROOM=B2B_DOCK ROOM=B2B_DOCK PP_HYDRA_ACC2_CONN 59 60
49
1 C8255 1 C8257 1 C8256 62
R8222 R8257 39PF 56PF 56PF
61.9K 5% 5% 5%
31 PP_CODEC_TO_MIC1_LOWER_BIAS 1 2 PP_CODEC_TO_MIC1_LOWER_BIAS_CONN 49 38 IO_NFC_TO_ARC_RESET_L 1 2 25V 25V 25V
IN 2 NP0-C0G 2 NP0/C0G 2 NP0/C0G
01005-2 ROOM=B2B_DOCK 1% 01005 01005 01005
1 1/32W ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK
150OHM-25%-200MA-0.7DCR C8222 MF
ROOM=B2B_DOCK 220PF 01005
5%
25V
2 COG
01005
R8260
ROOM=B2B_DOCK 1
IO_NFC_TO_ARC_TRIG
61.9K 2
38 IN
ROOM=B2B_DOCK 1%
1/32W
49 30
MIC4_LOWER_TO_CODEC_AIN4_P MF
OUT
01005 R8259
MIC4_LOWER_TO_CODEC_AIN4_N GPIO_PMU_NFC_TO_ARC_RESET_L 1
0.00 2
49 30 56
GPIO_PMU_NFC_TO_ARC_RESET_CONN_L 49
OUT IN
0%
1 C8223 1 C8224 1/32W
MF
56PF 56PF 01005
5% 5% R8262 ROOM=B2B_DOCK
25V 25V 0.00 49 7 IO_AP_FROM_CHARGER_VBUS_DETECT
2 NP0/C0G 2 NP0/C0G
1 2 OUT
01005 01005 56 IN
GPIO_PMU_NFC_TO_ARC_TRIG GPIO_PMU_NFC_TO_ARC_TRIG_CONN 49
ROOM=B2B_DOCK ROOM=B2B_DOCK 0% 1
1/32W 1 C8259 1 C8262 C8236
R8258 1 R8261 1 MF 220PF
200K 200K 01005 56PF 56PF 5%
1% 1% ROOM=B2B_DOCK
5% 5% 25V
R8225 25V 25V COG 2
1/32W 1/32W 2 NP0/C0G 2 NP0/C0G 01005
PP_CODEC_TO_MIC4_LOWER_BIAS 1 2 PP_CODEC_TO_MIC4_LOWER_BIAS_CONN 49 MF MF 01005 01005 ROOM=B2B_DOCK
B 31 B
ROOM=B2B_DOCK ROOM=B2B_DOCK
01005 2 01005 2
150OHM-25%-200MA-0.7DCR 1
01005-2 C8225
ROOM=B2B_DOCK 220PF
5%
25V
2 COG
01005
Buttons
ROOM=B2B_DOCK R8280
Dotara IO_BUTTON_RINGER_A 1
100 2 IO_BUTTON_RINGER_A_CONN
22 OUT 49
38 25 23 22 OUT
GPIO_TOUCH_TO_MANY_SCAN_ACTIVE
49 48 5%
C8280 1 1/32W
Hydra 56 49 IN
GPIO_PMU_TO_DOTARA_EN_EXT_1V8 MF
27PF 01005
5% ROOM=B2B_DOCK
49 36 35
PP_VAR_USB_RVP 49 33 22 IO_PMU_TO_DOTARA_RESET_L 6.3V
IN NP0-C0G 2
XW8230 0201
SHORT-01005 1 C8270 1 C8271 1 C8272 ROOM=B2B_DOCK
36 33
PP_HYDRA_ACC1 1 2 PP_HYDRA_ACC1_CONN 49
220PF 220PF 220PF
5% 5% 5%
ROOM=B2B_DOCK
2 25V 25V 25V R8281
COG 2 COG 2 COG
100
01005 01005 01005 22
IO_BUTTON_VOL_DOWN_L 1 2 IO_BUTTON_VOL_DOWN_CONN_L 49
ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK OUT
XW8231
SHORT-01005 5%
C8281 1 1/32W
36
PP_HYDRA_ACC2 1 2 PP_HYDRA_ACC2_CONN 49 MF
220PF 01005
ROOM=B2B_DOCK 5%
R8277 25V ROOM=B2B_DOCK
1 C8232 1 C8230 1 C8231 33.2 COG 2
220PF 100PF 100PF 22 13 IN
SPMI0_NUB_TO_PMU_DOTARA_CLK 1 2 SPMI0_NUB_TO_PMU_DOTARA_CLK_CONN 49 01005
5% 5% 5% ROOM=B2B_DOCK
16V 16V 1%
2 25V
COG 2 NP0-C0G 2 NP0-C0G 1/32W R8282
01005 01005-1 01005-1 MF 100
ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK
R8278 01005 IO_BUTTON_VOL_UP_L 1 2 IO_BUTTON_VOL_UP_CONN_L
22 OUT 49
33.2 ROOM=B2B_DOCK
22 13 BI
SPMI0_NUB_BI_PMU_DOTARA_DATA 1 2 SPMI0_NUB_BI_PMU_DOTARA_DATA_CONN 49 5%
1 1/32W
1% C8282 MF
1/32W 220PF 01005
MF 5%
01005 R8279 25V ROOM=B2B_DOCK
ROOM=B2B_DOCK 0.00 COG 2
R8233 38 CLK_BBPMU_TO_DOTARA_38M4_1V8 1 2 CLK_BBPMU_TO_DOTARA_38M4_1V8_CONN 49 01005
100 IN ROOM=B2B_DOCK
A 36
IO_E75_TO_HYDRA_CON_DETECT_L 1 2 IO_E75_TO_HYDRA_CON_DETECT_CONN_L 49 A
OUT 0%
1/32W 1 1 1
5% MF
C8277 C8278 C8279
1/32W 01005 27PF 56PF 56PF
MF 5% 5% 5%
01005 ROOM=B2B_DOCK 16V 25V 25V
ROOM=B2B_DOCK 2 NP0-C0G 2 NP0/C0G 2 NP0/C0G
IO_HYDRA_TO_CHARGER_VBUS1_VALID_L 01005-1 01005 01005
36 IN ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK
49
OMIT_TABLE
1 C8233 1 C8234
27PF 220PF
5% 5% TABLE_5_HEAD
16V
2 NP0-C0G 25V
2 COG PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM
01005-1 01005
117S0161 1 RES,0 OHM, 01005 C8279 CRITICAL COMMON
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Medusa Compatibility
21 PP3V0_S2 PP3V0_S2 46
MAKE_BASE=TRUE
PP3V0_S2 36
PP3V0_S2 35
PP3V0_S2 58
38 21 PP1V2_S2 PP1V2_S2 31
D
MAKE_BASE=TRUE
PP1V2_S2 20 D
39 38 33 21 20 3 PP_VDD_MAIN PP_VDD_MAIN 21
MAKE_BASE=TRUE
PP_VDD_MAIN 23
PP_VDD_MAIN 47
PP_VDD_MAIN 24
PP_VDD_MAIN 58
PP_VDD_MAIN 33 34
PP_VDD_MAIN 32
PP_VDD_MAIN 26
PP_VDD_MAIN 28
27 23 21 PP_VDD_BOOST PP_VDD_BOOST 34
MAKE_BASE=TRUE
PP_VDD_BOOST 31
PP_VDD_BOOST 24
PP_VDD_BOOST 28
PP_CPU_PCORE PP_CPU_PCORE
C 19 5
MAKE_BASE=TRUE
14
C
20 PP_CPU_ECORE PP_CPU_ECORE 14
MAKE_BASE=TRUE
19 5 PP_GPU PP_GPU 14
MAKE_BASE=TRUE
19 PP_AVE_S1 PP_AVE_S1 16
MAKE_BASE=TRUE
19 PP_SRAM_S1 PP_SRAM_S1 14
MAKE_BASE=TRUE
19 PP_DISP_S1 PP_DISP_S1 16
MAKE_BASE=TRUE
19 PP_DCS_S1 PP_DCS_S1 16
MAKE_BASE=TRUE
20 PP0V6_VDDQL_S1 PP0V6_VDDQL_S1 7 16
MAKE_BASE=TRUE
19 PP_SOC_S1 PP_SOC_S1 14
MAKE_BASE=TRUE
21 PP0V7_VDD_LOW_S2 PP0V7_VDD_LOW_S2 16
MAKE_BASE=TRUE
21 PP3V3_USB PP3V3_USB 16
MAKE_BASE=TRUE
PP1V1_S2 PP1V1_S2
19
MAKE_BASE=TRUE
t PP1V1_S2
21
16
B 21 PP1V2_SOC PP1V2_SOC 15 B
MAKE_BASE=TRUE
l PP1V2_SOC
PP1V2_SOC
15
8 15
49 38 19 PP1V8_S2 PP1V8_S2 16 29 46 49 54
MAKE_BASE=TRUE
PP1V8_S2 16
PP1V8_S2 35
PP1V8_S2 31
PP1V8_S2 36
PP1V8_S2 58
PP1V8_S2 22 46
55 52 45 43 41 40 33 19 PP1V8_IO PP1V8_IO 16
MAKE_BASE=TRUE
PP1V8_IO 11
PP1V8_IO 16
PP1V8_IO 16
PP1V8_IO 24 25
PP1V8_IO 18
PP1V8_IO 47
PP1V8_IO 6 8 53
PP1V8_IO 28
A A
21 PP0V8_SOC_FIXED_S1 PP0V8_SOC_FIXED_S1 15
MAKE_BASE=TRUE
PP0V8_SOC_FIXED_S1 15
PP0V8_SOC_FIXED_S1 15
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ISP: LPDP Lanes

90_LPDP_ISP_FROM_FCAM_RX_D0_N
op np on on on on no no no pnnp on 90_LPDP_ISP_FROM_FCAM_RX_D0_N
IOC PC P C P C P C P C P
9 OUT IN 43
MAKE_BASE=TRUE Polarity Swapped
9 OUT 90_LPDP_ISP_FROM_FCAM_RX_D0_P 90_LPDP_ISP_FROM_FCAM_RX_D0_P IN 43
MAKE_BASE=TRUE
9 OUT 90_LPDP_ISP_FROM_FCAM_RX_D1_N 90_LPDP_ISP_FROM_FCAM_RX_D1_N IN 43
9 OUT 90_LPDP_ISP_FROM_FCAM_RX_D1_P 90_LPDP_ISP_FROM_FCAM_RX_D1_P IN 43
MAKE_BASE=TRUE
9 OUT 90_LPDP_ISP_FROM_WIDE_RX_D0_P 90_LPDP_ISP_FROM_WIDE_RX_D0_P IN 40
MAKE_BASE=TRUE
9 OUT 90_LPDP_ISP_FROM_WIDE_RX_D0_N 90_LPDP_ISP_FROM_WIDE_RX_D0_N IN 40
MAKE_BASE=TRUE
MAKE_BASE=TRUE
9 OUT 90_LPDP_ISP_FROM_WIDE_RX_D2_N 90_LPDP_ISP_FROM_WIDE_RX_D2_N IN 40
D 9 OUT 90_LPDP_ISP_FROM_WIDE_RX_D1_N
MAKE_BASE=TRUE
90_LPDP_ISP_FROM_WIDE_RX_D1_N 40
D
IN
MAKE_BASE=TRUE
9 OUT 90_LPDP_ISP_FROM_SWIDE_RX_D2_N 90_LPDP_ISP_FROM_SWIDE_RX_D2_N 42
IN
9 OUT 90_LPDP_ISP_FROM_SWIDE_RX_D2_P 90_LPDP_ISP_FROM_SWIDE_RX_D2_P IN 42
MAKE_BASE=TRUE
9 OUT 90_LPDP_ISP_FROM_SWIDE_RX_D1_N 90_LPDP_ISP_FROM_SWIDE_RX_D1_N IN 42
MAKE_BASE=TRUE
9 OUT 90_LPDP_ISP_FROM_SWIDE_RX_D0_N 90_LPDP_ISP_FROM_SWIDE_RX_D0_N 42
IN
MAKE_BASE=TRUE
9 OUT NC_LPDP_ISP_RX_D8_P NO_TEST=1 NC_LPDP_ISP_RX_D8_P
MAKE_BASE=TRUE
9 OUT NC_LPDP_ISP_RX_D8_N NO_TEST=1 NC_LPDP_ISP_RX_D8_N
MAKE_BASE=TRUE
9 OUT 90_LPDP_ISP_FROM_TELE_RX_D1_P 90_LPDP_ISP_FROM_TELE_RX_D1_P IN 41
PC PC PC
MAKE_BASE=TRUE
9 OUT 90_LPDP_ISP_FROM_TELE_RX_D1_N 90_LPDP_ISP_FROM_TELE_RX_D1_N IN 41
MAKE_BASE=TRUE
9 OUT 90_LPDP_ISP_FROM_TELE_RX_D0_N 90_LPDP_ISP_FROM_TELE_RX_D0_N 41
IN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
9 OUT 90_LPDP_ISP_FROM_TELE_RX_D2_N 90_LPDP_ISP_FROM_TELE_RX_D2_N IN 41
MAKE_BASE=TRUE
ISP: LPDP Aux

LPDP_ISP_BI_FCAM_AUX_RX_D0P LPDP_ISP_BI_FCAM_AUX_RX_D0P
0 000
0 000
9 BI BI 43
MAKE_BASE=TRUE
9 BI
LPDP_ISP_BI_SWIDE_AUX_RX_D2P LPDP_ISP_BI_SWIDE_AUX_RX_D2P BI 42
MAKE_BASE=TRUE
LPDP_ISP_BI_TELE_AUX_RX_D5P LPDP_ISP_BI_TELE_AUX_RX_D5P
C 9 BI
MAKE_BASE=TRUE
BI 41
C
9 BI
LPDP_ISP_BI_WIDE_AUX_RX_D9P LPDP_ISP_BI_WIDE_AUX_RX_D9P BI 40
MAKE_BASE=TRUE
B B
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Mt. Whitney vs Avus
D D
56 PP1V8_IO PP1V8_IO 19 33 40 41 43 45 50 55
MAKE_BASE=TRUE
AP_GPIO19: PMU ID
WHITNEY: AP_GPIO_19 = NC
AVUS: AP_GPIO_19 = PP1V8_IO
C C
B B
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AP I2C0
AP I2C
NC_I2C0_AP_SCL MAKE_BASE=TRUE NC_I2C0_AP_SCL OUT 11
NO_TEST=1
D NC_I2C0_AP_SDA MAKE_BASE=TRUE NC_I2C0_AP_SDA 11

D
BI
NO_TEST=1
AP I2C1
53 50 8 6
PP1V8_IO
R1430 1 R1431 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF MASTER AP NUMBER I2C1 DIAGS NUMBER 1 SPEED 100KHZ
01005 2 01005 2
ROOM=SOC ROOM=SOC
DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
11 I2C1_AP_SCL MAKE_BASE=TRUE I2C1_AP_SCL OUT 44
MAKE_BASE=TRUE MIC2 PP1V8_IO 0x56 0xAC, 0xAD 1MHz STROBE_FLEX
11 I2C1_AP_SDA I2C1_AP_SDA BI 44
C C
AP I2C2
53 50 8 6
PP1V8_IO
R1440 1 R1441 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF MASTER AP NUMBER I2C2 DIAGS NUMBER 2 SPEED 1MHZ
01005 2 01005 2
ROOM=SOC ROOM=SOC
38 11 I2C2_AP_SCL MAKE_BASE=TRUE I2C2_AP_SCL
TOP SPK AMP PP1V8_IO 0x40 0x80, 0x81 1MHz MLB_BOT
38 11 I2C2_AP_SDA MAKE_BASE=TRUE I2C2_AP_SDA
B B
AP I2C3
48 19
PP1V8_TOUCH_S2
R1450 1 R1451 1
2.2K 2.2K MASTER AP NUMBER I2C3 DIAGS NUMBER 3 SPEED 400KHZ
5% 5%
1/32W 1/32W
MF MF DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
01005 2 01005 2
ROOM=SOC ROOM=SOC
ROSWELL PP1V8_TOUCH_S2 0x10 0x20, 0x21 1MHz TOUCH_FLEX
11 I2C3_AP_SCL MAKE_BASE=TRUE I2C3_AP_SCL 48
OUT
TOUCH EEPROM PP1V8_TOUCH_S2 0x51 0xA2, 0xA3 1MHz TOUCH_FLEX
11 I2C3_AP_SDA MAKE_BASE=TRUE I2C3_AP_SDA BI 48
AP I2C4
53 50 8 6
PP1V8_IO
A R1460 R1461 A
1
4.7K 4.7K
1% 1%
1/32W 1/32W
MF MF
01005 01005 MASTER AP NUMBER I2C4 DIAGS NUMBER 4 SPEED 400KHZ
2
ROOM=SOC ROOM=SOC

11 I2C4_AP_SCL MAKE_BASE=TRUE I2C4_AP_SCL 11
OUT
MAKE_BASE=TRUE LYNX PP1V8_IO 0x71 0xE2 TBD MLB_TOP
11 I2C4_AP_SDA I2C4_AP_SDA BI 11
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP1V8_S2
AOP I2C0 AOP/SMC I2C D
D 50 49 46 29 16
54
R1630 1 R1631 1
1.00K 1.00K MASTER AOP NUMBER I2C0 DIAGS NUMBER 5 SPEED 750KHZ
5% 5%
1/32W 1/32W
MF MF DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
01005 2 01005 2
ROOM=SOC ROOM=SOC DOPPLER PP1V8_S2 0x58 0xB0, 0xB1 1MHZ SENSOR_FLEX
13
I2C0_AOP_SCL MAKE_BASE=TRUE I2C0_AOP_SCL OUT 46 FOXHOUND PP1V8_S2 0x29 0x52, 0x53 1MHZ SENSOR_FLEX
13
I2C0_AOP_SDA MAKE_BASE=TRUE I2C0_AOP_SDA BI 46
YOGI PP1V8_S2 0x33 0x66, 0x67 1MHZ SENSOR_FLEX
I2C0_AOP_SCL
I2C0_AOP_SDA
oOUT 31
31
MOLY PP1V8_S2 0x0E 0x1C, 0x1D 1MHZ SENSOR_FLEX
BI
BRIGHTON PP1V8_S2 0x4A 0x94, 0x95 TBD MLB_TOP
AOP I2C1
50 49 46 29 16 PP1V8_S2
54
R1640 1 R1641 1 MASTER AOP NUMBER I2C1 DIAGS NUMBER 6 SPEED 400KHZ
2.2K 2.2K
5% 5% DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
1/32W 1/32W
MF MF
01005 2 01005 2 ARC AMP PP1V8_S2 0x41 0x82, 0x83 1MHZ SOUTH_HUB
ROOM=SOC ROOM=SOC
BOTTOM SPKR PP1V8_S2 0x40 0x80, 0x81 1MHZ SOUTH_HUB
13
I2C1_AOP_SCL MAKE_BASE=TRUE I2C1_AOP_SCL OUT 49
I2C1_AOP_SDA MAKE_BASE=TRUE K2 PP1V8_S2 0x5C 0xB8, 0xB9 400KHZ DOCK_FLEX
13 I2C1_AOP_SDA BI 49
C SAKONNET PP1V8_S2 0x08 0x10, 0x11 400KHZ ARC_FLEX C
SMC I2C0
54 50 49 46 29 16
PP1V8_S2
R1650 1 R1651 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005
ROOM=SOC ROOM=SOC2
13
13
I2C0_SMC_SCL
I2C0_SMC_SDA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
I2C0_SMC_SCL
I2C0_SMC_SDA =
[OUT
BI
> 35
35
MASTER
DEVICE
SMC NUMBER
VOLTAGE
I2C0
7-BIT ADDR
DIAGS NUMBER
8-BIT ADDR
7
MAX SPEED
SPEED 400KHZ
LOCATION
=>
CCG2 PP1V8_S2 0x12 0x24, 0x25 1MHz MLB_TOP
I2C0_SMC_SCL {OUT 23
I2C0_SMC_SDA 23
BOOST PP1V8_S2 0x75 0xEA, 0xEB 400KHZ MLB_TOP
BI
B SMC I2C1 B
50 49 46 29 16
PP1V8_S2
54
R1660 1 R1661 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
13
I2C1_SMC_SCL MAKE_BASE=TRUE I2C1_SMC_SCL OUT 36
13
I2C1_SMC_SDA MAKE_BASE=TRUE I2C1_SMC_SDA BI 36
MASTER SMC NUMBER I2C1 DIAGS NUMBER 8 SPEED 400KHZ
HYDRA PP1V8_S2 0x1A 0x34, 0x35 400KHZ MLB_TOP
I2C1_SMC_SCL 34
GECKO PP1V8_S2 0x52 0xA4, 0XA5 1MHZ MLB_TOP
OUT
I2C1_SMC_SDA BI 34
SMC I2C2
54 50 49 46 29 16
PP1V8_S2
R1670 1 R1671 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF MASTER SMC NUMBER I2C2 DIAGS NUMBER 9 SPEED 400KHZ
A 01005
ROOM=SOC2
01005
ROOM=SOC2 A
I2C2_SMC_SCL MAKE_BASE=TRUE YANGTZE PP1V8_S2 0x71 0xE2, 0xE3 400KHZ SOUTH_HUB

13 I2C2_SMC_SCL OUT 49
13
I2C2_SMC_SDA MAKE_BASE=TRUE I2C2_SMC_SDA BI 49 VERIDIAN PP1V8_S2 0x0B 0x16, 0X17 1MHZ BMU_FLEX
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
n
55 52 50 45 43 41 40 33 19 PP1V8_IO
1 1
R3810 R3811
1.00K 1.00K
5%
1/32W
MF
5%
1/32W
MF
CAM_PMU1 IC21: WIDE
01005
2 ROOM=CAM_PMU1 01005
2 ROOM=CAM_PMU1 MASTER CAMERA_PMU NUMBER I2C1 DIAGS NUMBER TBD SPEED 1MHZ

25 I2C1_CAM_PMU1_SCL MAKE_BASE=TRUE I2C1_CAM_PMU1_SCL OUT 40
TORONTO (ON) PP1V8_IO 0x10 0x20, 0x21 1MHz WIDE_CAM
25 I2C1_CAM_PMU1_SDA MAKE_BASE=TRUE I2C1_CAM_PMU1_SDA BI 40
RAMAN PP1V8_IO 0x3C 0x78, 0x79 1MHZ WIDE_CAM
rn
D 24
42
PP1V8_CAM_PMU1_IO_SW D
1 1
R3820 R3821
1.00K 1.00K
5% 5%
1/32W
MF
01005
1/32W
MF
01005
CAM_PMU1 I2C2: SWIDE/LEX/STROBE
2 ROOM=CAM_PMU1 2 ROOM=CAM_PMU1
MASTER CAMERA_PMU NUMBER I2C2 DIAGS NUMBER TBD SPEED 1MHZ

38 25 I2C2_CAM_PMU1_SCL MAKE_BASE=TRUE I2C2_CAM_PMU1_SCL OUT 42
38 25 I2C2_CAM_PMU1_SDA MAKE_BASE=TRUE I2C2_CAM_PMU1_SDA BI 42
WINNIPEG (MB) PP1V8_IO_SW 0x20 0x40, 0x41 1MHz SWIDE_CAM
I2C2_CAM_PMU1_SCL
I2C2_CAM_PMU1_SDA =
tOUT> 26
BI 26
LEX
STROBE
PP1V8_IO_SW
PP1V8_IO_SW
0x75
0x65
0xEA, 0xEB
0xCA, 0xCB
1MHZ
1MHZ
MLB_TOP
MLB_BOT
STROBE I2C: Connected through Interposer
50 45 43 41 40 33 19
55 52
PP1V8_IO
1 1
R3830 R3831
1.00K 1.00K
5% 5%
1/32W
MF
01005
2 ROOM=CAM_PMU1
1/32W
MF
01005
2 ROOM=CAM_PMU1
CAM_PMU1 I2C3: TELE MASTER CAMERA_PMU NUMBER I2C3 DIAGS NUMBER TBD SPEED 1MHZ
25 I2C3_CAM_PMU1_SCL MAKE_BASE=TRUE I2C3_CAM_PMU1_SCL OUT 41 BILLINGS+ (AB) PP1V8_IO 0x20 0x40, 0x41 1MHz TELE_CAM
25 I2C3_CAM_PMU1_SDA MAKE_BASE=TRUE I2C3_CAM_PMU1_SDA BI 41
RAMAN PP1V8_IO 0x1C 0x38, 0x39 1MHZ TELE_CAM
C C
55 52 50 45 43 41 40 33 19 PP1V8_IO
1 1
R3840 R3841
1.00K 1.00K
5%
1/32W
MF
5%
1/32W
MF
CAM_PMU1 I2C4: IRCAM/ROMEO
01005
2 ROOM=CAM_PMU1 01005
2 ROOM=CAM_PMU1
MASTER CAMERA_PMU NUMBER I2C4 DIAGS NUMBER TBD SPEED 1MHZ

25 I2C4_CAM_PMU1_SCL MAKE_BASE=TRUE I2C4_CAM_PMU1_SCL OUT 45
25 I2C4_CAM_PMU1_SDA MAKE_BASE=TRUE I2C4_CAM_PMU1_SDA BI 45 DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
JULIET PP1V8_IO 0x18 0x30, 0x31 1MHz MLB_TOP

I2C4_CAM_PMU1_SCL OUT 45
I2C4_CAM_PMU1_SDA BI 45 ROMEO PP1V8_IO 0x66 0xCC, 0xCD 1MHZ MLB_TOP
B 55 52 50 45 43 41 40 33 19 PP1V8_IO B
1 1
R1220 R1221
1.00K 1.00K
5%
1/32W
MF
5%
1/32W
MF
ISP I2C0: RIGEL
2 01005
ROOM=CAM_PMU1
01005
2 ROOM=CAM_PMU1
MASTER ISP NUMBER I2C0 DIAGS NUMBER TBD SPEED 1MHZ
9 I2C0_ISP_SCL I2C0_ISP_SCL 28
OUT DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
MAKE_BASE=TRUE
9 I2C0_ISP_SDA I2C0_ISP_SDA BI 28
MAKE_BASE=TRUE
RIGEL PP1V8_IO 0x55 0xAA, 0xAB 1MHz MLB_TOP
55 52 50 45 43 41 40 33 19 PP1V8_IO
1 1
R1230 R1231
1.00K 1.00K
5%
1/32W
MF
5%
1/32W
MF
ISP I2C2: FCAM
01005
2 ROOM=CAM_PMU1 2 01005
ROOM=CAM_PMU1
MASTER ISP NUMBER I2C1 DIAGS NUMBER TBD SPEED 1MHZ
9 I2C2_ISP_SCL I2C2_ISP_SCL OUT 43

MAKE_BASE=TRUE
9 I2C2_ISP_SDA I2C2_ISP_SDA BI 43
POTOMAC (MD) PP1V8_IO 0x10 0x20, 0x21 1MHz FCAM
MAKE_BASE=TRUE
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AOP_FUNC_0 GPIO_AOP_FROM_IMU_DATARDY
13 GPIO_AOP_FROM_IMU_DATARDY IN 5 29
MAKE_BASE=TRUE
AOP_FUNC_1 GPIO_AOP_TO_IMU_SPI_CS_L
13 GPIO_AOP_TO_IMU_SPI_CS_L OUT 29
MAKE_BASE=TRUE
AOP_FUNC_2 GPIO_AOP_FROM_PEARL_B2B_DETECT
13 GPIO_AOP_FROM_PEARL_B2B_DETECT IN 45
0 P
MAKE_BASE=TRUE
AOP_FUNC_3 GPIO_AOP_TO_R1_SPI_CS_L
SCM_SPI TRIGGER & CS > 13 GPIO_AOP_TO_R1_SPI_CS_L IN 58
MAKE_BASE=TRUE
AOP_FUNC_4 GPIO_AOP_FROM_R1_INT
13 GPIO_AOP_FROM_R1_INT IN 58
MAKE_BASE=TRUE D
D GPIO_AOP_TO_R1_COREDUMP_TRIGGER
AOP_FUNC_5 13 GPIO_AOP_TO_R1_COREDUMP_TRIGGER 58 NC_AP_GPIO[0-1]: Placeholder Great Dane [Dev]
OUT
MAKE_BASE=TRUE
GPIO_0 12 NC_AP_GPIO0 NC_AP_GPIO0
GPIO_AOP_TO_R1_TIME_SYNC MAKE_BASE=TRUE
AOP_FUNC_6 13 GPIO_AOP_TO_R1_TIME_SYNC 58 NO_TEST=1
OUT
p
MAKE_BASE=TRUE
GPIO_AOP_TO_CODEC_RESET_L MAKE_BASE=TRUE
AOP_FUNC_7 13 GPIO_AOP_TO_CODEC_RESET_L 5 31 NO_TEST=1
OUT
MAKE_BASE=TRUE
GPIO_AOP_TO_CODEC_CLP_EN MAKE_BASE=TRUE
AOP_FUNC_8 GPIO_AOP_TO_CODEC_CLP_EN NO_TEST=1
13 OUT 5 31
MAKE_BASE=TRUE
GPIO_3 12 GPIO_AP_FROM_WLAN_TIME_SYNC_1V2
GPIO_AP_FROM_WLAN_TIME_SYNC_1V2 38
IN
0
GPIO_AOP_FROM_IRCAM_B2B_DETECT MAKE_BASE=TRUE
AOP_FUNC_9 13 GPIO_AOP_FROM_IRCAM_B2B_DETECT 45
IN
MAKE_BASE=TRUE
1.2V GPIO_4 12 GPIO_AP_TO_BB_COREDUMP_1V2
GPIO_AP_TO_BB_COREDUMP_1V2 38
IN
GPIO_AOP_FROM_NFC_HOST_WAKE MAKE_BASE=TRUE
AOP_FUNC_10 13 GPIO_AOP_FROM_NFC_HOST_WAKE 38
IN
MAKE_BASE=TRUE
GPIO_AP_FROM_BB_RESET_DETECT_1V2_L GPIO_AP_FROM_BB_RESET_DETECT_1V2_L
GPIO_5 12 38
GPIO_AOP_FROM_SPKAMP_BOT_ARC_INT_L MAKE_BASE=TRUE
AOP_FUNC_11 13 GPIO_AOP_FROM_SPKAMP_BOT_ARC_INT_L 49
IN
p
MAKE_BASE=TRUE
L
GPIO_AOP_TO_WLAN_CONTEXT_A MAKE_BASE=TRUE
AOP_FUNC_12 13 GPIO_AOP_TO_WLAN_CONTEXT_A 38 NO_TEST=1
MAKE_BASE=TRUE OUT
GPIO_AOP_TO_WLAN_CONTEXT_B MAKE_BASE=TRUE
AOP_FUNC_13 13 GPIO_AOP_TO_WLAN_CONTEXT_B 38 NO_TEST=1
MAKE_BASE=TRUE OUT
GPIO_8 12 NC_AP_GPIO8
NC_AP_GPIO8
GPIO_AOP_FROM_TOUCH_CTS MAKE_BASE=TRUE
AOP_FUNC_14 GPIO_AOP_FROM_TOUCH_CTS NO_TEST=1
13 IN 48
AOP MAKE_BASE=TRUE
GPIO_9 12 GPIO_BOARD_REV3 GPIO_BOARD_REV3 IN 6
GPIO_AOP_BI_PROX_INT_L MAKE_BASE=TRUE
AOP_FUNC_15 13 GPIO_AOP_BI_PROX_INT_L 46
IN
MAKE_BASE=TRUE GPIO_BOARD_REV2
GPIO_10 12 GPIO_BOARD_REV2 6
IN
GPIO_AOP_FROM_ALS_INT_L MAKE_BASE=TRUE
SCM_I2CM0 TRIGGER ---> AOP_FUNC_16 13 GPIO_AOP_FROM_ALS_INT_L 46
IN
P P
MAKE_BASE=TRUE
GPIO_11 12 GPIO_BOARD_REV1
GPIO_BOARD_REV1 6
IN
GPIO_AOP_FROM_K2_INT_L MAKE_BASE=TRUE
AOP_FUNC_17 13 GPIO_AOP_FROM_K2_INT_L 49
IN
MAKE_BASE=TRUE
GPIO_12 12 GPIO_BOARD_REV0
GPIO_BOARD_REV0 6
C IN C
GPIO_AOP_FROM_COMPASS_INT MAKE_BASE=TRUE
AOP_FUNC_18 13 GPIO_AOP_FROM_COMPASS_INT 46
IN
MAKE_BASE=TRUE
GPIO_13 12 GPIO_AP_CANARY1
GPIO_AP_CANARY1 38
IN
P P
GPIO_AOP_FROM_HALL_CASE_INT_L MAKE_BASE=TRUE
AOP_FUNC_19 13 GPIO_AOP_FROM_HALL_CASE_INT_L 38
IN
MAKE_BASE=TRUE
SCM_I2CM1 TRIGGER > GPIO_14 12 GPIO_AP_CANARY2
GPIO_AP_CANARY2 38
SOC IN
GPIO_AOP_FROM_HALL_FLAP_INT_L MAKE_BASE=TRUE
AOP_FUNC_20 13 GPIO_AOP_FROM_HALL_FLAP_INT_L 49
IN
MAKE_BASE=TRUE
GPIO_15 12 GPIO_AP_BI_CCG2_SWDIO
GPIO_AP_BI_CCG2_SWDIO 35
BI
GPIO_AOP_FROM_TOUCH_INT_L GPIO_AOP_FROM_TOUCH_INT_L MAKE_BASE=TRUE
AOP_FUNC_21 13 48
IN
MAKE_BASE=TRUE
GPIO_16 12 GPIO_AP_TO_CCG2_SWCLK
GPIO_AP_TO_CCG2_SWCLK 5 35
OUT
GPIO_AOP_TOUCH_FROM_DISPLAY_BSYNC1 MAKE_BASE=TRUE
AOP_FUNC_22 13 GPIO_AOP_TOUCH_FROM_DISPLAY_BSYNC1 47 48
IN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=1
GPIO_18 12 GPIO_AP_FROM_DISPLAY_PANEL_ID
GPIO_AP_FROM_DISPLAY_PANEL_ID 47
IN
MAKE_BASE=TRUE
GPIO_PMU_TO_CCG2_RESET_L
GPIO_1 22 GPIO_PMU_TO_CCG2_RESET_L OUT 35
MAKE_BASE=TRUE GPIO_19 12 PP1V8_IO PP1V8_IO PMU_ID: AVUS=1, WHITNEY = NC
NC_PMU_GPIO_2
GPIO_2 22 NC_PMU_GPIO_2
MAKE_BASE=TRUE GPIO_20 12 NC_AP_GPIO20 NC_AP_GPIO20
NO_TEST=1
MAKE_BASE=TRUE
SWD_NUB_BI_PMU_SWDIO NO_TEST=1
22 SWD_NUB_BI_PMU_SWDIO MAKE_BASE=TRUE OUT 5 13
0
PMU_SWDIO GPIO_3 GPIO_21 12 NC_AP_GPIO21 NC_AP_GPIO21
MAKE_BASE=TRUE
NO_TEST=1
GPIO_PMU_FROM_WLAN_HOST_WAKE GPIO_PMU_FROM_WLAN_HOST_WAKE
22 IN 38
GPIO_4 MAKE_BASE=TRUE GPIO_22 12 GPIO_AP_TO_NFC_DEV_WAKE GPIO_AP_TO_NFC_DEV_WAKE 38
OUT
MAKE_BASE=TRUE
GPIO_PMU_NFC_TO_ARC_TRIG
22
GPIO_PMU_NFC_TO_ARC_TRIG 49
GPIO_5 OUT
MAKE_BASE=TRUE GPIO_23 12 NC_AP_GPIO23 NC_AP_GPIO23
MAKE_BASE=TRUE
NO_TEST=1
GPIO_PMU_NFC_TO_ARC_RESET_L GPIO_PMU_NFC_TO_ARC_RESET_L
22 OUT 49 GPIO_AP_FROM_CODEC_INT_L
GPIO_6 MAKE_BASE=TRUE GPIO_24 12 GPIO_AP_FROM_CODEC_INT_L 5 31
IN
MAKE_BASE=TRUE
NC_PMU_GPIO_7
GPIO_7 22 NC_PMU_GPIO_7 GPIO_AP_FROM_SPKRAMP_TOP_INT_L
MAKE_BASE=TRUE GPIO_25 12 GPIO_AP_FROM_SPKRAMP_TOP_INT_L 38
IN
B NO_TEST=1 MAKE_BASE=TRUE B
NC_PMU_GPIO_8
GPIO_8 22 NC_PMU_GPIO_8 GPIO_AP_TO_SPKRAMP_TOP_RESET_L GPIO_AP_TO_SPKRAMP_TOP_RESET_L
MAKE_BASE=TRUE GPIO_26 12 38
OUT
NO_TEST=1 MAKE_BASE=TRUE
GPIO_PMU_FROM_BB_PCIE_HOST_WAKE_1V2_L GPIO_AP_FROM_BT_AUDIO_SYNC
22 GPIO_PMU_FROM_BB_PCIE_HOST_WAKE_1V2_L 38 12 GPIO_AP_FROM_BT_AUDIO_SYNC 38
pc
GPIO_9 IN IN
MAKE_BASE=TRUE GPIO_27 MAKE_BASE=TRUE
NC_PMU_GPIO_10
GPIO_10 22 NC_PMU_GPIO_10 GPIO_AP_TO_AMUX_PMU_SYNC
MAKE_BASE=TRUE GPIO_28 12 GPIO_AP_TO_AMUX_PMU_SYNC 22
OUT
22
GPIO_PMU_FROM_CHARGER_INT_L GPIO_PMU_FROM_CHARGER_INT_L 38 49
GPIO_11 IN GPIO_AP_TO_TOUCH_RESET_L
MAKE_BASE=TRUE GPIO_29 12 GPIO_AP_TO_TOUCH_RESET_L 48
OUT
MAKE_BASE=TRUE
PMU 22
GPIO_PMU_FROM_CODEC_WAKE_L GPIO_PMU_FROM_CODEC_WAKE_L 31
IN
p
GPIO_12 MAKE_BASE=TRUE GPIO_30 12 NC_AP_GPIO30 NC_AP_GPIO30
MAKE_BASE=TRUE
GPIO_PMU_TO_AMUX_PMU_SUPER_TP GPIO_PMU_TO_AMUX_PMU_SUPER_TP NO_TEST=1
22 OUT 22
GPIO_13 MAKE_BASE=TRUE GPIO_31 12 NC_AP_GPIO31 NC_AP_GPIO31
CKPLUS_WAIVE=SINGLE_COMP_NET
MAKE_BASE=TRUE
GPIO_PMU_TO_R1_RESET_L NO_TEST=1
HOLD Bit: Held Through 1 Reset GPIO_14 22 GPIO_PMU_TO_R1_RESET_L OUT 58
MAKE_BASE=TRUE
GPIO_PMU_TO_NAND_LOW_BATT_BOOT_L
GPIO_15 22 GPIO_PMU_TO_NAND_LOW_BATT_BOOT_L OUT 18
MAKE_BASE=TRUE
CLK_GPIO_PMU_TO_DISPLAY_32K CLK_GPIO_PMU_TO_DISPLAY_32K
22 OUT 47
IRQ GPIO_16 MAKE_BASE=TRUE
GPIO_PMU_TO_WLAN_REG_ON GPIO_PMU_TO_WLAN_REG_ON: HOLD bit required
22 GPIO_PMU_TO_WLAN_REG_ON OUT 38
o
HOLD Bit: Held Through 1 Reset GPIO_17 MAKE_BASE=TRUE
CLK_GPIO_PMU_TO_WLAN_R1_32K CLK_GPIO_PMU_TO_WLAN_R1_32K CLK_GPIO_PMU_TO_WLAN_R1_32K: HOLD bit required
22 OUT 22 38 58
GPIO_PMU_TO_SPKAMP_BOT_RESET_L GPIO_PMU_TO_SPKAMP_BOT_RESET_L
22 OUT 49
GPIO_PMU_TO_DOTARA_EN_EXT_1V8
GPIO_20 22 GPIO_PMU_TO_DOTARA_EN_EXT_1V8 OUT 49
MAKE_BASE=TRUE
A A
GPIO_PMU_TO_BBPMU_RESET_L
22 GPIO_PMU_TO_BBPMU_RESET_L OUT 38
o
GPIO_21 MAKE_BASE=TRUE
Sequenced GPIOs GPIO_PMU_TO_NFC_EN
GPIO_22 22 GPIO_PMU_TO_NFC_EN OUT 38
p
MAKE_BASE=TRUE
GPIO_PMU_TO_BOOST_EN GPIO_PMU_TO_BOOST_EN
GPIO_23 22 OUT 23
MAKE_BASE=TRUE
GPIO_24 22
GPIO_PMU_TO_DISPLAY_PANICB GPIO_PMU_TO_DISPLAY_PANICB 47
OUT
MAKE_BASE=TRUE
GPIO_PMU_TO_DISPLAY_RESET_L GPIO_PMU_TO_DISPLAY_RESET_L
GPIO_25 22 OUT 47
MAKE_BASE=TRUE
8 7 6 5 4 3 2 CDS_LIB=apple
1
8 7 6 5 4 3 2 1
SOC: Display
SOC: Misc 10
NC_LPDP_AP_TX0P NC_LPDP_AP_TX0P
7
NC_AP_TMR32_PWM0 NC_AP_TMR32_PWM0 MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1 10
NC_LPDP_AP_TX0N NC_LPDP_AP_TX0N SOC: AON
7
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1 10
7
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1 10
NC_LPDP_AP_TX1N NC_LPDP_AP_TX1N
7
NC_PAD_MTR_VREF_POS NC_PAD_MTR_VREF_POS MAKE_BASE=TRUE
NO_TEST=1
NC_CLK_CLK24M_OUT
MAKE_BASE=TRUE
NC_LPDP_AP_TX2P 13 NC_CLK_CLK24M_OUT
NO_TEST=1 10 NC_LPDP_AP_TX2P MAKE_BASE=TRUE
NO_TEST=1
7
NC_PAD_MTR_VREF_NEG NC_PAD_MTR_VREF_NEG MAKE_BASE=TRUE
NO_TEST=1
D
MAKE_BASE=TRUE
NO_TEST=1 10
NC_LPDP_AP_TX2N NC_LPDP_AP_TX2N D
7
NC_USB_ID_AP NC_USB_ID_AP MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1 10
MAKE_BASE=TRUE
SOC: PCIe 10
NC_LPDP_AP_TX3N NC_LPDP_AP_TX3N
NO_TEST=1
MAKE_BASE=TRUE
NC_PCIE1_AP_CLKREQ_L NC_PCIE1_AP_CLKREQ_L NO_TEST=1
8
MAKE_BASE=TRUE 10
NC_LPDP_AP_AUXP NC_LPDP_AP_AUXP
NC_PCIE1_AP_REF_CLK_P NC_PCIE1_AP_REF_CLK_P NO_TEST=1
8
MAKE_BASE=TRUE 10
NC_LPDP_AP_AUXN NC_LPDP_AP_AUXN
NC_PCIE1_AP_REF_CLK_N NC_PCIE1_AP_REF_CLK_N NO_TEST=1
8
MAKE_BASE=TRUE 10
NC_LPDP_AP_RCALP NC_LPDP_AP_RCALP
NC_PCIE1_AP_RX_P NC_PCIE1_AP_RX_P NO_TEST=1
8
MAKE_BASE=TRUE 10
NC_LPDP_AP_RCALN NC_LPDP_AP_RCALN 13 NC_SPI1_AOP_MISO NC_SPI1_AOP_MISO
NO_TEST=1 MAKE_BASE=TRUE MAKE_BASE=TRUE
NO_TEST=1
NC_PCIE1_AP_RX_N NC_PCIE1_AP_RX_N NO_TEST=1
8
MAKE_BASE=TRUE 10
NC_I2C_DISP_SCL NC_I2C_DISP_SCL 13 NC_SPI1_AOP_MOSI NC_SPI1_AOP_MOSI
MAKE_BASE=TRUE MAKE_BASE=TRUE
NO_TEST=1
NC_PCIE1_AP_TX_P NC_PCIE1_AP_TX_P NO_TEST=1 NO_TEST=1
8
MAKE_BASE=TRUE 10
NC_I2C_DISP_SDA NC_I2C_DISP_SDA 13 NC_SPI1_AOP_SCLK NC_SPI1_AOP_SCLK
NO_TEST=1 MAKE_BASE=TRUE MAKE_BASE=TRUE
NC_PCIE1_AP_TX_N NC_PCIE1_AP_TX_N NO_TEST=1 NO_TEST=1
8
MAKE_BASE=TRUE 10
NC_TOUCH_BSYNC0_DISP NC_TOUCH_BSYNC0_DISP
NC_PCIE1_AP_RESET_L NC_PCIE1_AP_RESET_L NO_TEST=1
8
MAKE_BASE=TRUE 10
NC_TOUCH_BSYNC1_DISP NC_TOUCH_BSYNC1_DISP
NO_TEST=1
MAKE_BASE=TRUE
NC_PCIE2_CLKREQ_L NC_PCIE2_CLKREQ_L NO_TEST=1
8
MAKE_BASE=TRUE 10
NC_POL_DISP NC_POL_DISP
NC_PCIE2_AP_REF_CLK_P NC_PCIE2_AP_REF_CLK_P NO_TEST=1
8
MAKE_BASE=TRUE 10
NC_WAKEUP_DP_DISP NC_WAKEUP_DP_DISP
NC_PCIE2_AP_REF_CLK_N NC_PCIE2_AP_REF_CLK_N NO_TEST=1
8
NC_EDP_HPD_DISP NC_EDP_HPD_DISP
C NC_PCIE2_AP_RX_P
MAKE_BASE=TRUE
NO_TEST=1
10
MAKE_BASE=TRUE
NO_TEST=1
C
8 NC_PCIE2_AP_RX_P SOC: Serial
MAKE_BASE=TRUE
NO_TEST=1
8
NC_PCIE2_AP_RX_N NC_PCIE2_AP_RX_N 11
NC_UART1_AP_CTS_1V2_L NC_UART1_AP_CTS_1V2_L
NO_TEST=1
NO_TEST=1
8
NC_PCIE2_AP_TX_P NC_PCIE2_AP_TX_P 11
NC_UART1_AP_RTS_1V2_L NC_UART1_AP_RTS_1V2_L
NO_TEST=1
NO_TEST=1
8
NC_PCIE2_AP_TX_N NC_PCIE2_AP_TX_N 11
NC_UART1_AP_RXD_1V2 NC_UART1_AP_RXD_1V2
NO_TEST=1 NO_TEST=1
8
NC_PCIE2_AP_RESET_L NC_PCIE2_AP_RESET_L 11
NC_UART1_AP_TXD_1V2 NC_UART1_AP_TXD_1V2
NO_TEST=1 NO_TEST=1
11
NC_UART2_AP_CTS_L NC_UART2_AP_CTS_L
MAKE_BASE=TRUE
NO_TEST=1
NC_UART2_AP_RTS_L NC_UART2_AP_RTS_L
SOC: ISP 11
MAKE_BASE=TRUE
NO_TEST=1
9
NC_LPDP_ISP_AUX_RX_D1P NC_LPDP_ISP_AUX_RX_D1P 11
NC_UART2_AP_RXD NC_UART2_AP_RXD
NO_TEST=1 NO_TEST=1
9
NC_UART2_AP_TXD NC_UART2_AP_TXD
NO_TEST=1 NO_TEST=1
9
NC_UART3_AP_CTS_L NC_UART3_AP_CTS_L
NO_TEST=1 NO_TEST=1
9
NC_UART3_AP_RTS_L NC_UART3_AP_RTS_L
NO_TEST=1
NO_TEST=1
9
NO_TEST=1 NO_TEST=1
9 NC_LPDP_ISP_AUX_RX_D8P NC_LPDP_ISP_AUX_RX_D8P 11
B NO_TEST=1
NO_TEST=1
B
9
MAKE_BASE=TRUE
MAKE_BASE=TRUE NO_TEST=1
NO_TEST=1
9
MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
11
NC_I2S1_AP_MCLK NC_I2S1_AP_MCLK
MAKE_BASE=TRUE
NO_TEST=1
11
NC_I2S2_AP_MCLK NC_I2S2_AP_MCLK
9
NC_I2C1_ISP_SCL NC_I2C1_ISP_SCL MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
9
NC_I2C1_ISP_SDA NC_I2C1_ISP_SDA
MAKE_BASE=TRUE
NO_TEST=1
9 NC_ISP_GPIO6 NC_ISP_GPIO6
MAKE_BASE=TRUE
NO_TEST=1
9 NC_ISP_GPIO7 NC_ISP_GPIO7
MAKE_BASE=TRUE
NO_TEST=1 11 NC_I2S3_AP_DIN NC_I2S3_AP_DIN
MAKE_BASE=TRUE
NO_TEST=1
11 NC_I2S3_AP_DOUT NC_I2S3_AP_DOUT
MAKE_BASE=TRUE
NO_TEST=1
11
NC_I2S3_AP_BCLK NC_I2S3_AP_BCLK
MAKE_BASE=TRUE
NO_TEST=1
NC_I2S3_AP_LRCLK NC_I2S3_AP_LRCLK
A 11
MAKE_BASE=TRUE
NO_TEST=1
A
11 NC_I2S3_AP_MCK NC_I2S3_AP_MCK
MAKE_BASE=TRUE
NO_TEST=1
11 NC_PDM_AP_OUT_DAT NC_PDM_AP_OUT_DAT
MAKE_BASE=TRUE
NO_TEST=1
11
NC_SPI4_MISO_AP NC_SPI4_MISO_AP
MAKE_BASE=TRUE
NO_TEST=1
11
NC_SPI4_SCLK_AP NC_SPI4_SCLK_AP
MAKE_BASE=TRUE
NO_TEST=1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I218
69 38 50_WLAN_A_TX0 50_WLAN_A_TX0 PP_VDD_MAIN PP_VDD_MAIN 50 69
PP1V8_S2 PP1V8_S2 :FEM Imax = 40mA

Rcpt: 516S00529 <-- This one on MLB 69 38 50_WLAN_A_RX0_LAA 50_WLAN_A_RX0 PP1V8_S2 50 69
PP1V8_S4 :FEM Imax = 40mA
Plug: 516S00528 69 38 50_WLAN_A_TX1 50_WLAN_A_TX1 PP1V8_S4 PP1V8_S4 19 21 38 58 66 69
1 C9003 1 C9004 1 C9005
50_WLAN_A_RX1_LAA 50_WLAN_A_RX1 50_LAA_TO_ANT_LAT 50_LAA_TO_ANT_LAT 4UF 4UF 4UF
JUAT 69 38
50_LAA_TO_ANT_UAT 50_LAA_TO_ANT_UAT
58 63 69
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
MM3531-2700A22 58 64 69 CERM-X5R CERM-X5R CERM-X5R
F-ST-SM 69 38 5GHZ_C0_VDET 5GHZ_C0_VDET 0201 0201 0201
ROOM=LAT_FEM ROOM=LAT_FEM ROOM=LAT_FEM
1 12 69 38 5GHZ_C1_VDET 5GHZ_C1_VDET LAA_MLB 50_LAA_TO_XCVR_LAT 50_LAA_TO_XCVR_LAT 38 69
GND_VOID=TRUE 50_ANT6 58 64 PLACE_NEAR=U_5G_L_W.19:3MM PLACE_NEAR=U_5G_L_W.19:3MM PLACE_NEAR=U_5G_L_W.19:3MM
66666666666
ooooooooooo
2 13 50_LAA_TO_XCVR_UAT 50_LAA_TO_XCVR_UAT 38 69
3 14 69 38 RFA0_SW_CTRL0 RFA0_SW_CTRL0
GND_VOID=TRUE 50_R1_AOA1 58 67 69
4 15 69 38 RFA0_SW_CTRL1 RFA0_SW_CTRL1 RFFE_LAA_LAT_VIO VIO_RFFE_XCVR_TO_RX_1V8 VIO_RFFE_XCVR_TO_RX_1V8 38 58 60
64 58 UAT_SAWTOOTH_A_B2B 69
MAKE_BASE=TRUE
5 16 69 38 RFA0_SW_CTRL2 RFA0_SW_CTRL2 RFFE_LAA_LAT_CLK RFFE_XCVR_TO_FE_RX_CLK RFFE_XCVR_TO_FE_RX_CLK 38 58 60

50_R1_AOA3 MAKE_BASE=TRUE
D 6 17
GND_VOID=TRUE 58 67
69 38 RFA1_SW_CTRL0
RFA1_SW_CTRL1
RFA1_SW_CTRL0 RFFE_LAA_LAT_DATA
69
RFFE_XCVR_TO_FE_RX_DATA RFFE_XCVR_TO_FE_RX_DATA MAKE_BASE=TRUE
38 58 60 D
69 38 RFA1_SW_CTRL1 RFFE_LAA_UAT_VIO RFFE_LAA_UAT_VIO 38 69
7 18 GND_VOID=TRUE 50_ANT2 38 58
8 19 69 38 RFA1_SW_CTRL2 RFA1_SW_CTRL2 RFFE_LAA_UAT_CLK RFFE_LAA_UAT_CLK 38 69
RFFE_LAA_UAT_DATA RFFE_LAA_UAT_DATA 38 69
9 20 GND_VOID=TRUE 50_R1_AOA0 58 67
10 21
11 22 50_LAA_TO_R1 50_LAA_TO_R1 58 67 69
64 58 UAT_SAWTOOTH_B_B2B GND_VOID=TRUE 50_ANT4 38 58
R1_TO_BB_LAA_SW_CTRL IO_R1_TO_BB_LAA_SW_CTRL 38 58 66 69
SHLD
23 29
666666
24 30
25 31
m
26 32 I219
27 33 69 64 58 50_LAA_TO_ANT_UAT 50_LAA_TO_ANT_UAT VFE_LO_1V2 VFE_LO_1V2 38 60
28 34 69 63 58 50_LAA_TO_ANT_LAT 50_LAA_TO_ANT_LAT VFE_HI_3V15 VFE_HI_3V15 38 60
o
ROOM=BB_UAT
63 38 50_WLAN_G_LAT 50_WLAN_G_LAT VPA_ET_HB VPA_ET_HB 38 60
VPA_ET_UHB VPA_ET_UHB 38 61
67 64 58 50_R1_ANT_CH9 50_R1_ANT_CH9 VPA_2G VPA_2G 38 61
.c VIO_RFFE_XCVR_TO_TX_1V8
VIO_RFFE_XCVR_TO_RX_1V8
RFFE_XCVR_TO_LBTX_CLK
RFFE_XCVR_TO_LBTX_DATA
VIO_RFFE_XCVR_TO_TX_1V8
38 60
38 58 60
38 61
38 61
h
RFFE_XCVR_TO_HBTX_CLK RFFE_XCVR_TO_HBTX_CLK 38 60
RFFE_XCVR_TO_HBTX_DATA RFFE_XCVR_TO_HBTX_DATA 38 60
RFFE_XCVR_TO_FE_RX_CLK RFFE_XCVR_TO_FE_RX_CLK 38 58 60
c
RFFE_XCVR_TO_FE_RX_DATA RFFE_XCVR_TO_FE_RX_DATA 38 58 60
C 50_XCVR_TX0_HB 50_XCVR_TX0_HB 38 60 C
50_XCVR_TX0_MB3
e
50_XCVR_TX0_MB3 38 60
50_XCVR_TX1_HB 50_XCVR_TX1_HB 38 60
50_XCVR_TX1_MB1 50_XCVR_TX1_MB1 38 60
50_XCVR_TX0_MB2
T
50_XCVR_TX0_MB2 38 61
50_XCVR_TX0_LB2 50_XCVR_TX0_LB2 38 61
RADIO_MLB_ICE_LOFT
50_XCVR_TX0_MB1 50_XCVR_TX0_MB1 38 61
50_XCVR_TX1_UHB 50_XCVR_TX1_UHB
1
38 61
50_XCVR_RX2_UHB_PRX 50_XCVR_RX2_UHB_PRX 38 61
50_XCVR_RX6_MB_UHB_PRX 50_XCVR_RX6_MB_UHB_PRX 38 60
e
50_XCVR_RX8_MLB_HB_PRX 50_XCVR_RX8_MLB_HB_PRX 38 60
50_XCVR_RX9_MLB_HB_PRX
li
I223
50_XCVR_RX9_MLB_HB_PRX 38 60
50_XCVR_RX10_MLB_HB_PRX 50_XCVR_RX10_MLB_HB_PRX 38 60
69 66 58 38 21 19 PP1V8_S4 PP1V8_S4
50_XCVR_RX14_LB_MLB_PRX
50_XCVR_RX14_LB_MLB_PRX 38 61
66 21 PP1V0_R1_ANA_S4 PP1V0_R1_ANA
66 21 PP1V0_S4 PP1V0_R1_SOC
50_MMDSM_MHB_ANT 50_MMDSM_MHB_ANT 38 60
66 56 IN GPIO_PMU_TO_R1_RESET_L APPMU_TO_R1_RESET_L
50_MMDSM_UHB_ANT
b
50_MMDSM_UHB_ANT 38 61
66 56 38 22 IN CLK_GPIO_PMU_TO_WLAN_R1_32K APPMU_TO_WLAN_32K_CLK
QOC qc qc
66 56 IN GPIO_AOP_TO_R1_COREDUMP_TRIGGER AOP_TO_R1_COREDUMP_TRIG
50_ANT2
50_ANT2 38 58
Freq SPI: 10MHz 50_ANT4
50_ANT4 38 58
GPIO_AOP_TO_R1_SPI_CS_L
o
66 56 IN SPI_AOP_TO_R1_CS_L
50_ANT6_UHB 50_ANT6_UHB 38 64
66 29 13 IN SPI0_AOP_TO_IMU_R1_SCLK SPI_AOP_TO_R1_SCLK
50_HBPA_ANT3
50_HBPA_ANT3 38 60
66 29 13 IN SPI0_AOP_TO_IMU_R1_MOSI SPI_AOP_TO_R1_MOSI
50_HBPA_DRX_OUT
50_HBPA_DRX_OUT 38 60
66 29 13 OUT SPI0_AOP_FROM_IMU_R1_MISO SPI_R1_TO_AOP_MISO
50_LB_TX_ANT1
50_LB_TX_ANT1 38 63
66 56 GPIO_AOP_FROM_R1_INT R1_TO_AOP_INT
50_UHBPA_2G_LB_OUT
50_UHBPA_2G_LB_OUT 38 61
M
B 66 38 I2C_R1_TO_NFC_SCL I2C_R1_TO_SE_SCL
50_UHBPA_UHB 50_UHBPA_UHB 38 61 B
.
66 38 I2C_R1_BI_NFC_SDA I2C_R1_TO_SE_SDA ROSE_MLB
ROOM=R1 58 38 50_ANT2 50_ANT2 50_CPLL_CPLOUT1 50_CPLL_CPLOUT1 38 62

66 38 IO_BB_TO_R1_COEX BB_TO_R1_COEX
58 38 50_ANT4 50_ANT4 50_CPLL_CPLOUT2 50_CPLL_CPLOUT2 38 62
66 38 IO_WLAN_TO_R1_COEX WLAN_TO_R1_COEX
50_ANT6
w
64 58 50_ANT6
66 38 IO_R1_TO_WLAN_COEX R1_TO_WLAN_COEX
LAT_SUBUS_A LAT_SAWTOOTH_A 38 64
64 50 PP3V0_S2 PP3V0_S2 LAT_SUBUS_B LAT_SAWTOOTH_B 38 64

66 56 IN GPIO_AOP_TO_R1_TIME_SYNC AOP_TO_R1_TIME_SYNC
UAT_SAWTOOTH_A
UAT_SUBUS_A 38 64
66 38 IO_BT_TO_R1_TIME_SYNC BT_TO_R1_TIME_SYNC
UAT_SUBUS_B UAT_SAWTOOTH_B 38 44 64
66 38 GPIO_BT_TO_R1_DEV_WAKE
w
BT_TO_R1_WAKE
64 58 UAT_SAWTOOTH_A_B2B UAT_SUBUS_A_B2B
64 58 UAT_SAWTOOTH_B_B2B UAT_SUBUS_B_B2B
SWD_NUB_BI_R1_SWDIO
qq
66 13 BI SWD_AOP_BI_R1_SWDIO
66 38 22 18 13 IN SWD_NUB_TO_MANY_SWCLK SWD_AOP_TO_MANY_SWCLK
w
67 58 50_R1_AOA1 50_R1_ANT0 RADIO PA NTC
67 58 50_R1_AOA3 50_R1_ANT1
67 58 50_R1_AOA0 50_R1_ANT3 1
67 64 58 50_R1_ANT_CH9 50_R1_ANT_CH9 I228
OMIT
69 67 58 50_LAA_TO_R1 50_LAA_TO_R1 C3043 1 R3043 XW3043
100PF 10KOHM-1% NTC_RADIO_PA_P 22 SHORT-20L-0.05MM-SM
NO_TEST=1 5% NTC_RADIO_PA_N 1 2
66 NC_R1_TUNER_GPO1 R1_TUNER_GPO1 16V 2
NP0-C0G
01005
ROOM=PMU
NO_TEST=1 2 ROOM=PMU
NC_R1_TUNER_GPO2 01005-1
•if
66 R1_TUNER_GPO2 ROOM=PMU
69 66 58 38 IO_R1_TO_BB_LAA_SW_CTRL R1_TO_BB_LAA_SW_CTRL
POWER UP SEQUENCE: Assert PMU_TO_R1_RESET_L >500uS after PP1V8_S4 AND PP1V0_S4 rails
A A
CLEAR
DOMAIN NET RULE ASSIGNMENT CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* OVERRIDE
DOMAIN
(E,P,S)
CONSTRAINT SET COMMA SEPARATED NET NAMES (WILDCARD SUPPORT EX: DDR* ) CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
P PWR_100UM LAT_SAWTOOTH*, UAT_SAWTOOTH* RFFE_SHIELD S A_DIELECTRIC_2X LAT_SAWTOOTH*, UAT_SAWTOOTH* ?
CLEAR
DOMAIN
CLEAR
DOMAIN
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N S_PWR_100UM S 100UM-249UM_SPACING PP1V8_S4 ?
PWR_100UM P PWR_100UM PP1V8_S4 ? S_PWR_SHAPE S 250UM+_SPACING PP1V0_S4 ?
PWR_SHAPE P PWR_SHAPE PP1V0_S4 ? S_PWR_200UM S 100UM-249UM_SPACING PP1V0_R1_ANA_S4 ?
PWR_200UM P PWR_200UM PP1V0_R1_ANA_S4 ?
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ICE19.1 RADIO_MLB_LOFT
LAST_MODIFICATION=Fri May 3 22:17:25 2019 50_LAA_TO_ANT_UAT VFE_LO_1V2
00
0000 00 00000000 00 000000 00000000 00000000 000 00

64 58 61 60 58
D
IO
D 63 58 IO
50_LAA_TO_ANT_LAT 62 61 60 58 IO
VFE_HI_3V15
PAGE CSA CONTENTS SYNC DATE 63 58 50_WLAN_G_LAT 60 58 VPA_ET_HB

IO IO
59 1 SCH,RADIO_MLB_ICE_LOFT 61 58 IO
VPA_ET_UHB
58 50_R1_ANT_CH9 61 58 VPA_2G
60 2 HB SPAD 05/01/2018 64 IO IO
61 3 UHB MLB SPAD 05/01/2018 62 61 60 58 IO

VIO_RFFE_XCVR_TO_TX_1V8
61 60 58 VIO_RFFE_XCVR_TO_RX_1V8
62 4 LOWER COUPLER 05/01/2018 62 61 58
IO
IO
63 5 LOWER ANTENNA FEEDS 05/01/2018 62 61 58 IO

61 60 58 RFFE_XCVR_TO_HBTX_CLK
64 6 ANTENNA SYSTEM 05/01/2018 61 60 58
IO
RFFE_XCVR_TO_HBTX_DATA
IO
61 60 58 IO
RFFE_XCVR_TO_FE_RX_CLK
61 60 58 IO
RFFE_XCVR_TO_FE_RX_DATA
60 58 IO
50_XCVR_TX0_HB
60 58 IO
50_XCVR_TX0_MB3
60 58 IO
50_XCVR_TX1_HB
60 58 IO
50_XCVR_TX1_MB1
61 58 IO
50_XCVR_TX0_MB2
61 58 IO
50_XCVR_TX0_LB2
61 58 IO
50_XCVR_TX0_MB1
61 58 IO
50_XCVR_TX1_UHB
61 58 IO
50_XCVR_RX2_UHB_PRX
60 58 IO
50_XCVR_RX6_MB_UHB_PRX
C 60 58
60 58
IO
IO
50_XCVR_RX9_MLB_HB_PRX C
60 58 IO
61 58 IO
50_XCVR_RX14_LB_MLB_PRX
60 58 IO
50_MMDSM_MHB_ANT
61 58 IO
50_MMDSM_UHB_ANT
59 58 IO
50_ANT2
59 58 IO
50_ANT4
64 58 IO
50_ANT6_UHB
60 58 IO
50_HBPA_ANT3
60 58 IO
50_HBPA_DRX_OUT
63 58 IO
50_LB_TX_ANT1
61 58 IO
50_UHBPA_2G_LB_OUT
61 58 IO
50_UHBPA_UHB
50_ANT2 50_CPLL_CPLOUT1
000
59 58 IO 62 58 IO
58 IO
50_ANT4 62 58 IO
50_CPLL_CPLOUT2
59
58 IO
50_ANT6
64
64 58 IO
LAT_SAWTOOTH_A
58 IO
PP3V0_S2 64 58 IO
LAT_SAWTOOTH_B
64
64 58 IO
UAT_SAWTOOTH_A
64 58 IO
UAT_SAWTOOTH_B
UAT_SAWTOOTH_A_B2B
00
58 IO
64
58 UAT_SAWTOOTH_B_B2B
B
IO
B 64
CLASS TO CLASS SPACING

CLASS NAME CLASS NAME CONSTRAINT SET
50_WIDE 50_WIDE A_DIELECTRIC_4XV_50_WIDE_SE
50_WIDE 50_THIN A_DIELECTRIC_4XD_50_WIDE_SE
50_WIDE 50_THIN_UNSHIELDED A_DIELECTRIC_4XD_50_WIDE_SE
50_THIN 50_THIN A_DIELECTRIC_4XD_50_THIN_SE
50_THIN 50_THIN_UNSHIELDED A_DIELECTRIC_4XD_50_THIN_SE
50_THIN_UNSHIELDED 50_THIN_UNSHIELDED A_DIELECTRIC_2X
50_WIDE_L1_THIN 50_WIDE A_DIELECTRIC_4XV_50_WIDE_SE
50_WIDE_L1_THIN 50_THIN A_DIELECTRIC_4XD_50_WIDE_L1_THIN_SE
50_WIDE_L1_THIN 50_THIN_UNSHIELDED A_DIELECTRIC_4XD_50_WIDE_L1_THIN_SE
RF_SHIELD GND DEFAULT
RF_SHIELD RF_SHIELD A_DIELECTRIC_2XD
RFFE_SHIELD GND DEFAULT
RFFE_SHIELD RFFE_SHIELD DEFAULT
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
HB SPAD PA_HB_K
AFEM-8100-AP1
DSBGA
SYM 2 OF 2
A1 GND GND G19

A2 GND GND G20
A3 GND GND H8
A4 GND GND H9
59 58 VPA_ET_HB A5 H10
GND GND
A6 H11
D 1 C1400_K 1 C1430_K A7
GND
GND
GND
GND H12 D
5.6PF 12PF
+/-0.1PF 5% A8 GND GND H13
2 16V
NP0-C0G 2 16V
CER A9 H14
01005 01005 GND GND
A10 GND GND H15
RADIO_HB_PAD RADIO_HB_PAD A11 H16
62 61 59 58 VFE_HI_3V15 GND GND
A12 GND GND H17
62 61 59 58 VIO_RFFE_XCVR_TO_TX_1V8 A13 GND GND H18
RFFE_XCVR_TO_HBTX_CLK A14 GND GND H19
00
61 59 58 IN
61 59 58 RFFE_XCVR_TO_HBTX_DATA A15 GND GND H20
BI
A16 GND GND J1
1 C1404_K 1 C1405_K 1 C1406_K 1 C1402_K A17 GND GND J8
10PF 10PF 10PF 0.47UF A18 GND GND J9
5% 5% 5% 20%
16V
2 NP0/C0G 16V
2 NP0/C0G 16V
2 NP0/C0G 6.3V
2 X5R A19 GND GND J10
01005 01005 01005 01005-1 A20 GND GND J11
NOSTUFF NOSTUFF RADIO_HB_PAD B1 J12
RADIO_HB_PAD RADIO_HB_PAD RADIO_HB_PAD GND GND
61 59 58 VIO_RFFE_XCVR_TO_RX_1V8 B2 GND GND J13
RFFE_XCVR_TO_FE_RX_CLK B3 GND GND J14
OP
61 59 58 IN
61 59 58 RFFE_XCVR_TO_FE_RX_DATA VFE_LO_1V2 58 59 61
B4 GND GND J15
BI
B5 GND GND J16
B6 GND GND J17
M18
M19
B7 J18
N18
N19
P17
P18
USID RX=0X0E GND GND
G1
H1
D1
F1
B8 GND GND J19
USID TX=0X02 B9 J20
SDATA_RX
SCLK_RX
VIO_RX
SDATA_TX
SCLK_TX
VIO_TX
VBATT
VCC1
VCC2
VDD_LNA
GND GND
B10 GND GND K1
B12 GND GND K8
B14 GND GND K9
C R1402_K
B16
B18
GND GND K10
K11
C
GND GND
P13 B11 50_HBPA_DRX_OUT_M 0.00 2 B20 K12
59 58 IN
50_XCVR_TX0_MB3 TX_MB_IN1 PA_HB_K DRX_OUT 1 50_HBPA_DRX_OUT OUT 58 59 GND GND
AFEM-8100-AP1 0% TO HB DSM C1 GND GND K20
1/32W 1 C1415_K
DSBGA MF C2 GND GND L1
SYM 1 OF 2 01005 0.5PF
RADIO_HB_PAD +/-0.05PF C3 GND GND L8
16V
2 C0G-CERM C4 GND GND L9
01005
RADIO_HB_PAD C5 GND GND L10
NOSTUFF C6 L11
GND GND
C7 GND GND L12
C8 GND GND L20
R1404_K
2.3PF C9 GND GND M1
59 58 50_XCVR_TX1_MB1 O14 TX_MB_IN2 ANT1 B19 50_HBPA_ANT1_M 1 2 50_HBPA_ANT1 63
C10 GND GND M8
OUT
TO LAT TRIPLEXER4 C11 GND GND M9
1 +/-0.1PF 1
16V C19 GND GND M10
NP0-C0G
UJJJ
UJJJ
01005 C20 GND GND M11
C1423_K RADIO_HB_PAD C1414_K D2 M12
7.5NH-3%-0.3A-0.5OHM 6.2NH-3%-0.3A-0.4OHM GND GND
01005 01005 D3 GND GND M20
RADIO_HB_PAD RADIO_HB_PAD D4 N1
GND GND
2 2 D5 GND GND N8
D6 GND GND N9
R1410_K
6.0PF D7 GND GND N10
59 58 50_XCVR_TX0_HB P15 TX_HB_IN1 ANT2 D19 50_HBPA_ANT2_M 1 2 50_HBPA_ANT2 62
D8 GND GND N11
IN OUT
TO LAT COUPLER D9 GND GND N12
1 C1411_K +/-0.1PF 1
16V D10 GND GND N20
0.5PF NP0-C0G
UJJJ
+/-0.05PF 01005 D11 GND GND O1
16V
2 C0G-CERM RADIO_HB_PAD C1420_K D20 O8
B 01005
RADIO_HB_PAD
4.7NH-3%-0.35A-0.35OHM
01005 E1
GND
GND
GND
GND O9 B
NOSTUFF RADIO_HB_PAD E2 O10
GND GND
2 E3 GND GND O11
E4 GND GND O12
R1401_K E5 GND GND O13
P14 F19 50_HBPA_ANT3_M 1
0.00 2 E6 O15
59 58 IN
50_XCVR_TX1_HB TX_HB_IN2 ANT3 50_HBPA_ANT3 OUT 58 59 GND GND
0% TO UAT COUPLER E7 GND GND O16
1 C1413_K 1/32W 1 C1421_K
MF E8 GND GND O19
0.5PF 01005 0.5PF
+/-0.05PF RADIO_HB_PAD +/-0.05PF E9 GND GND O20
16V
2 C0G-CERM 16V
2 C0G-CERM E10 GND GND P1
01005 01005
RADIO_HB_PAD RADIO_HB_PAD E11 GND GND P8
NOSTUFF NOSTUFF E19 P9
GND GND
E20 GND GND P10
GND P11
GND P12
61 50_UHBPA_MLB_OUT B15 MLB_IN MIMO_RX_OUT B13 50_MMDSM_MHB_ANT 58 59 GND P16
IN OUT
TO MIMO DSM F5 GND GND P19
50_UHBPA_2G_HB_OUT B17 2G_IN
61 IN F6 GND GND P20
F7 GND GND Q1
F8 GND GND Q3
50_XCVR_RX6_MB_UHB_PRX Q4 PRX_OUT1
0000
59 58 F9
OUT
GND GND Q5
59 58 50_XCVR_RX8_MLB_HB_PRX Q8 PRX_OUT2
OUT F10 GND GND Q7
OUT F11 GND GND Q9
OUT F20 GND GND Q10
G8 GND GND Q11
A G9
G10
GND GND Q12
Q13
A
GND GND
G11 GND GND Q14
DOMAIN NET RULE ASSIGNMENT
CLEAR (E,P,S)
G12 GND GND Q15
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CONSTRAINT SET COMMA SEPARATED NET NAMES (WILDCARD SUPPORT EX: DDR* )
DOMAIN
OVERRIDE
G13 GND GND Q16
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N P A_50_THIN_SE 50_XCVR*, 50_HBPA_DRX_OUT_M
G14 GND GND Q17
RFFE_SHIELD S A_DIELECTRIC_2X *RFFE*, VIO_RFFE* Y P A_50_WIDE_L1_THIN_SE 50_HBPA_ANT2*, 50_HBPA_ANT3*, 50_HBPA_ANT1*, 50_HBPA_DRX_OUT
G15 GND GND Q18
DOMAIN NET RULE ASSIGNMENT CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
OVERRIDE
G16 GND GND Q19
DOMAIN
(E,P,S)
CONSTRAINT SET COMMA SEPARATED NET NAMES (WILDCARD SUPPORT EX: DDR* ) CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N G17 GND GND Q20
P PWR_200UM VFE_HI_3V15 50_THIN S A_DIELECTRIC_2X 50_XCVR*,50_HBPA_DRX_OUT_M Y G18 GND
P PWR_100UM VFE_LO_1V2, VIO_RFFE* 50_WIDE_L1_THIN S A_DIELECTRIC_2X_50_WIDE_L1_THIN_SE 50_HBPA_ANT2*, 50_HBPA_ANT3* Y
P PWR_SHAPE VPA_ET_HB, VPA_ET_UHB, VPA_2G 50_WIDE_L1_THIN S A_DIELECTRIC_2X_50_WIDE_L1_THIN_SE 50_HBPA_ANT1*, 50_HBPA_DRX_OUT Y
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
UHB MLB SPAD

TABLE_5_HEAD
VPA_2G 58 59
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_ITEM
353S01913 1 SKY78201-18 PA_UHB_K ROW C1514_K 1 1 C1515_K
K6
K7
TABLE_5_ITEM 4UF 4UF
353S01914 1 SKY78221-11 PA_UHB_K USCH 20% 20%
6.3V 2 6.3V
2G_VDD
2G_VDD
CERM-X5R 2 CERM-X5R
0201 0201
D RADIO_UHB_PAD RADIO_UHB_PAD D
PA_UHB_K
UHB-MLB-2GS-PAD
BGA
SYM 2 OF 3 R1511_K
0.00 2
59 58 IN
50_XCVR_TX0_LB2
2G TX INPUT
D2 2G_LB_IN 2G_LB_OUT F12 50_UHBPA_2G_LB
1 C1518_K
1
'WV
0%
1/32W
MF
50_UHBPA_2G_LB_OUT
1 C1521_K
=>
[OUT 58 59
TO LB SPAD
62 60 59 58 VIO_RFFE_XCVR_TO_TX_1V8 0.5PF 01005 0.5PF

+/-0.05PF RADIO_UHB_PAD +/-0.05PF
60 59 58 RFFE_XCVR_TO_HBTX_CLK 16V
2 C0G-CERM 16V
2 C0G-CERM
IN
01005 01005
62 59 58
o
IN
RADIO_UHB_PAD RADIO_UHB_PAD
1 1 1 NOSTUFF NOSTUFF
C1503_K C1504_K C1505_K
18PF 47PF 18PF RADIO_UHB_PAD
VFE_HI_3V15 58 59 60 62
5% 5% 5%
16V
2 NP0/C0G 2 16V 2 16V R1502_K
NP0-C0G NP0/C0G 1 C1501_K 1 C1533_K
01005 01005 01005 2.2NH-+/-0.1NH-0.50A
60 59 58 RFFE_XCVR_TO_HBTX_DATA
RADIO_UHB_PAD RADIO_UHB_PAD RADIO_UHB_PAD
NOSTUFF
0.47UF
20%
6.3V
2 X5R
0.47UF
20%
6.3V
2 X5R
59 58
=
[ IN > 50_XCVR_TX0_MB2
2G TX INPUT
F2 2G_HB_IN 2G_HB_OUT F10 50_UHBPA_2G_HB rrm
1
01005
2 50_UHBPA_2G_HB_OUT OUT 60
TO HB SPAD
BI 01005-1 01005-1 1 C1519_K
RFFE_XCVR_TO_LBTX_DATA RADIO_UHB_PAD RADIO_HB_PAD
62 59 58 BI
RADIO_UHB_PAD 0.8PF
OMIT_TABLE +/-0.05PF
1 C1523_K 1 C1524_K VPA_ET_UHB 58 59
16V
2 C0G-CERM
47PF 18PF 01005
5% 5% 1 C1506_K 1 C1526_K RADIO_UHB_PAD
16V
2 NP0-C0G 2 16V
NP0/C0G 12PF 12PF
01005 01005 5% 5%
RADIO_UHB_PAD RADIO_UHB_PAD 2 16V
NP0-C0G
16V
2 NP0-C0G PA_UHB_K
NOSTUFF 01005-1 01005-1 UHB-MLB-2GS-PAD
60 59 58 VIO_RFFE_XCVR_TO_RX_1V8 RADIO_UHB_PAD RADIO_UHB_PAD BGA
RFFE_XCVR_TO_FE_RX_CLK SYM 3 OF 3
C 60 59 58
60 59 58
IN
BI
VFE_LO_1V2 58 59 60
A1
A2
GND GND E14
F1
C
1 GND GND
1 1 1 C1530_K A3 F3
C1508_K C1509_K C1525_K 1000PF GND GND
18PF 18PF 18PF 10% A4 F4
B10
B12
GND GND
G7
H7
B9
B8
B7
B5
B3
B4
B6
B2
5% 5% 5% 6.3V
2 X5R-CERM
16V
2 NP0/C0G 2 16V 2 16V A5 GND GND F7
NP0/C0G NP0/C0G 01005
01005 01005 01005 A6 F8
SDATA_RX
SCLK_RX
VIO_RX
SDATA_TX2
SDATA_TX
SCLK_TX2
SCLK_TX
VIO_TX
VBATT
VCC1
VCC2
VDD_LNA
RADIO_UHB_PAD GND GND
RADIO_UHB_PAD RADIO_UHB_PAD RADIO_UHB_PAD A7 F9
NOSTUFF NOSTUFF GND GND
USID RX=0X0F A8
A9
GND GND F11
F13
GND GND
PA_UHB_K
USID TX=0X03 A10
A11
GND GND F14
F15
UHB-MLB-2GS-PAD GND GND
BGA R1505_K A12 GND GND G1
SYM 1 OF 3 0.6NH-+/-0.05NH-0.95A A13 GND GND G2
59 58 IN
50_XCVR_TX0_MB1 K2 TX_MLB_IN MLB_OUT L12 50_UHBPA_MLB 1 /TTT\ 2 50_UHBPA_MLB_OUT OUT 60
A14
A15
GND GND G3
G4
01005 TO HB SPAD GND GND
1 C1502_K RADIO_UHB_PAD 1 C1511_K B1 GND GND H1
0.5PF 0.5PF
+/-0.05PF +/-0.05PF B11 GND GND H3
16V
2 C0G-CERM 16V
2 C0G-CERM B13 GND GND H4
01005 01005
RADIO_UHB_PAD RADIO_UHB_PAD B15 GND GND H15
NOSTUFF NOSTUFF C1 J1
GND GND
C2 GND GND J2
R1510_K C3 GND GND J3
1.0NH-+/-0.1NH-0.9A-0.05OHM C4 GND GND J4
59 58
o
IN
50_XCVR_TX1_UHB H2 TX_UHB_IN UHB_TX_OUT E15 50_UHBPA_UHB_M 1 rrm
01005
2 50_UHBPA_UHB
TO UAT_COUPLER
OUT 58 59
C5
C6
GND
GND
GND
GND
J7
K1
1 C1507_K RADIO_UHB_PAD 1 C1532_K C7 GND GND K3
0.5PF 0.5PF
+/-0.05PF +/-0.05PF C15 K4
B 16V
2 C0G-CERM 16V
2 C0G-CERM D1
GND
GND
GND
GND K5 B
01005 01005
RADIO_UHB_PAD RADIO_UHB_PAD D3 GND GND K15
NOSTUFF NOSTUFF D4 L1
GND GND
D5 GND GND L2
D6 GND GND L3
R1512_K D7 GND GND L4
B14 G15 50_UHBPA_ANT1_M 1
0.00 2 D14 L5
50_XCVR_RX14_LB_MLB_PRX MLB_PRX_OUT UHB_ANT1 50_UHBPA_ANT1 GND GND
59 58 OUT AA0%/V OUT 62
D15 L6
TO LAT COUPLER GND GND
1/32W E1 L7
1 MF GND GND
01005 E2 L8
RADIO_UHB_PAD GND GND
C1531_K E3 GND GND L9
6.8NH-3%-0.3A-0.4OHM E4 GND GND L10
01005
RADIO_UHB_PAD E5 GND GND L11
RADIO_UHB_PAD E6 L13
GND GND
2 E7 L15
R1508_K GND GND
1.5NH-+/-0.1NH-0.70A
UHB_ANT2 J15 50_UHBPA_ANT2_M rrm
1
01005
2 50_UHBPA_ANT2
TO LAT TRIPLEXER4
OUT 63 RADIO_UHB_PAD
OMIT_TABLE
1 C1517_K 1 C1513_K
0.5PF 0.4PF
+/-0.05PF +/-0.05PF
16V
2 C0G-CERM 16V
2 C0G
01005 01005
RADIO_UHB_PAD RADIO_UHB_PAD
NOSTUFF
A 50_XCVR_RX2_UHB_PRX C14 L14 50_MMDSM_UHB_ANT

A
59 58 OUT UHB_PRX_OUT MIMO_RX_OUT OUT 58 59
TO MIMO DSM
RADIO_UHB_PAD
OMIT_TABLE
CLEAR
DOMAIN NET RULE ASSIGNMENT CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* OVERRIDE
DOMAIN
(E,P,S)
CONSTRAINT SET COMMA SEPARATED NET NAMES (WILDCARD SUPPORT EX: DDR* ) CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
P A_50_THIN_SE 50_UHBPA_UHB_M, 50_UHBPA_ANT2 50_THIN S A_DIELECTRIC_2X 50_UHBPA_UHB_M, 50_UHBPA_ANT2 Y

P A_50_THIN_SE 50_UHBPA_MLB, 50_UHBPA_2G_LB* 50_THIN S A_DIELECTRIC_2X 50_UHBPA_MLB, 50_UHBPA_2G_LB* Y
P A_50_WIDE_L1_THIN_SE 50_UHBPA_ANT1*, 50_UHBPA_ANT2_M, 50_UHBPA_2G_HB*, 50_UHBPA_UHB, 50_MMDSM* 50_WIDE_L1_THIN S A_DIELECTRIC_2X_50_WIDE_L1_THIN_SE 50_UHBPA_ANT1*, 50_UHBPA_ANT2_M, 50_UHBPA_2G_HB*, 50_UHBPA_UHB, 50_MMDSM* Y
P A_50_WIDE_L1_THIN_SE 50_UHBPA_MLB_OUT 50_WIDE_L1_THIN S A_DIELECTRIC_2X_50_WIDE_L1_THIN_SE 50_UHBPA_MLB_OUT Y
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LOWER/UPPER COUPLER
D D
R2000_K
1
0.00 2
VIO_RFFE_XCVR_TO_TX_1V8 VIO_CPLR_L VFE_HI_3V15
61 60 59 58
A /0%
W 58 59 60 61
1 1 C2013_K
1/32W CPLR_L C2012_K
61 59 58 IN
RFFE_XCVR_TO_LBTX_CLK MF
01005 0.1UF 47PF
61 59 58 RFFE_XCVR_TO_LBTX_DATA 20% 5%
BI 6.3V
2 X5R-CERM 16V
2 NP0-C0G
01005 01005
1 C2011_K CPLR_L CPLR_L
11
12
47PF
6
1
2
5%
16V
2 NP0-C0G
SDATA
SCLK
VIO
VBATT
USID
01005
CPLR_L
USID TX=0X08
R2024_K
CPLR_L_K 1.0NH-+/-0.1NH-0.9A-0.05OHM
SKY16710
LGA
CPL1ANT 20 50_ANT3_UHB_C 1
rrm 01005
2 50_ANT3_UHB
=>
-t OUT 63
SYM 1 OF 2 CPLR_L
L2002_K 1 1 C2014_K
0.5PF 0.4PF
+/-0.05PF +/-0.05PF
16V 16V
C0G-CERM 2 2 C0G
01005 01005
C CPLR_L
NOSTUFF
CPLR_L
C
61 50_UHBPA_ANT1 25 CPL1IN CPL2ANT 23 50_ANT1 64

IN OUT
R2018_K
1.0NH-+/-0.1NH-0.9A-0.05OHM
63 IN
50_ANT1_CPLR_IN rrm.
1
01005
2 50_CPLR_ANT1 22 CPL2IN CPL3ANT 5 50_ANT3_MHB OUT 63
CPLR_L 1
1 C2001_K 1 C2000_K
0.4PF 0.5PF C2015_K
+/-0.05PF +/-0.05PF 10NH-+/-3%-0.25A
16V
2 C0G 16V
2 C0G-CERM 01005
01005 01005 CPLR_L
CPLR_L CPLR_L
NOSTUFF 2
60 50_HBPA_ANT2 10 CPL3IN CPLOUT1 13 50_CPLL_CPLOUT1 58 59

OUT
B B
CPLOUT2 3 50_CPLL_CPLOUT2 58 59
OUT
CPLR_L
CPLR_L_K
SKY16710
LGA
SYM 2 OF 2
A 4 GND GND 16 A
7 GND GND 17
8 GND GND 18
9 GND GND 19 (E,P,S)
14 GND GND 21
P A_50_THIN_SE 50_CPLL_CPLOUT*
15 GND GND 24
P A_50_WIDE_SE 50_CPLR_ANT1
CPLR_L P A_50_WIDE_SE 50_ANT1
CLEAR
DOMAIN
DOMAIN NET RULE ASSIGNMENT CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
(E,P,S)
CONSTRAINT SET COMMA SEPARATED NET NAMES (WILDCARD SUPPORT EX: DDR* ) 50_THIN S A_DIELECTRIC_2X 50_CPLL_CPLOUT* Y
P PWR_100UM VIO_CPLR* 50_WIDE S A_DIELECTRIC_2X_50_WIDE_SE 50_CPLR_ANT1 Y
50_WIDE S A_DIELECTRIC_2X_50_WIDE_SE 50_ANT1 Y
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LOWER ANTENNA FEEDS
D D
LB-MHB-UHB TRIPLEXER4
FLANT1_K
R2210_K LFD2H788MPD8E917
59 58 BI
50_LB_TX_ANT1
1 C2221_K
2.2PF
+/-0.1PF
1
0.00 2
0%
1/32W
MF
01005
LAT
1 C2210_K
2.2PF
+/-0.1PF
60
61
BI
50_LB_TX_ANT1_M
50_HBPA_ANT1
50_UHBPA_ANT2
3
7
LB
MLB/MB/HB GND_VOID=TRUE
UHB
LGA
GND_VOID=TRUE
GND_VOID=TRUE
ANT 1 50_ANT1_CPLR_IN
GND_VOID=TRUE
TO COUPLER
BI 62
ANT1
16V
2 NP0-C0G 16V
2 NP0-C0G
BI
GND
01005 01005
NOSTUFF NOSTUFF LAT
2
4
6
8
9
LAT LAT
C C
5GHZ WLAN BPF

FLANT5_K
5GHZ
R2221_K LFB185G50FB1E803 R2204_K
59 58 BI
50_LAA_TO_ANT_LAT
1
1
0.00 2
AA0%/V
1/32W 1
50_ANT5_LAA 1 3 50_ANT5_M
R2205_K
1
1
0.00 2
AA0%/V
1/32W 1
50_ANT5
R2206_K
BI 64
ANT5
2
MF LAT MF
01005 0.00 01005 0.00
LAT 0% LAT 0%
L2220_K L2221_K 1/32W 1/32W
4.7NH-3%-0.270A 4.7NH-3%-0.270A MF MF
01005 2 01005
01005 01005 NOSTUFF 2 NOSTUFF
NOSTUFF NOSTUFF LAT LAT
LAT LAT
2 2
B MHB-UHB-2.4G TRIPLEXER2 B
FLANT3_K
ACFM-WE12-AP1
R2220_K LGA
0.00 2 1
59 58 BI
50_WLAN_G_LAT 1 50_ANT3_WLAN WI_FI R2200_K
GND_VOID=TRUE 1.3NH-+/-0.05NH-0.7A
UAT ANTENNAS
0%
1/32W
MF
01005
LAT
1 C2220_K
2.2PF
+/-0.1PF
16V
2 NP0-C0G
01005
NOSTUFF
62
62
BI
50_ANT3_UHB
50_ANT3_MHB
7 UHB
GND_VOID=TRUE
10 MB_HB
GND_VOID=TRUE
GND
ANT 4
GND_VOID=TRUE
50_ANT3_M 1
1 R2201_K
jTfTL
01005
LAT
2
1
50_ANT3
R2202_K
BI 64
ANT3
LAT 0.3PF 0.00
+/-0.05PF 0%
16V
2
3
5
6
8
9
11
12
13
LAT 2 C0G-CERM 1/32W

ANT2 ANT4 ANT6 01005
LAT
MF
2 01005
NOSTUFF
LAT
LB MB/HB UHB
LMB/MB/HB 2.4GHZ 5GHZ DOMAIN NET RULE ASSIGNMENT
L1 GNSS UHB (E,P,S)
P
CONSTRAINT SET
A_50_WIDE_SE
COMMA SEPARATED NET NAMES (WILDCARD SUPPORT EX: DDR* )
50_ANT5, 50_ANT5_M, 50_LB_TX_ANT1*, 50_ANT3_UHB*
P A_50_WIDE_SE 50_ANT3, 50_ANT3_M*, 50_ANT3_WLAN
P A_50_WIDE_SE 50_WLAN_G_LAT
P A_50_WIDE_SE 50_ANT1_CPLR_IN
A LAT ANTENNAS A
ANT1 ANT3 ANT5 CLASS NAME

CLASS DEFINITIONS
DOMAIN
E,P,S CONSTRAINT SET

COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR*
CLEAR
OVERRIDE
Y/N
LB MB/HB 5GHZ 50_WIDE

50_WIDE
S
S
A_DIELECTRIC_2X_50_WIDE_SE
50_ANT5, 50_ANT5_M, 50_LB_TX_ANT1*, 50_ANT3_UHB*
50_ANT3, 50_ANT3_M*, 50_ANT3_WLAN
Y
Y
LMB/MB/HB 2.4GHZ 50_WIDE
50_WIDE
S
S
50_WLAN_G_LAT
50_ANT1_CPLR_IN
Y
Y
UHB UHB
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

(E,P,S)
P A_50_WIDE_SE 50_ANT2*, 50_ANT4*, 50_ANT6*, 50_LAA_TO_ANT_UAT
ANTENNA SYSTEM CLASS NAME

50_WIDE
CLASS DEFINITIONS
DOMAIN
E,P,S
S
CONSTRAINT SET
COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR*
50_ANT2*, 50_ANT4*, 50_ANT6*
CLEAR
OVERRIDE
Y/N
Y
50_WIDE S A_DIELECTRIC_2X_50_WIDE_SE 50_LAA_TO_ANT_UAT Y
D R2500_K D
1
0.00 2
UAT_SAWTOOTH_A UAT_SAWTOOTH_A_B2B
59 58 BI AA0%/V BI 58 59
1/32W
MF 1 C2524_K
01005
UAT_TUNER 33PF
5%
2 16V
NP0-C0G
01005-1
UAT_TUNER
R2501_K
0.00 2
59 58 BI
UAT_SAWTOOTH_B 1
A/W- UAT_SAWTOOTH_B_B2B BI 58 59
0%
1/32W
MF 1 C2525_K
01005
UAT_TUNER 33PF
5%
2 16V
NP0-C0G
01005-1
UAT_TUNER
C C
UHB/5G/R
FLANT6_K
LFD2H3G55MZPF026
LGA
59 58 BI
50_LAA_TO_ANT_UAT
1
R2321_K
0.4NH-+/-0.1NH-1.0A-0.03OHM
1
01005
UP_RFFE
2
1
59 58
59 58
BI
BI
50_R1_ANT_CH9
50_ANT6_LAA
50_ANT6_UHB
3 FRODO2
5 5G/FRODO1
7 UHB
2 GND
ANT 1 50_ANT6 BI 58 59
ANT6
4
6
8
9
UP_RFFE
L2320_K L2321_K
4.7NH-3%-0.270A 4.7NH-3%-0.270A
2
01005
NOSTUFF
UP_RFFE
2
01005
NOSTUFF
UP_RFFE
LAT JLAT
MM3531-2700A10
F-ST-SM
20
12 16
13 17
B 64 LAT_SUBUS_B_B2B 1 6 LAT_SUBUS_A_B2B 64 B
2 7
63 BI
50_ANT3 3 8 PP3V0_LAT_B2B 64
GND_VOID=TRUE
4 9
R2502_K
0.00 2 63 50_ANT5 5 10 50_ANT1 62
1 BI
LAT_SAWTOOTH_A LAT_SUBUS_A_B2B
59 58 BI AA/V
0%
64 GND_VOID=TRUE
11 GND_VOID=TRUE
1/32W
MF 1 C2504_K 14 18
01005
LAT_TUNER 5.6PF 15 19
+/-0.1PF
2 16V 21
NP0-C0G
01005 LAT
LAT_TUNER
R2503_K
1
0.00 2
LAT_SAWTOOTH_B LAT_SUBUS_B_B2B
59 58 BI
AAAr
0%
64
1/32W
MF 1 C2506_K
01005
LAT_TUNER 5.6PF
+/-0.1PF
2 16V
NP0-C0G
01005
LAT_TUNER
FL2502_K
150OHM-25%-200MA-0.7DCR
59 58 PP3V0_S2 rrm
1
01005-2
2 PP3V0_LAT_B2B 64
LAT_TUNER 1 C2509_K
A 220PF
5% A
2 16V
C0G
01005
LAT_TUNER

(E,P,S)
P PWR_100UM PP3V0_LAT_B2B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
D ARROW MLB POWER

D
PP1V8_S4
000
66 58
66 58 IO
PP1V0_R1_ANA_S4
66 58 IO
PP1V0_S4
HOST IPC
SPI0_AOP_TO_IMU_R1_SCLK
00000 000 00 00 000 00 000 000000

66 58 IO
66 58 IO
GPIO_AOP_TO_R1_SPI_CS_L
66 58 IO
SPI0_AOP_FROM_IMU_R1_MISO
LAST_MODIFICATION=Fri May 3 22:17:25 2019 66 58 IO
SPI0_AOP_TO_IMU_R1_MOSI
66 58 IO
GPIO_AOP_TO_R1_COREDUMP_TRIGGER
GPIO_AOP_FROM_R1_INT
PAGE CSA CONTENTS SYNC DATE 66 58 IO
RESET/CLOCK
65
FRONT PAGE
1 FRONT PAGE 66 58 GPIO_PMU_TO_R1_RESET_L
IO
66 2 MODULE 66 58 IO
CLK_GPIO_PMU_TO_WLAN_R1_32K
66 58 GPIO_AOP_TO_R1_TIME_SYNC
67 3 FILTERS MATCHING IO
DEBUG
66 58 IO
SWD_NUB_TO_MANY_SWCLK
66 58 IO
SWD_NUB_BI_R1_SWDIO
SPMI/COEX GPIOS
66 58 IO
IO_R1_TO_WLAN_COEX
IO_BB_TO_R1_COEX
C 66 58
66 58
IO
IO
IO_WLAN_TO_R1_COEX C
SE IPC
66 58 IO
I2C_R1_TO_NFC_SCL
66 58 IO
I2C_R1_BI_NFC_SDA
BT TIME SYNC / WAKE
66 58 IO
IO_BT_TO_R1_TIME_SYNC
66 58 IO
GPIO_BT_TO_R1_DEV_WAKE
ANTENNA SWITCH CTRL

66 58 IO
NC_R1_TUNER_GPO1
66 58 IO
NC_R1_TUNER_GPO2
66 58 IO
IO_R1_TO_BB_LAA_SW_CTRL
ANTENNA
67 58 IO
50_R1_AOA1
67 58 IO
50_R1_AOA3
67 58 IO
50_R1_AOA0
67 58 IO
50_R1_ANT_CH9
67 58 IO
50_LAA_TO_R1
B B
A A
SCH #: 951-07279
PCB #: 920-05369
BOM #: 939-05686
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MODULE
D D
66 65 58 PP1V8_S4
66 65 58 PP1V8_S4 225MA 1 C200_R 1 C202_R
1 4UF 5.6PF
R200_R 20% +/-0.1PF U_ROSE_R
100K 4V
2 X5R 2 16V
5% NP0/C0G 2103-180901-10
1/32W
MF
U_ROSE_R 0201
ROSE
01005
ROSE LGA
01005 2 2103-180901-10 SYM 2 OF 2
LGA 66 65 58 PP1V0_R1_ANA_S4 ROSE
SYM 1 OF 2 20MA 18 PP1V8_IO GND 1
1 C201_R 1 C203_R
ROSE GND 2
SPI0_AOP_TO_IMU_R1_SCLK 21 SPI_CLK ANT3 41 50_UWB_ANT3 4UF 5.6PF 53 PP1V8_IO_RAD
0 0 00 0
66 65 58 67
IN BI 20% +/-0.1PF GND 3
66 65 58 GPIO_AOP_TO_R1_SPI_CS_L 111 SPI_CS* 4V
2 X5R 2 16V
IN 125 NP0/C0G 107 4
QpgpnpGDnr
ANT2_6G 50_UWB_ANT2_6G 67 0201 01005 PP1V0_ANA GND

66 65 58 SPI0_AOP_FROM_IMU_R1_MISO 70 SPI_MISO BI
OUT
ANT2_8G 149 50_UWB_ANT2_8G 67 ROSE ROSE 108 PP1V0_ANA GND 5
66 65 58 SPI0_AOP_TO_IMU_R1_MOSI 69 SPI_MOSI
BI
IN
GND 6
ANT1 45 50_UWB_ANT1 67 66 65 58 PP1V0_S4 56 PP1V0_SOC0
65 58 I2C_R1_TO_NFC_SCL 160 SMB_SCL
BI
GND 7
IN 57
26 48 500MA 1 1 PP1V0_SOC1 8
65 58 BI
I2C_R1_BI_NFC_SDA SMB_SDA ANT0 50_UWB_ANT0 BI 67 C205_R C204_R GND
4UF 5.6PF GND 9
65 58 IO_R1_TO_WLAN_COEX 66 SPMI_CLK 20% +/-0.1PF
OUT
2 4V 2 16V GND 10
65 58 IO_BB_TO_R1_COEX 68 SPMI_DAT X5R NP0/C0G
IN 0201 01005 GND 11
124 ROSE ROSE 12
65 58 IN
IO_WLAN_TO_R1_COEX UART_RXD GND
GND 13
65 58 SWD_NUB_TO_MANY_SWCLK 22 SWD_CLK
IN 91 GND GND 14
C 66 65 58 BI
SWD_NUB_BI_R1_SWDIO 27 SWD_DAT 92 GND GND 15 C
66 65 58 CLK_GPIO_PMU_TO_WLAN_R1_32K 148 CK_32K RF_SW7 158 IO_R1_TO_BB_LAA_SW_CTRL 58 65 66 93 GND GND 16
IN OUT
RF_SW0 133 RF_SW0 66 94 GND GND 17
66 65 58 GPIO_AOP_TO_R1_COREDUMP_TRIGGER 24 DUMP_TRIG
IN 95 GND GND 25
QSPI_DQ0 20 NC_R1_TUNER_GPO1
00
58 65
GPIO_PMU_TO_R1_RESET_L 146 EXT_RESET*
OUT 96 GND GND 28
POP
66 65 58 IN
QSPI_DQ1 19 NC_R1_TUNER_GPO2 58 65
OUT 97 GND GND 29
66 65 58 GPIO_AOP_FROM_R1_INT 67 HOST_WAKE
OUT 98 GND GND 30
66 65 58 GPIO_AOP_TO_R1_TIME_SYNC 159 RTC_SYNC 99 GND GND 31
IN
100 GND GND 32
65 58 IO_BT_TO_R1_TIME_SYNC 123 DEV_WAKE
IN 101 GND GND 33
65 58 GPIO_BT_TO_R1_DEV_WAKE 71 GPIO_CLK_REQ 102 GND GND 34
IN
103 GND GND 35
66 UART_R1_RXD 136 AP_UART_RXD 104 GND GND 36
66 UART_R1_TXD 23 AP_UART_TXD 105 GND GND 37
106 GND GND 38
I2C PULL-UPS AT NFC 109 GND GND 39
110 GND GND 40
112 GND GND 42
113 GND GND 43
114 GND GND 44
115 GND GND 46
116 GND GND 47
117 GND GND 49
118 GND GND 50
119 GND GND 51
120 GND GND 52
B 121 GND GND 54 B
122 GND GND 55
126 GND GND 58
127 GND GND 59
128 GND GND 60
129 GND GND 61
130 GND GND 62
131 GND GND 63
132 GND GND 64
PP209_R 134 GND GND 65
PP200_R P2MM-NSM 135 72
P2MM-NSM SM
1 GND GND
Q Q Q Q Q Q Q Q
SM PP1V0_R1_ANA_S4 58 65 66
1 66 PP 137 73
Q Q Q Q Q Q Q Q
PP
GPIO_PMU_TO_R1_RESET_L 58 GND GND
65 PP210_R 138 74
PP201_R P2MM-NSM GND GND
P2MM-NSM SM
1 139 75
SM PP1V0_S4 58 65 66 GND GND
1 CLK_GPIO_PMU_TO_WLAN_R1_32K 58 PP
PP
PP202_R
65 66
PP221_R
UNSECURE BOOT BOOTSTRAP PULLUP 140 GND GND 76
P2MM-NSM P2MM-NSM 141 GND GND 77
SM SM
1 SPI0_AOP_TO_IMU_R1_SCLK 58 65 66 1 IO_R1_TO_BB_LAA_SW_CTRL 58 65 66 142 GND GND 78
PP PP
PP1V8_S4 58 65 66
PP203_R PP211_R 143 GND GND 79
P2MM-NSM P2MM-NSM 144 80
SM SM GND GND
1 GPIO_AOP_TO_R1_SPI_CS_L 58 65 66 1 SWD_NUB_BI_R1_SWDIO 58 65 66
R210_R
PP PP
3.0K 1 145 GND GND 81
PP204_R PP212_R 2 UART_R1_TXD 66
147 82
P2MM-NSM P2MM-NSM GND GND
SM SM 1%
1 SPI0_AOP_FROM_IMU_R1_MISO 58 65 66 1 GPIO_AOP_TO_R1_COREDUMP_TRIGGER
58 65 66 1/32W 150 GND GND 83
PP PP
MF
PP205_R PP213_R 01005 151 GND GND 84
P2MM-NSM P2MM-NSM ROSE 152 85
SM SM NOSTUFF GND GND
1 SPI0_AOP_TO_IMU_R1_MOSI 58 65 66 1 GPIO_AOP_FROM_R1_INT 58 65 66
PP PP 153 GND GND 86
PP206_R PP214_R 154 87
P2MM-NSM P2MM-NSM GND GND
A SM
PP
1 UART_R1_RXD 66
SM
PP
1 GPIO_AOP_TO_R1_TIME_SYNC 58 65 66 155 GND GND 88 A
PP207_R PP208_R 156 GND GND 89
P2MM-NSM P2MM-NSM 157 90
SM SM GND GND
1 UART_R1_TXD 66 1 RF_SW0 66
PP PP
\
'\
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FILTERS/MATCHING AND ANTENNA

(E,P,S)
P A_50_WIDE_SE 50_R1*, 50_UWB*, 50_LAA_TO_R1*
D D
CLEAR
DOMAIN
50_WIDE S A_DIELECTRIC_2X_50_WIDE_SE 50_R1*, 50_UWB*, 50_LAA_TO_R1* ?

FLHPF6_R
R305_R LFH156G48RM1F015 R317_R
0.00 2 LGA 0.00 2
50_UWB_ANT2_6G 1 50_UWB_ANT2_6G_FL_IN 6 IN OUT 4 50_UWB_ANT2_6G_FL_OUT 1 50_LAA_TO_R1
66 BI AW
0% 1 NC 3
AA0%/V BI 58 65
NC NC NC
1/32W 1/32W TABLE_5_HEAD
MF MF PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

01005 01005 1 C300_R
1 GND
ROSE C310_R ROSE 0.3PF
TABLE_5_ITEM
OMIT_TABLE 0.3PF OMIT_TABLE +/-0.05PF 117S0161 1 RES,MF,0 OHM,1/32W,01005 R305_R ROSE.X
2
5
+/-0.05PF ROSE 16V
16V 2 C0G-CERM TABLE_5_ITEM
2 C0G-CERM 01005 117S0161 1 RES,MF,0 OHM,1/32W,01005 R317_R ROSE.X

01005 NOSTUFF TABLE_5_ITEM
NOSTUFF ROSE 117S0161 1 RES,MF,0 OHM,1/32W,01005 R306_R ROSE.X

ROSE TABLE_5_ITEM
152S01109 1 IND,FILM,0.6NH,950MA,01005 R316_R ROSE.X

TABLE_5_ITEM
131S00030 1 CAP,CER,C0G,0.4PF,16V,01005 C317_R ROSE.X

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM
152S01109 1 IND,FILM,0.6NH,950MA,01005 R309_R ROSE.X

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

FLBPF8_R TABLE_5_ITEM
DEA107987BT-3046D1SJ
C R306_R
0.00 2 6 IN
SM
4
R316_R
0.00 2
TABLE_5_ITEM
C
66 BI
50_UWB_ANT2_8G 1 50_UWB_ANT2_8G_FL_IN OUT 50_UWB_ANT2_8G_FL_OUT 1 50_R1_ANT_CH9 BI 58 65 152S00494 1 IND,FILM,0.8NH,900MA,01005 R307_R ROSE.X
0% 1 NC NC 3 0% TABLE_5_ITEM
1/32W 1 C311_R NC NC 1 C315_R 1/32W 1 C317_R 152S00494 1 IND,FILM,0.8NH,900MA,01005 R308_R ROSE.X

MF MF
01005 0.3PF GND
0.3PF 01005 0.3PF TABLE_5_ITEM
ROSE +/-0.05PF +/-0.05PF UP_RFFE +/-0.05PF 131S0369 1 CAP,CER,C0G,0.5PF,16V,01005 C315_R ROSE.X

OMIT_TABLE 16V
2 C0G-CERM 16V
2 C0G-CERM 16V
2 C0G-CERM
2
5
01005 ROSE 01005 OMIT_TABLE 01005
NOSTUFF NOSTUFF OMIT_TABLE
ROSE UP_RFFE UP_RFFE
TABLE_5_HEAD

TABLE_5_ITEM
152S00497 1 IND,FILM,0.5NH,1000MA,01005 R305_R ROSE.0

TABLE_5_ITEM

TABLE_5_ITEM
R307_R
TABLE_5_ITEM

1
0.00 2
50_UWB_ANT0 50_R1_AOA1
AA0%/V
TABLE_5_ITEM
66 BI BI 58 65
131S0893 1 CAP,CER,C0G,0.2PF,16V,01005 C317_R ROSE.0
1 C302_R 1/32W 1 C312_R TABLE_5_ITEM
MF 131S0893 1 CAP,CER,C0G,0.2PF,16V,01005 C304_R ROSE.0

0.3PF 01005 0.3PF
+/-0.05PF UAT +/-0.05PF TABLE_5_ITEM
16V
2 C0G-CERM OMIT_TABLE 16V
2 C0G-CERM 131S0893 1 CAP,CER,C0G,0.2PF,16V,01005 C314_R ROSE.0
01005 01005 TABLE_5_ITEM
OMIT_TABLE OMIT_TABLE 152S00496 1 IND,FILM,0.6NH,950MA,01005 R309_R ROSE.0

B UAT UAT
TABLE_5_ITEM
B
TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

R308_R TABLE_5_ITEM
0.00 2 131S0893 1 CAP,CER,C0G,0.2PF,16V,01005 C303_R ROSE.0

66 BI
50_UWB_ANT1
-AA0%/V
1 50_R1_AOA3 BI 58 65

TABLE_5_ITEM
1 C303_R 1/32W 1 C313_R

MF TABLE_5_ITEM
0.3PF 01005 0.3PF 131S00030 1 CAP,CER,C0G,0.4PF,16V,01005 C315_R ROSE.0

+/-0.05PF UAT +/-0.05PF
16V
2 C0G-CERM
01005 01005
NOSTUFF NOSTUFF
UAT UAT TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
339S00664 339S00665 ALT_PARTS U_ROSE_R MODULE,STRIDER,ES5.1
R309_R
0.00 2
^-
50_UWB_ANT3 1 50_R1_AOA0
66 BI AA0% BI 58 65
1 C304_R 1/32W 1 C314_R

MF
0.3PF 01005 0.3PF
+/-0.05PF UAT +/-0.05PF
16V
2 C0G-CERM
01005 01005
A UAT UAT
A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
LAA_WIFI (GODFATHER) D
LAST_MODIFICATION=Fri May 3 22:17:24 2019

PAGE CSA CONTENTS SYNC DATE
68
FEM MODULES
1 FEM MODULES
69 2 FEM MODULES 05/08/2018
C C
TABLE_5_HEAD

TABLE_5_ITEM
152S00422 1 IND,FILM,1.5NH,700MA,01005 R362_W WIFI.0

PP_VDD_MAIN
00 000000 00 00 000
69 58 IO
TABLE_5_ITEM
152S00498 1 IND,FILM,0.4NH,1000MA,01005 R363_W WIFI.0 69 58 IO

PP1V8_S2
PP1V8_S4
LAA
TABLE_5_ITEM
69 58 IO
152S00498 1 IND,FILM,0.4NH,1000MA,01005 R372_W WIFI.0
TABLE_5_ITEM
50_WLAN_A_TX0 50_LAA_TO_ANT_LAT
000000 00 0000
152S00496 1 IND,FILM,0.6NH,950MA,01005 R373_W WIFI.0 69 58 69 58 IO
TABLE_5_ITEM
69 58 IO
50_WLAN_A_RX0_LAA 69 58 IO
50_LAA_TO_ANT_UAT
131S0893 1 CAP,CER,C0G,0.2PF16V,01005 C361_W WIFI.0
69 58 IO
50_WLAN_A_TX1
69 58 IO
50_WLAN_A_RX1_LAA 69 58 IO
50_LAA_TO_XCVR_LAT
69 58 IO
50_LAA_TO_XCVR_UAT
TABLE_5_HEAD
B PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

TABLE_5_ITEM
69 58
69 58
IO
IO
5GHZ_C0_VDET
5GHZ_C1_VDET 69 58 IO
B
152S00419 1 IND,FILM,1.1NH,01005 R362_W WIFI.X
69 58 IO
TABLE_5_ITEM
117S0161 1 RES,MF,0 OHM,1/32W,01005 R363_W WIFI.X 69 58 IO

RFA0_SW_CTRL0 69 58 IO
TABLE_5_ITEM
69 58 IO
RFFE_LAA_UAT_VIO
117S0161 1 RES,MF,0 OHM,1/32W,01005 R372_W WIFI.X
69 58 IO
RFFE_LAA_UAT_CLK
TABLE_5_ITEM
117S0161 1 RES,MF,0 OHM,1/32W,01005 R373_W WIFI.X 69 58 IO

RFFE_LAA_UAT_DATA
TABLE_5_ITEM
69 58 IO
RFA1_SW_CTRL1
131S0893 1 CAP,CER,C0G,0.2PF,16V,01005 C361_W WIFI.X
69 58 IO
50_LAA_TO_R1
69 58 IO
IO_R1_TO_BB_LAA_SW_CTRL
A A
SCHEMATIC APN: 951-08431

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FEM MODULES
(E,P,S)
P PWR_100UM PP1V8_UAT_FEM_LNA, PP1V8_LAT_FEM_LNA, RFFE_*VIO, PP_1V8_VIO_LAA*
Table Modified Locally

CLEAR
DOMAIN
WLAN_SHIELD S A_DIELECTRIC_2X RFA0_SW*, RFA1_SW* ?

STUFF ONLY FOR VENDOR CONFIG RF_SHIELD S A_DIELECTRIC_2X *R1_TO_BB_LAA_SW*, 5GHZ_C* ?
50_THIN_UNSHIELDED S A_DIELECTRIC_2X 50_LAA_TO_XCVR* ?
R311_W
1
0.00 2
69 68 58 PP1V8_S2 PP1V8_S4 58 68 69
D 0%
1/32W
MF
01005
5GHZ UAT FEED DOMAIN NET RULE ASSIGNMENT
D
UAT_FEM FL302_W (E,P,S)
NOSTUFF 10-OHM-1.1A
P A_50_THIN_SE 50_LAA_TO_XCVR* Table Modified Locally
69 68 58 PP1V8_S4 1 2 PP1V8_UAT_FEM_LNA PP_VDD_MAIN 58 68 69
01005
UAT_FEM 1 C304_W
1 C305_W 1 C306_W
33PF CLASS TO CLASS SPACING
5% 10UF 33PF
2 16V
NP0-C0G
20% 5% CLASS NAME CLASS NAME CONSTRAINT SET
01005-1 2 10V
X5R-CERM 2 16V
NP0-C0G WLAN_SHIELD WLAN_SHIELD DEFAULT
R363_W UAT_FEM 0402-0.1MM 01005-1
0.00 2 UAT_FEM UAT_FEM WLAN_SHIELD GND DEFAULT
68 58 IN
50_WLAN_A_TX0 1 50_WLAN_A_TX0_VOID_FEM_IN
0%
18
19
1/32W 1 C366_W
8
MF
01005 0.3PF
+/-0.05PF
VCC2_PA
VCC1_PA
VDD_1V8
UAT_FEM R362_W
OMIT_TABLE 2 16V
C0G-CERM
01005 16 5G_TX_IN
0.00 2
5G_RX 14 50_WLAN_A_RX0_VOID_FEM_OUT 1 50_WLAN_A_RX0_LAA OUT 58 68
NOSTUFF GND_VOID=TRUE GND_VOID=TRUE
UAT_FEM 0%
68 58 5GHZ_C0_VDET 20 VDET 1/32W 1 C361_W
OUT
MF
ANT 6 50_LAA_TO_ANT_UAT 58 68 01005 0.3PF
68 58 RFA0_SW_CTRL0 24 RF_SW_CTRL0 U_5G_U_W GND_VOID=TRUE UAT_FEM +/-0.05PF
IN
35 2 16V
C0G-CERM
68 58 IN
RFA0_SW_CTRL1 RF_SW_CTRL1 MDFEGFFB-126 OMIT_TABLE 01005
68 58 RFA0_SW_CTRL2 28 RF_SW_CTRL2 LGA NOSTUFF
IN
26 UAT_FEM
68 58 IN
IO_R1_TO_BB_LAA_SW_CTRL RF_SW_CTRL3
1 C379_W 1 C382_W 1 C381_W 1 C380_W 12 LAA_RX
GND_VOID=TRUE RFFE_VIO 2
10PF 10PF 10PF 10PF
5% 5% 5% 5% 4 RFFE_DATA
2 16V
NP0/C0G 2 16V
NP0/C0G 2 16V
NP0/C0G 2 16V
NP0/C0G
01005 01005 01005 01005 3 RFFE_CLK
UAT_FEM UAT_FEM UAT_FEM UAT_FEM
C 68 58 OUT
50_LAA_TO_XCVR_UAT
23 USID1
GND
SAM 10 50_LAA_TO_R1
GND_VOID=TRUE
BI 58 68 C
68 58 BI
RFFE_LAA_UAT_DATA
UAT_FEM
1
5
7
9
11
13
15
17
21
22
25
27
29
30
31
32
33
34
68 58 IN
RFFE_LAA_UAT_CLK
1 C321_W 1 C322_W
18PF
5%
18PF
5% PRODUCT_ID=0X41 (LAA RDM)
2 16V
NP0/C0G 2 16V
NP0/C0G USID RX=0X6 (LAA RDM)
01005 01005
UAT_FEM UAT_FEM
NOSTUFF NOSTUFF
R310_W
68 58 IN
RFFE_LAA_UAT_VIO 1 2 PP_1V8_VIO_LAA_UAT
0.00 01005
1 C323_W
UAT_FEM
18PF
5%
2 16V
NP0/C0G
01005
UAT_FEM
5GHZ LAT FEED

FL312_W
10-OHM-1.1A 1X10UF / 4X2.2UF CAPS ADDED ON TOP LEVEL
69 68 58 PP1V8_S2 1 2 PP1V8_LAT_FEM_LNA PP_VDD_MAIN 58 68 69
01005
LAT_FEM 1 C314_W
1 C316_W
33PF
5% 33PF
2 16V
NP0-C0G
5%
01005-1 2 16V
NP0-C0G
R373_W LAT_FEM 01005-1
B 68 58 IN
50_WLAN_A_TX1 1
0.00 2
50_WLAN_A_TX1_VOID_FEM_IN
LAT_FEM
B
0%
18
19
1/32W 1 C376_W
8
MF
01005 0.3PF
+/-0.05PF
VCC2_PA
VCC1_PA
VDD_1V8
LAT_FEM R372_W
OMIT_TABLE 2 16V
C0G-CERM
01005 16 5G_TX_IN
0.00 2
5G_RX 14 50_WLAN_A_RX1_VOID_FEM_OUT 1 50_WLAN_A_RX1_LAA OUT 58 68
NOSTUFF GND_VOID=TRUE GND_VOID=TRUE
LAT_FEM 0%
68 58 5GHZ_C1_VDET 20 VDET 1/32W 1 C371_W
OUT
MF
ANT 6 50_LAA_TO_ANT_LAT BI 58 68 01005 0.3PF
68 58 RFA1_SW_CTRL0 24 RF_SW_CTRL0 U_5G_L_W GND_VOID=TRUE LAT_FEM +/-0.05PF
IN
35 OMIT_TABLE 2 16V
C0G-CERM
1 RF_SW_CTRL1 MDFEGFFB-126 01005
C383_W 28
10PF RF_SW_CTRL2 LGA NOSTUFF
5% 26 LAT_FEM
RF_SW_CTRL3
2 16V
NP0/C0G
01005 12 LAA_RX
UAT_FEM GND_VOID=TRUE RFFE_VIO 2
R375_W
0.00 2 4 RFFE_DATA
68 58 IN
RFA1_SW_CTRL1 1 RFA1_SW_CTRL1_FEM
0% 3 RFFE_CLK
1/32W 1 C384_W
MF
01005 10PF 23 USID1 SAM 10
LAT_FEM 5% GND_VOID=TRUE NC
GND
2 16V
NP0/C0G
01005 LAT_FEM
1
5
7
9
11
13
15
17
21
22
25
27
29
30
31
32
33
34
R376_W UAT_FEM
0.00 2
68 58 IN
RFA1_SW_CTRL2 1 RFA1_SW_CTRL2_FEM PRODUCT_ID=0X41 (LAA RPM)
0%
1/32W 1 C385_W
USID RX=0X5 (LAA RPM)
MF
01005 10PF
LAT_FEM 5%
2 16V
NP0/C0G
01005
A UAT_FEM
A
68 58 OUT
50_LAA_TO_XCVR_LAT
68 58 BI
68 58 IN
1 C325_W 1 C324_W R364_W
VIO_RFFE_XCVR_TO_RX_1V8 1 2 PP_1V8_VIO_LAA_LAT
18PF 18PF 68 58 IN
5% 5% 0.00 01005
2 16V 2 16V LAT_FEM 1 C333_W
NP0/C0G NP0/C0G
01005 01005 18PF
LAT_FEM LAT_FEM 5%
NOSTUFF NOSTUFF 2 16V
NP0/C0G
01005
LAT_FEM
8 7 6 5 4 3 2 1

Iphone 11 Pro Max - 2

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Iphone 11 Pro Max - 2

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MCO: 056-08495 EEEE Codes Sub Designs TABLE_HIERARCHY_CONFIG_HEAD

BOM: 639-07383 (ULTIMATE,ROW,D42)

825-7691 1 LNCH CRITICAL ULTIMATE_ROW_D42 D43 RADIO_MLB_ICE_LOFT 0.83.0 S 2019_04_30_16:40:16

EEEE FOR (MLB_TOP,639-06907,ULTIMATE,US+CH,D42) LNDJ CRITICAL ULTIMATE_USCH_D42

D42 ROSE_MLB 0.56.0 S 2019_05_02_11:27:27

D42 LAA_MLB 0.28.0 S 2019_04_26_11:43:12

BOM: 639-07387 (EXTREME.NA+CH,D42)

825-7691 1 EEEE FOR (MLB_TOP,639-06908,EXTREME,US+CH,D42) LNDX CRITICAL EXTREME_USCH_D42

825-7691 1 LND4 CRITICAL MAX_ROW_D42

EEEE FOR (MLB_TOP,639-06909,MAX,US+CH,D42) LNF8 CRITICAL MAX_USCH_D42

825-7691 1 EEEE FOR (MLB_TOP,639-06907,ULTIMATE,US+CH,D43) L38J CRITICAL ULTIMATE_USCH_D43

A BOM: 639-06878 (ULTIMATE,ROW,D43)

825-7691 1 EEEE FOR (MLB_TOP,639-06879,EXTREME,ROW,D43) L1WF CRITICAL EXTREME_ROW_D43

EEEE FOR (MLB_TOP,639-06880,MAX,ROW,D43) L1WR CRITICAL MAX_ROW_D43

BOM: 639-06880 (MAX,ROW,D43) 051-04448 1 SCH,MLB_TOP,D43 SCH CRITICAL ?

BOM: 639-06909 (MAX,NA+CH,D43)

820-01682 1 PCB,MLB_TOP,D43 PCB CRITICAL ?

NAND Global Alternates TABLE_CRITICAL_HEAD

CRITICAL PART# COMMENT

377S00001 ALT_PARTS ALL TVS,BIDIR,5.8V,6PF,01005

138S00136 ALT_PARTS ALL CAP,X5R,2.2UF,20%,10V.KYO,0201

TABLE_ALT_ITEM TABLE_ALT_ITEM 377S0183 TVS,BIDIR,5.8V,0201

TABLE_ALT_ITEM TABLE_ALT_ITEM 377S00129 SUPRESS,TRANS,6.8V,100PF,01005

TABLE_ALT_ITEM TABLE_ALT_ITEM 155S00200 FERR BD,150OHM,25%,200MA,0.7OHM DCR,01005

D Extreme 377S00173 377S0183 ALT_PARTS ALL TVS,BIDIR,5V,6.5PF,0201,SEMTECH

TABLE_ALT_ITEM 132S0316 CAP,X5R,0.1UF,20%,6.3V,01005

FERR BD,33OHM,25%,1.5A,55MOHM DCR,0201

TABLE_5_HEAD TABLE_ALT_ITEM 132S0639 CAP,CER,X5R,0.47UF,20%,25V,0201

TABLE_5_ITEM TABLE_ALT_ITEM 138S0706 CAP,X5R,1UF,20%,10V,0201

TABLE_ALT_ITEM 138S00264 CAP,X5R,1.5UF,20%,6.3V,0201

TABLE_ALT_ITEM 138S00008 CAP,X5R,1.5UF,20%,6.3V,0201

TABLE_ALT_ITEM 138S0831 CAP,CER,X5R,2.2UF,20%,6.3V,0201

TABLE_ALT_ITEM 138S00284 CAP,CER,X5R,2.2UF,20%,10V,0201

TABLE_ALT_ITEM 138S00164 CAP,X5R,4UF,20%,4V,0201

138S00149 0402-3T,10.5uF@1V TABLE_ALT_ITEM

138S00150 138S00149 ALT_PARTS ALL 0402-3T,10.5uF@1V, SEMCO

138S00151 138S00149 ALT_PARTS ALL 0402-3T,10.5uF@1V, TY

C PART NUMBER ALTERNATE FOR

138S00164 138S00139 ALT_PARTS ALL 0201,3uF@1V, TY

152S00721 152S00876 ALT_PARTS ALL Taiyo,IND,MLD,1UH,3.6A,60MO,2016 152S00876 Cyntec,IND TABLE_ALT_ITEM

155S00415 155S00524 ALT_PARTS ALL CMC,35O_OHM,7GHZ,TDK

152S00930 152S00897 ALT_PARTS ALL Cyntec,IND,CPLD,0.1UH,6.1A,27MO,2016 152S00897 Taiyo,IND

138S00221 138S00146 ALT_PARTS ALL 0402,5.1uF@3V, Kyocera

152S00994 152S00987 ALT_PARTS ALL Taiyo,IND,MLD,1UH,1.5A,67MO,2012 152S00987 Cyntec,IND

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

CRITICAL PART# COMMENT

TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

138S00003 138S00048 ALT_PARTS ALL 0402,15uF,6.3V, MURATA

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

Multi-Vendor Criticals XTAL Alternate

138S00140 138S00141 ALT_PARTS ALL 0201,1.1uF@3V, Kyocera

138S00268 138S00141 ALT_PARTS ALL 0201,1.1uF@3V, SEMCO

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_ALT_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

E_LPDP_FCAM E DIFF_PAIR DP:DP_90_LPDP_FCAM* ? (E,P,S)

E_MIPI_DISPLAY E DIFF_PAIR DP:DP_90_MIPIDISPLAY* ? P A_50_THIN_SE 50_LAA_TO_XCVR*