x86-64

x86-64 (also known as x64, x86_64, AMD64, and Intel 64)[note 1] is a 64-bit version of the x86
instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and
compatibility mode, along with a new 4-level paging mode.

With 64-bit mode and the new paging mode, it supports vastly larger amounts of virtual memory and physical
memory than was possible on its 32-bit predecessors, allowing programs to store larger amounts of data in
memory. x86-64 also expands general-purpose registers to 64-bit, and expands the number of them from 8
(some of which had limited or fixed functionality, e.g. for stack management) to 16 (fully general), and
provides numerous other enhancements. Floating-point arithmetic is supported via mandatory SSE2-like
instructions, and x87/MMX style registers are generally not used (but still available even in 64-bit mode);
instead, a set of 16 vector registers, 128 bits each, is used. (Each register can store one or two double-precision
numbers or one to four single-precision numbers, or various integer formats.) In 64-bit mode, instructions
are modified to support 64-bit operands and 64-bit addressing mode. AMD Opteron, the first CPU to
introduce the x86-64 extensions
The compatibility mode defined in the architecture allows 16- and 32-bit user applications to run unmodified, in April 2003
coexisting with 64-bit applications if the 64-bit operating system supports them.[11][note 2] As the full x86 16-
bit and 32-bit instruction sets remain implemented in hardware without any intervening emulation, these
older executables can run with little or no performance penalty,[13]
while newer or modified applications can
take advantage of new features of the processor design to achieve performance improvements. Also, a
processor supporting x86-64 still powers on in real mode for full backward compatibility with the 8086, as
x86 processors supporting protected mode have done since the 80286.

The original specification, created by AMD and released in 2000, has been implemented by AMD, Intel, and
VIA. The AMD K8 microarchitecture, in the Opteron and Athlon 64 processors, was the first to implement it.
This was the first significant addition to the x86 architecture designed by a company other than Intel. Intel
was forced to follow suit and introduced a modified NetBurst family which was software-compatible with
The five-volume set of the x86-64
AMD's specification. VIA Technologies introduced x86-64 in their VIA Isaiah architecture, with the VIA
Architecture Programmer's
Nano.
Manual, as published and
distributed by AMD in 2002
The x86-64 architecture is distinct from the Intel Itanium architecture (formerly IA-64). The architectures are not compatible on the native
instruction set level, and operating systems and applications compiled for one cannot be run on the other.

AMD64

History

AMD64 (also variously referred to by AMD in their literature and documentation as “AMD 64-bit Technology” and “AMD
x86-64 Architecture”) was created as an alternative to the radically different IA-64 architecture designed by Intel and
Hewlett-Packard, which was backward-incompatible with IA-32, the 32-bit version of the x86 architecture. AMD originally
announced AMD64 in 1999[14] with a full specification available in August 2000.[15] As AMD was never invited to be a AMD64 logo
contributing party for the IA-64 architecture and any kind of licensing seemed unlikely, the AMD64 architecture was
positioned by AMD from the beginning as an evolutionary way to add 64-bit computing capabilities to the existing x86
architecture while supporting legacy 32-bit x86 code, as opposed to Intel's approach of creating an entirely new, completely x86-incompatible
64-bit architecture with IA-64.

The first AMD64-based processor, the Opteron, was released in April 2003.

Implementations
AMD's processors implementing the AMD64 architecture include Opteron, Athlon 64, Athlon 64 X2, Athlon 64 FX, Athlon II (followed by "X2",
"X3", or "X4" to indicate the number of cores, and XLT models), Turion 64, Turion 64 X2, Sempron ("Palermo" E6 stepping and all "Manila"
models), Phenom (followed by "X3" or "X4" to indicate the number of cores), Phenom II (followed by "X2", "X3", "X4" or "X6" to indicate the
number of cores), FX, Fusion/APU and Ryzen/Epyc.

Architectural features

The primary defining characteristic of AMD64 is the availability of 64-bit general-purpose processor registers (for example, rax), 64-bit integer
arithmetic and logical operations, and 64-bit virtual addresses.
The designers took the opportunity to make other improvements as well.

Notable changes in the 64-bit extensions include:

64-bit integer capability

 All general-purpose registers (GPRs) are expanded from 32 bits to 64 bits, and all arithmetic and logical operations, memory-to-
register and register-to-memory operations, etc., can operate directly on 64-bit integers. Pushes and pops on the stack default
to 8-byte strides, and pointers are 8 bytes wide.
Additional registers
In addition to increasing the size of the general-purpose registers, the number of named general-purpose registers is increased
from eight (i.e. eax, ecx, edx, ebx, esp, ebp, esi, edi) in x86 to 16 (i.e. rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14,
r15). It is therefore possible to keep more local variables in registers rather than on the stack, and to let registers hold frequently
accessed constants; arguments for small and fast subroutines may also be passed in registers to a greater extent.
AMD64 still has fewer registers than many RISC instruction sets (e.g. PA-RISC, Power ISA, and MIPS have 32 GPRs; Alpha, 64-bit
ARM, and SPARC have 31) or VLIW-like machines such as the IA-64 (which has 128 registers). However, an AMD64
implementation may have far more internal registers than the number of architectural registers exposed by the instruction set
(see register renaming). (For example, AMD Zen cores have 168 64-bit integer and 160 128-bit vector floating-point physical
internal registers.)
Additional XMM (SSE) registers
Similarly, the number of 128-bit XMM registers (used for Streaming SIMD instructions) is also increased from 8 to 16.
The traditional x87 FPU register stack is not included in the register file size extension in 64-bit mode, compared with the XMM
registers used by SSE2, which did get extended. The x87 register stack is not a simple register file although it does allow direct
access to individual registers by low cost exchange operations.
Larger virtual address space
The AMD64 architecture defines a 64-bit virtual address format, of which the low-order 48 bits are used in current
implementations.[11]: 120  This allows up to 256 TB (248 bytes) of virtual address space. The architecture definition allows this limit
to be raised in future implementations to the full 64 bits,[11]: 2 : 3 : 13 : 117 : 120  extending the virtual address space to 16 EB (264
bytes).[16] This is compared to just 4 GB (232 bytes) for the x86.[17]
This means that very large files can be operated on by mapping the entire file into the process's address space (which is often
much faster than working with file read/write calls), rather than having to map regions of the file into and out of the address
space.
Larger physical address space
The original implementation of the AMD64 architecture implemented 40-bit physical addresses and so could address up to 1 TB
(240 bytes) of RAM.[11]: 24  Current implementations of the AMD64 architecture (starting from AMD 10h microarchitecture) extend
this to 48-bit physical addresses[18] and therefore can address up to 256 TB (248 bytes) of RAM. The architecture permits
extending this to 52 bits in the future[11]: 24 [19] (limited by the page table entry format);[11]: 131  this would allow addressing of up
to 4 PB of RAM. For comparison, 32-bit x86 processors are limited to 64 GB of RAM in Physical Address Extension (PAE)
mode,[20] or 4 GB of RAM without PAE mode.[11]: 4 
Larger physical address space in legacy mode
 When operating in legacy mode the AMD64 architecture supports Physical Address Extension (PAE) mode, as do most current
x86 processors, but AMD64 extends PAE from 36 bits to an architectural limit of 52 bits of physical address. Any implementation,
therefore, allows the same physical address limit as under long mode.[11]: 24 
Instruction pointer relative data access
Instructions can now reference data relative to the instruction pointer (RIP register). This makes position-independent code, as is
often used in shared libraries and code loaded at run time, more efficient.
SSE instructions
The original AMD64 architecture adopted Intel's SSE and SSE2 as core instructions. These instruction sets provide a vector
supplement to the scalar x87 FPU, for the single-precision and double-precision data types. SSE2 also offers integer vector
operations, for data types ranging from 8bit to 64bit precision. This makes the vector capabilities of the architecture on par with
those of the most advanced x86 processors of its time. These instructions can also be used in 32-bit mode. The proliferation of
64-bit processors has made these vector capabilities ubiquitous in home computers, allowing the improvement of the standards
of 32-bit applications. The 32-bit edition of Windows 8, for example, requires the presence of SSE2 instructions.[21] SSE3
instructions and later Streaming SIMD Extensions instruction sets are not standard features of the architecture.
No-Execute bit
The No-Execute bit or NX bit (bit 63 of the page table entry) allows the operating system to specify which pages of virtual
address space can contain executable code and which cannot. An attempt to execute code from a page tagged "no execute" will
result in a memory access violation, similar to an attempt to write to a read-only page. This should make it more difficult for
malicious code to take control of the system via "buffer overrun" or "unchecked buffer" attacks. A similar feature has been
available on x86 processors since the 80286 as an attribute of segment descriptors; however, this works only on an entire
segment at a time.
Segmented addressing has long been considered an obsolete mode of operation, and all current PC operating systems in effect
bypass it, setting all segments to a base address of zero and (in their 32-bit implementation) a size of 4 GB. AMD was the first
x86-family vendor to implement no-execute in linear addressing mode. The feature is also available in legacy mode on AMD64
processors, and recent Intel x86 processors, when PAE is used.
Removal of older features
A few "system programming" features of the x86 architecture were either unused or underused in modern operating systems
and are either not available on AMD64 in long (64-bit and compatibility) mode, or exist only in limited form. These include
segmented addressing (although the FS and GS segments are retained in vestigial form for use as extra-base pointers to
operating system structures),[11]: 70  the task state switch mechanism, and virtual 8086 mode. These features remain fully
implemented in "legacy mode", allowing these processors to run 32-bit and 16-bit operating systems without modifications.
Some instructions that proved to be rarely useful are not supported in 64-bit mode, including saving/restoring of segment
registers on the stack, saving/restoring of all registers (PUSHA/POPA), decimal arithmetic, BOUND and INTO instructions, and
"far" jumps and calls with immediate operands.
Virtual address space details

Canonical form addresses

Although virtual addresses are 64  bits wide in 64-bit mode, current Canonical address space implementations (diagrams not to scale)
implementations (and all chips that are known to be in the planning stages)
do not allow the entire virtual address space of 264 bytes (16 EB) to be used.
This would be approximately four billion times the size of the virtual
address space on 32-bit machines. Most operating systems and applications
will not need such a large address space for the foreseeable future, so
implementing such wide virtual addresses would simply increase the
complexity and cost of address translation with no real benefit. AMD,
therefore, decided that, in the first implementations of the architecture,
only the least significant 48 bits of a virtual address would actually be used
in address translation (page table lookup).[11]: 120 

In addition, the AMD specification requires that the most significant 16 bits
of any virtual address, bits 48 through 63, must be copies of bit 47 (in a
manner akin to sign extension). If this requirement is not met, the
Current 48-bit 57-bit implementation 64-bit implementation
processor will raise an exception.[11]: 131  Addresses complying with this rule
implementation
are referred to as "canonical form."[11]: 130  Canonical form addresses run
from 0 through 00007FFF'FFFFFFFF, and from FFFF8000'00000000
through FFFFFFFF'FFFFFFFF, for a total of 256 TB of usable virtual address space. This is still 65,536 times larger than the virtual 4 GB address
space of 32-bit machines.

This feature eases later scalability to true 64-bit addressing. Many operating systems (including, but not limited to, the Windows NT family) take
the higher-addressed half of the address space (named kernel space) for themselves and leave the lower-addressed half (user space) for
application code, user mode stacks, heaps, and other data regions.[22] The "canonical address" design ensures that every AMD64 compliant
implementation has, in effect, two memory halves: the lower half starts at 00000000'00000000 and "grows upwards" as more virtual address
bits become available, while the higher half is "docked" to the top of the address space and grows downwards. Also, enforcing the "canonical
form" of addresses by checking the unused address bits prevents their use by the operating system in tagged pointers as flags, privilege markers,
etc., as such use could become problematic when the architecture is extended to implement more virtual address bits.

The first versions of Windows for x64 did not even use the full 256  TB; they were restricted to just 8  TB of user space and 8  TB of kernel
space.[22] Windows did not support the entire 48-bit address space until Windows 8.1, which was released in October 2013.[22]
Page table structure

The 64-bit addressing mode ("long mode") is a superset of Physical Address Extensions (PAE); because of this, page sizes may be 4 KB (212 bytes)
or 2 MB (221 bytes).[11]: 120  Long mode also supports page sizes of 1 GB (230 bytes).[11]: 120  Rather than the three-level page table system used by
systems in PAE mode, systems running in long mode use four levels of page table: PAE's Page-Directory Pointer Table is extended from four
entries to 512, and an additional Page-Map Level  4 (PML4) Table is added, containing 512 entries in 48-bit implementations.[11]: 131  A full
mapping hierarchy of 4 KB pages for the whole 48-bit space would take a bit more than 512 GB of memory (about 0.195% of the 256 TB virtual
space).

Intel has implemented a scheme with a 5-level page table, which allows Intel 64 processors to support a 57-bit virtual address space.[23] Further
extensions may allow full 64-bit virtual address space and physical memory by expanding the page table entry size to 128-bit, and reduce page
walks in the 5-level hierarchy by using a larger 64 KB page allocation size that still supports 4 KB page operations for backward compatibility.[24]

Operating system limits

The operating system can also limit the virtual address space. Details, where applicable, are given in the "Operating system compatibility and
characteristics" section.

Physical address space details

Current AMD64 processors support a physical address space of up to 248 bytes of RAM, or 256 TB.[18] However, as of 2020, there were no known
x86-64 motherboards that support 256 TB of RAM.[25][26][27][28] The operating system may place additional limits on the amount of RAM that is
usable or supported. Details on this point are given in the "Operating system compatibility and characteristics" section of this article.

Operating modes

The architecture has two primary modes of operation: long mode and legacy mode.
 Operating Size (in bits)
No. of general-
Type of code operands
Operating system required purpose
mode sub-mode being run addresses (default in registers
italics)

64-bit OS, 64-bit UEFI firmware, or the previous two interacting

64-bit mode 64-bit 64 8, 16, 32, 64 16
via a 64-bit firmware's UEFI interface

Long 32-bit 32 8, 16, 32 8

mode Compatibility
Bootloader or 64-bit OS 16-bit
mode protected 16 8, 16, 32 8
mode

Bootloader, 32-bit OS, 32-bit UEFI firmware, or the latter two

32-bit 32 8, 16, 32 8
interacting via the firmware's UEFI interface
Protected
mode 16-bit
16-bit protected mode OS protected 16 8, 16, 32[m 1] 8
mode
Legacy
mode Virtual 8086 subset of real
16-bit protected mode or 32-bit OS 16 8, 16, 32[m 1] 8
mode mode

Unreal mode Bootloader or real mode OS real mode 16, 20, 32 8, 16, 32[m 1] 8

Bootloader, real mode OS, or any OS interfacing with a

Real mode real mode 16, 20, 21 8, 16, 32[m 1] 8
firmware's BIOS interface[29]

1. Note that 16-bit code written for the 80286 and below does not use 32-bit operand instructions. Code written for the 80386 and
above can use the operand-size override prefix (0x66). Normally this prefix is used by protected and long mode code for the
purpose of using 16-bit operands, as that code would be running in a code segment with a default operand size of 32 bits. In real
mode, the default operand size is 16 bits, so the 0x66 prefix is interpreted differently, changing operand size to 32 bits.

Long mode

Long mode is the architecture's intended primary mode of operation; it is a combination of the processor's native 64-bit mode and a combined
32-bit and 16-bit compatibility mode. It is used by 64-bit operating systems. Under a 64-bit operating system, 64-bit programs run under 64-bit
mode, and 32-bit and 16-bit protected mode applications (that do not need to use either real mode or virtual 8086 mode in order to execute at
any time) run under compatibility mode. Real-mode programs and programs that use virtual 8086 mode at any time cannot be run in long mode
unless those modes are emulated in software.[11]: 11  However, such programs may be
started from an operating system running in long mode on processors supporting
VT-x or AMD-V by creating a virtual processor running in the desired mode.

Since the basic instruction set is the same, there is almost no performance penalty
for executing protected mode x86 code. This is unlike Intel's IA-64, where
differences in the underlying instruction set mean that running 32-bit code must be
done either in emulation of x86 (making the process slower) or with a dedicated x86
coprocessor. However, on the x86-64 platform, many x86 applications could benefit
from a 64-bit recompile, due to the additional registers in 64-bit code and
guaranteed SSE2-based FPU support, which a compiler can use for optimization.
However, applications that regularly handle integers wider than 32 bits, such as
cryptographic algorithms, will need a rewrite of the code handling the huge integers
in order to take advantage of the 64-bit registers.

Legacy mode
State diagram of the x86-64 operating modes
Legacy mode is the mode that the processor is in when it is not in long mode.[11]: 14 
In this mode, the processor acts like an older x86 processor, and only 16-bit and 32-
bit code can be executed. Legacy mode allows for a maximum of 32  bit virtual addressing which limits the virtual address space to
4 GB.[11]: 14 : 24 : 118  64-bit programs cannot be run from legacy mode.

Protected mode

Protected mode is made into a submode of legacy mode.[11]: 14  It is the submode that 32-bit operating systems and 16-bit protected mode
operating systems operate in when running on an x86-64 CPU.[11]: 14 

Real mode

Real mode is the initial mode of operation when the processor is initialized, and is a submode of legacy mode. It is backwards compatible with the
original Intel 8086 and Intel 8088 processors. Real mode is primarily used today by operating system bootloaders, which are required by the
architecture to configure virtual memory details before transitioning to higher modes. This mode is also used by any operating system that needs
to communicate with the system firmware with a traditional BIOS-style interface.[29]
Intel 64
Intel 64 is Intel's implementation of x86-64, used and implemented in various processors made by Intel.

History

Historically, AMD has developed and produced processors with instruction sets patterned after Intel's original designs, but with x86-64, roles
were reversed: Intel found itself in the position of adopting the ISA that AMD created as an extension to Intel's own x86 processor line.

Intel's project was originally codenamed Yamhill[30] (after the Yamhill River in Oregon's Willamette Valley). After several years of denying its
existence, Intel announced at the February 2004 IDF that the project was indeed underway. Intel's chairman at the time, Craig Barrett, admitted
that this was one of their worst-kept secrets.[31][32]

Intel's name for this instruction set has changed several times. The name used at the IDF was CT[33] (presumably for Clackamas Technology,
another codename from an Oregon river); within weeks they began referring to it as IA-32e (for IA-32 extensions) and in March 2004 unveiled
the "official" name EM64T (Extended Memory 64 Technology). In late 2006 Intel began instead using the name Intel 64 for its implementation,
paralleling AMD's use of the name AMD64.[34]

The first processor to implement Intel 64 was the multi-socket processor Xeon code-named Nocona in June 2004. In contrast, the initial Prescott
chips (February 2004) did not enable this feature. Intel subsequently began selling Intel  64-enabled Pentium 4s using the E0 revision of the
Prescott core, being sold on the OEM market as the Pentium 4, model F. The E0 revision also adds eXecute Disable (XD) (Intel's name for the NX
bit) to Intel 64, and has been included in then current Xeon code-named Irwindale. Intel's official launch of Intel 64 (under the name EM64T at
that time) in mainstream desktop processors was the N0 stepping Prescott-2M.

The first Intel mobile processor implementing Intel 64 is the Merom version of the Core 2 processor, which was released on July 27, 2006. None
of Intel's earlier notebook CPUs (Core Duo, Pentium M, Celeron M, Mobile Pentium 4) implement Intel 64.

Implementations

Intel's processors implementing the Intel64 architecture include the Pentium 4 F-series/5x1 series, 506, and 516, Celeron D models 3x1, 3x6, 355,
347, 352, 360, and 365 and all later Celerons, all models of Xeon since "Nocona", all models of Pentium Dual-Core processors since "Merom-
2M", the Atom 230, 330, D410, D425, D510, D525, N450, N455, N470, N475, N550, N570, N2600 and N2800, all versions of the Pentium D,
Pentium Extreme Edition, Core 2, Core i9, Core i7, Core i5, and Core i3 processors, and the Xeon Phi 7200 series processors.
VIA's x86-64 implementation
VIA Technologies introduced their first implementation of the x86-64 architecture in 2008 after five years of development by its CPU division,
Centaur Technology.[35]
Codenamed "Isaiah", the 64-bit architecture was unveiled on January 24, 2008,[36] and launched on May 29 under the
VIA Nano brand name.[37]

The processor supports a number of VIA-specific x86 extensions designed to boost efficiency in low-power appliances.
It is expected that the
Isaiah architecture will be twice as fast in integer performance and four times as fast in floating-point performance as the previous-generation
VIA Esther at an equivalent clock speed. Power consumption is also expected to be on par with the previous-generation VIA CPUs, with thermal
design power ranging from 5 W to 25 W.[38]
Being a completely new design, the Isaiah architecture was built with support for features like the
x86-64 instruction set and x86 virtualization which were unavailable on its predecessors, the VIA C7 line, while retaining their encryption
extensions.

Microarchitecture levels
In 2020, through a collaboration between AMD, Intel, Red Hat, and SUSE, three microarchitecture levels on top of the x86-64 baseline were
defined: x86-64-v2, x86-64-v3, and x86-64-v4.[39][40] These levels define specific features that can be targeted by programmers to provide
compile-time optimizations. The features exposed by each level are as follows:[41]
 CPU microarchitecture levels

Level CPU features Example instruction

CMOV cmov

CX8 cmpxchg8b

FPU fld

FXSR fxsave
x86-64

MMX emms
(baseline: all x86-64 CPUs)
OSFXSR fxsave

SCE syscall

SSE cvtss2si

SSE2 cvtpi2pd

CMPXCHG16B cmpxchg16b
x86-64-v2

LAHF-SAHF lahf
(circa 2009: Nehalem and Jaguar)
POPCNT popcnt
Also:
SSE3 addsubpd
QEMU Emulation
SSE4_1 blendpd
Atom Silvermont (2013)
SSE4_2 pcmpestri
VIA Nano and Eden "C" (2015)
SSSE3 phaddd

x86-64-v3
AVX vzeroall
(circa 2015: Haswell and Excavator)
AVX2 vpermd
Also: BMI1 andn

Atom Gracemont (2021) BMI2 bzhi

F16C vcvtph2ps

FMA vfmadd132pd

LZCNT lzcnt
 MOVBE movbe

OSXSAVE xgetbv

AVX512F kmovw

AVX512BW vdbpsadbw
x86-64-v4

AVX512CD vplzcntd
(AVX-512's general-purpose subset)
AVX512DQ vpmullq

AVX512VL n/a

All levels include features found in the previous levels. Instruction set extensions not concerned with general-purpose computation, including
AES-NI and RDRAND, are excluded from the level requirements.

Differences between AMD64 and Intel 64

Although nearly identical, there are some differences between the two instruction sets in the semantics of a few seldom used machine
instructions (or situations), which are mainly used for system programming.[42] Compilers generally produce executables (i.e. machine code) that
avoid any differences, at least for ordinary application programs. This is therefore of interest mainly to developers of compilers, operating
systems and similar, which must deal with individual and special system instructions.

Recent implementations
Intel 64's BSF and BSR instructions act differently than AMD64's when the source is zero and the operand size is 32 bits. The
processor sets the zero flag and leaves the upper 32 bits of the destination undefined. Note that Intel documents that the
destination register has an undefined value in this case, but in practice in silicon implements the same behaviour as AMD
(destination unmodified). The separate claim about maybe not preserving bits in the upper 32 hasn't been verified, but has only
been ruled out for Core 2 and Skylake,[43] not all Intel microarchitectures like 64-bit Pentium 4 or low-power Atom.
AMD64 requires a different microcode update format and control MSRs (model-specific registers) while Intel 64 implements
microcode update unchanged from their 32-bit only processors.
Intel 64 lacks some MSRs that are considered architectural in AMD64. These include SYSCFG, TOP_MEM, and TOP_MEM2.
Intel 64 allows SYSCALL/SYSRET only in 64-bit mode (not in compatibility mode),[44] and allows SYSENTER/SYSEXIT in both modes.[45]
AMD64 lacks SYSENTER/SYSEXIT in both sub-modes of long mode.[11]: 33 
 In 64-bit mode, near branches with the 66H (operand size override) prefix behave differently. Intel 64 ignores this prefix: the
instruction has 32-bit sign extended offset, and instruction pointer is not truncated. AMD64 uses 16-bit offset field in the
instruction, and clears the top 48 bits of instruction pointer.
AMD processors raise a floating-point Invalid Exception when performing an FLD or FSTP of an 80-bit signalling NaN, while Intel
processors do not.
Intel 64 lacks the ability to save and restore a reduced (and thus faster) version of the floating-point state (involving the FXSAVE and
FXRSTOR instructions).
AMD processors ever since Opteron Rev. E and Athlon 64 Rev. D have reintroduced limited support for segmentation, via the Long
Mode Segment Limit Enable (LMSLE) bit, to ease virtualization of 64-bit guests.[46][47]
When returning to a non-canonical address using SYSRET, AMD64 processors execute the general protection fault handler in
privilege level 3,[48] while on Intel 64 processors it is executed in privilege level 0.[49]

Older implementations
The AMD64 processors prior to the Revision F[50] (distinguished by the switch from DDR to DDR2 memory and new sockets AM2,
F and S1) of 2006 lacked the CMPXCHG16B instruction, which is an extension of the CMPXCHG8B instruction present on most post-80486
processors. Similar to CMPXCHG8B, CMPXCHG16B allows for atomic operations on octa-words (128-bit values). This is useful for parallel
algorithms that use compare and swap on data larger than the size of a pointer, common in lock-free and wait-free algorithms.
Without CMPXCHG16B one must use workarounds, such as a critical section or alternative lock-free approaches.[51] Its absence also
prevents 64-bit Windows prior to Windows 8.1 from having a user-mode address space larger than 8 TB.[52] The 64-bit version of
Windows 8.1 requires the instruction.[53]
Early AMD64 and Intel 64 CPUs lacked LAHF and SAHF instructions in 64-bit mode. AMD introduced these instructions (also in 64-bit
mode) with their 90 nm (revision D) processors, starting with Athlon 64 in October 2004.[54][55] Intel introduced the instructions in
October 2005 with the 0F47h and later revisions of NetBurst.[61] The 64-bit version of Windows 8.1 requires this feature.[53]
Early Intel CPUs with Intel 64 also lack the NX bit of the AMD64 architecture. It was added in the stepping E0 (0F41h) in October
2004.[62] This feature is required by all versions of Windows 8.
Early Intel 64 implementations had a 36-bit (64 GB) physical addressing of memory while original AMD64 implementations had a
40-bit (1 TB) physical addressing. Intel used the 40-bit physical addressing first on Xeon MP (Potomac), launched on 29 March
2005. The difference is not a difference of the user-visible ISAs. Recent AMD64 implementations provide 256 TB of physical
address space (and as of 2021 AMD plans an expansion to 4 PB),[63] while Intel's Sandy Bridge E from 2011 features a 46-bit
(64 TB) physical addressing.[64][65] On the Ice Lake 3rd gen Xeon Scalable processors, Intel increased the virtual addressing to 57
bits (128 PB) and physical to 52 bits (4 PB).[66]
Adoption
In supercomputers tracked by TOP500, the appearance of 64-bit extensions for the x86
architecture enabled 64-bit x86 processors by AMD and Intel to replace most RISC
processor architectures previously used in such systems (including PA-RISC, SPARC,
Alpha and others), as well as 32-bit x86, even though Intel itself initially tried
unsuccessfully to replace x86 with a new incompatible 64-bit architecture in the Itanium
processor.

As of 2020, a Fujitsu A64FX-based supercomputer called Fugaku is number one. The first
ARM-based supercomputer appeared on the list in 2018[68] and, in recent years, non-CPU
architecture co-processors (GPGPU) have also played a big role in performance. Intel's
Xeon Phi "Knights Corner" coprocessors, which implement a subset of x86-64 with some
vector extensions,[69] are also used, along with x86-64 processors, in the Tianhe-2
supercomputer.[70]
An area chart showing the representation of different
families of microprocessors in the TOP500
supercomputer ranking list, from 1993 to 2019.[67]

Operating system compatibility and characteristics

The following operating systems and releases support the x86-64 architecture in long mode.

BSD

DragonFly BSD

Preliminary infrastructure work was started in February 2004 for a x86-64 port.[71] This development later stalled. Development started again
during July 2007[72]
and continued during Google Summer of Code 2008 and SoC 2009.[73][74] The first official release to contain x86-64
support was version 2.4.[75]

FreeBSD
FreeBSD first added x86-64 support under the name "amd64" as an experimental architecture in 5.1-RELEASE in June 2003. It was included as
a standard distribution architecture as of 5.2-RELEASE in January 2004. Since then, FreeBSD has designated it as a Tier 1 platform. The 6.0-
RELEASE version cleaned up some quirks with running x86 executables under amd64, and most drivers work just as they do on the x86
architecture. Work is currently being done to integrate more fully the x86 application binary interface (ABI), in the same manner as the Linux 32-
bit ABI compatibility currently works.

NetBSD

x86-64 architecture support was first committed to the NetBSD source tree on June 19, 2001. As of NetBSD 2.0, released on December 9, 2004,
NetBSD/amd64 is a fully integrated and supported port.
32-bit code is still supported in 64-bit mode, with a netbsd-32 kernel compatibility layer
for 32-bit syscalls. The NX bit is used to provide non-executable stack and heap with per-page granularity (segment granularity being used on 32-
bit x86).

OpenBSD

OpenBSD has supported AMD64 since OpenBSD 3.5, released on May 1, 2004. Complete in-tree implementation of AMD64 support was
achieved prior to the hardware's initial release because AMD had loaned several machines for the project's hackathon that year. OpenBSD
developers have taken to the platform because of its support for the NX bit, which allowed for an easy implementation of the W^X feature.

The code for the AMD64 port of OpenBSD also runs on Intel 64 processors which contains cloned use of the AMD64 extensions, but since Intel
left out the page table NX bit in early Intel 64 processors, there is no W^X capability on those Intel CPUs; later Intel 64 processors added the NX
bit under the name "XD bit". Symmetric multiprocessing (SMP) works on OpenBSD's AMD64 port, starting with release 3.6 on November 1,
2004.

DOS

It is possible to enter long mode under DOS without a DOS extender,[76] but the user must return to real mode in order to call BIOS or DOS
interrupts.

It may also be possible to enter long mode with a DOS extender similar to DOS/4GW, but more complex since x86-64 lacks virtual 8086 mode.
DOS itself is not aware of that, and no benefits should be expected unless running DOS in an emulation with an adequate virtualization driver
backend, for example: the mass storage interface.

Linux
Linux was the first operating system kernel to run the x86-64 architecture in long mode, starting with the 2.4 version in 2001 (preceding the
hardware's availability).[77][78] Linux also provides backward compatibility for running 32-bit executables. This permits programs to be
recompiled into long mode while retaining the use of 32-bit programs. Several Linux distributions currently ship with x86-64-native kernels and
userlands. Some, such as Arch Linux,[79] SUSE, Mandriva, and Debian allow users to install a set of 32-bit components and libraries when
installing off a 64-bit DVD, thus allowing most existing 32-bit applications to run alongside the 64-bit OS. Other distributions, such as Fedora,
Slackware and Ubuntu, are available in one version compiled for a 32-bit architecture and another compiled for a 64-bit architecture. Fedora and
Red Hat Enterprise Linux allow concurrent installation of all userland components in both 32 and 64-bit versions on a 64-bit system.

x32 ABI (Application Binary Interface), introduced in Linux 3.4, allows programs compiled for the x32 ABI to run in the 64-bit mode of x86-64
while only using 32-bit pointers and data fields.[80][81][82]
Though this limits the program to a virtual address space of 4 GB it also decreases the
memory footprint of the program and in some cases can allow it to run faster.[80][81][82]

64-bit Linux allows up to 128 TB of virtual address space for individual processes, and can address approximately 64 TB of physical memory,
subject to processor and system limitations.[83]

macOS

Mac OS X 10.4.7 and higher versions of Mac OS X 10.4 run 64-bit command-line tools using the POSIX and math libraries on 64-bit Intel-based
machines, just as all versions of Mac OS X 10.4 and 10.5 run them on 64-bit PowerPC machines. No other libraries or frameworks work with 64-
bit applications in Mac OS X 10.4.[84]
The kernel, and all kernel extensions, are 32-bit only.

Mac OS X 10.5 supports 64-bit GUI applications using Cocoa, Quartz, OpenGL, and X11 on 64-bit Intel-based machines, as well as on 64-bit
PowerPC machines.[85]
All non-GUI libraries and frameworks also support 64-bit applications on those platforms. The kernel, and all kernel
extensions, are 32-bit only.

Mac OS X 10.6 is the first version of macOS that supports a 64-bit kernel. However, not all 64-bit computers can run the 64-bit kernel, and not all
64-bit computers that can run the 64-bit kernel will do so by default.[86]
The 64-bit kernel, like the 32-bit kernel, supports 32-bit applications;
both kernels also support 64-bit applications. 32-bit applications have a virtual address space limit of 4 GB under either kernel.[87][88] The 64-bit
kernel does not support 32-bit kernel extensions, and the 32-bit kernel does not support 64-bit kernel extensions.

OS X 10.8 includes only the 64-bit kernel, but continues to support 32-bit applications; it does not support 32-bit kernel extensions, however.

macOS 10.15 includes only the 64-bit kernel and no longer supports 32-bit applications. This removal of support has presented a problem for
WineHQ (and the commercial version CrossOver), as it needs to still be able to run 32-bit Windows applications. The solution, termed
wine32on64, was to add thunks that bring the CPU in and out of 32-bit compatibility mode in the nominally 64-bit application.[89][90]
macOS uses the universal binary format to package 32- and 64-bit versions of application and library code into a single file; the most appropriate
version is automatically selected at load time. In Mac OS X 10.6, the universal binary format is also used for the kernel and for those kernel
extensions that support both 32-bit and 64-bit kernels.

Solaris
Solaris 10 and later releases support the x86-64 architecture.

For Solaris 10, just as with the SPARC architecture, there is only one operating system image, which contains a 32-bit kernel and a 64-bit kernel;
this is labeled as the "x64/x86" DVD-ROM image. The default behavior is to boot a 64-bit kernel, allowing both 64-bit and existing or new 32-bit
executables to be run. A 32-bit kernel can also be manually selected, in which case only 32-bit executables will run. The isainfo command can be
used to determine if a system is running a 64-bit kernel.

For Solaris 11, only the 64-bit kernel is provided. However, the 64-bit kernel supports both 32- and 64-bit executables, libraries, and system calls.

Windows

x64 editions of Microsoft Windows client and server—Windows XP Professional x64 Edition and Windows Server 2003 x64 Edition—were
released in March 2005.[91] Internally they are actually the same build (5.2.3790.1830 SP1),[92][93] as they share the same source base and
operating system binaries, so even system updates are released in unified packages, much in the manner as Windows 2000 Professional and
Server editions for x86. Windows Vista, which also has many different editions, was released in January 2007. Windows 7 was released in July
2009. Windows Server 2008 R2 was sold in only x64 and Itanium editions; later versions of Windows Server only offer an x64 edition.

Versions of Windows for x64 prior to Windows 8.1 and Windows Server 2012 R2 offer the following:

8 TB of virtual address space per process, accessible from both user mode and kernel mode, referred to as the user mode address
space. An x64 program can use all of this, subject to backing store limits on the system, and provided it is linked with the "large
address aware" option.[94] This is a 4096-fold increase over the default 2 GB user-mode virtual address space offered by 32-bit
Windows.[95][96]
8 TB of kernel mode virtual address space for the operating system.[95] As with the user mode address space, this is a 4096-fold
increase over 32-bit Windows versions. The increased space primarily benefits the file system cache and kernel mode "heaps"
(non-paged pool and paged pool). Windows only uses a total of 16 TB out of the 256 TB implemented by the processors because
early AMD64 processors lacked a CMPXCHG16B instruction.[97]
Under Windows 8.1 and Windows Server 2012 R2, both user mode and kernel mode virtual address spaces have been extended to 128 TB.[22]
These versions of Windows will not install on processors that lack the CMPXCHG16B instruction.

The following additional characteristics apply to all x64 versions of Windows:

Ability to run existing 32-bit applications (.exe programs) and dynamic link libraries (.dlls) using WoW64 if WoW64 is supported
on that version. Furthermore, a 32-bit program, if it was linked with the "large address aware" option,[94] can use up to 4 GB of
virtual address space in 64-bit Windows, instead of the default 2 GB (optional 3 GB with /3GB boot option and "large address
aware" link option) offered by 32-bit Windows.[98] Unlike the use of the /3GB boot option on x86, this does not reduce the kernel
mode virtual address space available to the operating system. 32-bit applications can, therefore, benefit from running on x64
Windows even if they are not recompiled for x86-64.
Both 32- and 64-bit applications, if not linked with "large address aware," are limited to 2 GB of virtual address space.
Ability to use up to 128 GB (Windows XP/Vista), 192 GB (Windows 7), 512 GB (Windows 8), 1 TB (Windows Server 2003), 2 TB
(Windows Server 2008/Windows 10), 4 TB (Windows Server 2012), or 24 TB (Windows Server 2016/2019) of physical random
access memory (RAM).[99]
LLP64 data model: "int" and "long" types are 32 bits wide, long long is 64 bits, while pointers and types derived from pointers are
64 bits wide.
Kernel mode device drivers must be 64-bit versions; there is no way to run 32-bit kernel mode executables within the 64-bit
operating system. User mode device drivers can be either 32-bit or 64-bit.
16-bit Windows (Win16) and DOS applications will not run on x86-64 versions of Windows due to the removal of the virtual DOS
machine subsystem (NTVDM) which relied upon the ability to use virtual 8086 mode. Virtual 8086 mode cannot be entered while
running in long mode.
Full implementation of the NX (No Execute) page protection feature. This is also implemented on recent 32-bit versions of
Windows when they are started in PAE mode.
Instead of FS segment descriptor on x86 versions of the Windows NT family, GS segment descriptor is used to point to two
operating system defined structures: Thread Information Block (NT_TIB) in user mode and Processor Control Region (KPCR) in
kernel mode. Thus, for example, in user mode GS:0 is the address of the first member of the Thread Information Block. Maintaining
this convention made the x86-64 port easier, but required AMD to retain the function of the FS and GS segments in long mode –
even though segmented addressing per se is not really used by any modern operating system.[95]
Early reports claimed that the operating system scheduler would not save and restore the x87 FPU machine state across thread
context switches. Observed behavior shows that this is not the case: the x87 state is saved and restored, except for kernel mode-
only threads (a limitation that exists in the 32-bit version as well). The most recent documentation available from Microsoft states
 that the x87/MMX/3DNow! instructions may be used in long mode, but that they are deprecated and may cause compatibility
problems in the future.[98]
Some components like Jet Database Engine and Data Access Objects will not be ported to 64-bit architectures such as x86-64 and
IA-64.[100][101][102]
Microsoft Visual Studio can compile native applications to target either the x86-64 architecture, which can run only on 64-bit
Microsoft Windows, or the IA-32 architecture, which can run as a 32-bit application on 32-bit Microsoft Windows or 64-bit
Microsoft Windows in WoW64 emulation mode. Managed applications can be compiled either in IA-32, x86-64 or AnyCPU modes.
Software created in the first two modes behave like their IA-32 or x86-64 native code counterparts respectively; When using the
AnyCPU mode, however, applications in 32-bit versions of Microsoft Windows run as 32-bit applications, while they run as a 64-bit
application in 64-bit editions of Microsoft Windows.

Video game consoles

Both the PlayStation 4 and Xbox One, and all variants of those consoles, incorporate AMD x86-64 processors, based on the Jaguar
microarchitecture.[103][104] Firmware and games are written in x86-64 code; no legacy x86 code is involved.

Their next generations, the PlayStation 5 and the Xbox Series X and Series S respectively, also incorporate AMD x86-64 processors, based on the
Zen 2 microarchitecture.[105][106]

The Steam Deck uses a custom AMD x86-64 accelerated processing unit (APU), based on the Zen 2 microarchitecture.[107]

Industry naming conventions

Since AMD64 and Intel 64 are substantially similar, many software and hardware products use one vendor-neutral term to indicate their
compatibility with both implementations. AMD's original designation for this processor architecture, "x86-64", is still sometimes used for this
purpose,[2] as is the variant "x86_64".[3][4] Other companies, such as Microsoft[6] and Sun Microsystems/Oracle Corporation,[5] use the
contraction "x64" in marketing material.

The term IA-64 refers to the Itanium processor, and should not be confused with x86-64, as it is a completely different instruction set.

Many operating systems and products, especially those that introduced x86-64 support prior to Intel's entry into the market, use the term
"AMD64" or "amd64" to refer to both AMD64 and Intel 64.

amd64
 Most BSD systems such as FreeBSD, MidnightBSD, NetBSD and OpenBSD refer to both AMD64 and Intel 64 under the
architecture name "amd64".
Some Linux distributions such as Debian, Ubuntu, Gentoo Linux refer to both AMD64 and Intel 64 under the architecture name
"amd64".
Microsoft Windows's x64 versions use the AMD64 moniker internally to designate various components which use or are
compatible with this architecture. For example, the environment variable PROCESSOR_ARCHITECTURE is assigned the value
"AMD64" as opposed to "x86" in 32-bit versions, and the system directory on a Windows x64 Edition installation CD-ROM is
named "AMD64", in contrast to "i386" in 32-bit versions.[108]
Sun's Solaris's isalist command identifies both AMD64- and Intel 64-based systems as "amd64".
Java Development Kit (JDK): the name "amd64" is used in directory names containing x86-64 files.
x86_64

The Linux kernel[109] and the GNU Compiler Collection refers to 64-bit architecture as "x86_64".
Some Linux distributions, such as Fedora, openSUSE, Arch Linux, Gentoo Linux refer to this 64-bit architecture as "x86_64".
Apple macOS refers to 64-bit architecture as "x86-64" or "x86_64", as seen in the Terminal command arch[3] and in their
developer documentation.[2][4]
Breaking with most other BSD systems, DragonFly BSD refers to 64-bit architecture as "x86_64".
Haiku refers to 64-bit architecture as "x86_64".

Licensing
x86-64/AMD64 was solely developed by AMD. AMD holds patents on techniques used in AMD64;[110][111][112] those patents must be licensed
from AMD in order to implement AMD64. Intel entered into a cross-licensing agreement with AMD, licensing to AMD their patents on existing
x86 techniques, and licensing from AMD their patents on techniques used in x86-64.[113] In 2009, AMD and Intel settled several lawsuits and
cross-licensing disagreements, extending their cross-licensing agreements.[114][115][116]

See also
AMD Generic Encapsulated Software Architecture (AGESA)
IA-32
x86
 Transient execution CPU vulnerability

Notes
1. Various names are used for the instruction set. Prior to the launch, x86-64 and x86_64 were used, while upon the release AMD
named it AMD64.[1]
Intel initially used the names IA-32e and EM64T before finally settling on "Intel 64" for its implementation.
Some in the industry, including Apple,[2][3][4] use x86-64 and x86_64, while others, notably Sun Microsystems[5]
(now Oracle
Corporation) and Microsoft,[6]
use x64. The BSD family of OSs and several Linux distributions[7][8]
use AMD64, as does Microsoft
Windows internally.[9][10]
2. In practice, 64-bit operating systems generally do not support 16-bit applications, although modern versions of Microsoft
Windows contain a limited workaround that effectively supports 16-bit InstallShield and Microsoft ACME installers by silently
substituting them with 32-bit code.[12]
a. The Register reported that the stepping G1 (0F49h) of Pentium 4 will sample on October 17 and ship in volume on November
14.[59] However, Intel's document says that samples are available on September 9, whereas October 17 is the "date of first
availability of post-conversion material", which Intel defines as "the projected date that a customer may expect to receive the post-
conversion materials. [...] customers should be prepared to receive the post-converted materials on this date".[60]

References
1. "Debian AMD64 FAQ" (http://wiki.debian.org/DebianAMD64Fa
q). Debian Wiki. Archived (https://web.archive.org/web/20190
926163758/https://wiki.debian.org/DebianAMD64Faq) from
the original on September 26, 2019. Retrieved May 3, 2012.
2. "x86-64 Code Model" (https://developer.apple.com/library/ma
c/#documentation/developertools/Conceptual/MachOTopics/
1-Articles/x86_64_code.html). Apple. Archived (https://web.arc
hive.org/web/20120602013413/https://developer.apple.com/li
brary/mac/#documentation/developertools/Conceptual/Mach
OTopics/1-Articles/x86_64_code.html) from the original on
June 2, 2012. Retrieved November 23, 2012.
3. arch(1) (https://www.unix.com/man-page/mojave/1/arch) –
 Darwin and macOS General Commands Manual
4. Kevin Van Vechten (August 9, 2006). "re: Intel XNU bug report"
(https://web.archive.org/web/20200201090447/https://lists.ap
ple.com/archives/Darwin-dev/2006/Aug/msg00095.html).
Darwin-dev mailing list. Apple Computer. Archived from the
original (http://lists.apple.com/archives/Darwin-dev/2006/Au
g/msg00095.html) on February 1, 2020. Retrieved October 5,
2006. "The kernel and developer tools have standardized on
"x86_64" for the name of the Mach-O architecture"
5. "Solaris 10 on AMD Opteron" (http://www.oracle.com/technet
work/server-storage/solaris/overview/solaris10amdopteron-js
p-140575.html). Oracle. Archived (https://web.archive.org/we
b/20170725114435/http://www.oracle.com/technetwork/serve
r-storage/solaris/overview/solaris10amdopteron-jsp-140575.h
tml) from the original on July 25, 2017. Retrieved December 9,
2010.
 6. "Microsoft 64-Bit Computing" (https://web.archive.org/web/2
0101212040212/http://www.microsoft.com/windowsserver200
8/en/us/64bit-computing.aspx). Microsoft. Archived from the
original (http://www.microsoft.com/windowsserver2008/en/u
s/64bit-computing.aspx) on December 12, 2010. Retrieved
December 9, 2010.
7. "AMD64 Port" (http://www.debian.org/ports/amd64/). Debian.
Archived (https://web.archive.org/web/20190926060654/http
s://www.debian.org/ports/amd64/) from the original on
September 26, 2019. Retrieved November 23, 2012.
8. "Gentoo/AMD64 Project" (http://www.gentoo.org/proj/en/bas
e/amd64/). Gentoo Project. Archived (https://web.archive.org/
web/20130603152916/http://www.gentoo.org/proj/en/base/a
md64/) from the original on June 3, 2013. Retrieved May 27,
2013.
9. "WOW64 Implementation Details" (https://msdn.microsoft.co
m/en-us/library/windows/desktop/aa384274(v=vs.85).aspx).
Archived (https://web.archive.org/web/20180413001932/http
s://msdn.microsoft.com/en-us/library/windows/desktop/aa38
4274(v=vs.85).aspx) from the original on April 13, 2018.
Retrieved January 24, 2016.
10. "ProcessorArchitecture Class" (https://msdn.microsoft.com/en
-us/library/microsoft.build.utilities.processorarchitecture.aspx).
Archived (https://web.archive.org/web/20170603232543/http
s://msdn.microsoft.com/en-us/library/microsoft.build.utilities.
processorarchitecture.aspx) from the original on June 3, 2017.
Retrieved January 24, 2016.
11. AMD Corporation (December 2016). "Volume 2: System
Programming" (http://support.amd.com/TechDocs/24593.pdf)
(PDF). AMD64 Architecture Programmer's Manual. AMD
Corporation. Archived (https://web.archive.org/web/20180713
145424/https://support.amd.com/TechDocs/24593.pdf) (PDF)
from the original on July 13, 2018. Retrieved March 25, 2017.
12. Raymond Chen (October 31, 2013). "If there is no 16-bit
emulation layer in 64-bit Windows, how come certain 16-bit
installers are allowed to run?" (https://devblogs.microsoft.co
m/oldnewthing/20131031-00/?p=2783). Archived (https://we
b.archive.org/web/20210714084610/https://devblogs.microsof
t.com/oldnewthing/20131031-00/?p=2783) from the original
on July 14, 2021. Retrieved July 14, 2021.
13. IBM Corporation (September 6, 2007). "IBM WebSphere
Application Server 64-bit Performance Demystified" (ftp://ftp.
software.ibm.com/software/webserver/appserv/was/64bitPerf.
pdf) (PDF). p. 14. Archived (https://web.archive.org/web/2022
0125121650/ftp://ftp.software.ibm.com/software/webserver/a
ppserv/was/64bitPerf.pdf) (PDF) from the original on January
25, 2022. Retrieved April 9, 2010. "Figures 5, 6 and 7 also show
the 32-bit version of WAS runs applications at full native
hardware performance on the POWER and x86-64 platforms.
Unlike some 64-bit processor architectures, the POWER and
x86-64 hardware does not emulate 32-bit mode. Therefore
applications that do not benefit from 64-bit features can run
with full performance on the 32-bit version of WebSphere
running on the above mentioned 64-bit platforms."
14. "AMD Discloses New Technologies At Microporcessor Forum"
(https://web.archive.org/web/20120308030806/http://www.a
md.com/us/press-releases/Pages/Press_Release_751.aspx)
(Press release). AMD. October 5, 1999. Archived from the
original (https://www.amd.com/us/press-releases/Pages/Press
_Release_751.aspx) on March 8, 2012. Retrieved November 9,
2010.
15. "AMD Releases x86-64 Architectural Specification; Enables
Market Driven Migration to 64-Bit Computing" (https://web.ar
chive.org/web/20120308025559/http://www.amd.com/us/pres
s-releases/Pages/Press_Release_715.aspx) (Press release).
AMD. August 10, 2000. Archived from the original (https://ww
w.amd.com/us/press-releases/Pages/Press_Release_715.aspx)
on March 8, 2012. Retrieved November 9, 2010.
16. Mauerer, W. (2010). Professional Linux kernel architecture.
John Wiley & Sons.
17. "Intel 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A: System Programming Guide, Part 1" (htt
p://www.intel.com/Assets/PDF/manual/253668.pdf) (PDF).
pp. 4–7. Archived (https://web.archive.org/web/201105161453
22/http://www.intel.com/Assets/PDF/manual/253668.pdf)
(PDF) from the original on May 16, 2011. Retrieved July 10,
2019.
18. "BIOS and Kernel Developer's Guide (BKDG) For AMD Family
10h Processors" (http://developer.amd.com/wordpress/media/
2012/10/31116.pdf) (PDF). p. 24. Archived (https://web.archiv
e.org/web/20160418185513/http://developer.amd.com/wordp
ress/media/2012/10/31116.pdf) (PDF) from the original on
April 18, 2016. Retrieved February 27, 2016. "Physical address
space increased to 48 bits."
19. "Myth and facts about 64-bit Linux" (https://web.archive.org/
web/20101010233951/http://www.amd64.org/fileadmin/user_
upload/pub/64bit_Linux-Myths_and_Facts.pdf) (PDF). March 2,
2008. p. 7. Archived from the original (http://www.amd64.org/f
ileadmin/user_upload/pub/64bit_Linux-Myths_and_Facts.pdf)
(PDF) on October 10, 2010. Retrieved May 30, 2010. "Physical
address space increased to 48 bits"
20. Shanley, Tom (1998). Pentium Pro and Pentium II System
Architecture (https://archive.org/details/pentiumpropentiu00s
han/page/445). PC System Architecture Series (Second ed.).
Addison-Wesley. p. 445 (https://archive.org/details/pentiumpr
opentiu00shan/page/445). ISBN 0-201-30973-4.
21. Microsoft Corporation. "What is PAE, NX, and SSE2 and why
does my PC need to support them to run Windows 8 ?" (htt
p://windows.microsoft.com/en-GB/windows-8/what-is-pae-nx
-sse2). Archived (https://web.archive.org/web/2013041100441
1/http://windows.microsoft.com/en-GB/windows-8/what-is-pa
e-nx-sse2) from the original on April 11, 2013. Retrieved
March 19, 2013.
22. "Memory Limits for Windows Releases" (http://msdn.microsof
t.com/en-us/library/windows/desktop/aa366778(v=vs.85).asp
x#memory_limits). MSDN. Microsoft. November 16, 2013.
Archived (https://web.archive.org/web/20140106195757/htt
p://msdn.microsoft.com/en-us/library/windows/desktop/aa36
6778(v=vs.85).aspx#memory_limits) from the original on
January 6, 2014. Retrieved January 20, 2014.
23. "5-Level Paging and 5-Level EPT" (https://software.intel.com/si
tes/default/files/managed/2b/80/5-level_paging_white_paper.
pdf) (PDF). Intel. May 2017. Archived (https://web.archive.org/
web/20181205041235/https://software.intel.com/sites/defaul
t/files/managed/2b/80/5-level_paging_white_paper.pdf) (PDF)
from the original on December 5, 2018. Retrieved June 17,
2017.
24. US patent 9858198 (https://worldwide.espacenet.com/textdo
c?DB=EPODOC&IDX=US9858198), Larry Seiler, "64KB page
system that supports 4KB page operation", published 2016-
12-29, issued 2018-01-02, assigned to Intel Corp.
25. "Opteron 6100 Series Motherboards" (http://www.supermicro.
com/Aplus/motherboard/Opteron6100/). Supermicro
Corporation. Archived (https://web.archive.org/web/20100603
182215/http://www.supermicro.com/Aplus/motherboard/Opt
eron6100/) from the original on June 3, 2010. Retrieved
June 22, 2010.
26. "Supermicro XeonSolutions" (http://www.supermicro.com/pro
ducts/motherboard/Xeon1333/#1366). Supermicro
Corporation. Archived (https://web.archive.org/web/20100527
224603/http://www.supermicro.com/products/motherboard/X
eon1333/#1366) from the original on May 27, 2010. Retrieved
June 20, 2010.
27. "Opteron 8000 Series Motherboards" (http://www.supermicro.
com/Aplus/motherboard/Opteron8000/). Supermicro
Corporation. Archived (https://web.archive.org/web/20100527
212322/http://www.supermicro.com/Aplus/motherboard/Opt
eron8000/) from the original on May 27, 2010. Retrieved
June 20, 2010.
28. "Tyan Product Matrix" (http://www.supermicro.com/products/
motherboard/Core/index.cfm#1366). MiTEC International
Corporation. Archived (https://web.archive.org/web/20100606
190740/http://www.supermicro.com/products/motherboard/C
ore/index.cfm#1366) from the original on June 6, 2010.
Retrieved June 21, 2010.
29. "From the AMI Archives: AMIBIOS 8 and the Transition to EFI"
(https://web.archive.org/web/20211025233343/https://www.a
mi.com/tech-blog/from-the-ami-archives-amibios-8-and-the-
transition-to-efi/). American Megatrends. September 8, 2017.
Archived from the original (https://www.ami.com/tech-blog/fr
om-the-ami-archives-amibios-8-and-the-transition-to-efi/) on
October 25, 2021. Retrieved October 25, 2021.
30. "Intel is Continuing the Yamhill Project?" (https://www.neowin.
net/news/intel-is-continuing-the-yamhill-project/). Neowin.
Retrieved June 5, 2022.
31. "Craig Barrett confirms 64 bit address extensions for Xeon.
And Prescott" (https://archive.today/20130112014446/http://
www.theinquirer.net/inquirer/news/1042795/craig-barrett-con
firms-bit-address-extensions-xeon-and-prescott). The Inquirer.
February 17, 2004. Archived from the original (https://www.th
einquirer.net/inquirer/news/1042795/craig-barrett-confirms-bi
t-address-extensions-xeon-and-prescott) on January 12, 2013.
Retrieved August 20, 2017.
32. " "A Roundup of 64-Bit Computing", from internetnews.com"
(https://web.archive.org/web/20120925003349/http://www.int
ernetnews.com/ent-news/article.php/3518781). Archived from
the original (http://www.internetnews.com/ent-news/article.ph
p/3518781) on September 25, 2012. Retrieved September 18,
2006.
33. Lapedus, Mark. "Intel to demo 'CT' 64-bit processor line at
IDF" (https://www.edn.com/intel-to-demo-ct-64-bit-processor
-line-at-idf/). EDN. AspenCore Media. Archived (https://web.ar
chive.org/web/20210525031727/https://www.edn.com/intel-t
o-demo-ct-64-bit-processor-line-at-idf/) from the original on
May 25, 2021. Retrieved May 25, 2021.
34. "Intel 64 Architecture" (http://www.intel.com/technology/intel
64/index.htm). Intel. Archived (https://web.archive.org/web/20
110629214538/http://www.intel.com/technology/intel64/inde
x.htm) from the original on June 29, 2011. Retrieved June 29,
2007.
35. "VIA to launch new processor architecture in 1Q08" (http://ww
w.digitimes.com/news/a20070725PD206.html) (subscription
required). DigiTimes. Archived (https://web.archive.org/web/2
0081203201340/http://www.digitimes.com/news/a20070725P
D206.html) from the original on December 3, 2008. Retrieved
July 25, 2007.
36. Stokes, Jon (January 23, 2008). "Isaiah revealed: VIA's new low-
power architecture" (https://arstechnica.com/articles/paedia/c
pu/via-cpu-isaiah.ars). Ars Technica. Archived (https://web.arc
hive.org/web/20080127095807/http://arstechnica.com/article
s/paedia/cpu/via-cpu-isaiah.ars) from the original on January
27, 2008. Retrieved January 24, 2008.
37. "VIA Launches VIA Nano Processor Family" (http://www.viatec
h.com/en/2008/05/via-launches-via-nano-processor-family/)
(Press release). VIA. May 29, 2008. Archived (https://web.archiv
e.org/web/20190203072901/https://www.viatech.com/en/200
8/05/via-launches-via-nano-processor-family/) from the
original on February 3, 2019. Retrieved May 25, 2017.
38. "VIA Isaiah Architecture Introduction" (https://web.archive.or
g/web/20080907181213/http://www.via.com.tw/en/download
s/presentations/processors/pb_via-isaiah_080124.pdf) (PDF).
VIA. January 23, 2008. Archived from the original (http://www.
via.com.tw/en/downloads/presentations/processors/pb_via-is
aiah_080124.pdf) (PDF) on September 7, 2008. Retrieved
July 31, 2013.
39. Weimer, Florian (July 10, 2020). "New x86-64 micro-
architecture levels" (https://lists.llvm.org/pipermail/llvm-dev/2
020-July/143289.html). llvm-dev (Mailing list). Archived (http
s://web.archive.org/web/20210414100705/https://lists.llvm.or
g/pipermail/llvm-dev/2020-July/143289.html) from the
original on April 14, 2021. Retrieved March 11, 2021.
40. Weimer, Florian (January 5, 2021). "Building Red Hat Enterprise
Linux 9 for the x86-64-v2 microarchitecture level" (https://dev
elopers.redhat.com/blog/2021/01/05/building-red-hat-enterp
rise-linux-9-for-the-x86-64-v2-microarchitecture-level). Red
Hat developer blog. Retrieved March 22, 2022.
41. "System V Application Binary Interface Low Level System
Information" (https://gitlab.com/x86-psABIs/x86-64-ABI/-/blo
b/master/x86-64-ABI/low-level-sys-info.tex). x86-64 psABI
repo. January 29, 2021. Archived (https://web.archive.org/we
b/20210202215134/https://gitlab.com/x86-psABIs/x86-64-AB
I/-/blob/master/x86-64-ABI/low-level-sys-info.tex) from the
original on February 2, 2021. Retrieved March 11, 2021 – via
GitLab.
42. Wasson, Scott (March 23, 2005). "64-bit computing in theory
and practice" (http://techreport.com/articles.x/8131/1). The
Tech Report. The Tech Report. Archived (https://web.archive.or
g/web/20110312004304/http://techreport.com/articles.x/813
1/1) from the original on March 12, 2011. Retrieved March 22,
2011.
43. "Discussion on Stack Overflow" (https://stackoverflow.com/qu
estions/66416287/in-x86-64-does-a-32-bit-cmov-clear-the-to
p-bits-if-the-condition-is-false/66416462#comment11746592
5_66416462). March 2021. Retrieved March 2, 2021.
44. "Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z" (htt
p://www.intel.com/content/dam/www/public/us/en/document
s/manuals/64-ia-32-architectures-software-developer-instructi
on-set-reference-manual-325383.pdf) (PDF). Intel. September
2013. pp. 4–397. Archived (https://web.archive.org/web/20131
020144800/http://www.intel.com/content/dam/www/public/u
s/en/documents/manuals/64-ia-32-architectures-software-de
veloper-instruction-set-reference-manual-325383.pdf) (PDF)
from the original on October 20, 2013. Retrieved January 21,
2014.
45. "Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z" (htt
p://www.intel.com/content/dam/www/public/us/en/document
s/manuals/64-ia-32-architectures-software-developer-instructi
on-set-reference-manual-325383.pdf) (PDF). Intel. September
2013. pp. 4–400. Archived (https://web.archive.org/web/20131
020144800/http://www.intel.com/content/dam/www/public/u
s/en/documents/manuals/64-ia-32-architectures-software-de
veloper-instruction-set-reference-manual-325383.pdf) (PDF)
from the original on October 20, 2013. Retrieved January 21,
2014.
46. "How retiring segmentation in AMD64 long mode broke
VMware" (http://www.pagetable.com/?p=25). Pagetable.com.
November 9, 2006. Archived (https://web.archive.org/web/201
10718104331/http://www.pagetable.com/?p=25) from the
original on July 18, 2011. Retrieved May 2, 2010.
47. "VMware and CPU Virtualization Technology" (http://downloa
d3.vmware.com/vmworld/2005/pac346.pdf) (PDF). VMware.
Archived (https://web.archive.org/web/20110717231306/htt
p://download3.vmware.com/vmworld/2005/pac346.pdf) (PDF)
from the original on July 17, 2011. Retrieved September 8,
2010.
48. "AMD64 Architecture Programmer's Manual Volume 3:
General-Purpose and System Instructions" (https://support.am
d.com/TechDocs/24594.pdf) (PDF). AMD. May 2018. p. 419.
Archived (https://web.archive.org/web/20180820123419/http
s://support.amd.com/TechDocs/24594.pdf) (PDF) from the
original on August 20, 2018. Retrieved August 2, 2018.
49. "Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z" (htt
p://www.intel.com/content/dam/www/public/us/en/document
s/manuals/64-ia-32-architectures-software-developer-instructi
on-set-reference-manual-325383.pdf) (PDF). Intel. September
2014. pp. 4–412. Archived (https://web.archive.org/web/20150
113223656/http://www.intel.com/content/dam/www/public/u
s/en/documents/manuals/64-ia-32-architectures-software-de
veloper-instruction-set-reference-manual-325383.pdf) (PDF)
from the original on January 13, 2015. Retrieved December 28,
2014.
50. "Live Migration with AMD-V™ Extended Migration
Technology" (http://developer.amd.com/wordpress/media/201
2/10/43781-3.00-PUB_Live-Virtual-Machine-Migration-on-AM
D-processors.pdf) (PDF). developer.amd.com.
51. Maged M. Michael. "Practical Lock-Free and Wait-Free
LL/SC/VL Implementations Using 64-Bit CAS" (http://www.rese
arch.ibm.com/people/m/michael/disc-2004.pdf) (PDF). IBM.
Archived (https://web.archive.org/web/20130502033436/htt
p://www.research.ibm.com/people/m/michael/disc-2004.pdf)
(PDF) from the original on May 2, 2013. Retrieved January 21,
2014.
52. darwou (August 20, 2004). "Why is the virtual address space
4GB anyway?" (https://blogs.msdn.microsoft.com/oldnewthin
g/20040817-00/?p=38153#comment-204583). The Old New
Thing. Microsoft. Archived (https://web.archive.org/web/2017
0326140218/https://blogs.msdn.microsoft.com/oldnewthing/2
0040817-00/?p=38153#comment-204583) from the original
on March 26, 2017. Retrieved March 25, 2017.
53. "System Requirements—Windows 8.1" (http://windows.micros
oft.com/en-us/windows-8/system-requirements). Archived (ht
tps://web.archive.org/web/20140428223434/http://windows.
microsoft.com/en-us/windows-8/system-requirements) from
the original on April 28, 2014. Retrieved April 27, 2014. "To
install a 64-bit OS on a 64-bit PC, your processor needs to
support CMPXCHG16b, PrefetchW, and LAHF/SAHF."
54. Petkov, Borislav (August 10, 2009). "Re: [PATCH v2] x86: clear
incorrectly forced X86_FEATURE_LAHF_LM flag" (https://lkml.o
rg/lkml/2009/8/10/159). Linux kernel mailing list.
55. " "Revision Guide for AMD Athlon 64 and AMD Opteron
Processors", from AMD" (http://support.amd.com/us/Processo
r_TechDocs/25759.pdf) (PDF). Archived (https://web.archive.or
g/web/20090824002650/http://support.amd.com/us/Processo
r_TechDocs/25759.pdf) (PDF) from the original on August 24,
2009. Retrieved July 18, 2009.
56. "Product Change Notification 105224 - 01" (https://web.archiv
e.org/web/20051117160702/http://developer.intel.com/desig
n/pcn/Processors/D0105224.pdf) (PDF). Intel. Archived from
the original (http://developer.intel.com/design/pcn/Processor
s/D0105224.pdf) (PDF) on November 17, 2005.
57. "Intel® Pentium® D Processor 800 Sequence and Intel®
Pentium® Processor Extreme Edition 840 Specification
Update" (https://www.intel.com/Assets/PDF/specupdate/3068
32.pdf) (PDF).
58. "Intel Xeon 2.8 GHz - NE80551KG0724MM /
BX80551KG2800HA" (https://www.cpu-world.com/CPUs/Xeo
n/Intel-Xeon%202.8%20GHz%20-%20NE80551KG0724MM%2
0(BX80551KG2800HA).html). CPU-World.
59. Smith, Tony (August 23, 2005). "Intel tweaks EM64T for full
AMD64 compatibility" (https://www.theregister.com/2005/08/
23/intel_fixes_em64t/). The Register.
60. "Product Change Notification 105271 – 00" (https://web.archiv
e.org/web/20051117162258/http://developer.intel.com/desig
n/pcn/Processors/D0105271.pdf) (PDF). Intel. Archived from
the original (http://developer.intel.com/design/pcn/Processor
s/D0105271.pdf) (PDF) on November 17, 2005.
61. 0F47h debuted in the B0 stepping of Pentium D on October
21,[56][57] but 0F48h which also supports LAHF/SAHF launched
on October 10 in the dual-core Xeon.[58][a]
62. "Product Change Notification 104101 – 00" (https://web.archiv
e.org/web/20040716131656/http://developer.intel.com/desig
n/pcn/Processors/D0104101.pdf) (PDF). Intel. Archived from
the original (http://developer.intel.com/design/pcn/Processor
s/D0104101.pdf) (PDF) on July 16, 2004.
63. Larabel, Michael (August 10, 2021). "AMD Preparing 5-Level
Paging Linux Support For Future CPUs" (https://www.phoroni
x.com/scan.php?page=news_item&px=AMD-5-Level-Paging-
KVM). Phoronix.
64. "Intel 64 architecture increases the linear address space for
software to 64 bits and supports physical address space up to
46 bits." on page Vol. 1 2-21 of Intel 64 and IA-32
Architectures Software Developer's Manual September 2014
(http://www.intel.com/content/www/us/en/architecture-and-t
echnology/64-ia-32-architectures-software-developer-manual
-325462.html) Archived (https://web.archive.org/web/2019051
4124207/https://www.intel.com/content/www/us/en/architect
ure-and-technology/64-ia-32-architectures-software-develop
er-manual-325462.html) May 14, 2019, at the Wayback
Machine
65. Logan, Tom (November 14, 2011). "Intel Core i7-3960X
Review" (https://overclock3d.net/reviews/cpu_mainboard/intel
_core_i7-3960x_review/2). Retrieved July 1, 2022.
66. Ye, Huaisheng. "Introduction to 5-Level Paging in 3rd Gen Intel
Xeon Scalable Processors with Linux" (https://lenovopress.leno
vo.com/lp1468.pdf) (PDF). Lenovo. Retrieved July 1, 2022.
67. "Statistics | TOP500 Supercomputer Sites" (http://www.top500.
org/statistics). Top500.org. Archived (https://web.archive.org/
web/20140319023302/http://www.top500.org/statistics/) from
the original on March 19, 2014. Retrieved March 22, 2014.
68. "Sublist Generator | TOP500 Supercomputer Sites" (https://ww
w.top500.org/statistics/sublist/). www.top500.org. Archived (ht
tps://web.archive.org/web/20181207200508/https://www.top5
00.org/statistics/sublist/) from the original on December 7,
2018. Retrieved December 6, 2018.
69. "Intel® Xeon PhiTM Coprocessor Instruction Set Architecture
Reference Manual" (https://software.intel.com/sites/default/fil
es/forum/278102/327364001en.pdf) (PDF). Intel. September 7,
2012. section B.2 Intel Xeon Phi coprocessor 64 bit Mode
Limitations. Archived (https://web.archive.org/web/201405210
50107/https://software.intel.com/sites/default/files/forum/278
102/327364001en.pdf) (PDF) from the original on May 21,
2014. Retrieved May 21, 2014.
70. "Intel Powers the World's Fastest Supercomputer, Reveals New
and Future High Performance Computing Technologies" (htt
p://newsroom.intel.com/community/intel_newsroom/blog/20
13/06/17/intel-powers-the-worlds-fastest-supercomputer-rev
eals-new-and-future-high-performance-computing-technolog
ies). Archived (https://web.archive.org/web/20130622162239/
http://newsroom.intel.com/community/intel_newsroom/blog/
2013/06/17/intel-powers-the-worlds-fastest-supercomputer-r
eveals-new-and-future-high-performance-computing-technol
ogies) from the original on June 22, 2013. Retrieved June 21,
2013.
71. "cvs commit: src/sys/amd64/amd64 genassym.c
src/sys/amd64/include asm.h atomic.h bootinfo.h coredump.h
cpufunc.h elf.h endian.h exec.h float.h fpu.h frame.h
globaldata.h ieeefp.h limits.h lock.h md_var.h param.h pcb.h
pcb_ext.h pmap.h proc.h profile.h psl.h ..." (http://leaf.dragonfl
ybsd.org/mailarchive/commits/2004-02/msg00011.html)
Archived (https://web.archive.org/web/20081204123450/htt
p://leaf.dragonflybsd.org/mailarchive/commits/2004-02/msg0
0011.html) from the original on December 4, 2008. Retrieved
May 3, 2009.
72. "AMD64 port" (http://leaf.dragonflybsd.org/mailarchive/users/
2007-07/msg00016.html). Archived (https://web.archive.org/w
eb/20100518104312/http://leaf.dragonflybsd.org/mailarchive/
users/2007-07/msg00016.html) from the original on May 18,
2010. Retrieved May 3, 2009.
73. "DragonFlyBSD: GoogleSoC2008" (http://www.dragonflybsd.or
g/docs/developer/GoogleSoC2008/). Archived (https://web.ar
chive.org/web/20090427115711/http://www.dragonflybsd.or
g/docs/developer/GoogleSoC2008/) from the original on April
27, 2009. Retrieved May 3, 2009.
74. "Summer of Code accepted students" (http://leaf.dragonflybs
d.org/mailarchive/users/2009-04/msg00091.html). Archived (h
ttps://web.archive.org/web/20100904021545/http://leaf.drago
nflybsd.org/mailarchive/users/2009-04/msg00091.html) from
the original on September 4, 2010. Retrieved May 3, 2009.
75. "DragonFlyBSD: release24" (http://www.dragonflybsd.org/rele
ase24/). Archived (https://web.archive.org/web/200909231527
27/http://www.dragonflybsd.org/release24/) from the original
on September 23, 2009. Retrieved May 3, 2009.
76. "Tutorial for entering protected and long mode from DOS" (ht
tps://web.archive.org/web/20170222181811/http://www.turbo
irc.com/asm/). Archived from the original (http://www.turboir
c.com/asm) on February 22, 2017. Retrieved July 6, 2008.
77. Andi Kleen (June 26, 2001). "Porting Linux to x86-64" (https://
web.archive.org/web/20100910014057/http://www.x86-64.or
g/pipermail/announce/2001-June/000020.html). Archived
from the original (http://www.x86-64.org/pipermail/announc
e/2001-June/000020.html) on September 10, 2010. "Status:
The kernel, compiler, tool chain work. The kernel boots and
work on simulator and is used for porting of userland and
running programs"
78. Andi Kleen. "Andi Kleen's Page" (http://www.halobates.de/).
Archived (https://web.archive.org/web/20091207131536/htt
p://www.halobates.de/) from the original on December 7,
2009. Retrieved August 21, 2009. "This was the original paper
describing the Linux x86-64 kernel port back when x86-64 was
only available on simulators."
79. "Arch64 FAQ" (https://wiki.archlinux.org/index.php/Arch64_FA
Q). April 23, 2012. Archived (https://web.archive.org/web/2012
0514030334/https://wiki.archlinux.org/index.php/Arch64_FAQ)
from the original on May 14, 2012. Retrieved May 11, 2012.
"You can either use the multilib packages or a i686 chroot."
80. Thorsten Leemhuis (September 13, 2011). "Kernel Log: x32 ABI
gets around 64-bit drawbacks" (https://web.archive.org/web/2
0111028081253/http://www.h-online.com/open/features/Kern
el-Log-x32-ABI-gets-around-64-bit-drawbacks-1342061.html).
www.h-online.com. Archived from the original (http://www.h-o
nline.com/open/features/Kernel-Log-x32-ABI-gets-around-64
-bit-drawbacks-1342061.html) on October 28, 2011. Retrieved
November 1, 2011.
81. "x32 - a native 32-bit ABI for x86-64" (http://linuxplumberscon
f.org/2011/ocw/sessions/531). linuxplumbersconf.org.
Archived (https://web.archive.org/web/20120505022446/htt
p://www.linuxplumbersconf.org/2011/ocw/sessions/531) from
the original on May 5, 2012. Retrieved November 1, 2011.
82. "x32-abi" (https://sites.google.com/site/x32abi/). Google Sites.
Archived (https://web.archive.org/web/20111030054600/htt
p://sites.google.com/site/x32abi/) from the original on
October 30, 2011. Retrieved November 1, 2011.
83. "AMD64 Port" (http://www.debian.org/ports/amd64/).
debian.org. Archived (https://web.archive.org/web/201909260
60654/https://www.debian.org/ports/amd64/) from the
original on September 26, 2019. Retrieved October 29, 2011.
84. "Apple – Mac OS X Xcode 2.4 Release Notes: Compiler Tools"
(https://web.archive.org/web/20090422045532/http://develop
er.apple.com/releasenotes/DeveloperTools/RN-CompilerTools/
index.html). Apple Inc. April 11, 2007. Archived from the
original (https://developer.apple.com/releasenotes/Developer
Tools/RN-CompilerTools/index.html) on April 22, 2009.
Retrieved November 19, 2012.
85. "Apple – Mac OS X Leopard – Technology - 64-bit" (https://we
b.archive.org/web/20090112055017/http://www.apple.com/m
acosx/technology/64bit.html). Apple Inc. Archived from the
original (https://www.apple.com/macosx/technology/64bit.ht
ml) on January 12, 2009. Retrieved November 19, 2012.
86. "Mac OS X v10.6: Macs that use the 64-bit kernel" (http://supp
ort.apple.com/kb/HT3770). Apple Inc. Archived (https://web.ar
chive.org/web/20090831113241/http://support.apple.com/k
b/HT3770) from the original on August 31, 2009. Retrieved
November 29, 2012.
87. John Siracusa. "Mac OS X 10.6 Snow Leopard: the Ars Technica
review" (https://arstechnica.com/apple/reviews/2009/08/mac-
os-x-10-6.ars/5). Ars Technica LLC. Archived (https://web.archi
ve.org/web/20091009161632/http://arstechnica.com/apple/re
views/2009/08/mac-os-x-10-6.ars/5) from the original on
October 9, 2009. Retrieved June 20, 2010.
88. "Mac OS X Technology" (https://web.archive.org/web/2011032
8170107/http://www.apple.com/macosx/technology/#sixtyfou
rbit). Apple Inc. Archived from the original (https://www.apple.
com/macosx/technology/#sixtyfourbit) on March 28, 2011.
Retrieved November 19, 2012.
89. "So We Don't Have a Solution for Catalina...Yet" (https://www.c
odeweavers.com/blog/jschmid/2019/9/10/so-we-dont-have-a
-solution-for-catalinayet). CodeWeavers Blog. Archived (http
s://web.archive.org/web/20210929085817/https://www.codew
eavers.com/blog/jschmid/2019/9/10/so-we-dont-have-a-solut
ion-for-catalinayet) from the original on September 29, 2021.
Retrieved September 29, 2021.
90. Thomases, Ken (December 11, 2019). "win32 on macOS" (http
s://www.winehq.org/pipermail/wine-devel/2019-December/15
6602.html). Archived (https://web.archive.org/web/202011111
90220/https://www.winehq.org/pipermail/wine-devel/2019-D
ecember/156602.html) from the original on November 11,
2020. Retrieved September 29, 2021.
91. "Microsoft Raises the Speed Limit with the Availability of 64-
Bit Editions of Windows Server 2003 and Windows XP
Professional | News Center" (http://news.microsoft.com/2005/
04/25/microsoft-raises-the-speed-limit-with-the-availability-of
-64-bit-editions-of-windows-server-2003-and-windows-xp-pr
ofessional/#sm.0000kw91cdgntf2kwp82ed9a9yn4e).
news.microsoft.com. Archived (https://web.archive.org/web/20
150225210214/http://news.microsoft.com/2005/04/25/micros
oft-raises-the-speed-limit-with-the-availability-of-64-bit-editio
ns-of-windows-server-2003-and-windows-xp-professional/#s
m.0000kw91cdgntf2kwp82ed9a9yn4e) from the original on
February 25, 2015. Retrieved August 14, 2016.
92. "A description of the x64-based versions of Windows Server
2003 and of Windows XP Professional x64 Edition" (https://sup
port.microsoft.com/en-gb/kb/888733). Microsoft Support.
Archived (https://web.archive.org/web/20160420135711/http
s://support.microsoft.com/en-gb/kb/888733) from the
original on April 20, 2016. Retrieved August 14, 2016.
93. "Windows Server 2003 SP1 Administration Tools Pack" (http
s://web.archive.org/web/20160827033240/http://www.micros
oft.com/en-us/download/details.aspx?id=3725). Microsoft
Download Center. Archived from the original (https://www.mic
rosoft.com/en-us/download/details.aspx?id=3725) on August
27, 2016. Retrieved August 14, 2016.
94. "/LARGEADDRESSAWARE (Handle Large Addresses)" (http://m
sdn.microsoft.com/en-us/library/wz223b1z(VS.80).aspx).
Visual Studio 2005 Documentation – Visual C++ – Linker
Options. Microsoft. Archived (https://web.archive.org/web/201
00701153209/http://msdn.microsoft.com/en-us/library/wz223
b1z%28VS.80%29.aspx) from the original on July 1, 2010.
Retrieved June 19, 2010. "The /LARGEADDRESSAWARE option
tells the linker that the application can handle addresses
larger than 2 gigabytes."
 95. Matt Pietrek (May 2006). "Everything You Need To Know To
Start Programming 64-Bit Windows Systems" (http://msdn.mic
rosoft.com/en-us/magazine/cc300794.aspx). Microsoft.
Archived (https://web.archive.org/web/20100620113139/htt
p://msdn.microsoft.com/en-us/magazine/cc300794.aspx) from
the original on June 20, 2010. Retrieved May 24, 2010.
96. Chris St. Amand (January 2006). "Making the Move to x64" (ht
tps://technet.microsoft.com/en-us/magazine/2006.01.insidem
scom.aspx). Microsoft. Archived (https://web.archive.org/web/
20100618130554/http://technet.microsoft.com/en-us/magazi
ne/2006.01.insidemscom.aspx) from the original on June 18,
2010. Retrieved May 24, 2010.
97. "Behind Windows x86-64's 44-bit Virtual Memory Addressing
Limit" (http://www.alex-ionescu.com/?p=50). Archived (http
s://web.archive.org/web/20081223145800/http://www.alex-io
nescu.com/?p=50) from the original on December 23, 2008.
Retrieved July 2, 2009.
98. "64-bit programming for Game Developers" (http://msdn.micr
osoft.com/en-us/library/ee418798(VS.85).aspx#Porting_to_64
bit). Archived (https://web.archive.org/web/20121111052133/
http://msdn.microsoft.com/en-us/library/ee418798%28VS.8
5%29.aspx#Porting_to_64bit) from the original on November
11, 2012. Retrieved August 21, 2013.
99. "Memory Limits for Windows Releases" (http://msdn.microsof
t.com/en-us/library/aa366778(VS.85).aspx). Microsoft.
Archived (https://web.archive.org/web/20100622125234/htt
p://msdn.microsoft.com/en-us/library/aa366778(VS.85).aspx)
from the original on June 22, 2010. Retrieved February 20,
2013.
100. "General Porting Guidelines" (https://docs.microsoft.com/en-u
s/windows/win32/winprog64/general-porting-guidelines).
Programming Guide for 64-bit Windows. Microsoft Docs.
Archived (https://web.archive.org/web/20210228011758/http
s://docs.microsoft.com/en-us/windows/win32/winprog64/gen
eral-porting-guidelines) from the original on February 28,
2021. Retrieved December 25, 2021.
101. "Driver history for Microsoft SQL Server" (https://docs.microso
ft.com/en-us/sql/connect/connect-history). Microsoft Docs.
Retrieved December 25, 2021.
102. "Microsoft OLE DB Provider for Jet and Jet ODBC driver are
available in 32-bit versions only" (https://docs.microsoft.com/
en-US/office/troubleshoot/access/jet-odbc-driver-available-32
-bit-version). Office Access. Microsoft Docs. KB957570.
Archived (https://web.archive.org/web/20220108071341/http
s://docs.microsoft.com/en-us/office/troubleshoot/access/jet-o
dbc-driver-available-32-bit-version) from the original on
January 8, 2022. Retrieved December 25, 2021.
103. Anand Lal Shimpi (May 21, 2013). "The Xbox One: Hardware
Analysis & Comparison to PlayStation 4" (http://www.anandte
ch.com/show/6972/xbox-one-hardware-compared-to-playstat
ion-4/2). Anandtech. Archived (https://web.archive.org/web/2
0130607031844/http://www.anandtech.com/show/6972/xbox-
one-hardware-compared-to-playstation-4/2) from the original
on June 7, 2013. Retrieved May 22, 2013.
104. "The Tech Spec Test: Xbox One Vs. PlayStation 4" (http://www.
gameinformer.com/b/news/archive/2013/05/21/the-tech-spec
-test-xbox-one-vs-playstation-4.aspx). Game Informer. May
21, 2013. Archived (https://web.archive.org/web/20130607180
640/http://www.gameinformer.com/b/news/archive/2013/05/
21/the-tech-spec-test-xbox-one-vs-playstation-4.aspx) from
the original on June 7, 2013. Retrieved May 22, 2013.
105. "What to expect from Sony 'PlayStation 5' launch in
November" (https://indianexpress.com/article/technology/ga
ming/sony-playstation-5-might-launch-on-november-13-6577
207/). The Indian Express. August 31, 2020. Archived (https://w
eb.archive.org/web/20200919053244/https://indianexpress.co
m/article/technology/gaming/sony-playstation-5-might-launc
h-on-november-13-6577207/) from the original on September
19, 2020. Retrieved September 14, 2020.
106. Cutress, Dr Ian. "Hot Chips 2020 Live Blog: Microsoft Xbox
Series X System Architecture (6:00pm PT)" (https://www.anand
tech.com/show/15994/hot-chips-2020-live-blog-microsoft-xb
ox-series-x-system-architecture-600pm-pt).
www.anandtech.com. Archived (https://web.archive.org/web/2
0200917190502/https://www.anandtech.com/show/15994/hot
-chips-2020-live-blog-microsoft-xbox-series-x-system-archite
cture-600pm-pt) from the original on September 17, 2020.
Retrieved September 14, 2020.
107. Hollister, Sean (November 12, 2021). "Steam Deck: Five big
things we learned from Valve's developer summit" (https://ww
w.theverge.com/22779252/steam-deck-things-we-learned-fro
m-valve-developer-summit). The Verge. Retrieved
November 12, 2021.
108. "ProcessorArchitecture Fields" (http://msdn.microsoft.com/en-
us/library/microsoft.build.utilities.processorarchitecture_fields.
aspx). Archived (https://web.archive.org/web/2015042819021
4/https://msdn.microsoft.com/en-us/library/microsoft.build.ut
ilities.processorarchitecture_fields.aspx) from the original on
April 28, 2015. Retrieved September 4, 2013.
109. "An example file from Linux 3.7.8 kernel source tree displaying
the usage of the term x86_64" (https://web.archive.org/web/2
0050923210216/http://lxr.linux.no/#linux+v3.7.8/arch/x86/con
figs/x86_64_defconfig). Archived from the original (http://lxr.li
nux.no/#linux+v3.7.8/arch/x86/configs/x86_64_defconfig) on
September 23, 2005. Retrieved February 17, 2013.
110. US 6877084 (https://worldwide.espacenet.com/textdoc?DB=E
PODOC&IDX=US6877084)
111. US 6889312 (https://worldwide.espacenet.com/textdoc?DB=E
PODOC&IDX=US6889312)
112. US 6732258 (https://worldwide.espacenet.com/textdoc?DB=E
PODOC&IDX=US6732258)
113. "Patent Cross License Agreement Between AMD and Intel" (htt
ps://web.archive.org/web/20070621084244/http://contracts.c
orporate.findlaw.com/agreements/amd/intel.license.2001.01.0
1.html). January 1, 2001. Archived from the original (http://con
tracts.corporate.findlaw.com/agreements/amd/intel.license.20
01.01.01.html) on June 21, 2007. Retrieved August 23, 2009.
114. "AMD Intel Settlement Agreement" (https://www.sec.gov/Arch
ives/edgar/data/2488/000119312509236705/dex101.htm).
Archived (https://web.archive.org/web/20170707043343/http
s://www.sec.gov/Archives/edgar/data/2488/000119312509236
705/dex101.htm) from the original on July 7, 2017. Retrieved
September 18, 2017.
115. Stephen Shankland and Jonathan E. Skillings (November 12,
2009). "Intel to pay AMD $1.25 billion in antitrust settlement"
(https://web.archive.org/web/20121108032512/http://news.cn
et.com/8301-1001_3-10396188-92.html). CNET. Archived from
the original (http://news.cnet.com/8301-1001_3-10396188-92.
html) on November 8, 2012. Retrieved April 24, 2012.
116. Smith, Ryan (November 12, 2009). "AMD and Intel Settle Their
Differences: AMD Gets To Go Fabless" (https://web.archive.or
g/web/20100513042947/http://www.anandtech.com/show/28
73). AnandTech. Archived from the original (http://www.anand
tech.com/show/2873) on May 13, 2010.

External links
AMD Developer Guides, Manuals & ISA Documents (https://developer.amd.com/resources/developer-guides-manuals/)
x86-64: Extending the x86 architecture to 64-bits (http://www.stanford.edu/class/ee380/Abstracts/O00927.html) – technical talk by
the architect of AMD64 (video archive (https://web.archive.org/web/20100813052749/http://stanford-online.stanford.edu/course
s/ee380/000927-ee380-100.asx)), and second talk by the same speaker (http://www.stanford.edu/class/ee380/Abstracts/040107.ht
 ml) (video archive (https://web.archive.org/web/20100813100133/http://stanford-online.stanford.edu/courses/ee380/040107-ee38
0-100.asx))
AMD's "Enhanced Virus Protection" (https://web.archive.org/web/20060623073619/http://www.xbitlabs.com/news/other/display/2
0041227094638.html)
Intel tweaks EM64T for full AMD64 compatibility (https://www.theregister.co.uk/2005/08/23/intel_fixes_em64t/)
Analyst: Intel Reverse-Engineered AMD64 (http://www.extremetech.com/extreme/56018-analyst-intel-reverseengineered-amd64)
Early report of differences between Intel IA32e and AMD64 (https://marc.info/?l=linux-kernel&m=107766481408468&w=2)
Porting to 64-bit GNU/Linux Systems (http://gcc.gnu.org/pub/gcc/summit/2003/Porting%20to%2064%20bit.pdf), by Andreas
Jaeger from GCC Summit 2003. An excellent paper explaining almost all practical aspects for a transition from 32-bit to 64-bit.
Intel 64 Architecture (http://www.intel.com/technology/intel64/index.htm)
Intel Software Network: "64 bits" (https://web.archive.org/web/20110403005033/http://software.intel.com/en-us/articles/all-about
-64-bits/)
TurboIRC.COM tutorials, including examples of how to of enter protected and long mode the raw way from DOS (https://web.archi
ve.org/web/20170222181811/http://www.turboirc.com/asm/)
Seven Steps of Migrating a Program to a 64-bit System (https://web.archive.org/web/20100123010204/http://software.intel.com/e
n-us/articles/seven-steps-of-migrating-a-program-to-a-64-bit-system/)
Memory Limits for Windows Releases (http://msdn.microsoft.com/en-us/library/aa366778%28VS.85%29.aspx)

Retrieved from "https://en.wikipedia.org/w/index.php?title=X86-64&oldid=1119352354"