Verification II

Accelerating Systems with
Programmable Logic Components

Lecture 09 Verification II
Basic concepts and methods of Verification
1DT109 ASPLOC
2022 VT1-VT2
Yuan Yao, yuan.yao@it.uu.se
2022-09-19 1
Verification technologies
• Linting
• Randomization
• Assertion
• Delta delay
• Functional coverage
2022-09-19 2
Linting
• “Lint” comes from the name of a UNIX utility that parses C
program and reports questionable uses and problems.
• A static checking technology requiring no stimulus
• Fast but can report false negatives
int my_func (addr_ptr, ratio)
int *addr_ptr;
1. Argument “ratio” unused
float ratio; {
Lint 2. addr_ptr may be used
return (*addr_ptr)++; before being set
}
3. Arg. 1 used inconsistently
main () {
4. my_func returns value
int my_addr;
which is always ignored
my_func (my_addr);
2022-09-19 } 3
Linting
• Getting the best out of Linting
• Carefully filter error and warning messages in Vivado
• Naming conventions can help output filtering
• Do not turn off checks/issue reporting
• Link code as it is written
• Enforce coding guidelines
2022-09-19 4
Linting
always_ff @ (a, b)
if (b)
c <= a;
2022-09-19 5
Linting
always_ff @ (a, b)
if (b)
c <= a;
2022-09-19 6
Linting
always_ff @ (a, b)
if (b)
c <= a;
always_comb
if (b)
c <= a;
2022-09-19 7
Linting
always_ff @ (a, b)
if (b)
c <= a;
always_comb
if (b)
c <= a;
2022-09-19 8
Linting
• Naming conventions can help output filtering Linting was not integrated
• Do not turn off checks/issue reporting into IDE as it is
• Link code as it is written nowadays.
However, Linting tool was
• Enforce coding guidelines available such as NLint.
always_ff @ (a, b)
if (b)
c <= a;
always_comb
if (b)
c <= a;
2022-09-19 9
Randomization – $random, $urandom
• Randomization ≠ aimless
• Good aim = clear context to exert potential bugs
• Randomization use $random, $urandom
• Both returns 32-bit random number
• $random returns signed number (-231 to 231-1)
• $urandom returns unsigned number (0 to 232-1)
• You can control the range of randomization using
• variable = $urandom_range( int unsigned maxval, int unsigned minval = 0 );
• a = $urandom_range(30,20);
• b = $urandom_range(20);
There is no $random_range
•2022-09-19 10
• b = $urandom_range(20);
•2022-09-19 Take “0” as min
11
• b = $urandom_range(20); How to generate
•2022-09-19 Take “0” as min negative using
urandom_range? 12
Hard to use within context and OOP.

• $random returns signed number (-2 to 2 -1)
31 31

• b = $urandom_range(20); How to generate
•2022-09-19 Take “0” as min negative using
urandom_range? 13
module demo_8;
initial begin
repeat (10)
$display("a=%2d, b=%2d, c=%2d",
$urandom_range(30, 20),
$urandom_range(20),
$signed($urandom_range(30, 20))-25);
end
endmodule
2022-09-19 14
module demo_8;
initial begin
repeat (10)
$display("a=%2d, b=%2d, c=%2d",
$urandom_range(30, 20),
$urandom_range(20),
$signed($urandom_range(30, 20))-25);
end
endmodule Must convert to
signed integer
here!
2022-09-19 15
Randomization – rand/randc
• Variables declared with the rand/randc keyword are standard
random variables. Their values are uniformly distributed over
their range.
• rand bit [3:0] addr; // Uniformly distributed among [4’b0000, 4’b1111]
• randc bit [3:0] addr; // Uniformly distributed among [4’b0000, 4’b1111]
addr doesn’t repeat until every possible value
has been assigned.
• Can be used together with constraints, which controls the
range of a rand variable.
• Can be used in randomized class object
• Easy to use within verification context.
2022-09-19 16
class packet;
rand bit [2:0] addr1;
randc bit [2:0] addr2;
endclass
module demo_9;
initial begin
packet pkt;
pkt = new();
repeat (8) begin
pkt.randomize();
$display(“ addr1 = %0d \t
addr2 = %0d ",
pkt.addr1,
pkt.addr2);
end
end
endmodule
2022-09-19 17
class packet;
endclass
Refresh the value of
module demo_9; addr1 and addr2
initial begin each time calling the
packet pkt; randomize() function
pkt = new();
repeat (8) begin
pkt.randomize();
addr2 = %0d ",
pkt.addr1,
pkt.addr2);
end
end
endmodule
2022-09-19 18
class packet;
endclass
initial begin each time calling the
packet pkt; randomize() function
pkt = new();
repeat (8) begin
pkt.randomize();
addr2 = %0d ",
pkt.addr1,
Twice of value
pkt.addr2);
“2” and “5”
end
end
endmodule
2022-09-19 19
class packet;
endclass
each time calling the No repeated
initial begin
randomize() function value.
packet pkt;
pkt = new();
repeat (8) begin
pkt.randomize();
addr2 = %0d ",
pkt.addr1,
Twice of value
pkt.addr2);
“2” and “5”
end
end
endmodule
2022-09-19 20
Randomization – rand/randc in Class
typedef enum {STACK=1, HEAP=2, WHOLE=3} region;
module demo_10;
class random_memory_loader; sparse_memory mem = new();
region mtype; random_memory_loader loader = new();
rand bit [63:0] addr;
rand logic [7:0] data;
initial begin
constraint addr_con { region mtype = mtype.first();
mtype == STACK -> { for (int i = 1; i <= mtype.num(); i++) begin
addr >= 64'h8000_0000_0000_0000; loader.mtype = mtype;
addr <= 64'hffff_ffff_ffff_ffff; repeat (10) begin
} loader.randomize();
mtype == HEAP -> { mem.write(loader.addr, loader.data);
addr >= 64'h0000_0000_0000_0000; loader.display();
addr < 64'h8000_0000_0000_0000;
end
}
mtype == WHOLE -> { mem.display();
addr >= 64'h0000_0000_0000_0000; mtype = mtype.next();
addr <= 64'hffff_ffff_ffff_ffff; end
} end
} endmodule
2022-09-19 21
endclass: random_memory_loader
module demo_10;
initial begin
addr < 64'h8000_0000_0000_0000;
end
}
} end
} endmodule
2022-09-19 22
module demo_10;
initial begin
addr < 64'h8000_0000_0000_0000;
end
}
} end
} endmodule
2022-09-19 23
module demo_10;
initial begin
addr < 64'h8000_0000_0000_0000;
end
}
} end
} endmodule
2022-09-19 24
module demo_10;
initial begin
addr < 64'h8000_0000_0000_0000;
end
}
} end
} endmodule
2022-09-19 25
module demo_10;
initial begin
addr < 64'h8000_0000_0000_0000;
end
}
} end
} endmodule
2022-09-19 26
module demo_10;
initial begin
addr < 64'h8000_0000_0000_0000;
end
}
} end
} endmodule
2022-09-19 27
module demo_10;
initial begin
addr < 64'h8000_0000_0000_0000;
end
}
} end
} endmodule
2022-09-19 28
module demo_10;
initial begin
addr < 64'h8000_0000_0000_0000;
end
}
} end
} endmodule
2022-09-19 29
module demo_10;
initial begin
addr < 64'h8000_0000_0000_0000;
end
}
} end
} endmodule
2022-09-19 30
Assertion
• Assertions are primarily used to validate the behavior
of a design.
• Assertions can be checked dynamically by simulation
• Or statically by a separate property checker tool.
• Such as formal verification tool (next lecture)
• There are two kinds of assertions in SystemVerilog
• Immediate assertion (assert)
• Check the design’s immediate behavior
• Concurrent assertion (assert property)
2022-09-19
• Check the design’s temporal behavior 31
Immediate assertions
• An immediate assertion is a module demo_11;
statement that something in the
design must be true. bit [3:0] A = 4'b0000;
• Conceptually like an if-statement bit [3:0] B = 4'b0000;
logic [3:0] C = 4'b000x;
• Difference with if-statement:
immediate assertion can issue initial begin
$fatal, $error, $warning when if (A == B)
failed. $display("A == B");
• If the conditional expression of the else
immediate assert evaluates to X, Z $display("A != B");
or 0, then the assertion fails, and
the simulator writes an error assert (A == C);
message. end
2022-09-19 32
Example – Immediate assertions
• All the following immediate assertions are valid.
assert (A == C)
$display ("OK. A equals C");
else
$warning ("It's gone wrong");
assert ((A == B) && (A == C))

else
$error ("It's gone wrong");
assert (A == C)
else
$fatal ("It's gone wrong");
2022-09-19 33
assert (A == C) An immediate assertion with both a pass
$display ("OK. A equals C"); statement and a failure statement.
else $warning -> does not terminate
$warning ("It's gone wrong"); simulation, can be suppressed.
assert ((A == B) && (A == C))

else
assert (A == C)
else
2022-09-19 34
assert ((A == B) && (A == C))

else
assert (A == C)
else
2022-09-19 35
An immediate assertion with a failure

assert ((A == B) && (A == C))
statement only.
else
$error -> does not terminate simulation,
cannot be suppressed.
assert (A == C)
else
2022-09-19 36

assert ((A == B) && (A == C))
statement only.
else
assert (A == C)
else
2022-09-19 37

assert ((A == B) && (A == C))
statement only.
else
assert (A == C)
statement only.
else
$fatal -> terminates simulation when fails.
2022-09-19 38

assert ((A == B) && (A == C))
statement only.
else
assert (A == C)
statement only.
else
2022-09-19 39

assert ((A == B) && (A == C))
statement only.
else
assert (A == C)
statement only.
else
2022-09-19 40
Concurrent assertions
• Concurrent assertions are used to check temporal
behavior of a logic.
• To use concurrent assertions:
1. Setup the property of the logic that you want to
monitor/check via the property structure
2. Define behaviors of interests (either immediate or temporal)
within the property structure
3. Monitor the behaviors of interests via the assert keyword
2022-09-19 41
Example – Concurrent assertions
• Step 1 – Setup the property of the logic that you want to
monitor/check via the property structure.
1. At each rising clk edge

module dff ( input wire d,
input wire rst, a) Output q pulled down
input wire clk, to 1’b0 if rst is 1’b0.
output reg q); b) Otherwise, output q
always_ff @ (posedge clk)
if (!rst) follows the value of
q <= 1’b0; input d.
else
q <= d;
2. The new value can only be
endmodule observed after the rising
clock edge passes.
2022-09-19 42
• Step 1 – Setup the property of the logic that you want to
monitor/check via the property structure.
1. At each rising clk edge

module dff ( input wire d,
input wire rst, a) Output q pulled down
input wire clk, to 1’b0 if rst is 1’b0.
output reg q); What properties
does this piece b) Otherwise, output q
if (!rst) of logic have? follows the value of
q <= 1’b0; input d.
else
q <= d;
2. The new value can only be
endmodule observed after the rising
clock edge passes.
2022-09-19 43
always_ff @ (posedge clk) property p_1a; Implication
if (!rst) @ (posedge clk) • s1 |-> s2
q <= 1’b0; !rst |=> q == 1’b0; • If s1 is false, the
else endproperty implication returns
q <= d; // demo_12 true without
evaluating s2.
property p_1b_v1;
• If s1 is true, the
1. At each rising clk edge implication evaluates
@ (posedge clk) s2 immediately.
a) Output q pulled down to d |=> q;
1’b0 if rst is 1’b0. • If s2 is true, the
endproperty implication returns
b) Otherwise, output q // demo_12 true. Otherwise,
follows the value of false.
input d. property p_1b_v2; • s1 |=> s2
2. The new value can only be @ (posedge clk) • When s1 is true, the
observed after the rising d |-> ##1 q; implication evaluates
endproperty s2 in the next clock
clock edge passes. cycle.
2022-09-19 // demo_12 44
Example – Implication evaluation

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 45

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 46

if (!rst) s1 |-> s2:
q <= 1’b0;
else
q <= d;
2022-09-19 47

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else
q <= d;
2022-09-19 48

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else
q <= d;
2022-09-19 49

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else
q <= d; s1 |=> s2:
2022-09-19 50

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else
q <= d; s1 |=> s2: s1
2022-09-19 51

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else
q <= d; s1 |=> s2: s1
s2
2022-09-19 52

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else
q <= d; s1 |=> s2: s1
s2
2022-09-19 53

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else
q <= d; s1 |=> s2: s1
s2
s1 |-> ## 1 s2:
2022-09-19 54

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else
q <= d; s1 |=> s2: s1
s2
s1 |-> ## 1 s2: s1
2022-09-19 55

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else
q <= d; s1 |=> s2: s1
s2
s1 |-> ## 1 s2: s1
2022-09-19 s2 56

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else property p_1a;
q <= d; s1 |=> s2: s1 @ (posedge clk)
s2 !rst |=> q == 1’b0;
endproperty
s1 |-> ## 1 s2: s1
2022-09-19 s2 57

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else property p_1a;
s2 !rst |=> q == 1’b0;
endproperty
s1 |-> ## 1 s2: s1
2022-09-19 s2 58

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else property p_1a;
q <= d; rst == 1’b1,
s1 |=> s2: s1 @ (posedge clk)
!rst is false
s2 !rst |=> q == 1’b0;
q == 1’b0 does not get
endproperty
evaluated, return true.
s1 |-> ## 1 s2: s1
2022-09-19 s2 59

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else property p_1a;
s2 !rst |=> q == 1’b0;
endproperty
s1 |-> ## 1 s2: s1
2022-09-19 s2 60

if (!rst) s1 |-> s2: s1
q <= 1’b0; s2
else property p_1a; rst == 1’b0,
q <= d; s1 |=> s2: s1 @ (posedge clk) !rst is true
s2 !rst |=> q == 1’b0; q==1’b0 is evaluated.
endproperty Property holds.
s1 |-> ## 1 s2: s1 (q has value 1’b0)
2022-09-19 s2 61
always_ff @ (posedge clk) property p_1a_f;

if (!rst) s1 |-> s2: s1 @ (posedge clk)
q <= 1’b0; s2 !rst |-> q == 1’b0;
else endproperty
q <= d; s1 |=> s2: s1
s2
s1 |-> ## 1 s2: s1
2022-09-19 s2 62
always_ff @ (posedge clk) property p_1a_f; rst == 1’b0,

if (!rst) s1 |-> s2: s1 @ (posedge clk) !rst is true
q <= 1’b0; s2 !rst |-> q == 1’b0; q==1’b0 is evaluated.
else endproperty Property fails.
q <= d; s1 |=> s2: s1 (q has value 1’b1)
s2
s1 |-> ## 1 s2: s1
2022-09-19 s2 63

s2
s1 |-> ## 1 s2: s1
2022-09-19 s2 64

s2
s1 |-> ## 1 s2: s1
2022-09-19 s2 65

s2
s1 |-> ## 1 s2: s1
2022-09-19 s2 66
always_ff @ (posedge clk) property p_1b_v1;

if (!rst) @ (posedge clk)
q <= 1’b0; d |=> q;
else endproperty
q <= d;
property p_1b_v2;
@ (posedge clk)
d |-> ##1 q;
2022-09-19 endproperty 67

if (!rst) @ (posedge clk) Are we safe?
q <= 1’b0; d |=> q;
else endproperty
q <= d;
property p_1b_v2;
@ (posedge clk)
d |-> ##1 q;

q <= 1’b0; d |=> q;
else endproperty
q <= d;
property p_1b_v2;
@ (posedge clk)
d |-> ##1 q;

q <= 1’b0; d |=> q;
else endproperty
q <= d;
property p_1b_v2;
@ (posedge clk)
d |-> ##1 q;

q <= 1’b0; d |=> q;
else endproperty
q <= d; No!
property p_1b_v2; When rst is 1’b0,
@ (posedge clk)
d |-> ##1 q; output q does not
2022-09-19 endproperty follow input d 71

q <= 1’b0; d |=> q;
else endproperty
q <= d; No!
@ (posedge clk)

q <= 1’b0; d |=> q;
else endproperty
q <= d; No!
@ (posedge clk)

q <= 1’b0; d |=> q;
else endproperty
q <= d; No!
@ (posedge clk)

q <= 1’b0; d |=> q;
else endproperty
q <= d; No!
@ (posedge clk)

q <= 1’b0; d |=> q;
else endproperty
q <= d; No!
@ (posedge clk)

q <= 1’b0; d |=> q;
else endproperty
q <= d; No!
@ (posedge clk)

q <= 1’b0; d |=> q;
else endproperty
q <= d; No!
@ (posedge clk)

q <= 1’b0; d |=> q;
else endproperty
q <= d; No!
@ (posedge clk)

q <= 1’b0; d |=> q;
else endproperty
q <= d; No!
@ (posedge clk)
Disable the property when reset is on!

q <= 1’b0; d |=> q;
else endproperty
q <= d; No!
@ (posedge clk)

if (!rst) @ (posedge clk) disable iff (!rst)
q <= 1’b0; d |=> q;
else endproperty
q <= d;
property p_1b_v2;
@ (posedge clk) disable iff (!rst)
d |-> ##1 q;

q <= 1’b0; d |=> q;
else endproperty
q <= d;
property p_1b_v2;
d |-> ##1 q;

q <= 1’b0; d |=> q;
else endproperty
q <= d;
property p_1b_v2;
d |-> ##1 q;

if (!rst) @ (posedge clk) disable iff (!rst) Are we safe?
q <= 1’b0; d |=> q;
else endproperty
q <= d;
property p_1b_v2;
d |-> ##1 q;

if (!rst) @ (posedge clk) disable iff (!rst) Are we safe?
q <= 1’b0; d |=> q;
else endproperty
q <= d; Yes!
property p_1b_v2; Disable the property
d |-> ##1 q; if-and-only-if when rst
2022-09-19 endproperty is 1’b0. 86

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 87
initial begin //demo_13

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 88

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 89

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 90

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 91

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 92

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 93

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 94

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 95

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 96

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 97

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 98

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 99

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 100

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 101

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 102

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 103

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 104

d = 1'b1;
end

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 105

d = 1'b1;
end
clk

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 106

d = 1'b1;
end
clk

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 107

d = 1'b1;
end
clk

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 108

d = 1'b1;
end
clk

if (!rst)
q <= 1’b0;
else
q <= d;
2022-09-19 109

d = 1'b1;
end
clk

if (!rst) D
q <= 1’b0;
else
q <= d;
2022-09-19 110

d = 1'b1;
end
clk

if (!rst) D
q <= 1’b0;
else
q <= d;
2022-09-19 111

d = 1'b1;
end
clk

if (!rst) D
q <= 1’b0;
else
q <= d;
2022-09-19 112

d = 1'b1;
end
clk

if (!rst) D
q <= 1’b0;
else
q <= d;
2022-09-19 113

d = 1'b1;
end
clk

if (!rst) D
q <= 1’b0;
else
q <= d;
2022-09-19 114

d = 1'b1;
end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
2022-09-19 115

d = 1'b1;
end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 116

d = 1'b1;
end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 117

d = 1'b1;
end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 118

d = 1'b1;
end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 119
initial begin //demo_13 initial begin //demo_13

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 120

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 121

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 122

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 123

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 124

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 125

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 126

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 127

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 128

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 129

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 130

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 131

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 132

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 133

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 134

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 135

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 136

d = 1'b1; d <= 1'b1;
end end
clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 137

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 138

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 139

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 140

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 141

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 142

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 143

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 144

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 145

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D D
q <= 1’b0;
else
D
q <= d;
Q
2022-09-19 146

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D D
q <= 1’b0;
else
D D
q <= d;
Q
2022-09-19 147

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D D
q <= 1’b0;
else
D D
q <= d;
Q Q
2022-09-19 148

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D D
q <= 1’b0;
else
D D
q <= d;
Q Q
2022-09-19 149

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D D
q <= 1’b0;
else
D D
q <= d;
Q Q
2022-09-19 150

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D D
q <= 1’b0;
else
D D
q <= d;
Q Q
2022-09-19 151

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D D
q <= 1’b0;
else
D D
q <= d;
Q Q
2022-09-19 152

d = 1'b1; d <= 1'b1;
end end
clk clk

if (!rst) D D
q <= 1’b0;
else
D D
q <= d;
Q Q
2022-09-19 153
Blocking and non-blocking assignments

d = 1'b1; d <= 1'b1;
end end
happen at different clk

instancesclk
across clock
edge in a seq logic.
if (!rst) D D
q <= 1’b0;
else
D D
q <= d;
Q Q
2022-09-19 154

if (!rst)
q <= 0;
else
q <= d*d;
2022-09-19 155

d = 5;
end

if (!rst)
q <= 0;
else
q <= d*d;
2022-09-19 156

d = 5; d <= 5;
end end

if (!rst)
q <= 0;
else
q <= d*d;
2022-09-19 157

d = 5; d <= 5;
end end

if (!rst)
q <= 0;
else
q <= d*d;
2022-09-19 158

d = 5; d <= 5;
Combi logic happens immediately.

end end

if (!rst)
q <= 0;
else
q <= d*d;
2022-09-19 159
Delta delay
• Verilog/SystemVerilog simulator is event-based.
• Way faster than time-based simulation. Especially efficient in
simulating large scale design.
• The simulator does not increment time by a basic time unit, timestep
or time increment.
• Regardless of the simulation resolution, the simulation advances
time as far as necessary, in a single step, to the next point in time
where there is useful work to do.
Time advances Same time
w.r.t. resolution Different delta
Head Tail
evaluate Event queue
2022-09-19 160
Simulation time increase
Delta delay
• Verilog/SystemVerilog simulator is event-based.
• Way faster than time-based simulation. Especially efficient in
simulating large scale design.
• The simulator does not increment time by a basic time unit, timestep
or time increment.
Singal change is the driving force.
• Regardless of the simulation resolution, the simulation advances
time as far as necessary, in a single step, to the next point in time
where there is useful work to do.
Time advances Same time
w.r.t. resolution Different delta
Head Tail
evaluate Event queue
2022-09-19 161
Simulation time increase
Example – Delta delay
IN: 1 A: 0
C: 0
B: 1
1
2022-09-19 162
Time Delta Event

IN: 1 A: 0
C: 0
B: 1
1
2022-09-19 163
Time Delta Event

IN: 1→0 A: 0 0 ns 1 IN: 1 → 0
C: 0
eval: INVERTER
B: 1
1
2022-09-19 164
Time Delta Event

IN: 1→0 A: 0→1 0 ns 1 IN: 1 → 0
C: 0
eval: INVERTER
2 A: 0 → 1
B: 1 eval: NAND, AND
1
2022-09-19 165
Time Delta Event

IN: 1→0 A: 0→1 0 ns 1 IN: 1 → 0
C: 0
eval: INVERTER
2 A: 0 → 1
B: 1→0 eval: NAND, AND
1 3 B: 1 → 0
2022-09-19 166
Time Delta Event

IN: 1→0 A: 0→1 0 ns 1 IN: 1 → 0
C: 0
eval: INVERTER
2 A: 0 → 1
1 3 B: 1 → 0
What is the value of C

when the simulator
evaluate the AND gate?
2022-09-19 167
Time Delta Event

IN: 1→0 A: 0→1 0 ns 1 IN: 1 → 0
C: 0→1
eval: INVERTER
2 A: 0 → 1
1 3 B: 1 → 0
C: 0 → 1 (A:1, B:1)
(use the old value of B)
eval: AND
2022-09-19 168
Time Delta Event

IN: 1→0 A: 0→1 0 ns 1 IN: 1 → 0
C: 0→1
eval: INVERTER
2 A: 0 → 1
1 3 B: 1 → 0
C: 0 → 1 (A:1, B:1)
eval: AND
Why is that?
2022-09-19 169
Time Delta Event

IN: 1→0 A: 0→1 0 ns 1 IN: 1 → 0
C: 0→1
eval: INVERTER
2 A: 0 → 1
1 3 B: 1 → 0
C: 0 → 1 (A:1, B:1)
eval: AND
Enable parallel always
blocks!
The second block is
evaluated twice! Why is that?
2022-09-19 170
Time Delta Event

IN: 1→0 A: 0→1 0 ns 1 IN: 1 → 0
C: 0→1
eval: INVERTER
2 A: 0 → 1
1 3 B: 1 → 0
always @ (IN) C: 0 → 1 (A:1, B:1)
A = ~IN; (use the old value of B)
eval: AND
Enable parallel always always @ (A, B)
blocks! C = A & B;
The second block is
evaluated twice! always @ (A) Why is that?
2022-09-19 B = A ~& 1’b1; 171
Time Delta Event

IN: 1→0 A: 0→1 0 ns 1 IN: 1 → 0
C: 0→1→0
eval: INVERTER
2 A: 0 → 1
1 3 B: 1 → 0
always @ (IN) C: 0 → 1 (A:1, B:1)
A = ~IN; (use the old value of B)
eval: AND
Enable parallel always always @ (A, B) 4 C: 1 → 0 (A:1, B:0)
blocks! C = A & B; (use the new value of B)
The second block is
evaluated twice! always @ (A)
2022-09-19 B = A ~& 1’b1; 172
Functional coverage
• Functional coverage is a measure of what functionalities or
features of the design have been exercised by the test.
• This can work together with constrained random verification
(CRV) to evaluate how well/thorough the design has been
tested.
• N.B. Function coverage can not help detecting unimplemented
or omitted features in the design.
• It can only help testing what has been implemented.
2022-09-19 173
Functional coverage
• Functional coverage samples variables class random_memory_loader;
of interest in the testbench and analyze region mtype;
if they have reached certain sets of rand logic [7:0] data;
values. /****************************/
• Variables of interest are mentioned as function new();
cov_grp = new();
a coverpoint. endfunction: new
• Coverpoints are put together in a /****************************/
covergroup cov_grp;
covergroup block. coverpoint data {
• Bins are to be “hit/covered” when the bins data_low_end = {0};
bins data_high_end = {255};
variable reaches the corresponding bins data_low = {[0 : 127]};
values or value ranges. bins data_high = {[128 : 255]};
• If data is randomized as 0, then bin }
coverpoint mtype {
“data_low_end” is hit 1 time. bins mtype_bin [] = {[mtype.first : mtype.last]};
• If data is randomized between [0:127], }
endgroup
then bin data_low is hit 1 time. endclass: random_memory_loader
2022-09-19 174
Functional coverage
• Functional coverage samples variables class random_memory_loader;
of interest in the testbench and analyze region mtype;
if they have reached certain sets of rand logic [7:0] data;
values. /****************************/ Covergroup need
• Variables of interest are mentioned as function new();
cov_grp = new();
to be initialized
a coverpoint. endfunction: new
before use.
• Coverpoints are put together in a /****************************/
covergroup cov_grp;
covergroup block. coverpoint data {
• Bins are to be “hit/covered” when the bins data_low_end = {0};
variable reaches the corresponding bins data_low = {[0 : 127]};
values or value ranges. bins data_high = {[128 : 255]};
• If data is randomized as 0, then bin }
coverpoint mtype {
“data_low_end” is hit 1 time. bins mtype_bin [] = {[mtype.first : mtype.last]};
• If data is randomized between [0:127], }
endgroup
then bin data_low is hit 1 time. endclass: random_memory_loader
2022-09-19 175
Example – Functional coverage
class random_memory_loader;
region mtype; module demo_10;
rand bit [63:0] addr; sparse_memory mem = new();
rand logic [7:0] data; random_memory_loader loader = new();
/****************************/
function new(); initial begin
cov_grp = new(); region mtype = mtype.first();
endfunction: new for (int i = 1; i <= mtype.num(); i++) begin
/****************************/ loader.mtype = mtype;
covergroup cov_grp; repeat(10) begin
coverpoint data { loader.randomize();
bins data_low_end = {0}; loader.cov_grp.sample();
bins data_high_end = {255}; mem.write(loader.addr, loader.data);
bins data_low = {[0 : 127]}; loader.display();
bins data_high = {[128 : 255]}; end
} mem.display();
coverpoint mtype { mtype = mtype.next();
bins mtype_bin [] = {[mtype.first : mtype.last]}; end
} end
endgroup endmodule
2022-09-19 176
class random_memory_loader;
region mtype; module demo_10;
rand bit [63:0] addr; sparse_memory mem = new();
rand logic [7:0] data; random_memory_loader loader = new();
/****************************/
function new(); initial begin
cov_grp = new(); region mtype = mtype.first();
endfunction: new for (int i = 1; i <= mtype.num(); i++) begin
/****************************/ loader.mtype = mtype;
covergroup cov_grp; repeat(10) begin
coverpoint data { loader.randomize();
bins data_low_end = {0}; loader.cov_grp.sample();
bins data_high_end = {255}; mem.write(loader.addr, loader.data);
bins data_low = {[0 : 127]}; loader.display();
bins data_high = {[128 : 255]}; end Use of covergroup is easy.
} mem.display(); Each time when a random
coverpoint mtype { mtype = mtype.next(); object is randomized, call
bins mtype_bin [] = {[mtype.first : mtype.last]}; end the sample() function of a
} end
endgroup endmodule
covergroup to do variable
2022-09-19
statistics. 177
• After simulation is done, Vivado can report statistics for the
declared covergroup in html table format.
• All the statistics will be saved in the folder “xsim.covdb” under the
simulation repository “verification_1_demo.sim”.
• To generate the html table, you need to use the “xcrg” command in
the TCL command line to interpret the statistics.
• xcrg -report_format html -dir
E:/VivadoProject/ASPLOC/verification_1_demo/verification_1_demo.sim/si
m_1/behav/xsim/xsim.covdb/
• The generated html table is called “dashboard.html”, which is by
default created in
“..\AppData\Roaming\Xilinx\Vivado\xcrg_report”
in Win10.
2022-09-19 178
covergroup cov_grp;
coverpoint data {
bins data_low_end = {0};
bins data_low = {[0 : 127]};
bins data_high = {[128 : 255]};
}
coverpoint mtype {
bins mtype_bin [] = {[mtype.first : mtype.last]};
}
endgroup
repeat(10) begin
loader.randomize();
loader.cov_grp.sample();
mem.write(loader.addr, loader.data);
loader.display();
end
2022-09-19 179
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
bins data_high = {[128 : 255]};
}
coverpoint mtype {
}
endgroup
repeat(10) begin
loader.randomize();
loader.display();
end
2022-09-19 180
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
bins data_high = {[128 : 255]};
}
coverpoint mtype {
}
endgroup
repeat(10) begin
loader.randomize();
loader.display();
end
2022-09-19 181
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
bins data_high = {[128 : 255]};
}
coverpoint mtype {
30 samples
}
endgroup
repeat(10) begin
loader.randomize();
loader.display();
end
2022-09-19 182
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
bins data_high = {[128 : 255]}; None hits here
}
coverpoint mtype {
30 samples
}
endgroup
repeat(10) begin
loader.randomize();
loader.display();
end
2022-09-19 183
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
}
coverpoint mtype {
30 samples
}
endgroup
repeat(10) begin
loader.randomize();
loader.display();
end
2022-09-19 184
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
}
coverpoint mtype {
30 samples
}
endgroup
repeat(10) begin
loader.randomize();
loader.display();
end 30 samples
2022-09-19 185
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
}
coverpoint mtype {
30 samples
}
endgroup
repeat(10) begin
loader.randomize();
mem.write(loader.addr, loader.data); Evenly hits.
loader.display();
end 30 samples
2022-09-19 186
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
bins data_high = {[128 : 255]};
}
coverpoint mtype {
}
endgroup
repeat(100) begin
loader.randomize();
loader.display();
end
2022-09-19 187
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
bins data_high = {[128 : 255]};
}
coverpoint mtype {
}
endgroup
repeat(100) begin
loader.randomize();
loader.display();
end
2022-09-19 188
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
bins data_high = {[128 : 255]};
}
coverpoint mtype {
}
endgroup
repeat(100) begin
loader.randomize();
loader.display();
end
2022-09-19 189
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
bins data_high = {[128 : 255]};
}
coverpoint mtype { 300 samples
}
endgroup
repeat(100) begin
loader.randomize();
loader.display();
end
2022-09-19 190
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]}; None hits here
bins data_high = {[128 : 255]};
}
}
endgroup
repeat(100) begin
loader.randomize();
loader.display();
end
2022-09-19 191
covergroup cov_grp;
coverpoint data {
bins data_high = {[128 : 255]};
}
}
endgroup
repeat(100) begin
loader.randomize();
loader.display();
end
2022-09-19 192
covergroup cov_grp;
coverpoint data {
bins data_high = {[128 : 255]};
}
}
endgroup
repeat(100) begin
loader.randomize();
loader.display(); 300 samples
end
2022-09-19 193
covergroup cov_grp;
coverpoint data {
bins data_high = {[128 : 255]};
}
}
endgroup
repeat(100) begin
loader.randomize();
loader.cov_grp.sample(); Evenly hits.
end
2022-09-19 194
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
bins data_high = {[128 : 255]};
}
coverpoint mtype {
}
endgroup
repeat(1000) begin
loader.randomize();
loader.display();
end
2022-09-19 195
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
bins data_high = {[128 : 255]};
}
coverpoint mtype {
}
endgroup
repeat(1000) begin
loader.randomize();
loader.display();
end
2022-09-19 196
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
bins data_high = {[128 : 255]};
}
coverpoint mtype {
}
endgroup
repeat(1000) begin
loader.randomize();
loader.display();
end
2022-09-19 197
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]};
bins data_high = {[128 : 255]};
} 3000 samples
coverpoint mtype {
}
endgroup
repeat(1000) begin
loader.randomize();
loader.display();
end
2022-09-19 198
covergroup cov_grp;
coverpoint data {
bins data_low = {[0 : 127]}; All hits, but not
bins data_high = {[128 : 255]}; evenly.
} 3000 samples
coverpoint mtype {
}
endgroup
repeat(1000) begin
loader.randomize();
loader.display();
end
2022-09-19 199
covergroup cov_grp;
coverpoint data {
} 3000 samples
coverpoint mtype {
}
endgroup
repeat(1000) begin
loader.randomize();
loader.display();
end
2022-09-19 200
covergroup cov_grp;
coverpoint data {
} 3000 samples
coverpoint mtype {
}
endgroup
repeat(1000) begin
loader.randomize();
end
2022-09-19 201
covergroup cov_grp;
coverpoint data {
} 3000 samples
coverpoint mtype {
}
endgroup
repeat(1000) begin
loader.randomize();
end
2022-09-19 202
covergroup cov_grp;
coverpoint data {
}
How to reach the conner cases faster?

3000 samples
coverpoint mtype {
}
endgroup
repeat(1000) begin
loader.randomize();
end
2022-09-19 203
Monitor FSM state transition using functional coverage
2022-09-19 204
module tb;
reg car_sensor, clk, n_rst;

wire [2:0] light_1, light_2;
traffic DUT(car_sensor, clk, n_rst, light_1, light_2);
localparam
S_1 = 4'b0001,
S_2 = 4'b0010,
S_3 = 4'b0100,
S_4 = 4'b1000;
covergroup cov @ (posedge clk);

coverpoint traffic.cur_state {
bins S_1_2 = (S_1 => S_2);
bins S_2_3 = (S_2 => S_3);
bins S_3_4 = (S_3 => S_4);
bins S_4_1 = (S_4 => S_1);
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
bins S_4_3 = (S_4 => S_3);
}
2022-09-19
endgroup 205
cov cov_fsm = new();
• Functional coverage can be used to track module tb;
variable transition, too. reg car_sensor, clk, n_rst;
localparam
S_1 = 4'b0001,
S_2 = 4'b0010,
S_3 = 4'b0100,
S_4 = 4'b1000;

bins S_1_2 = (S_1 => S_2);
bins S_2_3 = (S_2 => S_3);
bins S_3_4 = (S_3 => S_4);
bins S_4_1 = (S_4 => S_1);
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
bins S_4_3 = (S_4 => S_3);
}
2022-09-19
endgroup 206
• This is helpful to monitor FSM state wire [2:0] light_1, light_2;
transition coverage. traffic DUT(car_sensor, clk, n_rst, light_1, light_2);
localparam
S_1 = 4'b0001,
S_2 = 4'b0010,
S_3 = 4'b0100,
S_4 = 4'b1000;

bins S_1_2 = (S_1 => S_2);
bins S_2_3 = (S_2 => S_3);
bins S_3_4 = (S_3 => S_4);
bins S_4_1 = (S_4 => S_1);
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
bins S_4_3 = (S_4 => S_3);
}
2022-09-19
endgroup 207
• FSM state transition covergroup
added to the traffic light testbench localparam
S_1 = 4'b0001,
(recall Verilog III). S_2 = 4'b0010,
S_3 = 4'b0100,
S_4 = 4'b1000;

bins S_1_2 = (S_1 => S_2);
bins S_2_3 = (S_2 => S_3);
bins S_3_4 = (S_3 => S_4);
bins S_4_1 = (S_4 => S_1);
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
bins S_4_3 = (S_4 => S_3);
}
2022-09-19
endgroup 208
S_1 = 4'b0001,
(recall Verilog III). S_2 = 4'b0010,
• The covergroup is automatically S_3 = 4'b0100,
sampled on every clock rising edge. S_4 = 4'b1000;

bins S_1_2 = (S_1 => S_2);
bins S_2_3 = (S_2 => S_3);
bins S_3_4 = (S_3 => S_4);
bins S_4_1 = (S_4 => S_1);
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
bins S_4_3 = (S_4 => S_3);
}
2022-09-19
endgroup 209
Covergroup cov
S_1 = 4'b0001,
(recall Verilog III). S_2 = 4'b0010, automatically samples
• The covergroup is automatically S_3 = 4'b0100, on clk posedge.

bins S_1_2 = (S_1 => S_2);
bins S_2_3 = (S_2 => S_3);
bins S_3_4 = (S_3 => S_4);
bins S_4_1 = (S_4 => S_1);
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
bins S_4_3 = (S_4 => S_3);
}
2022-09-19
endgroup 210
Covergroup cov
S_1 = 4'b0001,
• Bins e.g. S_1_2 = (S_1 => S_2) is hit covergroup cov @ (posedge clk);
when traffic.cur_state changes from coverpoint traffic.cur_state {
bins S_1_2 = (S_1 => S_2);
S_1 to S_2 on any clock rising edge. bins S_2_3 = (S_2 => S_3);
bins S_3_4 = (S_3 => S_4);
bins S_4_1 = (S_4 => S_1);
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
bins S_4_3 = (S_4 => S_3);
}
2022-09-19
endgroup 211
Covergroup cov
S_1 = 4'b0001,
when traffic.cur_state changes from coverpoint traffic.cur_state {
bins S_1_2 = (S_1 => S_2);
S_1 to S_2 on any clock rising edge. bins S_2_3 = (S_2 => S_3);
• Bins S_2_3_4 is hit when S_2 holds bins S_3_4 = (S_3 => S_4);
for 5000 cycles first, then S_3 for bins S_4_1 = (S_4 => S_1);
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
30000 cycles, and then S_4 for 5000 bins S_4_3 = (S_4 => S_3);
cycles, across 40000 sequential }
clock posedges.
2022-09-19
endgroup 212
Covergroup cov
S_1 = 4'b0001,
when traffic.cur_state changes from coverpoint traffic.cur_state { Monitor state
bins S_1_2 = (S_1 => S_2);
S_1 to S_2 on any clock rising edge. bins S_2_3 = (S_2 => S_3); transition sequence.
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
clock posedges.
2022-09-19
endgroup 213
Covergroup cov
S_1 = 4'b0001,
when traffic.cur_state changes from coverpoint traffic.cur_state { Monitor state
bins S_1_2 = (S_1 => S_2);
S_1 to S_2 on any clock rising edge. bins S_2_3 = (S_2 => S_3); transition sequence.
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
clock posedges.
2022-09-19
endgroup Don’t forget to instantiate
214
cov cov_fsm = new(); the covergroup
Monitor FSM state transition using
functional coverage
module tb;
localparam
S_1 = 4'b0001,
S_2 = 4'b0010,
S_3 = 4'b0100,
S_4 = 4'b1000;

bins S_1_2 = (S_1 => S_2);
bins S_2_3 = (S_2 => S_3);
bins S_3_4 = (S_3 => S_4);
bins S_4_1 = (S_4 => S_1);
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
bins S_4_3 = (S_4 => S_3);
}
endgroup
cov 2022-09-19
cov_fsm = new(); 215
functional coverage
module tb;
localparam
S_1 = 4'b0001,
S_2 = 4'b0010,
S_3 = 4'b0100,
S_4 = 4'b1000;

bins S_1_2 = (S_1 => S_2);
bins S_2_3 = (S_2 => S_3);
bins S_3_4 = (S_3 => S_4);
bins S_4_1 = (S_4 => S_1);
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
bins S_4_3 = (S_4 => S_3);
}
endgroup
cov 2022-09-19
functional coverage
module tb;
localparam
S_1 = 4'b0001,
S_2 = 4'b0010,
S_3 = 4'b0100,
S_4 = 4'b1000;
We can never reach this
state transition. That’s
bins S_1_2 = (S_1 => S_2); why it is never hit.
bins S_2_3 = (S_2 => S_3);
bins S_3_4 = (S_3 => S_4);
bins S_4_1 = (S_4 => S_1);
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
bins S_4_3 = (S_4 => S_3);
}
endgroup
cov 2022-09-19
functional coverage
module tb;
localparam
S_1 = 4'b0001,
S_2 = 4'b0010,
S_3 = 4'b0100,
S_4 = 4'b1000;
We can never reach this
state transition. That’s
bins S_1_2 = (S_1 => S_2); why it is never hit.
bins S_2_3 = (S_2 => S_3);
bins S_3_4 = (S_3 => S_4);
bins S_4_1 = (S_4 => S_1); In the current TB we
bins S_2_3_4 = (S_2[*5000] => S_3[*30000] => S_4[*5000]);
bins S_4_3 = (S_4 => S_3);
only has exercised each
} state transition once,
endgroup thus the hit count for
cov 2022-09-19
cov_fsm = new(); each bin 218
is 1.
Questions?
2022-09-19 219

Verification II

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Verification II

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Accelerating Systems with

Programmable Logic Components

Yuan Yao, yuan.yao@it.uu.se

Hard to use within context and OOP.

• $urandom returns unsigned number (0 to 232-1)

assert ((A == B) && (A == C))

assert ((A == B) && (A == C))

assert ((A == B) && (A == C))

An immediate assertion with a failure

An immediate assertion with a failure

An immediate assertion with a failure

An immediate assertion with a failure

An immediate assertion with a failure

1. At each rising clk edge

1. At each rising clk edge

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk)

always_ff @ (posedge clk) property p_1a_f;

always_ff @ (posedge clk) property p_1a_f; rst == 1’b0,

always_ff @ (posedge clk) property p_1a_f; rst == 1’b0,

always_ff @ (posedge clk) property p_1a_f; rst == 1’b0,

always_ff @ (posedge clk) property p_1a_f; rst == 1’b0,

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

Disable the property when reset is on!

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk) property p_1b_v1;

always_ff @ (posedge clk)

initial begin //demo_13

always_ff @ (posedge clk)

initial begin //demo_13

always_ff @ (posedge clk)

initial begin //demo_13