Verilog II

Accelerating Systems with
Programmable Logic Components

Lecture 04 Verilog II
1DT109 ASPLOC
2022 VT1-VT2
Yuan Yao, yuan.yao@it.uu.se
2022-09-17 Courtesy to Philipp Rümmer 1

Agenda
• Review module-based modelling in Verilog
• Combinational vs. sequential logic
• Blocking vs. nonblocking assignment
• Writing testbench using Verilog
2022-09-17 2
Module-based modelling in Verilog
my_module
module my_module(A, B, C, O);
A And
1
input A, B, C;
Not1
B
output O; Or1 O
And
C 2
wire w_not, w_and1, w_and2;
not Not1(.out(w_not), .in1(C));

and And1(.out(w_and1), .in1(A), .in2(w_not));
OR
assign O = (A & ~C) | (B & C);
endmodule
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my_module
A And
1
input A, B, C;
Not1
B
output O; Or1 O
And
C 2

OR
assign O = (A & ~C) | (B & C);
endmodule
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my_module
A And
1
input A, B, C;
Not1
B
output O; Or1 O
And
C 2
my_module
declaration

OR
assign O = (A & ~C) | (B & C);
endmodule
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my_module
A And
1
input A, B, C;
Not1
B
output O; Or1 O
And
C 2
my_module
declaration

OR
assign O = (A & ~C) | (B & C);
endmodule
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my_module
A And
1
input A, B, C;
output O;
input/output port definition B
Not1
Or1 O
And
C 2
my_module
declaration

OR
assign O = (A & ~C) | (B & C);
endmodule
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my_module
A And
1
input A, B, C;
output O;
Not1
Or1 O
And
C 2
my_module
declaration

OR
assign O = (A & ~C) | (B & C);
endmodule
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my_module
A And
1
input A, B, C;
output O;
Not1
Or1 O
And
C 2
my_module
declaration
wire w_not, w_and1, w_and2; connecting wire

OR
assign O = (A & ~C) | (B & C);
endmodule
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my_module
A And
1
input A, B, C;
output O;
Not1
Or1 O
And
C 2
my_module
declaration

OR
assign O = (A & ~C) | (B & C);
endmodule
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my_module
A And
1
input A, B, C;
output O;
Not1
Or1 O
And
C 2
my_module
declaration

gate-level modeling
OR
assign O = (A & ~C) | (B & C);
endmodule
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my_module
A And
1
input A, B, C;
output O;
Not1
Or1 O
And
C 2
my_module
declaration

gate-level modeling
OR
assign O = (A & ~C) | (B & C);
endmodule
2022-09-17 12
my_module
A And
1
input A, B, C;
output O;
Not1
Or1 O
And
C 2
my_module
declaration

gate-level modeling
OR
assign O = (A & ~C) | (B & C); data-flow level modeling
endmodule
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my_module
A And
1
input A, B, C;
output O;
Not1
Or1 O
And
2
This is for combinational logic.

C
my_module
declaration

gate-level modeling
OR
assign O = (A & ~C) | (B & C); data-flow level modeling
endmodule
2022-09-17 14
Combinational vs Sequential logic
• Combinational logic is defined as the time independent
logic which do not depends upon previous inputs to
generate any output.
• Examples – Encoder, Decoder, Multiplexer, Demultiplexer
• Sequential logic is a type of logic circuit whose output
depends not only on the present value of its input signals
but on the sequence of past inputs, the input history as well.
• Examples – Flip-flops, counters, memory
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Sequential logic example: counter
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Input
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Input Output = Input + 1
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Adder
(combinational logic)
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Adder
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Adder
Mem component
such as Flip-Flop
(sequential logic)
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Adder
Mem component
such as Flip-Flop
(sequential logic)
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Input Output = Cur

Input+ +1 1
Adder
Mem component
such as Flip-Flop
(sequential logic)
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Input Output = Cur

Input+ +1 1
Adder
Mem component
such as Flip-Flop
(sequential logic)
2022-09-17 clk 26
Input Output = Cur

Input+ +1 1
Adder
Mem component
such as Flip-Flop
(sequential logic)
2022-09-17 clk 27
Input Output = Cur

Input+ +1 1
Adder
Mem component
such as Flip-Flop
(sequential logic)
2022-09-17 clk 28
Input Output = Cur

Input+ +1 1
Adder
Mem component
such as Flip-Flop
(sequential logic)
2022-09-17 clk 29
Input Output = Cur

Input+ +1 1
Adder
Mem component
such as Flip-Flop
(sequential logic)
2022-09-17 clk 30
Sequential logic example: critical path break
input output
Combinational logic
Delay=X > threshold
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input output
Combinational logic
Delay=X > threshold
FF
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input output
Combinational logic
Delay=X > threshold
Combi
FF
logic
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input output
Combinational logic
Delay=X > threshold
Combi
FF
logic
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input output
Combinational logic
Delay=X > threshold
Combi
FF
logic
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input output
Combinational logic
Delay=X > threshold
input
Combi
FF
logic
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input output
Combinational logic
Delay=X > threshold
input output
Combi
FF
logic
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input output
Combinational logic
Delay=X > threshold
input output
Combi
FF
logic
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input output
Combinational logic
Delay=X > threshold
input output
Combi
FF
logic
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input output
Combinational logic
Delay=X > threshold
input output
Combi
FF
logic
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input output
Combinational logic
Delay=X > threshold
input output
Combi
FF
logic
Delay=X/2 < threshold

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input output
Combinational logic
Delay=X > threshold
input output
Combi
FF
logic

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input output
Combinational logic
Delay=X > threshold
input output
Combi
FF
logic

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input output
Combinational logic
Delay=X > threshold
input output
Combi
FF
logic

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input output
Combinational logic
Delay=X > threshold
input output
Combi
FF
logic
Delay=X/2 < threshold Delay=X/2 < threshold

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input output
Combinational logic
Delay=X > threshold
input output
Combi
FF
logic

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input output
Combinational logic
Delay=X > threshold
input output
Combi Combi
FF
logic logic

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input output
Combinational logic
Delay=X > threshold
input output
Combi Combi
FF
logic logic

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input output
Combinational logic
Speed/area tread off.Delay=X > threshold
input output
Combi Combi
FF
logic logic

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Model flip-flop (FF) using Verilog
• Step 1: Find the schema of an FF
• Step 2: Use gate-level or data-flow level modeling for FF
D Q
clk
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D Q
D_FF
clk
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D Q
D_FF
clk
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Do we have other options?

D Q
D_FF
clk
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• We can use RTL-level modeling in Verilog to model FF
• The recommended way to model combinational logic in Verilog
module d_ff(clk, D, Q);
input clk, D;
output Q;
D Q
reg Q;
D_FF
always @ (posedge clk) begin
Q <= D;
clk
end
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endmodule 54
The always block
An always block is one of the procedural blocks in Verilog.
• Statements inside an always block are executed sequentially.
• But they may take effect simultaneously
a=1; a=1;
b=2; b=2;
always @ (a, b) begin always @ (a, b) begin
a <= b; a = b;
b <= a; b = a;
end // a=2, b=1; end // a=2, b=2;
2022-09-17 55
The sensitivity list
• A sensitivity list is the expression that defines when the always
block should be executed and is specified after the @ operator
within parentheses ( ).
• Sensitivity list is the key to differentiate combinational logic and
sequential logic.
Execute always block whenever value of Execute always block only on the rising
“a” or “b” change – combinational logic edge of signal clk – sequential lock
always @ (a, b) always @ (posedge clk)

begin begin
c = a | b; c <= a | b;
end
2022-09-17
end 56
within parentheses ( ).
• Sensitivity list is the key to differentiate combinational logic and
sequential logic.
“a” or “b” change – combinational logic edge of signal clk – sequential lock

begin begin
c = a | b; c <= a | b; Can also use
negedge
end
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end for falling edge
57
within parentheses Rules
( ). of thumb No.1:
1. Put all input
• Sensitivity list issignals
the key tointo the sensitivity
differentiate list and
combinational logic for
sequential logic.
combinational logic
2. Put only the clock (and reset
“a” or “b” change – combinational logic
if needed) signal
edge of signal clk – sequential lock
into the
always sensitivity
@ (a, b) list for always
sequential @ (posedge logic clk)
begin begin
c = a | b; c <= a | b; Can also use
negedge
end
2022-09-17
end for falling edge
58
The reg data type (vs wire)
• Verilog data types are divided into two main groups: nets (wire) and
variables (reg). The distinction comes from how they are intended to
represent different hardware structures.
• A net (wire) data type represents a physical connection between
structural entities. (Recall the my_module example)
• A variable (reg) data type represents a piece of storage.
wire c; reg c; reg c;

assign c = a | b;
begin begin
c = a | b; c <= a | b;
2022-09-17 end end 59
The reg data type (vs wire)
• Verilog data types are divided into two main groups: nets (wire) and
variables (reg). The distinction comes from how they are intended to
represent differentRules ofstructures.
hardware thumb No.2:
• A net (wire) data type represents a physical connection between
1. Drive a Verilog
structural wirethewith
entities. (Recall assign
my_module statement or port
example)
output
• A variable (reg) data type represents a piece of storage.
2. Drive a Verilog reg from an always block.
assign c = a | b;
begin begin
c = a | b; c <= a | b;
2022-09-17 end end 60
Demo 1
• my_module from Verilog I
using always block
module demo_1(A,B,C,O);
input A, B, C;
output O;
assign O = reg_o;
reg reg_o;
always @ (A, B, C) begin

reg_o = A & ~B | B & C;
end
endmodule
2022-09-17 61
my_module
Demo 1 A And
1
B Not
• my_module from Verilog I 1
And
Or1 O
using always block C 2
input A, B, C;
output O;
assign O = reg_o;
reg reg_o;

reg_o = A & ~B | B & C;
end
endmodule
2022-09-17 62
my_module
Demo 1 A And
1
B Not
And
Or1 O
input A, B, C; 𝑂 =𝐴∙𝐶+𝐵∙𝐶
output O;
assign O = reg_o;
reg reg_o;

reg_o = A & ~B | B & C;
end
endmodule
2022-09-17 63
my_module
Demo 1 A And
1
B Not
And
Or1 O
input A, B, C; 𝑂 =𝐴∙𝐶+𝐵∙𝐶
output O;
assign O = reg_o;
reg reg_o;

reg_o = A & ~B | B & C;
end
endmodule
2022-09-17 64
Putting them all together
• Q only reflects the value of D on a rising edge
• Rising edge means 0 in the past of input and 1 in the current

input clk, D;
output Q; D Q
reg Q; D_FF
Q <= D; clk
end
2022-09-17
endmodule 65
Putting them all together
• Q only reflects the value of D on a rising edge
• Rising edge means 0 in the past of input and 1 in the current

input clk, D; Can also use non-
clock signals as
output Q; trigger D Q
reg Q; D_FF
Q <= D; clk
end
2022-09-17
endmodule 66
D_FF with synchronous reset
• Add a reset to the D_FF
• Synchronous reset means that the D_FF can only be reset on clock
edge (in our case, a rising edge)
input clk, D;
output Q; Q
D
reg Q;
reset
D_FF
if(!reset)
Q <= 1’b0;
clk
else
Q <= D;
end
endmodule
2022-09-17 67
input clk, D;
output Q; Q
D
reg Q;
reset
D_FF
if(!reset)
Q <= 1’b0;
clk
else
Q <= D;
end Added gates!
endmodule
2022-09-17 68
How to add asynchronous reset?
input clk, D;
output Q; Q
D
reg Q;
reset
D_FF
if(!reset)
Q <= 1’b0;
clk
else
Q <= D;
end Added gates!
endmodule
2022-09-17 69
D_FF with asynchronous reset
• Asynchronous reset means that the D_FF can be reset on reset
edge (in our case, a falling edge)
input clk, D;
output Q;
reg Q; D Q
always @ (posedge clk,
negedge reset) begin
D_FF
if(!reset)
Q <= 1’b0;
else clk
Q <= D;
end
reset
2022-09-17 endmodule 70
input clk, D;
output Q;
reg Q; D Q
D_FF
if(!reset)
Q <= 1’b0;
else clk
Q <= D;
end
reset
2022-09-17 endmodule 71
input clk, D;
output Q;
reg Q; D Q
D_FF
if(!reset)
Q <= 1’b0;
else clk
Q <= D; No added gates
end needed!
reset
2022-09-17 endmodule 72
Always use asynchronous D_FF.
It keeps your datapath shorter/faster.

input clk, D;
output Q;
D Q
(why???)
reg Q;
D_FF
if(!reset)
Q <= 1’b0;
else clk
Q <= D; No added gates
end needed!
reset
2022-09-17 endmodule 73
Blocking vs. non-blocking assignment
• Different ways to drive wire and reg.
• = is called blocking assignment.
• Blocking assignment executes “in series” because a blocking
assignment blocks execution of the next statement until it completes.
• <= is called non-blocking assignment.
• Non-blocking assignment executes “in parallel” because it describes
assignments that all occur at the same time.
Blocking assignment Non-blocking assignment
assign c = a | b; always @ (a, b) always @ (posedge clk)
begin begin
c = a | b; c <= a | b;
2022-09-17 end end 74
Rules of thumb No.3:
1. Use blocking assignment to model combinational
logic.
2. Use non-blocking assignment
assignment blocks execution to model
of the next statement sequential
until it completes.
logic.
assign c = a | b; always @ (a, b) always @ (posedge clk)
begin begin
c = a | b; c <= a | b;
2022-09-17 end end 75
Rules of thumb No.3:
1. Use blocking assignment to model combinational
logic.
2. Use non-blocking assignment
assignment blocks execution to model
of the next statement sequential
until it completes.
logic.
Bad styles can lead to both buggy and
assign c = a | b; incorrect circuit.

begin begin
c = a | b; c <= a | b;
2022-09-17 end end 76
Blocking assignment – Good and bad styles
A
B
O
C
Good style Bad style

reg r_and, r_or; reg r_and, r_or;
assign O = r_or; assign O = r_or;
always @ (A, B, C) begin always @ (A, B, C) begin

r_and = A & B; r_and <= A & B;
r_or = r_and | C; r_or <= r_and | C;
end //demo_2 end //demo_2
2022-09-17 77
A
B
O
C


2022-09-17 78
A
B
O
C
Behavioral

2022-09-17 79
A
B
O
C
Behavioral

2022-09-17 80
A
B
O
C
Behavioral Behavioral

2022-09-17 81
A
B
O
C

2022-09-17 82
A
B
O
C

2022-09-17 83
A
B
O
C

2022-09-17 84
Post-synth
A
B
O
C

2022-09-17 85
Post-synth Post-synth
A
B
O
C

2022-09-17 86
A
B
O
C
Results
always @ (A, B, C) begin Match!
r_and = A & B; (no bug) r_and <= A & B;
2022-09-17 87
A
B
O
C
Results
Results Mismatch!
always @ (A, B, C) begin Match!
r_and = A & B; r_and <= A & B; (bug in
(no bug) front-end)
2022-09-17 88
Non-blocking assignment – Good and bad styles
D_1 D_2 Q
D_FF D_FF
clk

reg D_2, _Q; reg D_2, _Q;
assign Q = _Q; assign Q = _Q;
always @ (posedge clk) always @ (posedge clk)
begin begin
D_2 <= D_1; D_2 = D_1;
_Q <= D_2; _Q = D_2;
2022-09-17 89
D_1 D_2 Q
D_FF D_FF
clk

begin begin
D_2 <= D_1; D_2 = D_1;
_Q <= D_2; _Q = D_2;
2022-09-17 90
D_1 D_2 Q
D_FF D_FF
clk

begin begin
D_2 <= D_1; D_2 = D_1;
_Q <= D_2; _Q = D_2;
2022-09-17 91
D_1 D_2 Q
D_FF D_FF
clk

begin begin
D_2 <= D_1; D_2 = D_1;
_Q <= D_2; _Q = D_2;
2022-09-17 92
Design pitfalls
• Multi drive always module
• Combinational loop
2022-09-17 93
Multi-drive always blocks
• Statements within always are
always @ (a, b) begin evaluated sequentially from
… the first to the last.
x = a | b;
… • However, different always
end blocks are executed
randomly.
always @ (c, d) begin • The execution order of the
green and blue always are
…
totally random run-to-run.
x = c & d;
…
end
2022-09-17 94
x = a | b;
randomly.
…
x = c & d;
…
end
2022-09-17 95
x = a | b;
randomly.
…
x = c & d; Critical warning
… generated during
end synthesis.
2022-09-17 96
x = a | b;
• However, different always
… Rules of thumbblocksNo.4:
are executed
end
Each reg should only be driven by one always block.
randomly.
…
x = c & d; Critical warning
… generated during
end synthesis.
2022-09-17 97
Bit-vector is the only data type in Verilog
• A bit can take on one of four values
Vdd Vdd Vdd
2022-09-17 Vss Vss Vss98

Value Meaning
0 Logic zero
Vdd Vdd Vdd
2022-09-17 Vss Vss Vss99

Value Meaning
0 Logic zero
Vdd Vdd Vdd
2022-09-17 Vss Vss Vss

100
Value Meaning
0 Logic zero
1 Logic one Vdd Vdd Vdd

101
Value Meaning
0 Logic zero

102
Value Meaning
0 Logic zero
Z High impedance, floating

103
Value Meaning
0 Logic zero

104
Value Meaning
0 Logic zero

X Unknown logic value

105
Value Meaning
0 Logic zero


106
Value Meaning
0 Logic zero

An X bit might be a 0, 1, Z, or in transition. We can set bits

to be X in situations where we don’t care what the value
is. This can help catch bugs and improve synthesis quality
(Lecture 5 – Verilog III).
107
Value Meaning
0 Logic zero

An X bit might be a 0, 1, Z, or in transition. We can set bits

to be X in situations where we don’t care what the value
is. This can help catch bugs and improve synthesis quality
(Lecture 5 – Verilog III).
108
Bit literals
2022-09-17 109
Bit literals
4’b10_11
2022-09-17 110
Bit literals
4’b10_11
2022-09-17 111
Bit literals
4’b10_11
Decimal number
Representing size in bits
2022-09-17 112
Bit literals
4’b10_11
Decimal number
2022-09-17 113
Bit literals
4’b10_11
Base format
(B, O, H, D)
Decimal number
2022-09-17 114
Bit literals
4’b10_11
Base format
(B, O, H, D)
Decimal number
2022-09-17 115
Bit literals
4’b10_11
Underscores
are ignored
Base format
(B, O, H, D)
Decimal number
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Bit literals • Binary literals
4’b10_11
Underscores
are ignored
Base format
(B, O, H, D)
Decimal number
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• 2’b01 (01)
4’b10_11
Underscores
are ignored
Base format
(B, O, H, D)
Decimal number
2022-09-17 118
• 2’b01 (01)
• 8’b0001_1111 (00011111)
4’b10_11
Underscores
are ignored
Base format
(B, O, H, D)
Decimal number
2022-09-17 119
• 2’b01 (01)
• 8’b0001_1111 (00011111)
• -3’b1 (111)
4’b10_11
Underscores
are ignored
Base format
(B, O, H, D)
Decimal number
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• 2’b01 (01)
• 8’b0001_1111 (00011111)
• -3’b1 (111)
4’b10_11 • Octal literals
Underscores
are ignored
Base format
(B, O, H, D)
Decimal number
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• 2’b01 (01)
• 8’b0001_1111 (00011111)
• -3’b1 (111)

• 6’o12 (001_010)
Underscores
are ignored
Base format
(B, O, H, D)
Decimal number
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• 2’b01 (01)
• 8’b0001_1111 (00011111)
• -3’b1 (111)

• 6’o12 (001_010)
• Hexadecimal literals
Underscores
are ignored
Base format
(B, O, H, D)
Decimal number
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• 2’b01 (01)
• 8’b0001_1111 (00011111)
• -3’b1 (111)

• 6’o12 (001_010)
Underscores • 6’h1f (01_1111)
are ignored
Base format
(B, O, H, D)
Decimal number
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• 2’b01 (01)
• 8’b0001_1111 (00011111)
• -3’b1 (111)

• 6’o12 (001_010)
are ignored • 16’haxxz (1010_xxxx_xxxx_zzzz)
Base format
(B, O, H, D)
Decimal number
2022-09-17 125
• 2’b01 (01)
• 8’b0001_1111 (00011111)
• -3’b1 (111)

• 6’o12 (001_010)
Base format • Decimal literals
(B, O, H, D)
Decimal number
2022-09-17 126
• 2’b01 (01)
• 8’b0001_1111 (00011111)
• -3’b1 (111)

• 6’o12 (001_010)
(B, O, H, D) • 4’d1 (0001)
Decimal number
2022-09-17 127
• 2’b01 (01)
• 8’b0001_1111 (00011111)
• -3’b1 (111)

• 6’o12 (001_010)
(B, O, H, D) • 4’d1 (0001)
Decimal number • -4’d1 (1111)
2022-09-17 128
• 2’b01 (01)
• 8’b0001_1111 (00011111)
• -3’b1 (111)

• 6’o12 (001_010)
(B, O, H, D) • 4’d1 (0001)
Representing size in bits • reg[3:0] a = 1; (0001)
2022-09-17 129
• 2’b01 (01)
• 8’b0001_1111 (00011111)
• -3’b1 (111)

• 6’o12 (001_010)
(B, O, H, D) • 4’d1 (0001)
• reg[3:0] a = -1; (1111)
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• 2’b01 (01)
• 8’b0001_1111 (00011111)
• -3’b1 (111)

• 6’o12 (001_010)
(B, O, H, D) • 4’d1 (0001)
• reg[3:0] a = -1; (1111)
• integer a = 1; (0000_0000_..._0001, 32-bit)
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• 2’b01 (01)
• 8’b0001_1111 (00011111)
• -3’b1 (111)

• 6’o12 (001_010)
(B, O, H, D) • 4’d1 (0001)
• reg[3:0] a = -1; (1111)
• integer a = 1; (0000_0000_..._0001, 32-bit)
2022-09-17 • Integer a = -1; (1111_1111_..._1111, 32-bit)
132
Combinational loop – the obvious case
always @ (a, b)
begin
c = a | b;
end
always @ (a, b)
begin
c = a | b | c;
end //demo_4
2022-09-17 133
always @ (a, b)
begin
c = a | b;
end
always @ (a, b)
begin
c = a | b | c;
end //demo_4
2022-09-17 134
always @ (a, b)
begin
c = a | b;
end
always @ (a, b)
begin
c = a | b | c;
end //demo_4
2022-09-17 135
always @ (a, b)
begin
c = a | b;
end
always @ (a, b)
begin
c = a | b | c;
end //demo_4
2022-09-17 136
always @ (a, b)
begin
c = a | b;
end
always @ (a, b)
begin
c = a | b | c;
end //demo_4
2022-09-17 137
always @ (a, b)
begin
c = a | b;
end
always @ (a, b)
begin
c = a | b | c;
end //demo_4
2022-09-17 138
always @Hard
(a, b)
to use simulation
begin results to detect combi-
c = a | b; loop.
end
always @ (a, b)
begin
c = a | b | c;
end //demo_4
2022-09-17 139
always @Hard
(a, b)
to use simulation
c = a | b; loop.
end
always @ (a, b)
begin
c = a | b | c;
end //demo_4
2022-09-17 140
always @Hard
(a, b)
to use simulation
c = a | b; loop.
end No error generated at both pre
and post synthesis simulation.
But a non-critical warning is
alwaysgenerated
@ (a, b)during synthesis.
begin
c = a | b | c;
end //demo_4
2022-09-17 141
always @Hard
(a, b)
to use simulation
c = a | b; loop.
alwaysgenerated
begin
c = a | b | c;
end //demo_4
2022-09-17 142
always @Hard
(a, b)
to use simulation
c = a | b; loop.
alwaysgenerated
begin
c message
Or an error = a | b is| c;
generated during later
end
bit //demo_4
stream generation.
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always @Hard
(a, b)
to use simulation
c = a | b; loop. Rules of thumb No.5:
Remember to check
the Vivado methodology report
at each step.
alwaysgenerated
begin
c message
Or an error = a | b is| c;
generated during later
end
bit //demo_4
stream generation.
2022-09-17 144
Combinational loop – the covert case
always @ (a, x) begin
…
y = a| x;
…
y
end
always @ (y, b) begin

… x
x = y | b;
…
end
2022-09-17 145
Combinational loop – the covert case
always @ (a, x) begin
…
y = a| x;
…
end
A combi-loop may hide within the
y
ocean of
always @ (y, b) begin
gates in a large design.
… x
x = y | b;
…
end
2022-09-17 146
Writing testbench using Verilog
• Testbenches are used to test/debug Verilog design with
synthetic inputs and collect the outputs.
• Testbenches are usually top modules in a Verilog project.
• The design-under-test is a sub-modules in a testbench module
• Testbenches are not supposed to be synthesizable.
2022-09-17 147
testbench
2022-09-17 148
testbench
DUT/UUT
2022-09-17 149
testbench
DUT/UUT
2022-09-17 150
testbench
DUT/UUT
2022-09-17 151
testbench
DUT/UUT
2022-09-17 152
testbench
DUT/UUT
2022-09-17 153
testbench
inputs
DUT/UUT
2022-09-17 154
testbench
inputs outputs
DUT/UUT
2022-09-17 155
testbench
inputs outputs
DUT/UUT
2022-09-17 156
testbench
inputs outputs
DUT/UUT
2022-09-17 157
testbench
inputs outputs
DUT/UUT
2022-09-17 158
testbench
inputs outputs
DUT/UUT
2022-09-17 159
A testbench example
DUT.v tb.v
module demo_2(A, B, C, O); `timescale 1ns/1ps
module tb;
input A, B, C; reg a, b, c;
output O; wire o;
reg r_and, r_or; demo_2 UUT(a, b, c, o);

assign O = r_or; localparam period = 1;
always @ (A, B, C) begin initial begin
r_and = A & B; a = 0; b = 0; c = 0;
r_or = r_and | C; #period;
a = 1; b = 0; c = 0;
end #period;
a = 1; b = 1; c = 0;
Endmodule ...
end
2022-09-17 endmodule 160
A testbench example
DUT.v tb.v
module tb; Top module, no
input A, B, C; reg a, b, c; input nor
output O; wire o; outpus
r_and = A & B; a = 0; b = 0; c = 0;
a = 1; b = 0; c = 0;
end #period;
a = 1; b = 1; c = 0;
Endmodule ...
end
2022-09-17 endmodule 161
A testbench example
DUT.v tb.v
r_and = A & B; a = 0; b = 0; c = 0;
a = 1; b = 0; c = 0;
end #period;
a = 1; b = 1; c = 0;
Endmodule ...
end
2022-09-17 endmodule 162
A testbench example
DUT.v tb.v
r_and = A & B; a = 0; b = 0; c = 0;
a = 1; b = 0; c = 0;
end #period;
a = 1; b = 1; c = 0;
Endmodule ...
end
2022-09-17 endmodule 163
A testbench example
DUT.v tb.v What we get from DUT.v
r_and = A & B; a = 0; b = 0; c = 0;
a = 1; b = 0; c = 0;
end #period;
a = 1; b = 1; c = 0;
Endmodule ...
end
2022-09-17 endmodule 164
A testbench example
module tb; Top module, no A
input A, B, C; reg a, b, c; input nor B
O
reg r_and, r_or; demo_2 UUT(a, b, c, o); C
r_and = A & B; a = 0; b = 0; c = 0;
a = 1; b = 0; c = 0;
end #period;
a = 1; b = 1; c = 0;
Endmodule ...
end
2022-09-17 endmodule 165
A testbench example
O

What we get from tb.v
r_and = A & B; a = 0; b = 0; c = 0;
a = 1; b = 0; c = 0;
end #period;
a = 1; b = 1; c = 0;
Endmodule ...
end
2022-09-17 endmodule 166
A testbench example
O

r_and = A & B; a = 0; b = 0; c = 0;
a = 1; b = 0; c = 0;
end #period;
a = 1; b = 1; c = 0;
Endmodule ...
end
2022-09-17 endmodule 167
A testbench example
O

r_and = A & B; a = 0; b = 0; c = 0;
a = 1; b = 0; c = 0;
end #period;
a = 1; b = 1; c = 0;
Endmodule ...
end
2022-09-17 endmodule 168
A testbench example
O

r_and = A & B; a = 0; b = 0; c = 0;
a = 1; b = 0; c = 0;
end #period;
a = 1; b = 1; c = 0;
Endmodule ...
end
2022-09-17 endmodule 169
A testbench example
O

r_and = A & B; a = 0; b = 0; c = 0;
a = 1; b = 0; c = 0;
end #period;
a = 1; b = 1; c = 0;
Endmodule ...
end
2022-09-17 endmodule 170
A testbench example
O

r_and = A & B; a = 0; b = 0; c = 0;
a = 1; b = 0; c = 0;
end #period;
a = 1; b = 1; c = 0;
Endmodule ...
end
2022-09-17 endmodule 171
A testbench example
O

r_and = A & B; a = 0; b = 0; c = 0;
a = 1; b = 0; c = 0;
end #period;
a = 1; b = 1; c = 0;
Endmodule ...
end
2022-09-17 endmodule 172
What defines a good testbench and how
to achieve them
• Input coverage
• As much different input patterns as possible
• Loop statement
• Reliability
• Mimic the electronic properties of real-word signals
• Timing control
• Delay control
• Edge sensitive event control
• Level sensitive event control
• Named event (Lecture 9 – Verification)
• Reusability/readability
• Functionalities encapsulation
• Function and task
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Loop statement
• Verilog provides four ways to do loop
• for
• while
• repeat
• forever
• Loop statements are synthesizable for iterations with finite
values known at elaboration (compile) time
• Loop statements are synthesized with hardware replication
• Although possible but is it a bad practice
• Loop statements are better match for test bench and verification
2022-09-17 174
For loop statement
tb.v
`timescale 1ns/1ps
module tb;
reg a, b, c;
wire o;
demo_5 UUT(a, b, c, o);

localparam period = 1;
initial begin
a = 0; b = 0; c = 0;
#period;
a = 1; b = 0; c = 0;
#period;
a = 1; b = 1; c = 0;
...
end
2022-09-17 175
endmodule
For loop statement
tb.v
`timescale 1ns/1ps
module tb;
reg a, b, c;
wire o;

initial begin
a = 0; b = 0; c = 0;
#period;
a = 1; b = 0; c = 0;
#period;
a = 1; b = 1; c = 0;
...
end
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endmodule
For loop statement
tb.v
`timescale 1ns/1ps
module tb;
reg a, b, c;
wire o;

initial begin
a = 0; b = 0; c = 0;
#period; Need 8 lines to
a = 1; b = 0; c = 0; exhaust all
#period; input patterns.
a = 1; b = 1; c = 0;
...
end
2022-09-17 177
endmodule
For loop statement
tb.v
`timescale 1ns/1ps What if the input
module tb; contains 16 signals?
reg a, b, c; 216 lines!
wire o;

initial begin
a = 0; b = 0; c = 0;
#period; Need 8 lines to
a = 1; b = 0; c = 0; exhaust all
#period; input patterns.
a = 1; b = 1; c = 0;
...
end
2022-09-17 178
endmodule
For loop statement
tb.v tb.v
`timescale 1ns/1ps What if the input `timescale 1ns/1ps
module tb; contains 16 signals? module tb;
reg a, b, c; 216 lines! reg [2:0] a;
wire o; wire o;
demo_5 UUT(a, b, c, o); demo_5 UUT(a[2], a[1], a[0], o);

localparam period = 1; localparam period = 1;
integer i;
initial begin initial begin
a = 0; b = 0; c = 0; for (i=0; i<8; i=i+1) begin

#period; Need 8 lines to a = {i[2], i[1], i[0]};
a = 1; b = 0; c = 0; exhaust all #period;
#period; input patterns. end
a = 1; b = 1; c = 0;
... end
end endmodule
2022-09-17 179
endmodule
3-bit reg “a”, with
For loop statement MSB at the most left.
tb.v tb.v
module tb; contains 16 signals? module tb;
reg a, b, c; 216 lines! reg [2:0] a;
wire o; wire o;

integer i;

a = 1; b = 1; c = 0;
... end
end endmodule
2022-09-17 180
endmodule
tb.v tb.v
module tb; contains 16 signals? module tb; assign bit a[2] to the first port of
reg a, b, c; 216 lines! reg [2:0] a; UUT, and so on. That is:
wire o; wire o; a[2] to a, A[1] to b, A[0] to c.

integer i;

a = 1; b = 1; c = 0;
... end
end endmodule
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endmodule
tb.v tb.v

Interger data type
integer i;
(32-bit) i for loop
counter.
a = 1; b = 1; c = 0;
... end
end endmodule
2022-09-17 182
endmodule
tb.v tb.v

The initial block is
like the always block Interger data type
integer i;
except that it is (32-bit) i for loop
executed just once. counter.
a = 1; b = 1; c = 0;
... end
end endmodule
2022-09-17 183
endmodule
tb.v tb.v

integer i;
a = 1; b = 0; c = 0; exhaust all #period; The loop body
a = 1; b = 1; c = 0;
... end
end endmodule
2022-09-17 184
endmodule
tb.v tb.v

integer i;
a = 1; b = 1; c = 0; Wrap up the last three bits of i
... end using “{}” and assign them all to a.
end endmodule This is equivalent to:
2022-09-17 185
endmodule a[2] = i[2], a[1] = i[1], a[0]=i[0];
tb.v tb.v

integer i;
a = 1; b = 1; c = 0; Wrap up the last three bits of i
... end using “{}” and assign them all to a.
end endmodule This is equivalent to:
2022-09-17 186
endmodule a[2] = i[2], a[1] = i[1], a[0]=i[0];
While and repeat loop statements
2022-09-17 187
tb.v
`timescale 1ns/1ps
module tb;
reg [2:0] a;
wire o;
demo_5 UUT(a[2], a[1], a[0], o);

integer i;
initial begin
i=0;
while (i < 8) begin
i = i + 1;
a = {i[2], i[1], i[0]};
#period;
end
end
endmodule
2022-09-17 188
tb.v
`timescale 1ns/1ps
module tb;
reg [2:0] a;
wire o;
demo_5 UUT(a[2], a[1], a[0], o);

integer i;
initial begin
i=0;
while (i < 8) begin
i = i + 1;
a = {i[2], i[1], i[0]};
#period;
end
end
endmodule
2022-09-17 189
tb.v
`timescale 1ns/1ps
module tb;
reg [2:0] a;
wire o;
demo_5 UUT(a[2], a[1], a[0], o);

integer i;
initial begin
i=0;
while (i < 8) begin Loop body
i = i + 1; using
a = {i[2], i[1], i[0]}; while
#period;
end
end
endmodule
2022-09-17 190
tb.v tb.v
`timescale 1ns/1ps `timescale 1ns/1ps
module tb; module tb;
reg [2:0] a; reg [2:0] a;
wire o; wire o;
demo_5 UUT(a[2], a[1], a[0], o); demo_5 UUT(a[2], a[1], a[0], o);
integer i; integer i;
i=0; i=0;
while (i < 8) begin Loop body repeat (8) begin
i = i + 1; using i = i + 1;
a = {i[2], i[1], i[0]}; while a = {i[2], i[1], i[0]};
#period; #period;
end end
end end
endmodule
2022-09-17 endmodule 191
tb.v tb.v
reg [2:0] a; reg [2:0] a;
wire o; wire o;
i=0; i=0;
while (i < 8) begin Loop body repeat (8) begin
i = i + 1; using i = i + 1;
a = {i[2], i[1], i[0]}; while a = {i[2], i[1], i[0]};
#period; #period;
end end
end end
endmodule
2022-09-17 endmodule 192
tb.v tb.v
reg [2:0] a; reg [2:0] a;
wire o; wire o;
i=0; i=0;
while (i < 8) begin Loop body repeat (8) begin Loop body
i = i + 1; using i = i + 1; using
a = {i[2], i[1], i[0]}; while a = {i[2], i[1], i[0]}; repeat
#period; #period;
end end
end end
endmodule
2022-09-17 endmodule 193
Verilog operators
2022-09-17 194
Verilog operators
Operator Name
[] Bit-select
~ Bit-Negation
& Bit-AND
| Bit-OR
~& Bit-NAND
~| Bit NOR
^ Bit XOR
~^ or ~^ Bit XNOR
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Verilog operators
Operator Name
[] Bit-select
~ Bit-Negation
& Bit-AND
| Bit-OR
~& Bit-NAND
~| Bit NOR
^ Bit XOR
~^ or ~^ Bit XNOR
wire w_reduce;
assign w_reduce = ~&tmp[3:0]
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Verilog operators
Operator Name Operator Name
[] Bit-select ! Logic-Negation
~ Bit-Negation < <= >= > Logic-Comparison
& Bit-AND == != Logic-Comparison
| Bit-OR && Logic-AND
~& Bit-NAND || Logic-OR
~| Bit NOR ?: Logic-Conditional
^ Bit XOR
~^ or ~^ Bit XNOR
wire w_reduce;
assign w_reduce = ~&tmp[3:0]
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Verilog operators
Operator Name Operator Name
[] Bit-select ! Logic-Negation
~ Bit-Negation < <= >= > Logic-Comparison
& Bit-AND == != Logic-Comparison
| Bit-OR && Logic-AND
~& Bit-NAND || Logic-OR
~| Bit NOR ?: Logic-Conditional
^ Bit XOR Operator Name
~^ or ~^ Bit XNOR {} concatenate
{{}} replication
wire w_reduce;
assign w_reduce = ~&tmp[3:0] + - * / % Arithmetic
2022-09-17 198
Verilog operators
module replication_operator();
Operator Name Operator Name reg [3:0] r_VAL_1 = 4'b0111;
[] Bit-select ! Logic-Negation parameter c_MULTIPLIER = 4'b0010;
initial
~ Bit-Negation < <= >= > Logic-Comparison begin
// Replication Only
& Bit-AND == != Logic-Comparison $display("Replication of 0x7, 3 times is 0x%h",
{3{r_VAL_1}} );
| Bit-OR && Logic-AND // Replication is possible using a constant (parameter)

// Note that replication multiplier CANNOT be a reg
$display("Replication of 0x7, %1d times is 0x%h",
~& Bit-NAND || Logic-OR c_MULTIPLIER, {c_MULTIPLIER{r_VAL_1}} );
// Replication and Concatenation together

~| Bit NOR ?: Logic-Conditional $display("Concatenate 4 with replication of 0xA twice: 0x%h",
{4'h4,{2{4'hA}}} );
^ Bit XOR Operator Name // Replication and Concatenation 2
$display("Replicate the concatenation of 0xB and 0xC 4 times: 0x%h",
~^ or ~^ Bit XNOR {} concatenate {4{4'hB, 4'hC}} );
#20;
{{}} replication $finish;
end
wire w_reduce; endmodule // replication_operator
assign w_reduce = ~&tmp[3:0] + - * / % Arithmetic
2022-09-17 199
Verilog timing control
• There are four types of timing controls in Verilog
1. Delay control
2. Edge sensitive event control
3. Level sensitive event control
4. Named events
2022-09-17 200
Delay control
• # N: delay of N time units
• Example:
Example 1
always begin
a = 1’b0;
#5;
a = 1’b1;
#3;
a=1’b0;
end
2022-09-17 201
Delay control
• Example:
Example 1
always begin
a = 1’b0;
#5;
a = 1’b1;
#3;
a=1’b0;
end
2022-09-17 202
Delay control
• Example:
Example 1 Example 2
always begin …
a = 1’b0; localparam period = 1;
#5;
a = 1’b1; integer i;
#3; initial begin
a=1’b0; i=0;
end while (i < 8) begin
i = i + 1;
a = {i[2], i[1], i[0]};
#period;
end
end
2022-09-17 203
endmodule
Delay control
• Example:
Example 1 Example 2
always begin …
a = 1’b0; localparam period = 1;
#5;
a = 1’b1; integer i;
#3; initial begin
a=1’b0; i=0;
end while (i < 8) begin
i = i + 1;
a = {i[2], i[1], i[0]}; Delay can be controlled
#period; using local var.
end Delay for 1 unit time at
end the end of each loop
2022-09-17
endmodule iteration. 204
Delay control
Example 3
• # N: delay of N time units …
• Example: reg clk;
Example 1 Example 2
always begin … initial begin
a = 1’b0; localparam period = 1; clk=0;
#5; forever begin
a = 1’b1; integer i; #period clk = ~clk;
#3; initial begin end
a=1’b0; i=0; end
end while (i < 8) begin endmodule
i = i + 1;
2022-09-17
Delay control
Clock generator Example 3
Example 1 Example 2
#5; forever begin
a=1’b0; i=0; end
i = i + 1;
2022-09-17
Delay control
Clock generator Example 3
Example 1 Example 2
#5; forever begin
a=1’b0; i=0; end
i = i + 1;
2022-09-17
Delay control – Time unit
• `timescale time_unit base / precision base
• The first argument specifies “#1” delay
• The second argument specifies the how delay values are
rounded
• Base is in
• s 1s
• ms 1-3s
• us 1-6s
• ns 1-9s
• ps 1-12s
• fs 1-15s
2022-09-17 208
rounded
• Base is in Example
• s 1s
• ms 1-3s
• us 1-6s
• ns 1-9s
• ps 1-12s
• fs 1-15s
2022-09-17 209
rounded
• s 1s
• ms 1-3s
• us 1-6s
• ns 1-9s
• ps 1-12s
• fs 1-15s
2022-09-17 210
rounded
• s 1s `timescale 1ns/1ns
• ms 1-3s
• us 1-6s
• ns 1-9s
• ps 1-12s
• fs 1-15s
2022-09-17 211
rounded
• ms 1-3s Delay Meaning Sim. Time

• us 1-6s
• ns 1-9s
• ps 1-12s
• fs 1-15s
2022-09-17 212
rounded

• us 1-6s #1 // Delay 1 ns 1
• ns 1-9s
• ps 1-12s
• fs 1-15s
2022-09-17 213
rounded

• us 1-6s #1 // Delay 1 ns 1
• ns 1-9s #0.49 // Delay 0 ns 1
• ps 1-12s
• fs 1-15s
2022-09-17 214
rounded

• us 1-6s #1 // Delay 1 ns 1
• ns 1-9s #0.49 // Delay 0 ns 1
#0.5 // Delay 1 ns 2
• ps 1-12s
• fs 1-15s
2022-09-17 215
rounded

• us 1-6s #1 // Delay 1 ns 1
• ns 1-9s #0.49 // Delay 0 ns 1
#0.5 // Delay 1 ns 2
• ps 1-12s #0.51 // Delay 1 ns 3
• fs 1-15s
2022-09-17 216
rounded

• us 1-6s #1 // Delay 1 ns 1
• ns 1-9s #0.49 // Delay 0 ns 1
#0.5 // Delay 1 ns 2
• ps 1-12s #0.51 // Delay 1 ns 3
• fs 1-15s #5 // Delay 5 ns 8
2022-09-17 217
Delay control – Gate delay
• So far, we have assumed perfect signal response time
• It takes no time for signal to change from 0 to 1
• This cannot be true in real life where the electronic properties of gates take
effect
• Three kinds of delays
2022-09-17 218
effect
• Rise delay
The time taken for the output of a gate to
change from 0,x,z, to 1 is called a rise delay.
2022-09-17 219
effect
• Rise delay
2022-09-17 220
effect
• Rise delay
• Fall delay
change from 1,x,z, to 0 is called a fall delay.
2022-09-17 221
effect
• Rise delay
• Fall delay
2022-09-17 222
effect
• Rise delay
• Fall delay
• Turn-off delay
change from 0,1,x, to z is called a turn-off delay.
2022-09-17 223
effect
• Rise delay
• Fall delay
• Turn-off delay
change from 0,1,x, to z is called a turn-off delay.
2022-09-17 224
• Verilog uses # to control rise/fall/turn-off delay of signals
• Let’t talk about gate delay of an “and” gate
2022-09-17 225
• and and1(o,a,b) // Ideal “and” gate
2022-09-17 226
• and #1 and1(o,a,b) // All delays
2022-09-17 227
• and #(1,1) and1(o,a,b) // t_rise=1, t_fall=1
2022-09-17 228
• and #(1,2,3) and1(o,a,b) // t_rise=1, t_fall=2, t_off=3
2022-09-17 229
• and #(1:2:3,2:3:4,3:4:5) and1(o,a,b) // min:typ:max
2022-09-17 230
Min Typ Max
t_rise t_fall t_max t_rise t_fall t_max t_rise t_fall t_max
1 2 3 2 3 4 3 4 5
2022-09-17 231
Min Typ Max
1 2 3 2 3 4 3 4 5
2022-09-17 232
Min Typ Max
1 2 3 2 3 4 3 4 5
2022-09-17 The default choice 233

Gate•• and
delays
and #1
are used in post-synthesis
and1(o,a,b) // Ideal “and” gate
and1(o,a,b) // All delays
timing
simulation,
• and where only
#(1,1) the gate
and1(o,a,b) delays
// t_rise=1, t_fall=1 of the
• and
• and
gate library
#(1,2,3)
vendor are used.
and1(o,a,b) // t_rise=1, t_fall=2, t_off=3
#(1:2:3,2:3:4,3:4:5) and1(o,a,b) // min:typ:max
Min Typ Max
1 2 3 2 3 4 3 4 5
2022-09-17 The default choice 234

Gate delay example
module demo_6( input a, b, output out1, out2);
and #(1:2:3, 2:3:4) and1 (out1, a, b);
and and2 (out2, a, b);
endmodule
module tb;
reg a,b;
wire out1, out2;
demo_6 UUT(a, b, out1, out2);
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 235
Gate delay example Pre-synthesis behavioral simulation
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule
module tb;
reg a,b;
wire out1, out2;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 236
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule
module tb;
reg a,b;
wire out1, out2;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 237
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule
module tb;
reg a,b;
wire out1, out2;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 238
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule
module tb;
reg a,b;
wire out1, out2;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 239
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule
module tb;
reg a,b;
wire out1, out2;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 240
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule
module tb;
reg a,b;
wire out1, out2;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 241
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule
module tb;
reg a,b;
wire out1, out2;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 242
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule
module tb;
reg a,b;
wire out1, out2;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 243
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule
module tb; 2ns

reg a,b;
wire out1, out2;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 244
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule
module tb; 2ns 3ns

reg a,b;
wire out1, out2;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 245
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule
module tb; 2ns 0ns 3ns

reg a,b;
wire out1, out2;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 246
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule
module tb; 2ns 0ns 3ns 0ns

reg a,b;
wire out1, out2;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 247
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule

reg a,b;
wire out1, out2; Post-synthesis timing simulation
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 248
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule

reg a,b;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 249
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule

reg a,b;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 250
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule

reg a,b;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 251
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule

reg a,b;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 252
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule

reg a,b;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 253
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule

reg a,b;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 254
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule

reg a,b;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end
endmodule
2022-09-17 255
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule

reg a,b;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end ~5ns
endmodule
2022-09-17 256
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule

reg a,b;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end ~5ns ~5ns
endmodule
2022-09-17 257
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule

reg a,b;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end ~5ns ~5ns
endmodule
2022-09-17 258
and #(1:2:3, 2:3:4) and1 (out1, a, b);
endmodule

reg a,b;
initial begin
{a, b} <= 0;
#10 a <= 1;
#10 b <= 1;
#10 a <= 0;
#10 b <= 0;
end ~5ns ~5ns
endmodule
2022-09-17 259
Edge sensitive event control
2022-09-17 260
• A statement happens only when the posedge and/or negedge
event happens
2022-09-17 261
event happens
1. Can be attached to sensitivity list of an “always” block
always @ (posedge clk);
2022-09-17 262
event happens
Execute the always block at each rising edge of signal “clk”
2022-09-17 263
event happens
2. Or to individual assignments
@ (posedge clk) X <= Y;
2022-09-17 264
event happens
Delay assignment X<=Y until the positive edge of “clk”.
X <= @ (posedge clk) Y;
2022-09-17 265
event happens
Read y immediately but delay the assignment to posedge “clk”.
2022-09-17 266
event happens
Read y immediately but delay the assignment to posedge “clk”.
3. At positive and/or negative edges
@(posedge x and negedge y)
@(posedge x or negedge y)
2022-09-17 267
module tb; //demo_7 module tb; //demo_7
reg clk; reg clk;

reg [2:0] a, b, c, d; reg [3:0] a, b, c, d;
clk = 0; clk = 0;
forever begin forever begin
#5 clk = ~clk; #5 clk = ~clk;
end end
end end
always begin always begin

@(posedge clk) a=3'd1; @(posedge clk) a<=3'd1;
@(posedge clk) b=3'd2; @(posedge clk) b<=3'd2;
@(posedge clk) c=3'd3; @(posedge clk) c<=3'd3;
@(posedge clk) d=3’d4; @(posedge clk) d<=3’d4;
$display("time is %0t",$time); $display("time is %0t",$time);
end end
endmodule endmodule
2022-09-17 268
reg clk; reg clk;

reg [2:0] a, b, c, d; reg [3:0] a, b, c, d;
clk = 0; clk = 0;
end end
end end

end end
endmodule endmodule
2022-09-17 269
reg clk; reg clk;

reg [2:0] a, b, c, d; reg [3:0] a, b, c, d;
clk = 0; clk = 0;
end end
end end

end end
endmodule endmodule
2022-09-17 270
reg clk; reg clk;

reg [2:0] a, b, c, d; reg [3:0] a, b, c, d;
clk = 0; clk = 0;
end time is 35 ns end
time is 115 ns
always begin time is 155 ns always begin
@(posedge clk) a=3'd1; time is 195 ns @(posedge clk) a<=3'd1;
@(posedge clk) b=3'd2; time is 235 ns @(posedge clk) b<=3'd2;
@(posedge clk) c=3'd3; time is 275 ns @(posedge clk) c<=3'd3;
@(posedge clk) d=3’d4; time is 315 ns @(posedge clk) d<=3’d4;
$display("time is %0t",$time); time is 355 ns $display("time is %0t",$time);
endmodule time is 435 ns endmodule
2022-09-17 271
reg clk; reg clk;

reg [2:0] a, b, c, d; reg [3:0] a, b, c, d;
clk = 0; clk = 0;
end time is 35 ns end time is 35 ns
time is 115 ns time is 115 ns
always begin time is 155 ns always begin time is 155 ns
@(posedge clk) a=3'd1; time is 195 ns @(posedge clk) a<=3'd1; time is 195 ns
@(posedge clk) b=3'd2; time is 235 ns @(posedge clk) b<=3'd2; time is 235 ns
@(posedge clk) c=3'd3; time is 275 ns @(posedge clk) c<=3'd3; time is 275 ns
@(posedge clk) d=3’d4; time is 315 ns @(posedge clk) d<=3’d4; time is 315 ns
$display("time is %0t",$time); time is 355 ns $display("time is %0t",$time); time is 355 ns
endmodule time is 435 ns endmodule time is 435 ns
2022-09-17 272
Level sensitive event control
• @(X, Y)
• A block will be executed each time a variable changes its value
• @* or @(*)
• A block will be executed at change of any variable that is read in its
scope
• Always use blocking assignment “=” inside @*/@(*)
• wait( )
• A block will be executed until a condition becomes true within the wait()
function.
2022-09-17 273
Example of wait()
module tb;
reg [3:0] ctr;
reg clk;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
$display ("T=%0t Counter reached non-zero value 0x%0h", $time, ctr);
wait (ctr == 4’b0100)
$display ("T=%0t Counter reached 0x%0h", $time, ctr);
$finish;
end
always clk = #10 ~clk;
always @ (posedge clk)

ctr <= ctr + 1;
2022-09-17 274
endmodule
Example of wait()
module tb;
reg [3:0] ctr;
reg clk;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
$finish;
end

ctr <= ctr + 1;
2022-09-17 275
endmodule
Example of wait()
module tb;
reg [3:0] ctr;
reg clk;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
$finish;
end

ctr <= ctr + 1;
2022-09-17 276
endmodule
Example of wait()
module tb;
reg [3:0] ctr;
reg clk;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
$finish;
end

ctr <= ctr + 1;
2022-09-17 277
endmodule
Example of wait()
module tb;
reg [3:0] ctr;
reg clk; Executed at simulation
time 0. {ctr, clk} <=0
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
$finish;
end

ctr <= ctr + 1;
2022-09-17 278
endmodule
Example of wait()
module tb;
reg [3:0] ctr;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
$finish;
end

ctr <= ctr + 1;
2022-09-17 279
endmodule
Example of wait()
module tb;
reg [3:0] ctr;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
$finish; Executed at simulation
end time 0.

ctr <= ctr + 1;
2022-09-17 280
endmodule
Example of wait()
module tb;
reg [3:0] ctr;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
always clk = #10 ~clk; Blocked for 10 UT.

ctr <= ctr + 1;
2022-09-17 281
endmodule
Example of wait()
module tb;
reg [3:0] ctr;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
always @ (posedge clk) Executed at

ctr <= ctr + 1; simulation time 0.
2022-09-17 282
endmodule
Example of wait()
module tb;
reg [3:0] ctr;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.

2022-09-17
Blocked until 283
endmodule posedge clk.
Example of wait()
module tb;
reg [3:0] ctr;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.

2022-09-17
Blocked until 284
Example of wait()
module tb; Initial block first
reg [3:0] ctr;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.

2022-09-17
Blocked until 285
Example of wait()
reg [3:0] ctr;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1
Blocked for 10 UT.
2022-09-17
Blocked until 286
Example of wait()
reg [3:0] ctr;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1
Blocked for 10 UT.
2022-09-17
Blocked until 287
Example of wait()
reg [3:0] ctr;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1
Blocked for 10 UT.
2022-09-17
Blocked until 10 UT: ctr = 1 288
endmodule posedge clk. Wait for posedge.
Example of wait()
reg [3:0] ctr;
initial begin
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1
Blocked for 10 UT.
2022-09-17
Example of wait()
reg [3:0] ctr;
time 0. {ctr, clk} <=0 10 UT: execute the
first $display.
initial begin Blocked until crt is 4
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1
Blocked for 10 UT.
2022-09-17
Example of wait()
reg [3:0] ctr;
first $display.
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1
Blocked for 10 UT.
2022-09-17
Example of wait()
module tb; Initial block first Trigger order
reg [3:0] ctr;
first $display.
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1
Blocked for 10 UT.
2022-09-17
Example of wait()
reg [3:0] ctr;
first $display.
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1 20 UT: clk = 0
Blocked for 10 UT. Blocked for 10 UT.
2022-09-17
Example of wait()
reg [3:0] ctr;
first $display.
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1 20 UT: clk = 0
always @ (posedge clk) Executed at 70 UT: clk = 1
ctr <= ctr + 1; simulation time 0. Blocked for 10 UT.
2022-09-17
Example of wait()
reg [3:0] ctr;
first $display.
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1 20 UT: clk = 0
2022-09-17
Example of wait()
reg [3:0] ctr;
first $display.
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1 20 UT: clk = 0
2022-09-17
Blocked until 10 UT: ctr = 1 70 UT:296
ctr = 4
endmodule posedge clk. Wait for posedge. Blocked for 10 UT.
Example of wait()
reg [3:0] ctr;
first $display.
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1 20 UT: clk = 0
2022-09-17
ctr = 4
Example of wait()
reg [3:0] ctr;
time 0. {ctr, clk} <=0 10 UT: execute the 70 UT: execute the
first $display. second $display.
initial begin Blocked until crt is 4 Simulation finishes.
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1 20 UT: clk = 0
2022-09-17
ctr = 4
Example of wait()
reg [3:0] ctr;
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1 20 UT: clk = 0
2022-09-17
ctr = 4
Example of wait()
module tb; Initial block first Trigger order Trigger order
reg [3:0] ctr;
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1 20 UT: clk = 0
2022-09-17
ctr = 4
Example of wait()
reg [3:0] ctr;
A hideous Executed at simulation
reg clk; 10 UT: execute the 70 UT: execute the
bug here time 0. {ctr, clk} <=0
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1 20 UT: clk = 0
2022-09-17
ctr = 4
Example of wait()
reg [3:0] ctr;
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
wait (ctr == 4’b0100)
end time 0.
10 UT: clk = 1 20 UT: clk = 0
2022-09-17
ctr = 4
Example of wait()
reg [3:0] ctr;
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
Should$display
be ("T=%0t Counter reached non-zero value 0x%0h", $time, ctr);
=, notwait
<= (ctr == 4’b0100)
end time 0.
10 UT: clk = 1 20 UT: clk = 0
2022-09-17
ctr = 4
Example of wait()
reg [3:0] ctr;
{ctr, clk} <= {4’b0000, 1’b0};
wait (ctr);
Should$display
be ("T=%0t Counter reached non-zero value 0x%0h", $time, ctr);
=, notwait
<= (ctr == 4’b0100)
end time 0.
10 UT: clk = 1 20 UT: clk = 0
2022-09-17
ctr = 4
Verilog function vs task
• Verilog provides function and task for code reuse.
• Help to improve reusability readability in large projects.
• They are similar but differ in many aspects.
2022-09-17 305
• Verilog provides Function
function and task for code reuse. Task
1 Do not allow initial or always block.
• Help to improve reusability readability in large projects.
2022-09-17 306
• Verilog provides Function function and task for code reuse. Task
• Help
2 A to improve
function reusability
takes 0 simulation readability
time to execute. intakes
A task large projects.
arbitrary simulation time to execute
depending on the timing control statements within.
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• Help
2 A to improve
• They
3
are similar but differ in many aspects.
A function cannot contain timing control statements A task can contain timing control statements.
such as: # delay, posedge, negedge, etc.
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• Help
2 A to improve
• They
3
4 A function can call other functions but can not call A task can call other functions or tasks.
tasks. (Because of rule 2 and 3)
(Because of Rule 2 & 3)
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• Help
2 A to improve
• They
3
5 A function must have at least one input argument A task can have any number (zero or more) of
but cannot have output arguments. input and output ports.
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• Help
2 A to improve
• They
3
6 A function can return a single value. A task cannot return a value but can achieve the
same effect using output arguments.
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• Help
2 A to improve
• They
3
7 A function can be called in an expression or can be A task must be specifically called with a statement.
called with a statement (disconnected function). (Because of Rule 5 and 6)
2022-09-17 (Because of Rule 5 and 6) 312
• Help
2 A to improve
• They
3
are
Rules
similar but
of
differ
thumb
in many
No.6:
aspects.
4 Usecanfunction
A function to
call other functions but can model
not call A taskcombi-logic.
can call other functions or tasks.
Use task toofmodel either combi- or sequential logic.

(Because Rule 2 & 3)
7 A function can be called in an expression or can be A task must be specifically called with a statement.
called with a statement (disconnected function). (Because of Rule 5 and 6)
2022-09-17 (Because of Rule 5 and 6) 313
module has_function (x_in, rev_x); //demo_9 module has_task (x_in, rev_x); //demo_9
parameter maxbits = 8; parameter maxbits = 8;
input [maxbits - 1 : 0] x_in; input [maxbits - 1 : 0] x_in;

output reg [maxbits - 1 : 0] rev_x; output reg [maxbits - 1 : 0] rev_x;
function [maxbits - 1 : 0] reverse_bits; task reverse_bits;
input [maxbits - 1 : 0] din; input [maxbits - 1 : 0] din;

output [maxbits - 1 : 0] dout;
integer k; integer k;
begin begin
for (k=0; k < maxbits; k = k +1) for (k=0; k < maxbits; k = k +1)
reverse_bits[maxbits-1-k] = din[k]; dout[maxbits-1-k] = din[k];
end end
endfunction endtask
always @ (x_in) always @ (x_in)

rev_x = reverse_bits(x_in); reverse_bits(x_in, rev_x);
endmodule endmodule
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input [maxbits - 1 : 0] din; input [maxbits - 1 : 0] din;

integer k; integer k;
begin begin
end end
endfunction endtask

endmodule endmodule
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function name is the
input [maxbits - 1 : 0] din; implicit output reg name. input [maxbits - 1 : 0] din;
Don’t declare your local
integer k; reg with the same name! integer k;
begin begin
end end
endfunction endtask

endmodule endmodule
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begin begin
end end
endfunction endtask

endmodule endmodule
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begin begin
end end
endfunction endtask

endmodule endmodule
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Questions?
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Verilog II

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Verilog II

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Accelerating Systems with

Programmable Logic Components

Yuan Yao, yuan.yao@it.uu.se

2022-09-17 Courtesy to Philipp Rümmer 1

not Not1(.out(w_not), .in1(C));

assign O = (A & ~C) | (B & C);

not Not1(.out(w_not), .in1(C));

assign O = (A & ~C) | (B & C);

wire w_not, w_and1, w_and2;

not Not1(.out(w_not), .in1(C));

assign O = (A & ~C) | (B & C);

wire w_not, w_and1, w_and2;

not Not1(.out(w_not), .in1(C));

assign O = (A & ~C) | (B & C);

wire w_not, w_and1, w_and2;

not Not1(.out(w_not), .in1(C));

assign O = (A & ~C) | (B & C);

wire w_not, w_and1, w_and2;

not Not1(.out(w_not), .in1(C));

assign O = (A & ~C) | (B & C);

wire w_not, w_and1, w_and2; connecting wire

not Not1(.out(w_not), .in1(C));

assign O = (A & ~C) | (B & C);

wire w_not, w_and1, w_and2; connecting wire

not Not1(.out(w_not), .in1(C));

assign O = (A & ~C) | (B & C);

wire w_not, w_and1, w_and2; connecting wire

not Not1(.out(w_not), .in1(C));

assign O = (A & ~C) | (B & C);

wire w_not, w_and1, w_and2; connecting wire

not Not1(.out(w_not), .in1(C));

assign O = (A & ~C) | (B & C);

wire w_not, w_and1, w_and2; connecting wire

not Not1(.out(w_not), .in1(C));

assign O = (A & ~C) | (B & C); data-flow level modeling

This is for combinational logic.

wire w_not, w_and1, w_and2; connecting wire

not Not1(.out(w_not), .in1(C));

assign O = (A & ~C) | (B & C); data-flow level modeling

Input Output = Input + 1

Input Output = Input + 1

Input Output = Input + 1

Input Output = Input + 1

Input Output = Input + 1

Input Output = Cur

Input Output = Cur

Input Output = Cur

Input Output = Cur

Input Output = Cur

Input Output = Cur

Delay=X > threshold

Delay=X > threshold

Delay=X > threshold

Delay=X > threshold

Delay=X > threshold

Delay=X > threshold

Delay=X > threshold

Delay=X > threshold

Delay=X > threshold

Delay=X > threshold

Delay=X > threshold

Delay=X/2 < threshold

Delay=X > threshold