EEE413/ETE419/CSE413

Verilog HDL: Modeling and Simulation

Lab-01: Introduction with Modelsim .Design ‘AND’ gate with gate

level Modeling

A basic AND gate in modelsim is a 2- input and gate with input pin A and B. The output
pin is O and it has the following truth table:

A (INPUT 1) B (INPUT2) O (OUTPUT)

0 0 0
0 1 0
1 0 0
1 1 1

Now we will write the verilog code in MODELSIM and check whether we get the
same truth table or not.

Main Module:
(and2.v)
module and2 (o, a, b);
output o; // o is output of 1-bit wide
input a, b; //a, b are inputs of 1-bit wide
and a1(o, a, b); // this line is the main(instantiation) part of the gate level modeling
endmodule

Test Bench:
(stimulus. v)
module stimulus; // Define the stimulus module (no ports)
wire O; // Declare output wire
reg A,B; // Declare variables to be connected to inputs
// Instantiate the Design Under Test (DUT)
and2 b1(O,A,B);
initial
begin
$monitor($time, "O=%b, A=%b , B=%b", O, A, B);
//monitor time and the value of the signals O, A and B
end
// Stimulate the inputs
initial
begin
#3 A=1'b0; B=1'b0; //A=0;B=0;
 #5 A=1'b0; B=1'b1; //A=0;B=1;
#5 A=1'b1; B=1'b0; //A=1;B=0;
#5 A=1'b1; B=1'b1; //A=1;B=1;
#20 $finish; //End the simulation
end
endmodule