Verilog I

Accelerating Systems with
Programmable Logic Components

Lecture 03 FPGAs + Verilog I
1DT109 ASPLOC
2022 VT1-VT2
Yuan Yao, yuan.yao@it.uu.se
2022-09-17 1
Agenda
• Introduction to PLD and FPGAs
• PLD
• FPGA and its enablers
• Know your MINIZED board
• FPGA design flow
• Verilog I
• Introduction to Verilog
• Gate-level modeling using Verilog
• Data-flow/RTL-level modeling using Verilog
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Introduction to PLD and FPGAs
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Need for programmable logic devices (PLD)
• PROM – early 70’s
• EPROM – early 70’s
• PLA – mid 70’s
• PAL – late 70’s
• EEPROM – early 80’s
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Programmable Read-Only Memory (PROM)
• Programmable Read-Only
Memory (PROM) - early 70’s
• Address-line used as inputs
(in canonical normal form)
• The value stored at an
address defines the output
for the specified input
• One-time programmable
(OTP) using fuse/anti-fuse
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A PROM example
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A PROM example
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A PROM example
Address Data
A0 A1 D3 D2 D1 D0
0 0 0 1 0 0
0 1 0 1 0 1
1 0 1 0 0 1
1 1
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0 0 1 0 8
Erasable PROM (EPROM)
• Erasable PROM (EPROM)
• Erased by Ultraviolet light
• An Intel 1702A EPROM,
one of the earliest EPROM
types (1971), 256 by 8 bit.
• The small quartz window
admits UV light for erasure.
• BIOS in old PCs
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Programmable logic array (PLA)
• Mid 1970’s
• Programmable AND and OR
gates matrices (planes)
• Flexible
• Support large number of
functions
• Expensive
• Slow
• Hard to program
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Programmable array logic (PAL)
• Late 1970’s
• Programmable AND and
fixed OR gates
• Less flexible
• Support limited number of
functions
• Cheap
• Fast
• Hard to program but easier
than PLA
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Programmable array logic (PAL)
• Late 1970’s
• Programmable AND and
Electronical world always welcomes
fixed OR gates
• Less flexible
• Support cheap
limited numberand
of fast things.
functions
• Cheap
• Fast
• Hard to program but easier
than PLA
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Electronically EPROM (EEPROM)
• Early 80’s
• Breakthrough in PLD
• Metal + Oxide + Semi-
conductor = MOS
• Breakthrough in information
storage
• Flexible
• Cheap
• Fast
• Easy to program
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• Early 80’s
• Breakthrough in PLD Metal
(Semi
• Metal + Oxide + Semi- nowadays)
conductor = MOS
storage
• Flexible
• Cheap
• Fast
• Easy to program
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• Early 80’s
(Semi
conductor = MOS
storage Oxide
• Flexible
• Cheap
• Fast
• Easy to program
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• Early 80’s
(Semi
conductor = MOS
storage Oxide
• Flexible
• Cheap Semi-conductor
• Fast
• Easy to program
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EEPROM: Write the “1” bit
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(High voltage)
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(High voltage)
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Can last for 10+ years!
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Field Programmable Gate Array (FPGA)
• Mid 80’s
• Xilinx co-founders Ross Freeman and Bernard
Vonderschmitt invented the first commercially viable field-
programmable gate array in 1985 – the XC2064.
• 64 logic blocks only
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FPGA – Xilinx timeline
• 1985: View and configure logic and routing resources
manually
• “High-level” features such as Boolean expressions, K-maps,
truth-tables, etc
• 1986: Automatic transition from schematic to physical
(automatic placing & routing)
• We will learn how EDA plays a routing algorithm in Lecture 7
• 1995: Hardware Description Languages (HDL)
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FPGA - Architecture
• Overall idea:
Connecting simple
but distributed
reconfigurable
units (called logic
blocks) together
towards complicated
functions.
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FPGA – Configurable Logic Block (CLB)
• The Look Up Table
(LUT) can implement
any function for the
input combinations.
• The Flip-Flop (FF) is
used for store the
result of the LUT.
• The Mux can
implement the CLB
as combinational or
sequential logic.
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CLB - LUT
LUT
• Core of the FPGA architecture. 0
• Change the contents of the 1

SRAM to define outputs for 0
different input patterns. 0
1 1 0
A B C Output
1
0 0 0 SRAM0 0 0
0 0 1 SRAM1
0 1 0 SRAM2
1 1
0 1 1 SRAM3
1 0 0 SRAM4 0
1 0 1 SRAM5
1
1 1 0 SRAM6
1 1 1 SRAM7
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CLB - LUT
LUT
Write into mem to reconfigure LUT.

SRAM to define outputs for
0 0
different input patterns.
1 1 0
A B C Output
1
0 0 0 SRAM0 0 0
0 0 1 SRAM1
0 1 0 SRAM2
1 1
0 1 1 SRAM3
1 0 0 SRAM4 0
1 0 1 SRAM5
1
1 1 0 SRAM6
1 1 1 SRAM7
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CLB - LUT
LUT
Write into mem to reconfigure LUT.

SRAM to define outputs for
0 0
different input patterns.
How to implement 2-bits output
A B C Output
1 1 0
functions for input A,B,C?

1
0 0 0 SRAM0 0 0
0 0 1 SRAM1
0 1 0 SRAM2
1 1
0 1 1 SRAM3
1 0 0 SRAM4 0
1 0 1 SRAM5
1
1 1 0 SRAM6
1 1 1 SRAM7
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How to implement the following function
using the CLB we introduced?
A B C O1 O2
0 0 0 1 0
0 0 1 0 0
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 1
1 1 1 0 1
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How to implement the following function
using the CLB we introduced?
A B C O1 O2
0 0 0 1 0
0 0 1 0 0
Using Two LUTs across Two CLBs!
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 1
1 1 1 0 1
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Implement O1 in CLB1
LUT in CLB1
1 0
A B C O1 O2
0 1
0 0 0 1 0
0
0 0 1 0 0 1 0
1 0
0 1 0 1 1 1 1
1 O1
0 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1
1 0 1 1 0 1 0
1 1 0 1 1 0 1
1
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1 1 0 1 130
Implement O2 in CLB2
LUT in CLB2
0 0
A B C O1 O2
0 1
0 0 0 1 0
0
0 0 1 0 0 1 0
1 0
0 1 0 1 1 0 1
1 O2
0 1 1 1 0 1 0 0
1 0 0 0 1 0 1 1
1 0 1 1 0 1 0
1 1 0 1 1 1 1
1
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1 1 0 1 131
Connecting CLB1 and CLB2
ABC O2
O1
• Connecting CLBs
can only be done
using the CLB1
programmable
interconnect,
which resides CLB2
outside the CLBs.
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FPGA - programmable interconnect
• Programmable switch
matrices (PSMs)
• Connecting CLBs
• Are reconfigurable
themselves!
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matrices (PSMs)
• Connecting CLBs
themselves!
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matrices (PSMs)
• Connecting CLBs
themselves!
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matrices (PSMs)
• Connecting CLBs
themselves!
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Switch matrix interconnect point
• With a 6-bit memory bitfield, 6
switched can be controlled at
one intersection. Hence, all
connection possibilities can be
achieved.
M0 M1 M2 M3 M4 M5
0 0 0 0 0 1 a-b
0 0 0 0 1 0 b-d
0 0 0 1 0 0 a-d
0 0 1 0 0 0 a-c
0 1 0 0 0 0 c-d
1 0 0 0 0 0 b-d
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Switch matrix interconnect point
• With a 6-bit memory bitfield, 6
switched can be controlled at
Write into mem to reconfigure

one intersection. Hence, all
connection possibilities can be
connections.
achieved.
M0 M1 M2 M3 M4 M5
0 0 0 0 0 1 a-b
0 0 0 0 1 0 b-d
0 0 0 1 0 0 a-d
0 0 1 0 0 0 a-c
0 1 0 0 0 0 c-d
1 0 0 0 0 0 b-d
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FPGA – I/O blocks
• Tri-state gate.
• In the output mode, the
output buffer is switched
on and the input buffer
switched off.
• In the input mode, the
off and the input buffer
switched on.
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FPGA – I/O blocks
• Tri-state gate.
• In the output mode, the
on and the input buffer
switched off.
• In the input mode, the
off and the input buffer
switched on.
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FPGA – past and now
Xilinx XC2064 Xilinx XCVU440 Xilinx Zynq 7Z007S

Logic cells 64 4.4M 23K
CLB Flip-Flops 64 5.0M ??
Total Block RAM 0 88.6Mb 1.8Mb
DSP Slices 0 2880 0
Maximum Number of
38 1456 54
I/O Pins
Differential Multi-Gigabit
0 48 0
Transceivers
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Total Block RAM 0 Still, compared
88.6Mb to ASICs: 1.8Mb
DSP Slices 0FPGAs require 2880
20-35x more area0
Maximum Number of
38
10x more
1456
power 54
I/O Pins
But 3-4x slower
0 48 0
Transceivers
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But FPGAs are cheap and easy/quick

to do implementation!
Total Block RAM 0 Still, compared
88.6Mb to ASICs: 1.8Mb
DSP Slices 0FPGAs require 2880
20-35x more area0
Maximum Number of
38
10x more
1456
power 54
I/O Pins
But 3-4x slower
0 48 0
Transceivers
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The MINIZED starter kit board
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FPGA
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FPGA
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FPGA
Mem
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FPGA
Mem
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Flash
FPGA
Mem
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Flash
FPGA
Mem
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Flash
Boot
Loader
Flash
FPGA
Mem
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Flash
Boot
Loader
Flash
FPGA
Mem
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Flash
Boot
Loader
Flash
FPGA
Mem
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Flash
Boot
Loader
Flash
FPGA
Mem
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Flash
Boot
Loader
Flash
FPGA
Mem
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Flash
Boot
Loader
Flash
FPGA
Mem
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The MINIZED starter kit board PS
Flash
Boot
Loader
Flash
FPGA
Mem
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Flash
Boot
Loader
Flash
FPGA
Mem
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Flash
Boot
Loader
Flash
FPGA
Mem
PL
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FPGA applications
• Test and prototyping before ASIC
• Low-volume production (military, space, etc)
• Accelerators (PS+PL)
• Resilience to cosmic radiation (re-programmability)
From https://forums.xilinx.com/t5/Xilinx-Xclusive-
Blog/Touchdown-NASA-s-Perseverance-Rover-Lands-on-
Mars-with-Xilinx/ba-p/1209732
Hello MARS...Congratulations to the amazing engineers
and scientists at NASA and Jet Propulsion Labs (JPL) for
a successful touchdown on the Mars Jezero Crater on
February 18, 2021! We are so proud to be part of this
mission with Xilinx FPGAs in the lander rover and
instruments, including the vision processor to perform
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FPGA design flow
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FPGA design flow
Early Days
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FPGA design flow
Early Days
Schematic entry
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FPGA design flow
Early Days
Schematic entry
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FPGA design flow
Early Days
Schematic entry
Design deploying to
FPGA
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FPGA design flow
Early Days
Schematic entry
Design deploying to
FPGA
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FPGA design flow
Early Days
Schematic entry
Design deploying to
FPGA
Program FPGA
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FPGA design flow
Early Days
Schematic entry
Design deploying to
FPGA
Program FPGA
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FPGA design flow
Early Days
Schematic entry
Design deploying to
FPGA
Program FPGA
Test FPGA In-System
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FPGA design flow
Early Days
Schematic entry
Design deploying to
FPGA
Program FPGA
Test FPGA In-System
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FPGA design flow
Early Days
Schematic entry
Design deploying to
FPGA
Debug
Program FPGA
Test FPGA In-System
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FPGA design flow
Early Days
Schematic entry
Design deploying to
FPGA
Debug
Program FPGA
Test FPGA In-System
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Today
FPGA design flow
Early Days
Schematic entry
Design deploying to
FPGA
Debug
Program FPGA
Test FPGA In-System
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Today
FPGA design flow
Early Days HDL & Graphic entry
Schematic entry
Design deploying to
FPGA
Debug
Program FPGA
Test FPGA In-System
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Today
FPGA design flow
Schematic entry
Functional verification
Design deploying to
FPGA
Debug
Program FPGA
Test FPGA In-System
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Today
FPGA design flow
Schematic entry
Design deploying to
FPGA
Debug
Program FPGA
Test FPGA In-System
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Today
FPGA design flow
Schematic entry Debug

Design deploying to
FPGA
Debug
Program FPGA
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
FPGA
Debug
Program FPGA
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
FPGA
Debug
Program FPGA
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Program FPGA
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Program FPGA
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Routing
Program FPGA
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Routing
Program FPGA
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Routing
Program FPGA
Timing verification
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Routing
Program FPGA
Timing verification
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Routing
Program FPGA
Timing verification
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Debug
Routing
Program FPGA
Timing verification
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Debug
Routing
Program FPGA
Timing verification
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Debug
Routing
Program FPGA
Timing verification
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Debug
Routing
Program FPGA
Timing verification
Test FPGA In-System

Program & System test
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Debug
Routing
Program FPGA
Timing verification
Test FPGA In-System

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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Debug
Routing
Program FPGA
Timing verification
Debug
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Debug
Routing
Program FPGA
Timing verification
Debug
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Debug
Routing
Program FPGA
Timing verification
Debug
Test FPGA In-System
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Today
FPGA design flow

Design deploying to
Synthesis
FPGA
Debug
Map & Place &
Debug
Routing
Program FPGA
Timing verification
Debug
Test FPGA In-System
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Verilog I
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Introduction to Verilog HDL
• Verilog is a Hardware Description Language
(HDL)
• A hardware description language is a language
used to describe a digital system
• Why using an HDL?
• Design abstraction: HDL v.s. layout by human
• Reduce cost and time to design hardware
• Design reuse (IPs)
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Brief history of HDLs
• Late 70’s and early 80’s
• ISP, HiLo, PALASM, CUPL, ABEL, etc
• 1971: Notion of “Register Transfer Level” (RTL) modeling
• Mid 80’s:
• Verification & Logic (Verilog) by Gateway Design Automation
• C-like simulation language
• 1989: Cadence acquires Gateway Design Automation
• 1990: Verilog in public domain
• Very High-speed integrated circuit hardware Description Language
(VHDL) by US Department of Defense
• Ada-like syntax
• Used for documentation and simulation
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Brief history of HDLs All require working
with Boolean functions
• Late 70’s and early 80’s to some extent.
• Mid 80’s:
• Very High-speed integrated circuit hardware Description Language
(VHDL) by US Department of Defense
• Ada-like syntax
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Brief history of HDLs All require working
with Boolean functions
• Late 70’s and early 80’s to some extent.
• Mid 80’s:
• Very High-speed integrated circuit hardware Description Better
Language
(VHDL) by US Department of Defense abstraction!
• Ada-like syntax
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Think in hardware, not in software
• Verilog is for hardware C Verilog
modeling/specification a=1; a=1;

• The model/specification b=2;
c=0;
b=2;
c=0;
can be simulated and
then synthesized into a=b; // a=b=2 a <= b; // a=b=2
c=a; // c=a=b=2 c <= a; // c=a=1
hardware
Compiled to the following Synthesized to the following
• Think in hardware! sequential instructions: concurrent hardware structure:
• Explicit notion of
time/concurrency Load %a, %b // Synthesize the
Load %c, %a design in Vivado
• Data-flow
Result: c=a=b=2 Result: c=1, a=b=2;
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• The model/specification b=2;
c=0;
b=2;
c=0;
then synthesized into a=b; // a=b=2 a <= b; // a=b=2
c=a; // c=a=b=2 c <= a; // c=a=1
hardware
• Data-flow
2022-09-17 202
Think in hardware.
• The model/specification b=2; b=2;
c=0; c=0;
Schema come first than code.
then synthesized into
hardware
a=b; // a=b=2
c=a; // c=a=b=2
a <= b; // a=b=2
c <= a; // c=a=1

• Data-flow
2022-09-17 203
Demo 1
• Blocking/non-blocking assignments.
Verilog Verilog
//demo_1 //demo_2
a=1; a=1;
b=2; b=2;
c=0; c=0;
a <= b; // a=b=2 a = b; // a=b=2

c <= a; // c=a=1 c = a; // c=a=2
Synthesized to the following Synthesized to the following

concurrent hardware structure: concurrent hardware structure:
// Synthesize the // Synthesize the

design in Vivado design in Vivado
2022-09-17 204
Result: c=1, a=b=2; Result: c=a=b=2;
Demo 1
Verilog Verilog
//demo_1 //demo_2
a=1; a=1;
b=2; b=2;
c=0; c=0;
a <= b; // a=b=2 a = b; // a=b=2

c <= a; // c=a=1 c = a; // c=a=2


2022-09-17 205
Demo 1
Verilog Verilog
//demo_1 //demo_2
a=1; a=1;
b=2; b=2;
c=0; c=0;
a <= b; // a=b=2 a = b; // a=b=2

c <= a; // c=a=1 c = a; // c=a=2


2022-09-17 206
Verilog supports various levels of abstraction
1. Less detail
• Behavioral model (relying more on EDA)
2. Faster simulation
• Data flow model or 3. Shorter time-to-market
register transfer level 4. Less optimization
(RTL) model
• Gate level model 1. More detail
(relying less on EDA)
• Switch level model or 2. Slower simulation
transistor level model 3. Longer time-to-market
4. More optimization
2022-09-17 207
In more detail, verilog can model…
• Constructs used only for simulation
• Gate delays
• Signal strength
• Verilog procedural interface (VPI)
• Facilities for debugging/verification
• ...
• Constructs used for both simulation and synthesis
• Registers
• Wires
• Assignments
• Operators
•…
2022-09-17 208
Use synthesizable constructs for
• Gate delays
• Signal strength
HW interface
• Verilog procedural implementation.
(VPI)
• ...
• Registers
• Wires
• Assignments
• Operators
•…
2022-09-17 209
Use synthesizable constructs for
• Gate delays
• Signal strength
HW interface
• Verilog procedural implementation.
(VPI)
Use• ...non-synthesizable constructs for
verification/debugging.
• Registers
• Wires
• Assignments
• Operators
•…
2022-09-17 210
Verilog example (digital design recap)
• Implement the following function use Verilog
A B C O
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
2022-09-17 211
A B C O
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
2022-09-17 212
A B C O
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
2022-09-17 213
A B C O
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
2022-09-17 214
A B C O
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
2022-09-17 215
A B C O
0 0 0 0
0 0 1 0 𝑂 =𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
2022-09-17 216
A B C O
0 0 0 0
0 0 1 0 𝑂 =𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶
0 1 0 0 𝑂 =𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
2022-09-17 217
A B C O
0 0 0 0
0 0 1 0 𝑂 =𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶
0 1 0 0 𝑂 =𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶
0 1 1 1
1 0 0 1
𝑂 = 𝐴 + 𝐴 ∙ 𝐵 ∙ 𝐶 + 𝐴 ∙ 𝐶 ∙ (𝐵 + 𝐵)
1 0 1 0
1 1 0 1
1 1 1 1
2022-09-17 218
A B C O
0 0 0 0
0 0 1 0 𝑂 =𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶
0 1 0 0 𝑂 =𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶
0 1 1 1
1 0 0 1
𝑂 = 𝐴 + 𝐴 ∙ 𝐵 ∙ 𝐶 + 𝐴 ∙ 𝐶 ∙ (𝐵 + 𝐵)
1 0 1 0 𝑂 =𝐴∙𝐶+𝐵∙𝐶
1 1 0 1
1 1 1 1
2022-09-17 219
A B C O
Let us start with

0
0
0
0𝑂 =gate-level
𝐴 ∙ 𝐵 ∙ 𝐶 + 𝐴 ∙ 𝐵 ∙ 𝐶 + 𝐴 ∙modeling.
0
1
0
0 𝐵∙𝐶+𝐴∙𝐵∙𝐶
0 1 0 0 𝑂 =𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶+𝐴∙𝐵∙𝐶
0 1 1 1
1 0 0 1
𝑂 = 𝐴 + 𝐴 ∙ 𝐵 ∙ 𝐶 + 𝐴 ∙ 𝐶 ∙ (𝐵 + 𝐵)
1 0 1 0 𝑂 =𝐴∙𝐶+𝐵∙𝐶
1 1 0 1
1 1 1 1
2022-09-17 220
Step 1 – Schema comes first than code
2022-09-17 221
𝑂 =𝐴∙𝐶+𝐵∙𝐶
2022-09-17 222
my_module
A
And1
Not1
B
Or1 O
And2
C
2022-09-17 223
Step 2 – Model the module using gale-level Verilog
2022-09-17 224
module my_module(A, B, C, O); 𝑂 =𝐴∙𝐶+𝐵∙𝐶
2022-09-17 225
endmodule
2022-09-17 226
endmodule
2022-09-17 227
my_module
declaration
endmodule
2022-09-17 228
my_module
declaration
my_module
endmodule
2022-09-17 229
my_module
declaration
my_module
endmodule
2022-09-17 230
input A, B, C; my_module
declaration
my_module
endmodule
2022-09-17 231
output O; declaration
my_module
endmodule
2022-09-17 232
my_module
endmodule
2022-09-17 233
input A, B, C; input/output my_module

my_module
endmodule
2022-09-17 234

my_module
endmodule
2022-09-17 235

my_module
endmodule
2022-09-17 236

my_module
endmodule
2022-09-17 237

my_module
endmodule
2022-09-17 238

my_module
endmodule
C
2022-09-17 239

my_module
endmodule
C
2022-09-17 240

my_module
B
O
endmodule
C
2022-09-17 241

my_module
B
O
endmodule
C
2022-09-17 242

not Not1();
my_module
B
O
endmodule
C
2022-09-17 243

not Not1();
and And1(); my_module
B
O
endmodule
C
2022-09-17 244

not Not1();
and And2();
A
B
O
endmodule
C
2022-09-17 245

not Not1();
and And2();
A
or Or1();
B
O
endmodule
C
2022-09-17 246

not Not1();
and And2();
A
or Or1();
B
O
endmodule
C
2022-09-17 247

not Not1(); sub module

and And2();
A
or Or1();
B
O
endmodule
C
2022-09-17 248


and And2();
A And
or Or1(); 1
B
O
endmodule
C
2022-09-17 249


and And2();
A And
or Or1(); 1
B
O
endmodule
C
2022-09-17 250


and And2();
A And
or Or1(); 1
B
O
endmodule
C
2022-09-17 251


and And2();
A And
or Or1(); 1
B
O
endmodule And
C 2
2022-09-17 252


and And2();
A And
or Or1(); 1
B
O
endmodule And
C 2
2022-09-17 253


and And2();
A And
or Or1(); 1
Not1
B
O
endmodule And
C 2
2022-09-17 254


and And2();
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 255


and And2();
A And
or Or1(); 1
Not1
B
Or1 O
endmodule Gate primitives provided in And
2
libraries: C
2022-09-17 GateName (out, in1, in2, in3, ... ) 256

Step 3 – connecting submodules up
input A, B, C; Gate primitives provided in

output O; libraries:
GateName (out, in1, in2, in3, ... )
not Not1();
and And2();
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 257


and And2();
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 258

not Not1(.in1(C));
and And2();
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 259

not Not1(.in1(C));
and And2();
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 260

not Not1(.in1(C));
and And2();
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 261

not Not1(.in1(C));
and And2();
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 262

not Not1(.in1(C));
my_module
and And2();
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 263

not Not1(.in1(C));
and And1(.in1(A)); my_module
and And2();
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 264

not Not1(.in1(C));
and And2();
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 265

not Not1(.in1(C));
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 266

not Not1(.in1(C));
and And2(.in1(B), .in2(C));
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 267

not Not1(.in1(C));
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 268

not Not1(.in1(C));
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 269

not Not1(.in1(C));
A And
or Or1(); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 270

not Not1(.in1(C));
A And
1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 271

not Not1(.in1(C));
A And
or Or1(.out(O)); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 272

not Not1(.in1(C));
A And
or Or1(.out(O)); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 273

not Not1(.in1(C));
A And
or Or1(.out(O)); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 274

wire w_not, w_and1, w_and2; GateName (out, in1, in2, in3, ... )
not Not1(.in1(C));
A And
or Or1(.out(O)); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 275

not Not1(.in1(C));
A And
or Or1(.out(O)); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 276

output O; internal signal libraries:
not Not1(.in1(C));
A And
or Or1(.out(O)); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 277

not Not1(.in1(C));
A And
or Or1(.out(O)); Wires are used for 1
Not1
B
connecting different Or1 O
endmodule elements. They can be And
C 2
treated as physical wires.
2022-09-17 278

not Not1(.out(w_not), .in1(C));
and And1(.in1(A), .in2(w_not)); my_module
A And
or Or1(.out(O)); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 279

A And
or Or1(.out(O)); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 280

A And
or Or1(.out(O)); 1
Not1 w_not
B
Or1 O
endmodule And
C 2
2022-09-17 281

and And1(.out(w_and1), .in1(A), .in2(w_not)); my_module
A And
or Or1(.out(O), .in1(w_and1)); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 282

A And
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 283

A And w_and1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 284
Gate primitives provided in
input A, B, C;
libraries:
output O; internal signal
wire w_not, w_and1, w_and2;
and And2(.out(w_and2), .in1(B), .in2(C));
A And
or Or1(.out(O), .in1(w_and1), in2(2_and2)); 1
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 285
input A, B, C;
libraries:
A And
Not1
B
Or1 O
endmodule And
C 2
2022-09-17 286
input A, B, C;
libraries:
A And
Not1
B
Or1 O
endmodule And
C 2 w_and2
2022-09-17 287
input A, B, C;
libraries:
A lot of time on port mapping.
A And
Not1
B
Or1 O
endmodule And
C 2 w_and2
2022-09-17 288
input A, B, C;
libraries:
A lot of time on port mapping.
or Or1(.out(O), .in1(w_and1), in2(2_and2));
A Solution
And
1
B Not1
1 Or1 O
endmodule And
C 2 w_and2
2022-09-17 289
Port mapping by name vs by order
By name By order
module my_module(A, B, C, O); module my_module(A, B, C, O);
input A, B, C; input A, B, C;
output O; output O;
wire w_not, w_and1, w_and2; wire w_not, w_and1, w_and2;
not Not1(.out(w_not), .in1(C)); not Not1(w_not, C);
and And1(.out(w_and1), .in1(A), .in2(w_not)); and And1(w_and1, A, w_not);
and And2(.out(w_and2), .in1(B), .in2(C)); and And2(w_and2, B, C);
or Or1(.out(O), .in1(w_and1), in2(2_and2)); or Or1(O, w_and1, 2_and2);
endmodule endmodule
2022-09-17 290
By name By order
You can shuffle input/output order in

outputnamed mapping, but output

notO; in order
O;
not Not1(.out(w_not), .in1(C)); mapping.not Not1(w_not, C);

and And1(.out(w_and1), .in1(A), .in2(w_not)); and And1(w_and1, A, w_not);

or Or1(.out(O), .in1(w_and1), in2(2_and2)); or Or1(O, w_and1, 2_and2);
endmodule endmodule
2022-09-17 291
By name By order
You can shuffle input/output order in

outputnamed mapping, but output

notO; in order
O;
not Not1(.out(w_not), .in1(C)); mapping.not Not1(w_not, C);

and And1(.out(w_and1), .in1(A), .in2(w_not)); SolutionA, w_not);

and And1(w_and1,
or Or1(.out(O), .in1(w_and1), in2(2_and2));
2
or Or1(O, w_and1, 2_and2);
endmodule endmodule
2022-09-17 292
Any other way to do my_module?
1. Less detail
• Data flow model or 3. Shorter time-to-market
(RTL) model
2022-09-17 293
Any other way to do my_module?
1. Less detail
• Data flow model or
Let’s do my_module in data-flow level.
3. Shorter time-to-market
(RTL) model
2022-09-17 294
Data-flow level modeling
• Step 1 – Schema comes first than code
my_module
A
And1
Not1
B
Or1 O
And2
C
2022-09-17 𝑂 =𝐴∙𝐶+𝐵∙𝐶 295

Step 2 – Model the module using data-flow
level Verilog
module my_module(A, B, C, O);
input A, B, C;
output O;
my_module
assign w_not = ~C;
assign w_and1 = A & w_not;
A And w_and1
assign w_and2 = B & C; 1
assign O = w_and1 | w_and2; B Not1 w_not
Or1 O
And
endmodule C 2 w_and2
2022-09-17 𝑂 =𝐴∙𝐶+𝐵∙𝐶 296

level Verilog Signals of type wire requires the
module my_module(A, B, C, O); continuous assignment of a value.
In Verilog, this concept is realized by the
input A, B, C; assign statement where any wire can be
driven continuously with a value.
output O;
my_module
assign w_not = ~C;
A And w_and1
assign w_and2 = B & C; 1
Or1 O
And
2022-09-17 𝑂 =𝐴∙𝐶+𝐵∙𝐶 297

level Verilog Signals of type wire requires the
module my_module(A, B, C, O); continuous assignment of a value.
In Verilog, this concept is realized by the
input A, B, C; assign statement where any wire can be
driven continuously with a value.
output O;
my_module
assign w_not = ~C;
A And w_and1
assign w_and2 = B & C; 1Solution
3 Or1 O
And
2022-09-17 𝑂 =𝐴∙𝐶+𝐵∙𝐶 298

level Verilog
input A, B, C;
output O;
assign O = (A & ~C) | (B & C);
endmodule
2022-09-17 299
level Verilog
input A, B, C;
output O;
assign O = (A & ~C) | (B & C);
endmodule
2022-09-17 300
level Verilog
input A, B, C;
output O;
assign O = (A & ~C) | (B & C);
Solution
4
endmodule
2022-09-17 301
level Verilog
input A, B, C;
output O;
endmodule
2022-09-17 302
level Verilog
input A, B, C;
output O;
endmodule
2022-09-17 303
level Verilog
input A, B, C;
output O;
assign O = (C) ? B : A;
endmodule
2022-09-17 304
level Verilog
input A, B, C;
output O;
A
MUX
O
B
endmodule C
2022-09-17 305
level Verilog
input A, B, C;
output O;
A
MUX
O Solution
B
5
endmodule C
2022-09-17 306
level Verilog
my_module is actually a way to
input A, B, C;
output O;
implement
assign O = (C) ? B : A; multiplexer using gates.
A
MUX
O Solution
B
5
endmodule C
2022-09-17 307
EDA Synthesis
• The five solutions differ in coding style, complicity, readability,
conciseness, etc
• Choose wisely according to your project’s/teammates’ needs
• All the four solutions yield the same synthesis result in Vivado.
2022-09-17 308
EDA Synthesis
conciseness, etc
Unlike in ASIC, you cannot see the

gates but only LUTs in FPGA synthesis.
2022-09-17 309
EDA Synthesis
conciseness, etc
Unlike in ASIC, you cannot see the

gates but only LUTs in FPGA synthesis.
If you like, you can still see the “gates”
under RTL analysis -> schematic.
2022-09-17 310
Questions?
2022-09-17 311

Verilog I

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Verilog I

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Accelerating Systems with

Programmable Logic Components

Yuan Yao, yuan.yao@it.uu.se

Can last for 10+ years!

• Change the contents of the 1

• Change the contents of the 1

Write into mem to reconfigure LUT.

• Change the contents of the 1

Write into mem to reconfigure LUT.

functions for input A,B,C?

outside the CLBs.

Write into mem to reconfigure

Xilinx XC2064 Xilinx XCVU440 Xilinx Zynq 7Z007S

Xilinx XC2064 Xilinx XCVU440 Xilinx Zynq 7Z007S

But FPGAs are cheap and easy/quick

Test FPGA In-System

Test FPGA In-System

Test FPGA In-System

Test FPGA In-System

Test FPGA In-System

Test FPGA In-System

Test FPGA In-System

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Test FPGA In-System

Schematic entry Debug

Schematic entry Debug

Schematic entry Debug

Schematic entry Debug

modeling/specification a=1; a=1;

modeling/specification a=1; a=1;

modeling/specification a=1; a=1;

Compiled to the following Synthesized to the following

a <= b; // a=b=2 a = b; // a=b=2

Synthesized to the following Synthesized to the following