Scribd Logo
Upload

Welcome to Scribd!

  • 8088 Microprocessor 02

    Uploaded by

    fa20-bce-047
    7 views12 pages
    This document discusses interfacing memory with the 8088 microprocessor using a line decoder. It explains that a line decoder is needed when using multiple memory chips to select the appropriate chip based on the address lines. It provides an example of using 8 memory chips that each need 3 address lines from the decoder to be selected, in addition to 7 address lines to access the internal memory cells. The document then provides details on how a 3-input NAND gate can be used as the line decoder, and describes how the address lines are connected to the decoder and memory chips. It concludes by listing some common memory types and their storage capacities that can be used with the 8088 microprocessor.

    Original Description:

    Original Title

    8088 microprocessor 02

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    This document discusses interfacing memory with the 8088 microprocessor using a line decoder. It explains that a line decoder is needed when using multiple memory chips to select the appropriate chip based on the address lines. It provides an example of using 8 memory chips that each need 3 address lines from the decoder to be selected, in addition to 7 address lines to access the internal memory cells. The document then provides details on how a 3-input NAND gate can be used as the line decoder, and describes how the address lines are connected to the decoder and memory chips. It concludes by listing some common memory types and their storage capacities that can be used with the 8088 microprocessor.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    7 views12 pages

    8088 Microprocessor 02

    Uploaded by

    fa20-bce-047
    This document discusses interfacing memory with the 8088 microprocessor using a line decoder. It explains that a line decoder is needed when using multiple memory chips to select the appropriate chip based on the address lines. It provides an example of using 8 memory chips that each need 3 address lines from the decoder to be selected, in addition to 7 address lines to access the internal memory cells. The document then provides details on how a 3-input NAND gate can be used as the line decoder, and describes how the address lines are connected to the decoder and memory chips. It concludes by listing some common memory types and their storage capacities that can be used with the 8088 microprocessor.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 12

    Microprocessor Systems and

    Interfacing
    CPE 342

    M. Hassan Aslam
    mhassanaslam@cuilahore.edu.pk
    https://sites.google.com/ciitlahore.edu.pk/mianhassanaslam/
    Microprocessor 8088
    CLO Bloom Taxonomy Specific Outcome

    Integrate the RAM/ROM with 8088 microprocessors using


    CLO2 C5
    NAND address decoding techniques.

    ◼ Outline
    ❑ Memory Interfacing with 8088

    Wednesday, March 2, 2022 2


    Memory Interfacing using Line Decoder

    Wednesday, March 2, 2022 3


    Why Line Decoder?
    ◼ Let’s assume a very simple microprocessor with
    10 address lines (1KB memory)
    ◼ Let’s assume we wish to implement all its
    memory space and we use 128x8 memory chips
    ◼ SOLUTION
    ❑ We will need 8 memory chips (8x128=1024)
    ❑ We will need 3 address lines to select each one of the
    8 chips
    ❑ Each chip will need 7 address lines to address its
    internal memory cells

    Wednesday, March 2, 2022 4


    Memory Interfacing using Line Decoder

    Wednesday, March 2, 2022 5


    Line Decoder

    Wednesday, March 2, 2022 6


    Line Decoder

    Wednesday, March 2, 2022 7


    Line Decoder

    Wednesday, March 2, 2022 8


    Line Decoder
    ◼ The outputs of the decoder in the figure, are
    connected to eight different 2764
    ◼ EPROM memory devices.
    ❑ The decoder selects eight 8K-byte blocks of memory for a
    total capacity of 64K bytes.
    ❑ The decoder’s outputs are connected to the CE inputs of
    the EPROMs,
    ❑ The RD signal from the 8088 is connected to the OE inputs
    of the EPROMs
    ❑ In this circuit, a three-input NAND gate is connected to
    address bits A19–A17

    Wednesday, March 2, 2022 9


    Line Decoder
    ❑ When all three address inputs are high, the output of this
    NAND gate goes low and enables input G2B of the
    74LS138.
    ❑ Input G1 is connected directly to A16.
    ❑ In order to enable this decoder, the first four address
    connections (A19–A16) must all be high.
    ❑ Address inputs C, B, and A connect to microprocessor
    address pins A15–A13.
    ❑ These three address inputs determine which output pin
    goes low and which EPROM is selected whenever 8088
    outputs a memory address within this range to the memory
    system.

    Wednesday, March 2, 2022 10


    Line Decoder

    Wednesday, March 2, 2022 11


    Memory Bank
    Memory Type Part number Storage capacity
    27C16 2KB
    27C64 8KB
    EPROMs 27C128 16KB
    27C256 32KB
    27C512 64KB
    61C16 2KB
    SRAMs
    62C256 32KB
    28C16 2KB
    EEPROMs 28C32 4KB
    28C256 32KB

    Wednesday, March 2, 2022 12

    You might also like