Analog and Digital Electronics (Subject Code: 17CS32) Lecturer Notes

VISVESVARAYA TECHNOLOGICAL UNIVERSITY
BELGAUM
ANALOG AND DIGITAL ELECTRONICS

(Subject Code: 17CS32)
LECTURER NOTES
(MODULE-1)
III-SEMESTER
Mr Rakesh M R
Assistant Professor, Dept of ISE
AJIET
A J INSTITUTE OF ENGINEERING & TECHNOLOGY
DEPARTMENT OF INFORMATION SCIENCE AND ENGINEERING
(A unit of Laxmi Memorial Education Trust. (R))
NH - 66, KottaraChowki, Kodical Cross - 575 006
ANALOG AND DIGITAL ELECTRONICS -17CS32
Module -1
Field Effect Transistors: Junction Field Effect Transistors, MOSFETs, Differences between
JFETs and MOSFETs, Biasing MOSFETs, FET Applications, CMOS Devices.
Wave-Shaping Circuits: Integrated Circuit(IC) Multivibrators. Introduction to Operational

Amplifier: Ideal v/s practical Opamp, Performance Parameters,
Operational Amplifier Application Circuits:Peak Detector Circuit, Comparator, Active

Filters, Non- Linear Amplifier, Relaxation Oscillator, Current-To-Voltage Converter,
Voltage-To- Current Converter.
Text book: Anil K Maini, Varsha Agarwal: Electronic Devices and Circuits, Wiley, 2012.
Ch 5: 5.2, 5.3, 5.5, 5.8, 5.9, 5.1.Ch13: 13.10.Ch 16: 16.3, 16.4. Ch 17: 7.12, 17.14, 17.15,
17.18, 17.19, 17.20, 17.21.
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Dept. of CSE/ISE AJIET Mangaluru
The Field Effect Transistor

The Field Effect Transistor (FET) uses the voltage that is applied to their input
terminal, called the Gate to control the current flowing through them resulting in the output
current being proportional to the input voltage. As their operation relies on an electric field
(hence the name field effect) generated by the input Gate voltage, this then makes the Field
Effect Transistor a voltage operated device.
The Field Effect Transistor is a three terminal uni-polar semiconductor device that has
high efficiency, instant operation, robust and cheap and can be used in most electronic circuit
applications. Field effect transistors can be made much smaller than an equivalent BJT
transistor and along with their low power consumption and power dissipation makes them
ideal for use in integrated circuits such as the CMOS range of digital logic chips. There are
two basic types of FET, which basically describes the physical arrangement of the P-type and
N-type semiconductor materials from which they are made.
 The N-channel FET
 The P-channel FET.
The field effect transistor is a three terminal device that is constructed with no PN-
junctions within the main current carrying path between the Drain and the Source terminals.
The current path between these two terminals is called the channel which may be made of
either a P-type or an N-type semiconductor material. The control of current flowing in this
channel is achieved by varying the voltage applied to the Gate. The Field Effect Transistor on
the other hand is a uni-polar device that depends only on the conduction of electrons (N-
channel) or holes (P-channel). There are two main types of field effect transistor, the Junction
Field Effect Transistor or JFET and the Insulated-gate Field Effect Transistor or IGFET),
which is more commonly known as the standard Metal Oxide Semiconductor Field Effect
Transistor or MOSFET for short.
Difference between BJT and FET
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BIPOLAR JUNCTION TRANSISTOR(BJT) FIELD EFFECT TRANSISTOR(FET)

Current controlled device Voltage controlled device
Bipolar device Uni-polar device
Flow of both majority & minority charge Only the majority charge carriers flow.
carriers.
Terminals namely emitter, base and collector Terminals namely source, drain and gate
Input impedance low Input impedance high
Medium switching time Fast switching time
Cheap More expensive
Medium size Smaller in size
Overall gain high Overall Gain is low
Small amount of current to switch on the No current is required to keep the transistor
transistor ON
Applicable for low current applications Applicable for low voltage applications
Less temperature stable More temperature stable
Slightly larger in construction. Smaller in construction
1.1. Junction Field Effect Transistors

Junction Field Effect Transistor (JFET) is the three terminal devices where the voltage
applied at one terminal controls the current through the other two terminals. The Junction
Field Effect Transistor (JFET) has a narrow piece of high-resistivity semiconductor material
forming a Channel of either N-type or P-type silicon for the majority carriers to flow through
with two ohmic electrical connections at either end commonly called the Drain and the
Source respectively. Depending upon the semiconductor material for channel, JFET are
classified as the N-channel JFET and the P-channel JFET.
Construction and principle of operation

In N channel JFET, N-type semiconductor material forms a channel between
embedded layers of p type material. In P channel JFET, P-type semiconductor material forms
a channel between embedded layers of N type material. Two P-N junctions are formed
between the semiconductor channel and the embedded semiconductor layers. Contacts are
made at the top and bottom of the channel and are referred as the drain and source terminals.
In N channel JFET both the embedded P type layers are connected together and form a gate
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terminal. In P channel JFET both the embedded N type layers are connected together and
form a gate terminal. In the absence of any externally applied potential both P-N junctions are
open circuit and small depletion region is formed at each of the junctions (shown in fig). The
externally applied potential between gate and source terminals controls the flow of drain
current for a given potential between the drain and source terminal.
Figure: cross section of (a) an N-channel JFET; (b) a P- channel JFET
Figure: circuit symbol of (a) an N-channel JFET; (b) a P- channel JFET
Characteristic curves
Consider N channel JFET with a situation when a positive drain- source voltage ( )
is applied to the JFET with the gate terminal shorted to the source terminal ( =0). When
the drain- source voltage ( ) applied, the electrons in the N channel are attracted to the
drain terminal establishing the flow of drain current ( ). The value of ID is determined by the
value of the applied and the resistance of the N channel between the drain and the source
terminals.
Case I: Consider the case where no voltage is applied to the device i.e. VDS = 0 and VGS = 0.
At this state, the device will be idle and no current flows through it i.e. IDS = 0.
Case II: Now consider that the drain terminal of the device is connected to the positive
terminal of the battery while its negative is connected to the source i.e. VDS = +ve. However
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let the gate terminal remain at unbiased state, which means VGS = 0. At this instant, the
electrons within the n-substrate of the device start moving towards the drain being attracted
by the positive force exerted by the battery. At the same time, the electron will also be
repelled from the source as it is connected to the negative terminal of the voltage supply. This
result in a net flow of current from drain to source (as per conventional direction) whose
value is restricted only by the resistance offered to it by the channel.
Figure: N- channel JFET with VGS = 0 and positive value of VDS
Figure: versus VDS for VGS = 0

Further, it is seen that the increase in VDS increases the current flowing through the
device at an initial state which can be termed to be JFET's Ohmic region. However, it is to be
noted that the increase in VDS also causes an increase in the width of the depletion regions
near drain region than the source region. This in-turn causes the channel width to reduce,
thereby increasing its resistance. This phenomenon continues till both of the depletion
regions grow up to an extent wherein they almost seem to touch each other, a condition
referred to as pinch-off. The corresponding value of VDS is referred to as pinch-off voltage,
VP. When VDS reaches the value of does not change with further increase in the value
of VDS called pinch off condition. Nevertheless, even in this case, a narrow channel with high
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current density exists within the device due to which IDS will get saturated to a level of IDSS.
For VDS > VP, essentially remains constant and JFET which causes it to behave as a
constant current source.
Figure: N- channel JFET with VGS = 0 and VDS ≥ VP

Case III: Next, for the set-up described in Case II, let us add the voltage source at the gate
terminal such that the gate is negative w.r.t source i.e. VGS = -ve while VDS is +ve. In this
case, the device behaves in a way very-similar to that in Case II, but for a lower value of VDS.
This means that the pinch-off and the saturation occur quite earlier and are decided by the
negative potential applied at the gate i.e. more negative the VGS, earlier the pinch-off due to
which earlier will be the saturation, reducing IDSS. Drain current becomes zero for VGS equals
to – VP
As the phenomenon continues, it is seen that a condition arises wherein the saturation
level of the drain-to-source current occurs right for a value of 0mA. This means that there
is no current flow through the device and essentially the device will turn OFF. The value of
VDS for which this happens will be nothing but the negative pinch-off voltage i.e. VGS = -VP.
The voltage VGS applied to the Gate controls the current flowing between the Drain
and the Source terminals. VGS refers to the voltage applied between the Gate and the Source
while VDS refers to the voltage applied between the Drain and the Source. Because a Junction
Field Effect Transistor is a voltage controlled device, NO current flows into the gate, then the
Source current ( ) flowing out of the device equals the Drain current flowing into it and
therefore ( = ). It is essential that the Gate voltage is never positive since if it is all the
channel current will flow to the Gate and not to the Source, the result is damage to the JFET.
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Figure: N-channel JFET biasing circuit.
Figure: Output characteristic curve of an N-channel JFET
Drain resistance in saturation region is given by
= resistance at =0
= = resistance at particular value of
= pinch off voltage
Then we can calculate the Drain current, ID in the saturation region for any given of input
as follows:
= drain current for short circuit connection between gate and source. This expression is
Shockley’s equation.
Transfer characteristic of an FET device is plot between and
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Figure: Transfer characteristic curve of N-channel JFET.

The characteristics curves for a P-channel junction field effect transistor are the same as those
above. In the case of p-channel JFET, the major portion made of the device is made of p type
into which embedded are the two small n-type regions. Thus it has an n-type gate terminal
and p-type source and drain, causing the channel to be of p-type where the holes will be the
majority charge carriers. The Drain current decreases with an increasing positive Gate-
Source voltage . The Drain current is zero when = . For normal operation, is
biased to be somewhere between and 0.
Figure: Characteristic curve of p-channel JFET

Effect of Temperature on JFET Parameters
JFET offer better thermal stability as compared to BJTs. Increase in JFET temperature
results in decrease in the depletion region width and decrease in the carrier mobility.
Decrease in the width of depletion region results in increase in channel width, which in turn
increases in . This results in positive temperature coefficient for . Increase in with
temperature results in increase in with temperature. also has a positive
temperature coefficient of the order 2.2mV/°C. Decrease in carrier mobility gives a
negative temperature coefficient. Since both the mechanisms occur simultaneously, the effect
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of one mechanism compensates for the other. Therefore, JFETs offer better temperature
stability.
1.2. Metal Oxide Field Effect Transistor

MOSFETs are three terminal devices with a Gate, Drain and Source, where drain
current is controlled by applied gate voltage. Metal Oxide in the name MOSFET stands for
the thin insulating layer of silicon oxide layer in the region between metal and
semiconductor. MOSFET are also referred to as Insulated Gate Field Effect
Transistor or IGFET.
Two types of MOSFETs depending on Mode of Operations are,
 Depletion Type – the transistor requires the Gate-Source voltage, (VGS) to switch
the device OFF. The depletion mode MOSFET is equivalent to a Normally Closed
switch.
 Enhancement Type – the transistor requires a Gate-Source voltage, (VGS) to switch
the device ON. The enhancement mode MOSFET is equivalent to a Normally Open
switch.
Depletion MOSFETs
In a DE-MOSFET a channel is physically constructed between the drain and the
source terminals. Depending on the channel material DE-MOSFET are classified as
 n-channel depletion-type MOSFET
 p-channel depletion-type MOSFET
Figure: cross section of an N-channel DE-MOSFET
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Figure: cross section of a p-channel DE-MOSFET

Figure shows the construction of N-channel depletion MOSFET. It consists of a
highly doped P-type substrate into which two blocks of heavily doped N-type material are
diffused forming the source and drain. An N-channel is formed by diffusion between the
source and drain. The gate terminal is connected to the insulating silicon dioxide (SiO2) layer
on the top of the N- channel. Hence there is no direct electrical connection between the gate
terminal and the channel of DE-MOSFET
There is a capacitance that exists between the gate terminal and the channel as the
metal gate contact and the channel act as walls of a parallel palate capacitor and SiO2 layer
form the dielectric. Hence input impedance of DE-MOSFET is very high.
Figure: circuit symbol of (a) an N-channel DE-MOSFET; (b) a P- channel DE-MOSFET
The MOSFET symbol above show an additional terminal called the Substrate and is
not normally used as either an input or an output connection but instead it is used for
grounding the substrate.
Case I: The gate-to-source voltage is set to zero volts by the direct connection from one
terminal to the other, and a voltage is applied across the drain-to-source terminals. The
result is an attraction for the positive potential at the drain by the free electrons of the n-
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channel and a current established through the channel. The current increases with increase in
and after certain value of , it becomes constant .
Figure: N-channel DE-MOSFET

Case II: When has been set at a negative voltage. The negative potential at the gate will
tend to pressure electrons toward the p-type substrate (like charges repel) and attract holes
from the p-type substrate (opposite charges attract). Depending on the magnitude of the
negative bias established by , a level of recombination between electrons and holes will
occur that will reduce the number of free electrons in the n-channel available for conduction.
The more negative the bias, the higher the rate of recombination. The resulting level of drain
current is therefore reduced with increasing negative bias for .
Figure: Output characteristic curve of N-channel DE-MOSFET

Case III: For positive values of , the positive gate will draw additional electrons (free
carriers) from the p-type substrate due to the reverse leakage current and establish new
carriers through the collisions resulting between accelerating particles. As the gate-to-source
voltage continues to increase in the positive direction, the drain current will increase at a
rapid rate. Due to the rapid rise, the user must be aware of the maximum drain current rating
since it could be exceeded with a positive gate voltage. The application of a positive gate-to-
source voltage has enhanced the level of free carriers in the channel compared to that
encountered with =0 V. For this reason the region of positive gate voltages on the drain
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or transfer characteristics is often referred to as the enhancement region, with the region for
zero and negative values of referred to as the depletion region.
It is particularly interesting and helpful that Shockley’s equation will continue to be
applicable for the depletion-type MOSFET characteristics in both the depletion and
enhancement regions.
Figure: Transfer characteristic curve of N-channel DE-MOSFET
Enhancement MOSFETs
The construction of an E-MOSFET is similar to that of a DE-MOSFET with the
difference that there is no physical channel between the source and drain terminal in the E-
MOSFET. Depending on the channel material E-MOSFET are classified as,
 N-channel enhancement-type MOSFET
 P-channel enhancement-type MOSFET
Figure: cross section of (a) an N-channel E-MOSFET; (b) a P- channel E-MOSFET
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Figure: circuit symbol of (a) an N-channel E-MOSFET; (b) a P- channel E-MOSFET
The basic construction of the n-channel enhancement-type MOSFET is provided in

Figure. A slab of p-type material is formed from a silicon base and is again referred to as the
substrate. The source and drain terminals are again connected through metallic contacts to n-
doped regions, but the absence of a channel between the two n-doped regions. This is the
primary difference between the construction of depletion-type and enhancement-type
MOSFETs—the absence of a channel as a constructed component of the device. The SiO2
layer is still present to isolate the gate metallic platform from the region between the drain
and source.
Figure: Working of N-channel E-MOSFET

when gate to source voltage is set at 0 V and a voltage applied between the drain
and source of the device, the absence of an n-channel (with its generous number of free
carriers) will result in a drain current of effectively zero amperes. It is not sufficient to have a
large accumulation of carriers (electrons) at the drain and source (due to the n-doped
regions). E-MOSFET are normally off when =0.
If both and have been set at some positive voltage greater than 0V,
establishing the drain and gate at a positive potential with respect to the source. When
positive potential at the gate, the electrons in the p-substrate (the minority carriers of the
material) will be attracted to the positive gate and accumulate in the region near the surface of
the SiO2 layer. The SiO2 layer and its insulating qualities will prevent the negative carriers
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from being absorbed at the gate terminal. As increases in magnitude, the concentration
of electrons near the SiO2 surface increases until eventually the induced n-type region can
support a measurable flow between drain and source. The level of that result in the
significant increase in drain current is called the threshold voltage and is given the symbol .
Since the channel is nonexistent with =0 V and enhanced by the application of a
positive gate-to-source voltage, this type of MOSFET is called an enhancement-type
MOSFET. As is increased beyond the threshold level, the density of free carriers in the
induced channel will increase, resulting in an increased level of drain current. However, if we
hold constant and increase the level of , the drain current will eventually reach
saturation. The levelling off of is due to a pinching-off process depicted by the narrower
channel at the drain end of the induced channel
Figure: Pinching phenomenon in E-MOSFET
Figure: Output characteristic curves for an N-channel E-MOSFET

In fact, the saturation level for is related to the level of applied by
Therefore, for a fixed value of , the higher the level of , the more the saturation
level for . For levels of > , the drain current is related to the applied gate-to-source
voltage by the following nonlinear relationship:
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The K term is a constant

The value of K can be determined from the following equation, where and are
the values for each at a particular point on the characteristics of the device
In this case, however, it must be remembered that the drain current is 0mA for . For
an n-channel enhancement mode MOSFET: +VGS turns the transistor ON, while a zero or -
VGS turns the transistor OFF. Then, the enhancement-mode MOSFET is equivalent to a
normally-open switch.
Figure: Transfer characteristics of an N-channel E-MOSFET

The reverse is true for the p-channel enhancement MOS transistor. When VGS = 0 the
device is OFF and the channel is open. The application of a negative (-ve) gate voltage to the
p-type E-MOSFET enhances the channels conductivity turning it ON. Then for a p-channel
enhancement mode MOSFET: +VGS turns the transistor OFF, while -VGS turns the transistor
ON.
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1.3. Difference between JFETs and MOSFETs
JFET MOSFET
Operated in depletion mode only DE-MOSFET operated in both enhancement
and depletion mode, E-MOSFET operated in
enhancement mode.
Input resistance is greater than 109Ω Input resistance is higher than JFET.
Higher drain resistance(100KΩ to 1MΩ) Drain resistance is in the range 1 to 50KΩ
Gate current is in the range of 100µa to 10na Gate current is in the range of 100na to 10pa
Leakage current in MOSFET is much smaller than that in JFET

MOSFETs are easier to construct and are used more widely than JFETs.
1.4. Biasing MOSFETs

Biasing is done to produce the required gate to source to get the desired value of
drain current . The biasing circuits should maintain the drain current and drain source
voltage within reasonable limits. Application of some voltages to establish a fixed level of
current and voltage called biasing.
Depletion MOSFETs
D-MOSFET operates in both positive and negative value of gate to source voltage.
Example:
Figure shows a biasing configuration using DE-MOSFET. Given that the saturation drain
current is 8mA and the pinch off voltage is -2v, determine value of gate source voltage, drain
current and drain source voltage.
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Solution:
MOSFET operates in enhancement region
Here, , ,
So,
Apply Kirchhoff’s voltage law to output section,
Enhancement MOSFETs
Two most popular biasing arrangements for enhancement-type MOSFETs are
 Feedback Biasing Arrangement
 Voltage-Divider Biasing Arrangement
Feedback Biasing Arrangement
Figure: Feedback biasing configuaraion for N-channel E-MOSFETand its DC euivalent of

the circuit
A popular biasing arrangement for enhancement-type MOSFETs is provided in

Figure. The resistor brings a suitably large voltage to the gate to drive the MOSFET on.
Since =0mA and =0V, the dc equivalent network appears as shown in Figure.
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Applying Kirchhoff’s voltage law to the input sections, we get

------ (1)
Applying Kirchhoff’s voltage law to the output sections, we get
------ (2)
By these two equations we clear that
The result is an equation 1&2 that relates the same two variables, permitting the plot of each
on the same set of axes. Since Eq. (1) is that of a straight line, the same procedure described
earlier can be employed to determine the two points that will define the plot on the graph.
Substituting =0 mA into Eq. (1) gives
Substituting into Eq. (1), we have
The plot defined by Eq. (1) appears in figure with the resulting operating point.
Figure: Graphical method for determining the operating point for the circuit
Operating points are given by . These points can also establish using graphical
method. The operating point can be obtained by
 Superimposing the equation 1 on the transfer characteristics of the MOSFET
 Superimposing the DC load line defined by equation2 on the output characteristics
curves of the MOSFET.
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Voltage-Divider Biasing Arrangement
Figure: Voltage divider biasing configuration for N-channel E-MOSFET and its DC
equivalent circuit
A second popular biasing arrangement for the enhancement-type MOSFET appears in
Figure. The fact that =0mA results in the following equation for as derived from an
application of the voltage-divider rule:
Applying Kirchhoff’s voltage law around the indicated loop of Figure will result in
and
or -------- (1)
For the output section

and
or --------- (2)
Since the characteristics are a plot of versus and Eq. (1) relates the same two
variables, the two curves can be plotted on the same graph and a solution determined at their
intersection. Once and are known, all the remaining quantities of the network such
as , and can be determined.
1.5. FET Applications

FET has very high input impedance (100 Mega ohms in case of JFETs and 104 to 109
Mega Ohm in case of MOSFETs), the major shortcomings of ordinary transistor i.e. low
input impedance with consequent of loading of signal source is eliminated in FET. Hence
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FET is an ideal device for use in almost every application in which transistors can be used.
FETs are widely used as input amplifiers in oscilloscopes, electronic voltmeters and other
measuring and testing equipment because of their high input impedance. As a FET chip
occupies very small space as compared to BJT chip, FETs are widely used in ICs. FETs are
used as voltage-variable resistors (VVRs) in operational amplifiers (op-amps) and tone
controls etc, for mixer operation on FM and TV receivers and in logic circuits. FETs are
generally used in digital switching circuits though their operating speed is lower.
 Amplifier
FET device are commonly used as Low Noise Amplifier and as Buffer
Amplifier. Every electronic device produces certain amount of noise but FET is a
device which causes very little noise. This is especially important near the front-end
of the receivers and other electronic equipment because the subsequent stages amplify
front-end noise along with the signal. If FET is used at the front-end, we get less
amplified noise (disturbance) at the final output. A buffer amplifier is a stage of
amplification that isolates the preceding stage from the following stage. Source
follower (common drain) is used as a buffer amplifier. Because of the high input
impedance and low output impedance a FET acts an excellent buffer amplifier. Owing
to high input impedance almost all the output voltage of the preceding stage appears
at the input of the buffer amplifier and owing to low output impedance all the output
voltage from the buffer amplifier reaches the input of the following stage, even there
may be a small load resistance.
 Analog Switch
FET as an analog switch is shown in figure. When no gate voltage is applied
to the FET i.e. VGG = 0, FET becomes saturated and it behaves like a small resistance
usually of the value of less than 100 ohm and act as closed switch. When a negative
voltage equal to VGG is applied to the gate, the FET operates in the cut-off region and
it acts like a very high resistance usually of some mega ohms and act as an open
switch
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Figure: FET as an analog switch

 Multiplexer
An analog multiplexer, a circuit that steers one of the input signals to the
output line, is shown in figure. In this circuit each JFET acts as a single-pole single-
throw switch. When the control signals are more negative than VGS(0ff) all input signals
are blocked. By making any control voltage equal to zero, one of the inputs can be
transmitted to the output. For instance, when control input 2 is zero, the signal
obtained at the output will be the input. Normally, only one of the control signals is
zero.
Figure: FET as a multiplexer

 Current Limiter
JFET current limiting circuit is shown in figure. Almost all the supply voltage
therefore appears across the load. When the load current tries to increase to an
excessive level (may be due to short-circuit or any other reason), the excessive load
current forces the JFET into saturation region, where it limits the current. The JFET
now acts as a current source and prevents excessive load current.
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Figure: FET for current limiting

 Voltage Variable Resistor
FETs when operated in the ohmic region (for small positive value of ) act
as voltage variable resistor. In this region the can be controlled by . For an N
channel FET the value of increases with increase in the negative value of .if
AC voltage applied between Drain and source terminal then FET act as a linear
resistor for give .
Figure: Characteristics of an N channel JFET in the ohmic region

 Oscillator
JFET can incorporate the amplifying action as well as feedback action. It,
therefore, acts well as a phase shift oscillator. The high input impedance of FET is
especially very valuable in phase-shift oscillators in order to minimize the loading
effect. A typical phase shift oscillator employing N-channel JFET is shown in figure.
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Figure: FET based phase shift oscillator.

1.6. Dual-Gate MOSFET
The dual gate MOSFET, Metal Oxide Semiconductor field effect transistor offers
additional capability and flexibility of operation over the standard MOSFET: with two gates
it has two control terminals.
Figure: N-channel dual gate DE-MOSFET
Figure: transfer characteristics of an N-channel dual gate DE-MOSFET.
One form of MOSFET that is particularly popular in many RF applications is the dual
gate MOSFET. The dual gate MOSFET is used in many RF and other applications where two
control gates are required in series. The dual gate MOSFET is essentially a form of MOSFET
where two gates are fabricated along the length of the channel - one after the other. In this
way, both gates affect the level of current flowing between the source and drain.
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In effect, the dual gate MOSFET operation can be considered the same as two
MOSFET devices in series. Both gates affect the overall MOSFET operation and hence the
output. The dual gate MOSFET has what may be referred to as a tetrode construction where
the two grids control the current through the channel with two low noise gain controlled
amplifiers in a single package. The different gates control different sections of the channel
which are in series with each other. Single gate FETs is most widely used. The characteristics
of the dual gate MOSFET can provide some very useful improvements in performance in
some applications.
1.7. CMOS Devices

A very effective logic circuit can be established by constructing a p-channel and an n-
channel MOSFET on the same substrate as shown in Figure. Note the induced p-channel on
the left and the induced n-channel on the right for the p- and n-channel devices, respectively.
The configuration is referred to as a complementary MOSFET arrangement (CMOS) that has
extensive applications in computer logic design. The relatively high input impedance, fast
switching speeds, and lower operating power levels of the CMOS configuration have resulted
in a whole new discipline referred to as CMOS logic design.
Figure: CMOS inverter

One very effective use of the complementary arrangement is as an inverter, as shown
in Figure. As introduced for switching transistors, an inverter is a logic element that inverts
the applied signal. That is, if the logic levels of operation are 0 V (0-state) and 5 V (1-state),
an input level of 0 V will result in an output level of 5 V, and vice versa. Note in Figure that
both gates are connected to the applied signal and both drain to the output . The source of
the p-channel MOSFET (Q2) is connected directly to the applied voltage , while the
source of the n-channel MOSFET (Q1) is connected to ground. For the logic levels defined
above, the application of 5 V at the input should result in approximately 0 V at the output.
With 5 V at (with respect to ground), and Q1 is on, resulting in a relatively low
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resistance between drain and source as shown in Figure. Since and are at 5 V,
V, which is less than the required for the device, resulting in an off state. The
resulting resistance level between drain and source is quite high for Q2, as shown in Figure.
A simple application of the voltage-divider rule will reveal that is very close to 0 V or the
0-state, establishing the desired inversion process. For an applied voltage of 0 V (0-state),
=0 V and Q1 will be off with 5 V, turning on the p-channel MOSFET. The
result is that Q2 will present a small resistance level, Q1 a high resistance, and = =5 V
(the 1-state). Since the drain current that flows for either case is limited by the off transistor
to the leakage value, the power dissipated by the device in either state is very low.
Figure: simplified diagram of CMOS inverter
1.8. Integrated Circuit Multivibrator

A multivibrator (like an oscillator) is a circuit with regenerative feedback, which
produce a pulsed output. The three types of multivibrator circuits are
 Astable multivibrator, in which the circuit is not stable in either state —it continually
switches from one state to the other. It functions as a relaxation oscillator.
 Monostable multivibrator, in which one of the states is stable, but the other state is
unstable (transient). A trigger pulse causes the circuit to enter the unstable state. After
entering the unstable state, the circuit will return to the stable state after a set time. Such a
circuit is useful for creating a timing period of fixed duration in response to some
external event. This circuit is also known as a one shot.
 Bistable multivibrator, in which the circuit is stable in either state. It can be flipped from
one state to the other by an external trigger pulse. This circuit is also known as a flip-flop.
It can store one bit of information, and is widely used in digital logic and computer
memory.
26
Digital IC Based Monostable Multivibrator

The ICs that can be used as Monostable multivibrators includes TTL family and
CMOS family.
 TTL family:
74121(Single Monostable Multivibrator): The IC provides Features for triggering on
either low to high or high to low edge trigger pulses. Output pulse width depends on
external R and C, and can computed from T=0.7RC.
74221(Dual Monostable multivibrators)
74122(single Retrigerable Monostable Multivibrators)
74123(Dual Retrigerable Monostable Multivibrators ): The IC provides Features for
triggering on either low to high or high to low edge trigger pulses. Output pulse width
depends on external R and C, and can computed from
Where R in kilo ohm, C in pico farad and T is in nano seconds.
 CMOS family
4098B (Dual Retrigerable Monostable Multivibrators)
Figure: (a) high to low edge triggering of 74121. (b) low to high edge triggering of 74121
Figure: (a) high to low edge triggering of 74123. (b) low to high edge triggering of 74123
27
Timer IC Based Multivibrators

Timer IC is the one of the most commonly used general purpose linear integrated
circuits. Timer IC 555 comprises two opamp comparator, a flip-flop, a discharge transistor, a
reset transistor, three identical resistors and an output stage.
The 555 Timers name comes from the fact that there are three 5kΩ resistors
connected together internally producing a voltage divider network between the supply
voltage at pin 8 and ground at pin 1. The voltage across this series resistive network holds the
negative inverting input of comparator two at 2/3 and the positive non-inverting input to
comparator one at 1/3 .
The two comparators produce an output voltage dependent upon the voltage
difference at their inputs which is determined by the charging and discharging action of the
externally connected RC network. The outputs from both comparators are connected to the
two inputs of the flip-flop which in turn produces either a HIGH or LOW level output. The
flip-flop complementary outputs feed the output stage and the base of the discharge transistor.
Hence, when the output is high, the discharge transistor is off and when the output is low, the
discharge transistor is ON.
Figure: Internal schematic of timer IC 555
Astable Multivibrator Using 555 Timer

An Astable Multivibrator is an oscillator circuit that continuously produces
rectangular wave without the aid of external triggering. So Astable Multivibrator is also
known as Free Running Multivibrator. The working of this as follows,
28
 When the circuit is switched ON, the capacitor (C) voltage will be less than 1/3 .
So the output of the lower comparator will be HIGH and of the higher comparator
will be LOW. This SETs the output of the SR Flip-flop.
 Thus the discharging transistor will be OFF and the capacitor C starts charging from
through resistor &
 When the capacitor voltage will become greater than 1/3 (less than 2/3 ), the
output of both comparators will be LOW and the output of SR Flip-flop will be same
as the previous condition. Thus the capacitor continuous to charge.
 When the capacitor voltage will becomes slightly greater than 2/3 the output of the
higher comparator will be HIGH and of lower comparator will be LOW. This resets
the SR Flip-flop.
 Thus the discharging transistor turns ON and the capacitor starts discharging through
resistor .
 Soon the capacitor voltage will be less than 2/3 and output of both comparators
will be LOW. So the output of the SR Flip-flop will be the previous state.
 So the discharging of capacitor continuous.
 When the capacitor voltage will become less than 1/3 , the output SETs since the
output of lower comparator is HIGH and of higher comparator is LOW and the
capacitor starts charging again.
 This process continuous and a rectangular wave will be obtained at the output.
Figure: (a) Astable multivibrator (b) relevant waveform

Since the Control Voltage (pin 5) is not used the comparator reference voltages will
be 2/3 and 1/3 respectively. So the output of the 555 will set (goes high), when the
capacitor voltage goes below 1/3 and output will reset (goes low) when the capacitor
29
voltage goes above 2/3 . Reset pin (pin 4) is directly connected to Reset of the flip-flop.
This is an active Low pin and normally connected to VCC for preventing accidental Reset. So
this is called Astable mode because none of the state is stable and 555 automatically
interchange its state from HIGH to LOW and LOW to HIGH, so it is called Free running
Multivibrator.
Now the OUTPUT HIGH and OUTPUT LOW duration, is determined by the
Resistors R1 & R2 and capacitor C. This can be calculated using below formulas:
Time High (Seconds)
Time Low (Seconds)
Time Period T = Time High + Time Low
Frequency f = 1/Time Period = 1/ =
Duty Cycle: Duty cycle is the ratio of time for which the output is HIGH to the total time.
Duty cycle %: (Time HIGH/ Total time) * 100 = (Thigh/T) 100 =
In this case the high state time period is always greater than the low state time
period. The bellow figure shows a modified circuit where high state and low state time
periods can be chosen independently. Then equations are given by,
Time High (Seconds)
Time Low (Seconds)
Time Period T = Time High + Time Low = 1.38 R C
Since = =R
Freqeuncy f = 1/Time Period = 1/ 1.38 R C
Figure: Modified astable multivibrator circuits.
30
Monostable Multivibrator Using 555 Timer

Monostable multivibrators have only one stable state that is used to generate a single
o/p pulse of a specified width either high or low when an external trigger pulse is applied.
This trigger pulse starts a timing cycle, which causes the o/p to change its state at the time of
start of timing cycle and continues in the second state which is decided by the time constant
of the capacitor C and resistor R until it returns to its original state. It will continue in this
state until another i/p signal is received. Monostable multivibrators can produce a much
longer rectangular waveform. When a trigger pulse is applied externally then the leading edge
of the waveform rises with the externally applied trigger. Here, trailing edge depends upon
the RC time constant of the feedback components used. This RC time constant may be varied
with time to produce a series of pulses which have a fixed time delay to the original triggered
pulse.
Figure: (a) Monostable multivibrator circuit. (b) relevant waveform

Initially when the circuit is in the stable state i.e., when the output is low, discharge
transistor is ON and the capacitor C is shorted out to ground. Upon the application of a
negative trigger pulse to pin 2, discharge transistor is turned OFF, which releases the short
circuit across the external capacitor C and drives the output high. The capacitor C now starts
charging up towards VCC through R. When the voltage across the capacitor equals 2/3 ,
comparator 1’s output switches from low to high, which in-turn drives the output to its low
state via the output of the flip-flop. At the same time the output of the flip-flop turns
discharge transistor ON and hence the capacitor C rapidly discharges through the transistor.
The output of the monostable remains low until a trigger pulse is again applied. Then the
cycle repeats. The pulse width of the trigger input must be smaller than the expected pulse
31
width of the output waveform. Also the trigger pulse must be a negative going input signal
with amplitude larger than 1/3 .
The time during which the output remains high is given by
Seconds
Where R is in Ohms and C is in Farads.
Once triggered, the circuit’s output will remain in the high state until the set time, T elapses.
The output will not change its state even if an input trigger is applied again during this time
interval T. The circuit can be reset during the timing cycle by applying negative pulse to the
reset terminal. The output will remain in the low state until a trigger is again applied.
It is desirable to trigger a monostable multivibrator either on the trailing (high to low)
or leading edges (low to high) of the trigger waveform. To achieve that external circuit
required between trigger input and pin2 of IC 555.
 For trailing edges: constitutes differentiators circuit. Diode D clamps the
positive going differentiated pulses to about +0.7v.
Figure: (a) Monoshot configuration triggered on trailing edges. (b) Relevant waveform
 For leading edges
constitutes differentiator circuit. Diode D clamps the negative going differentiated
pulses to about -0.7v and positive pulses are applied to the base of a transistor switch.
Collector terminal of transistor switch feeds the required pulses to terminal2 of IC.
32
Figure: (a) Monoshot configuration triggered on leading edges. (b) Relevant waveform
1.9. Ideal Op Amp versus Practical Op Amp

An operational amplifier (op-amp) is a Direct-Coupled high-gain, high bandwidth
differential amplifier with very high value of input impedance and very low value of output
impedance. Figure shows the thevenin’s equivalent model of a generalized amplifier with
source resistance , load resistance , and are infinite zero valued resistor
respectively.
Figure: Thevenin’s equivalent model of generalized opamp.
Figure:Thevenin’s equivalent model of an practical opamp.
33
Figure shows the thevenin’s equivalent model of an practical opamp.

Here, = Inverting input.
= Non-inverting input.
= open loop differential voltage gain
The ideal opamp model was derived to simplify circuit calculations. The ideal opamp
model makes 3 assumptions. They are:
1. Input impedance, = ∞.
2. Output impedance, = 0.
3. Open-loop gain, = ∞.
From the above 3 assumptions, other assumptions can be derived. They are:
1. Since = ∞, II = INI = 0.
2. Since, = 0, = .
3. For linear mode of opamp, output voltage finite, is infinite, =0.
4. Common mode gain = 0.
5. Bandwidth = ∞ and Slew Rate = ∞, as no frequency dependencies are assumed.
6. Drift = 0, as there is no temperature and power supply variations and so on.
Figure shows the thevenin’s equivalent model of an ideal opamp.
Figure shows the thevenin’s equivalent model of an ideal opamp.

Properties of ideal opamp are:
1. Infinite open-loop differential voltage gain.
2. Infinite input impedance.
3. Zero output impedance.
4. Infinite bandwidth.
5. Zero DC input and output offset voltages.
6. Zero input differential voltage.
34
Properties Ideal Opamp Practical Opamp

Voltage Gain. Ideal opamps have infinite open- Practical opamps have open-loop
loop voltage gain. gain in the range of 10,000 to
100,000.
Input Impedance. Ideal opamps have infinite input Input impedance varies from
impedance. hundreds of KΩ for some low-grade
opamps to TΩ for high-grade
opamps.
Output Ideal opamps have zero output Output impedance may be in the
Impedance. impedance. range of 10 to 100 KΩ.
Bandwidth. Infinite bandwidth i.e. ideal Bandwidth is limited and is
opamp amplifies all signals from specified by gain-bandwidth
DC to highest AC frequencies. product.
DC Input & An ideal opamp produces a zero For real devices, there may be some
output DC output when both the inputs finite DC output even when both the
offset voltages. are grounded. inputs are grounded. Output offset
may vary from few nano-volts for
ultra-low offset opamps to kw milli-
volts for general-purpose opamps.
Input differential Zero input differential voltage. Practical Opamp exhibits offsets
voltage. Voltage appearing at 1 input also and non-linearity.
appears at the other input for
linear mode of operation i.e.
differential inputs stick together.
1.10. Performance Parameters

1. Bandwidth
 Bandwidth refers to range of frequencies the opamp can amplify for a given
amplifier-gain.
 When the opamp is used in the closed-loop mode, the bandwidth increases at the cost
of the gain.
 The bandwidth is usually expressed in terms of the unity gain crossover frequency
(also called gain-bandwidth product).
 It is 1 MHz in the case of opamp 741. It is 1500 MHz in the case of high-bandwidth
opamp.
2. Slew Rate
 Slew-rate is defined as the rate of change of output-voltage with time.
35
 It gives us an idea about how well the output follows a rapidly changing waveform at
the input.
 The incapability of a opamp to follow rapidly rising and falling input is, respectively
due to the minimum charge and discharge time required by an internally connected
capacitor across the output.
 In case of fully internally compensated amplifier, capacitor has stable operation and
gain is unity.
 In case uncompensated amplifier, capacitor need to be connected externally, controls
the slew rate specification (connect smaller capacitor and thus get a higher slew rate.)
 It limits the large signal bandwidth.
 For a sinusoidal signal, peak-to-peak output-voltage( ), slew rate & bandwidth
are inter-related by following equation:
3. Open-loop Gain
 Open-loop gain is the ratio of single-ended output to the differential input.
 This parameter has a great bearing on the gain-accuracy specification of the opamp.
 The ratio of the open-loop gain to the closed-loop gain is called the loop-gain.
 Accuracy depends on the magnitude of the loop-gain.
 The magnitude of loop-gain depends directly on the value of the open-loop gain, as
the value of closed-loop gain is fixed.
 Higher open loop gain gives a smaller error for a given closed loop gain.
Figure: open loop gain versus frequency curve of an opamp.
4. Common Mode Rejection Ratio (CMRR)

 CMRR is the ratio of the desired differential gain ( ) to the undesired common
mode gain ( ). i.e. CMRR=20 log( / ) dB
36
 It is a measure of the ability of the opamp to suppress common mode signals.

 Variation in common mode input leads to large variation in the output of the
differential amplifier then CMRR is low (Common mode input is average value of
two inputs).
 CMRR is also defined as ratio of the change in the common mode input to the
corresponding change in the output offset voltage.
 Exceeding input voltage range will degrade the CMRR.
5. Power Supply Rejection Ratio (PSRR)
 PSRR is defined as the ratio of change in the power supply voltage to corresponding
change in the output-voltage.
 PSRR should be zero for an ideal opamp.
 PSRR falls with increase in frequency.
 PSRR also defined as ratio of the change in the one of the power supply voltage to the
change in the input offset voltage with the other power supply voltage held constant.
6. Input Impedance
 Input Impedance is the ratio of input-voltage to input-current.
 It is the impedance looking into the input terminals of the opamp.
 It is expressed in terms of resistance.
 It is assumed to be infinite to prevent any current flowing from the source supply into
the amplifiers input circuitry.
 In inverting amplifier, Input impedance=input resistance connected externally from
the source of the input signal to the inverting input terminal.
 In non inverting amplifier, Input impedance=product of the loop gain and the
specified opamp input impedance.
7. Output Impedance
 Output Impedance (Zo) is defined as the impedance between the output terminal of
the opamp and ground.
 The output impedance of the ideal operational amplifier is assumed to be zero acting
as a perfect internal voltage source with no internal resistance so that it can supply as
much current as necessary to the load. This internal resistance is effectively in series
with the load there by reducing the output voltage available to the load.
Effect of resistive load on the output signal:
37
Figure: Effect of resistive load on the output signal.
Effect of capacitive load on the output signal:
Figure: Effect of capacitive load on the output signal.
Where and is output impedance
8. Settling Time
 Settling Time is a parameter specified in the case of high speed opamps or the opamps
with a high value of gain-bandwidth product
 It gives response of the opamp to large step inputs.
 It is expressed as the time taken by the opamp output to settle within the specified
percentage of the final value (0.1% or 0.01% of the final expected value) in response
to a step at its input.
38
Figure: settling time

9. Offsets and offset drifts
 An ideal opamp should produce a zero output for a zero differential input. But it is not
so in the case of real opamps, and need to apply a DC differential voltage externally
to get a zero output.
 This externally applied input is referred to as the input offset voltage.
 Output offset voltage is the voltage at the output with both the input terminals
grounded.
 Input offset current, is the difference between the two bias current flowing towards
the input of the opamp.
 Input bias current, average of the two bias currents flowing into the two input
terminals of the opamp.
 These input, Output offset voltage and Input bias current tend to drift with
temperature.
Example:
Opamp LM 741 is specified to have a slew rate of 0.5V/µs. If the opamp were used as an
amplifier and the expected peak output voltage were 10V. Determine the highest sinusoidal
frequency that would get satisfactorily amplified
Solution:
Highest sinusoidal frequency
Here, slew rate =0.5V/µs

peak output voltage = 10V
Then =7.96kHz
39
Example:
The differential voltage gain and CMRR of an opamp when expressed in decibel are 110dB
and 100dB, respectively. Determine the common mode gain expressed as a ratio.
Solution:
CMRR (in dB) = 20log
CMRR (in dB) =20log 20log

20log =20log CMRR (in dB)
20log =110-100
20log =10dB
log =10/20
log =0.5
=3.16
Example:
In the case of a certain opamp, 0.5V change in common mode input causes a DC output
offset change of 5µV. Determine CMRR in dB.
Solution:
CMRR =
CMRR (in dB) = 20log =100dB
1.11. Peak Detector Circuit

 It is one of the applications of opamp (Figure 17.34).
 Peak detector circuit produces a voltage at the output equal to peak amplitude of the
input signal.
 Essentially, it is a clipper-circuit with a parallel resistor-capacitor connected at its
output.
Figure: peak detector circuit
40
 Here is how it works:

 The clipper reproduces the positive half cycles.
 During this period, the diode D1 is forward-biased.
 The capacitor rapidly charges to the positive peak from the output of the
opamp.
 As the input starts decreasing beyond the peak, the diode gets reverse biased,
thus isolating the capacitor from the output of the opamp.
 The capacitor can now discharge only through the resistor (R) connected
across it.
 The value of the resistor is much larger than the forward-biased diode’s ON
resistance.
 The buffer-circuit prevents any discharge of the capacitor due to loading effects of the
circuit.
 The circuit can be made to respond to the negative peaks by reversing the polarity of
the diode.
 The parallel R-C circuit time constant is typically 100 times the time period
corresponding to the minimum frequency of operation.
 The R-C time constant also controls the response time(time needed to respond to a
decreasing peak amplitude of the input signal)
 Large time constant would make the response low, so to improve response time,
decreasing time constant will make output ripple high.
 Slew rate is the primary specification that needs to be looked into while choosing the
right opamp for the clipper portion.
 Slew rate is at least equal to the highest frequency of operation.
1.12. Comparator
 A comparator circuit is a two input, one-output building block.
 It produces a high or low output depending upon the relative magnitudes of the two
inputs.
 An opamp can be very conveniently used as a comparator when used without negative
feedback.
 Because of very large value of open-loop voltage gain, it produces either positively
saturated or negatively saturated output-voltage.
41
 The output-voltage depends on whether the amplitude of the voltage applied at the
non-inverting terminal is more or less positive than the voltage applied at the
inverting input terminal.
Zero Crossing Detectors
 The comparator has two inputs:
 First input is connected to standard reference voltage.
 Second input is connected to input-voltage that needs to be compared with the
reference voltage.
 In special case, where reference voltage is 0, the circuit is referred to as zero-crossing
detector.
There are two cases: Non-inverting zero-crossing detector and inverting zero-crossing
detector.
Figure: non inverting zero cross detector

 In non-inverting zero-crossing detector, input-voltage more positive than zero
produces a positively saturated output-voltage (Figure).
 Diodes D1 and D2 connected at the input are to protect the sensitive input circuits
inside the opamp from excessively large input-voltages.
Figure: inverting zero cross detector

 In inverting zero-crossing detector, input-voltage slightly more positive than zero
produces a negatively saturated output-voltage (Figure).
Common Application of zero-crossing detector: To convert sine wave signal to a square wave
signal.
42
Figure: waveform of (a) non inverting zero cross detector. (b) Figure: inverting zero cross
detector
 In general, reference voltage may be
 positive (Figure) or
 negative voltage (Figure).
Figure: non inverting comparator with positive reference
Figure: non inverting comparator with negative reference

 In case of non-inverting comparator,
 A positive reference voltage, is given by
 A negative reference voltage, is given by
43
Opamp Comparator
General purpose opamp when used as a comparator suffers from slew rate limitation.
Low slew rate leads more transition time from one state to another. This problem can be
overcome by using a high speed opamp with compensation capacitor removed; the only
capacitance remaining is the stray capacitance across the output. Thus slew rates can be very
high. Two important parameter of a comparator is its ability to operate from a single supply
and interface conveniently with popular logic families. Figure shows schematic diagram of
opamp comparator with open collector output stage. For output stage to work properly,
output terminal needs to be connected to pull up resistor which pulls the output voltage to the
supply voltage when the output transistor Q5 is in cut-off state.
Figure: basic circuit schematic arrangement of opamp comparator.

Comparator with Hysteresis
When the input signal applied to the comparator contains noise, transition at the
output around the trip point tends to become highly erratic.
Figure: (a) ideal input signal. (b) noisy input signal

Here we consider Inverting comparator & Non-inverting comparator.
1. Inverting Comparator with Hysteresis
44
Figure: Inverting Comparator with Hysteresis

 Here is how it works:
 Let us assume that the output is in positive saturation (+ ). (Figure).
 Voltage at non-inverting input is
 Due to this small positive voltage at the non-inverting input, the output is
reinforced to stay in positive saturation.
 The input signal needs to be more positive than this voltage for the output to
go to negative saturation.
 Once the output goes to negative saturation ( ), voltage fed back to non-
inverting input becomes
 A negative voltage at the non-inverting input reinforces the output to stay in

negative saturation.
 In this manner, the circuit offers a hysteresis of
2. Non-inverting Comparator with Hysteresis
Figure: non inverting Comparator with Hysteresis

 Non-inverting comparator with hysteresis can be built by applying the input signal to
the non-inverting input (Figure).
45
 Operation is similar to that of inverting comparator.

 Upper and lower trip points and hysteresis is given by
Window Comparator
 In the case of a conventional comparator, the output changes state when the input-
voltage goes above or below the preset reference voltage (Figure).
 There are two reference voltages called lower and the upper trip points (LTP & UTP).
(Figure).
Figure: window comparator
Figure: Transfer characteristics of window comparator

Here is how it works:
Case 1:
 When the input-voltage is less than the voltage-reference corresponding to the lower
trip point (LTP), output of opamp A1 is at + and the opamp A2 is at .
 Diodes D1 and D2 are respectively forward and reverse biased.
 Consequently, output across RL is at + .
Case 2:
 When the input-voltage is greater than the reference voltage corresponding to then
upper trip point (UTP), the output of opamp A1 is and that of opamp A2 is at
+ .
 Diodes D1 and D2 are respectively reverse and forward biased.
46
 Consequently, output across RL is at + .

Case 3:
 When the input-voltage is greater than LTP voltage and lower than UTP voltage, the
output of both opamps is at – .
 Both diodes D1 and D2 are reverse biased.
 Consequently, the output across RL is zero.
1.13. Active Filters

Opamp circuits can be used to build:
 Low-pass filters.
 High-pass filters.
 Band-pass filters.
 Band-reject filters.
Also, filters can be classified depending on their order like first-order and second-
order. Order of an active filter is determined by number of RC sections used in the filter.
First-Order Filters
 A simple low-pass and high-pass active filters are constructed by connecting lag &
lead type of RC sections, respectively, to the non-inverting input of the opamp
(Figure).
Figure: First-Order active Filters (a) Low-pass filters. (b) High-pass filters
Here is how the low-pass filter works (Figure):
 At low frequencies, reactance offered by the capacitor is much larger than the
resistance value. Therefore, applied input signal appears at the output mostly un-
attenuated.
 At high frequencies, the capacitive reactance becomes much smaller than the
resistance value. Thus forcing the output to be near zero.
47
 When the signal frequency is such that, the capacitive reactance is equal to resistance
value, the output is 0.707 times the input. This is called as upper cut off frequency.
Here is how the high-pass filter works (Figure):
 At high frequencies, reactance offered by the capacitor is much larger than the
resistance value. Therefore, applied input signal appears at the output mostly un-
attenuated.
 At low frequencies, the capacitive reactance becomes much smaller than the
resistance value. Thus, forcing the output to be near zero.
Here, we consider two cases: Inverting Filter & Non-Inverting Filter.
Case 1: Non-Inverting Filter with gain
Figure: First-Order active Filters with gain (a) Low-pass filters. (b) High-pass filters
The cut-off frequency ( ) in both cases (Figure) is given by
The voltage gain (Av) in both cases is given by
Case 2: Inverting Filter with gain
Figure: First-Order Filters using inverting configuration (a) Low-pass filters. (b) High-pass
filters
In case of inverting filters (Figure). The cut-off frequency ( ) & voltage gain ( ) is given by
48
Low-pass filters,
High-pass filters,
Second Order Filters (Butterworth Filter)

 Butterworth filter is also called as maximally flat filter.
 It offers a relatively flat pass and stop band response.
Figure: Generalized form of second order Butterworth filter

Here is how it works (Figure):
 If Z1 = Z2 = R and Z3 = Z4 = C, we get a second-order low-pass filter.
 If Z1 = Z2 = C and Z3 = Z4 = R, we get a second-order high-pass filter.
 The cut-off frequency( ) & pass band gain(Av) is given by
Here, we consider 2 types of filters: 1) Band-pass filters & 2) Band-reject filters.

1) Band-pass filters
 Band-pass filters can be formed by cascading high-pass & low-pass filter sections in
series.
 These filters are simple to design and offer large bandwidth.
Figure: Narrow band pass filter
49

 At very low frequencies, and offer very high reactance. As a result, the input
signal is prevented from reaching the output.
 At very high frequencies, the output is shorted to the inverting input, which converts
the circuit to an inverting amplifier with zero gain. Again, there is no output.
 At some intermediate band of frequencies, the gain provided by the circuit offsets the
loss due to potential divider - . The resonant frequency is given by
Where Q is the quality factor

 For = = C, the quality factor and voltage gain is given by
2) Band-reject filters
 Band-reject filters can be implemented by summing together the outputs of the low-
pass and high-pass filters.
 These filters are simple to design and have a broad reject frequency range.
 It uses a twin-T network that is connected in series with the non-inverting input of the
opamp.
Figure: Second order band reject filter

 Very low frequency signals find their way to the output via the low-pass filter formed
by - - .
50
 Very high frequency signals reach the output through the high-pass filter formed by,
.
 Intermediate band of frequencies pass through both the filters, net signal reaching the
noninverting input and hence the output is zero.
 Component values are chosen by following equations:
Examples:
Refer to the first order low pass filter of figure. Determine the cutoff frequency and the gain
value at four times the cutoff frequency.
Solution:
Cutoff frequency
Gain,
In terms of dB, 20log11=20.82dB.

Gain at cutoff point= 20log11-20log0.707=17.827dB
Gain at frequency 4 times the cutoff frequency will be, 4 20log0.707=12dB.
Therefore 20.827-12=8.827dB
Example:
Figure shows a second order low pass filter built around a single opamp. Calculate the values
of R1, R2, C1, C2 and R3 if the filter had a cut off frequency of 10 kHz, Q factor of 0.707
and input impedance not less than 10kΩ
51
Solution:
For , cut off frequency is
Q factor is
Input impedance of 10KΩ, then Ω

Given Q=0.707,
Then
By formula,
Example:
Design an opamp based twin T band reject filter having a notch frequency of 100 kHz.
Specify the small signal bandwidth of the chosen opamp if the highest expected frequency
were 1 MHz.
Solution:
For band reject filter,
52
Let
1.14. Non-Linear Amplifier

 Here, the gain value is a non-linear function of the amplitude of the signal applied at
the input.
 For example, the gain may be
 Very large for weak input signals and
 Very small for large input signals.
 For a very large change in the amplitude of input signal, resultant change in amplitude
of output signal is very small.
Figure: Non linear amplifier

 For small values of input signal,
 diodes act as open circuit and
 gain is high due to minimum feedback (Figure).
 When the amplitude of input signal is large, diodes offer very small resistance and
thus gain is low.
 Resistance R1 decides the compression ratio.
53
 Higher the value of resistor R1, lesser is the compression ratio.

Common Application: AC Bridge balance detectors (Figure).
 The output of bridge may vary over a wide range around its null point.
 In order to achieve null, the output is usually applied to an AC milli voltmeter.
 If the bridge output is applied to the non-linear amplifier, the output of the non linear
amplifier will vary only in a small range for a wide variation of bridge output.
Figure: Application of non linear amplifier in AC bridge balance detector
1.15. Relaxation Oscillator

 Relaxation oscillator is an oscillator circuit, produces a non-sinusoidal output whose
time period is dependent on the charging time of a capacitor. The capacitor is
connected as a part of the oscillator circuit.
 Let us assume that the output is initially in positive saturation.
 voltage at non-inverting input of opamp is,
 This force the output to stay in positive saturation as the capacitor C is initially in
fully discharged state.
 Capacitor C starts charging towards through R.
 The moment the capacitor voltage exceeds the voltage appearing at the non-inverting
input, the output switches to – .
 The voltage appearing at non-inverting input also changes to
 The capacitor starts discharging after reaching zero; it begins to discharge towards
.
 Again, as soon as it becomes more negative than the negative threshold appearing at
non-inverting input of the opamp, the output switches back to .
54
 The cycle repeats thereafter.

 The output is a rectangular wave.
The expression for time period of output waveform can be derived from the exponential
charging and discharging process and is given by
Where B=
Figure: Relaxation oscillator and its relevant waveform

Example:
Refer to the relaxation oscillator circuit of figure. determine the peak to peak amplitude and
frequency of the square wave output given that saturation output voltage of the opamp is
±12.5V at power supply voltages of ±15V.
Solution:
The feedback factor B= = =0.825
Output waveform time period
=0.469ms
Peak to peak amplitude of Output
55
1.16. Current-To-Voltage Converter

 Current-to-voltage converter is a trans-impedance amplifier (Figure).
 An ideal trans-impedance amplifier makes a perfect current-to-voltage converter, as it
has
 zero input impedance &
 zero output impedance.
 Opamp wired as trans-impedance amplifier very closely approaches a perfect current-
to-voltage converter.
Figure: Current-to-voltage converter

 The circuit is characterized by voltage shunt feedback with a feedback factor of unity.
 The output-voltage is given by
 For AOL>>1, we have
 Closed loop input impedance is given by
 Closed loop output impedance is given by
Where is the output impedance of the opamp.

Example:
For current to voltage converter circuit of figure, determine output voltage, closed loop input
and output impedance given that chosen opamp has open loop trans-impedance gain of
100000, input impedance of 1MΩ and output impedance of 100Ω
56
Solution:
,
Then output voltage,
Closed loop input impedance Ω
Close loop output impedance, Ω
1.17. Voltage-To-Current Converter

 Voltage-to-current converter is a trans-conductance amplifier (Figure).
 An ideal trans-conductance amplifier makes a perfect voltage-controlled current
source or a voltage to- current converter.
 Opamp wired as trans-conductance amplifier very closely approaches a perfect
voltage-to-current converter.
Figure: Voltage-to-current converter

 The circuit is characterized by current series feedback.
 The output-current is given by
 For AOL>>1, we have
57
 Closed loop input impedance is given by
Where is the input impedance of the OPAMP

 Closed loop output impedance is given by
Possible Questions
1. Explain the working of an N-channel E-MOSFET with neat diagram. Explain with a
diagram output characteristic of the same. (10 Marks)(June 2014)
2. Explain the working of a CMOS inverter. (10 Marks) (June 2015)
3. Explain the construction & working and principle of operation of an n-channel JFET.
(10 Marks)(Dec 2015)
4. What are the differences between JFET & MOSFET? (2 Marks)(Dec 2015)
5. Explain with neat sketches the operation and characteristics of N-channel DE-
MOSFET ( 8 Marks) (Dec 2014)
6. Explain with neat diagram Peak detector circuit and their working.
(5 Marks)(July 2015)
7. Explain the working of an N-channel E-MOSFET with neat diagram.
(8 marks)(jan2017)
8. With circuit diagram explain any two applications of FET. (6 marks)(Jan 2017)
9. How CMOS can be used as inverter switch (2 marks)(Jan 2017)
10. Design a voltage divider bias network using a DE-MOSFET with a supply voltage
VDD=16V, IDSS=10mA, and VP=5V to have a quiescent drain current of 5mAand gate
voltage of 4V. (Assume RD=4RS and R2=1KΩ). (8 marks)(jan2017)
11. Explain the performance parameters of OPAMP. (8marks)(jan2017)
12. List out difference between BJT and FET. (6 marks)(Jan 2014)
13. Explain the working of an OPAP window comparator with circuit diagram.
(8 marks)(Jan 2014)
14. Explain N channel JFET with neat diagram. Show the output and transfer
characteristics.
15. Explain the DE-MOSFET with neat diagram
58
16. Mention merits and demerits of IGBT.

17. Explain enhancement MOSFET.
18. Differentiate JFET with MOSFET
19. Explain how the biasing can be done for MOSFET’s.
20. Brief note on popular biasing arrangements for enhance type MOSFET
21. What are the applications of FET? Explain any of the four applications.
22. How CMOS can be used as inverter
23. Explain timer IC 555 with diagram
24. Describe of multivibrator with diagrams.
25. Show how timer 555 is used to construct astable multivibator.
26. Design monostable multivibrator using timer 555.
27. What should be the slew rate choosen for an OPAMP as an inverting amplifier
configuration with gain of 10 when input is sinusoidal signal with peak to peak value
2V and highest frequency expected is 50Hz?
28. Differentiate ideal and practical OPAMPs
29. List out performance parameter of the OPAMP and explain any six.
30. Write a short note on peak detector circuit
31. Explain comparator with different possibilities.
32. Describe active filters with circuit diagram and formula
33. Write a note on
 Non linear filter
 Relaxation oscillator
 Current to voltage converter
 Voltage to current converter
59

Analog and Digital Electronics (Subject Code: 17CS32) Lecturer Notes

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Analog and Digital Electronics (Subject Code: 17CS32) Lecturer Notes

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VISVESVARAYA TECHNOLOGICAL UNIVERSITY

ANALOG AND DIGITAL ELECTRONICS

Wave-Shaping Circuits: Integrated Circuit(IC) Multivibrators. Introduction to Operational

Operational Amplifier Application Circuits:Peak Detector Circuit, Comparator, Active

The Field Effect Transistor

Difference between BJT and FET

BIPOLAR JUNCTION TRANSISTOR(BJT) FIELD EFFECT TRANSISTOR(FET)

1.1. Junction Field Effect Transistors

Construction and principle of operation

Figure: cross section of (a) an N-channel JFET; (b) a P- channel JFET

Figure: circuit symbol of (a) an N-channel JFET; (b) a P- channel JFET

Figure: N- channel JFET with VGS = 0 and positive value of VDS

Figure: versus VDS for VGS = 0

Figure: N- channel JFET with VGS = 0 and VDS ≥ VP

Figure: N-channel JFET biasing circuit.

Figure: Output characteristic curve of an N-channel JFET

Drain resistance in saturation region is given by

Figure: Transfer characteristic curve of N-channel JFET.

Figure: Characteristic curve of p-channel JFET

1.2. Metal Oxide Field Effect Transistor

Figure: cross section of an N-channel DE-MOSFET

Figure: cross section of a p-channel DE-MOSFET

Figure: circuit symbol of (a) an N-channel DE-MOSFET; (b) a P- channel DE-MOSFET

Figure: N-channel DE-MOSFET

Figure: Output characteristic curve of N-channel DE-MOSFET

Figure: Transfer characteristic curve of N-channel DE-MOSFET

Figure: cross section of (a) an N-channel E-MOSFET; (b) a P- channel E-MOSFET

Figure: circuit symbol of (a) an N-channel E-MOSFET; (b) a P- channel E-MOSFET

The basic construction of the n-channel enhancement-type MOSFET is provided in

Figure: Working of N-channel E-MOSFET

Figure: Pinching phenomenon in E-MOSFET

Figure: Output characteristic curves for an N-channel E-MOSFET

The K term is a constant

Figure: Transfer characteristics of an N-channel E-MOSFET

1.3. Difference between JFETs and MOSFETs

Leakage current in MOSFET is much smaller than that in JFET

1.4. Biasing MOSFETs

MOSFET operates in enhancement region

Apply Kirchhoff’s voltage law to output section,

Feedback Biasing Arrangement

Figure: Feedback biasing configuaraion for N-channel E-MOSFETand its DC euivalent of

A popular biasing arrangement for enhancement-type MOSFETs is provided in

Applying Kirchhoff’s voltage law to the input sections, we get

Substituting into Eq. (1), we have

Voltage-Divider Biasing Arrangement

For the output section

1.5. FET Applications

Figure: FET as an analog switch

Figure: FET as a multiplexer

Figure: FET for current limiting

Figure: Characteristics of an N channel JFET in the ohmic region

Figure: FET based phase shift oscillator.

Figure: N-channel dual gate DE-MOSFET

Figure: transfer characteristics of an N-channel dual gate DE-MOSFET.

1.7. CMOS Devices

Figure: CMOS inverter

Figure: simplified diagram of CMOS inverter

1.8. Integrated Circuit Multivibrator

Digital IC Based Monostable Multivibrator

Timer IC Based Multivibrators

Figure: Internal schematic of timer IC 555

Astable Multivibrator Using 555 Timer