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    5 views23 pages

    Us 11373568 B2 - I

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    卓七越

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    © All Rights Reserved
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    c2) United States Patent Kong et al. US 11,373,568 B2 Jun, 28, 2022 USOLI373S68B2 (10) Patent No. (45) Date of Patent i) om cc 7 o en (2) 65) @) sp (2) (8) LED GHOST IMAGE REMOVAL Applicant: Dialog Semiconductor (UK) Limited, London (GB) Inventors: Lingxin Kong. Beijing (CN): Niaogang, ‘Zhao, Beijing (CN): Ze Han, Beijing (CN): Nallong Wang, Bejing (CN): ‘aenyu Song, Besine (CN) Assignce: Dialog Semiconductor (UK) Limited, London (GB) [Notices Subject to any diselaimer, the ter of this patent is extendod or adjusted under 35 USC. 154(b) by 0 days Appl. No. 167245,563, Filed: Jan, 11, 2019 Prior Publication Data US 201910223266 AI Jul. 18, 2019 Related U.S. Application Data Contimation of application No. PCTICN2018072451, filed on an. 12,2018, Inch sb 48/32 (202001) G9 314 (2006.01) Osh 45/46 (202001) vs.cL Ce) G0N6 3/14 2013.01), HOST 45/46 (202001) Field of Classification Search oc 'HOSB 330815; HSB 33/0827; Hos SOSSS: HOSD 45/46; [10SB 48/328 usec SIS/86, 192, 198, ‘See application file for complete search history 0) References Cited US. PATENT DOCUMENTS Songs W2¢ 7202 Tate a HOR 86 Sisse 22122002 fn Sesolst Boe 30K4 Lynch Hosp 446 sisi sass not 82015 Lin rosnate Gin Bas $3016 Saiaa 2 HOS (Contin FOREIGN PATENT DOCUMENTS 8 aan 8 vole OTHER PUBLICATIONS CT Iferntional Such Report and Wren Opinio, Internation Application No, PCTICN2OING724S1, dat Oct 11,2018, 10 res. (Consinved) Primary Examiner — Tong X Le (174) Attrnes, Agent, or Firm Stephen f Ackerman “) ABSTRACT, Aight emitting diode (LED) circuit for preventing parasitic ‘eurren ow trough a fst LED when the fst LED is in a ‘off sate js deseribed, where the parasitic cumeat flow i result of one or more parasitic capoctances, the LED circuit ‘comprising the fist LED, anda fist current switch coupled to the fir LED and arranged to enable a etrrent Row trough the fast LED when the ist eueret swe inn fon slate, where the fist current switch is aranged 10 ‘discharge the one oF more parasite espacitanees when the First eurent site isin the on sate 14 Claims, 13 Drawing Sheets US 11,373,568 B2 Pape 2 (66) References Cited US, PATENT DOCUMENTS, dasiess m2 92016 in oosineet 7 A+ 102008 Thien awe x3216 20100295845 AL_ 11/2010 Somerville x aL aosoniaion At* 12013 Lin cosa 2ouaionaass at cin an SHS82 2ovgoseosee at Be Hosa 2ULDOLATTBS Ate Yao 6006332 (OTHER PUBLICATIONS “minting Ghost snage Curt in Color.ED Dip Syms Using the MAX6O72-MAN6O7S LED Diver,” maim itt. Maxim > Design Support > Techical Document > Apiction Notes» Misellaness Circuits» Applicaton Note 411, pp. 1-10 Cine ie Aion. Apia No. 17 ‘in Dai Semiconductor (UK) Lind, ded Feb 23,3022 1 rages * cit by examiner US 11,373,568 B2 Sheet 1 of 13 Jun, 28, 2022 U.S. Patent 14V 400d } OIA US 11,373,568 B2 Sheet 2 of 13 Jun, 28, 2022 U.S. Patent 14Y 409d & ‘OIA = 06I~]/-89 _ wI~ Pa OTE I 800 7 fe 92 set fw snT.,, cout 20, 2 os gt Na on He UE ag oe Maa x OBY y 901 U.S, Patent Jun, 28, 2022 Sheet 3 of 13 US 11,373,568 B2 ‘cmc oe FIG. 3 Prior Art — oe U.S, Patent Jun, 28, 2022 Sheet 4 of 13 US 11,373,568 B2 Time 4 Prior Art FIG. s a Jun, 28, 2022 U.S. Patent tl amy auny sbzmyos%p Jouotnippy SP ybusy ay S seT os ag 4abuay pay ‘ ito au = U.S, Patent Jun, 28, 2022 Sheet 6 of 13 US 11,373,568 B2 114615 606 3 | i. Real length a 0 Response time FIC. 6 ——— Real length in — meer 708 710, Response time a iAgitiongt FIG. 7 U.S, Patent Jun, 28, 2022 Sheet 7 of 13 US 11,373,568 B2 800- | 802- a i | ie ae current ge Real length aie \agg \eggg Response time Additional, discharge time #1617 18 a li = 06, Response tine FIG. 9 U.S, Patent Jun, 28, 2022 Sheet 8 of 13 US 11,373,568 B2 #19 120 121 122 1000 ‘ Pt : ' 1 1002: i oa 73 i 1004 1 1 a Additional discharge tine FIG. 10 U.S, Patent Jun, 28, 2022 Sheet 9 of 13 US 11,373,568 B2 LL | 1134- FIG. U.S, Patent Jun, 28, 2022 Sheet 10 of 13 US 11,373,568 B2 FIG. 12 RRRR US 11,373,568 B2 Sheet 11 of 13 Jun, 28, 2022 U.S. Patent Ge LiJt~sees 1 9281 “Frege e+} “tet ---b-f ye op fe US 11,373,568 B2 Z 8 0% 202 00 = J Vis | a Edd @dd] bd 7 “tte Taras you eet SA! 2 5 2 = & 4G a U.S, Patent Jun, 28, 2022 Sheet 13 of 13 US 11,373,568 B2 1500- ™~ Start 1501 Providing a light emitting diode (LED) circuit, comprising a first LED, a first current switch, and one or more parasitic capacitances 1502 Enabling via the first current switch a current to flow through the first LED, when the first current switch is in an on state and discharging the one or more parasitic capacitances 1503 Preventing a parasitic current flow through the first LED when the first LED is in an off state, where the parasitic current flow is a result of the one or more capacitances FIG. 15 US 11,373,568 B2 dl LED GHOST IMAGE REMOVAL “This application is a Continuation application (DSI- (0856) of application no. PCT/CN2014/072451, filed on Jan. 12,2018, omned by common assignee, and which is herein incorporated by reference in its entirety. ‘TECHNICAL FIELD The present disclosure relates to light emiting diode (LED) apparatus and methods for operating LED appara Jn panicula, this disclosure rates to ghost image removal in multiplexed LED circuit. BACKGROUND A multiplexed light emitting diode (LED) may is a type of LED eiouit that may be used in applications involving LED matrix bocklhting, where hundeeds or thousands of LEDs are controlled independently to provide backlighting for a liguid erystal display (LCD). Altematively, a mul plexed LED array may he used to provide an LED display. ‘AED isa diode that emits light Types of LEDs include bot are not mite to, MiniL EDs and MicroL EDs. Types of LED displays inlude, but are not limited to, dot-matix lisplays and multiple-seument displays such ak: seven se4> rent displays: nine segment displays; fourteen segment splays: an sixteen segment displays FIG. isa schematic diagram ofa multiplexed LED array 100 in accordance with the prior art. The multiplexed LED aay comprises a plurality of LEDs and a plurality of Sites, Operation ofthe svtches controls the Muminato ‘of the LEDs. The switches ate selectively operated so that the LEDS inthe ary 100 canbe selectively switched on oF ‘off so thot desired illumination pattems ean be exeated. Parasitic capacitances are present in the multiplexed LED aray 100 and may, for example, be a result of pockage pin ‘spscitance, printed circuit board (PCB) tracking eapsci= tance or LED capacitance. IG. 2 is an altemative schematic digram of the mul plexed LED array 100 of FIG. I with parasitic capacitances Shown. The parasite capacitances are represented in the Schematic diagram of the multiplexed LED array 100 FIG. 2 bya plurality of parasitic capacitor symbols, and may ‘he reed to herein generally as "parasite capacitors” for Daring operation of the multiplexed LED army 100, change may be sored due to the parasitic capacitances, ‘which can result ina ghost image. FIG. 3 isa schematic of 4 seven sogment LED display counting sequentially from 1 to 3 10 demonstrate ghost images Ata list display step 300, the seven segment LED display illuminates a fist segment 302 apd a second segment 304 with the remsining segments ssitched off, AU second lisplay step 306, the seven seament LED display iluinates. the necesstryseginents to display the number "2", with the remaining sepments switched off, However, the second Seument M4, which should be switched of, appears dimly iluminates the necessary segments to display the umber °3", with the remaining segments switched off However, a third segment 310, which should be switched coll appears dimly It he dimly lit sggments are ghost images and result from the parasitic eapaeitanees of the mliplesed LED array 10, Tteambe observed tat the ghost images appear om segments 2 which were illuminated on aa immediately preceding dis- Play step and are switched off on the current display sep. Existing systems implement additional, dedicated ‘cuit to provide a resistive discharge ath to discharge the parasitic capacitances to prevent the oecurtence of ghost images SUMMARY Iv desirable o provide « mntplexed LED array that ‘doos not require ational, dedicated circuitry prevent the occurence of ghost images that aise due to parasitic ‘capacitances. ‘According 1 fist aspect of the disclosure thore is provided alight emitting diode (LED) circuit for preventing Pras curren Now through fist LED when the ist LED 'sinan offstae, wherein the parasitic euret flow i result fof one of more parasitic capacitnees, the LED cecuit ‘comprising the frst LED and fist current switch coupled. to the first LED and arranged to enable a current fw trough the frst LED when the First eueret swite sin an ‘on sate, wherein the fist current switch is amanged (0 sischarge the one or more parsitie capacitances when the frst curent site inthe on sit ‘Optional, the fist current switch provides a curent regulation function to provide the current flow through the fist LED when the fir current switch isin an om state, ‘Optionally, the fst LED is in an on state when the fist LED is coupled 10 a supply voltae and the frst curent site ii the on stat, ethervise the frst LED is the off ly, the LED eiteuit comprises a fist power the first LED is coupled to the supply ‘ole when the fst power switch si anon state and the Fist LED is decouple rom the supply voltage when the first power switch i i an off state ‘Optional, te is current switch is inthe on slate prior to the fist power switch changing tothe on state, ‘Optionally. de ist current switch remains inthe on state at least uni the fst power switch changes to the on state Optional, the fist curent switch and the fist power site both change then state at approximately the same ‘Optionally, the one or more parasitic capacitances are lscamged when the frst current switch and the fist power svt are bot inthe on state Optionally, the one or more parasitic capacitances are sligchanled When te frst cureen witch inthe on state snd tho fist power switch i in the off ‘Optionally, the fist current switch sin the on sate afer the fist power switch has changed tothe of state ‘Optionally, de first current switch remains inthe on state hilt the fist poser switch changes fom the on sate tothe off sate Optionally, the parasitic capacitances comprise «fist porate expocitince and a socond paste capacitance. ‘Optionally, the LED circuit comprises a second LED and 1 sevond curren switch coupled fo the second LED and ‘mange 10 enable current flow though the second LED ‘hen the second curren switch i in anon slate, whervin the second current switch i arranged to dselage the one a more of the first parstic capacitance and other parasitic ‘capacitances when the second current switch isin the oa ‘Optionally the other parasitic capocitances comprise & Ihied parasitic capacitance US 11,373,568 B2 3 Optionally, de first current switch provides fist current regulation fonction o provide the current flow through the first LED when the first eueret switch isin an on state and the fist current switch is aranged to discharge one or more ‘ofthe fist and second parasitic capacitances and the second ‘current switch provides a second current regulation funtion to provide the curent flew through the second LED when the sone eurent switch is in an on state and the second ‘current swite is aranged to discharge one or more of the fist and thie pansiie capacitances ‘Optionally, the fst LED is in an on state when the fst LED js coupled to a supply voltage and the frst curent sovte iin the om ste, others he first LED isi the ofl State andthe soeond LED i a anon sate when the second LLED is coupled tothe supply vollage and the ist curent svt is inthe on ste, otrwise the second LED isin the ff sate Optionally, the LED circuit comprises a fist power sovteh, wherein the frst LED is coupled to the supply ‘voltae when the fst power switch sin anon state, and the Fist LED is decoupled from the supply voltage when the fist power switch i ia an off state and the second LED is coupled tothe supply voltage when the fist power switch is. ian on state, andthe second LED is decoupled from the supply voltage when te frst power swviteh is in an of state. ‘Optional, one or both ofthe fist current site and the second current switch ae inthe on sate peor to the frst power switch changing to the on stat. ‘Optionally. ene or both ofthe fst cureat switch and the secon eurent sith retain inte on sate atleast ut the power switch changes (othe on state ‘Optional, one or both ofthe fist current swith and the second current switch tothe on sate at approximately the Same time asthe first power switch changes to the on stato ‘Optionally, the second parasitic capacitance is discharge ‘when the first current switch and te fit power swith are both in the om state, and the thi parasite capacitance is dligcharged when the second current switch snd the first ower switch are bot inthe on sate ‘Optionally. the fst parasitic capacitance is discharged ‘when atleast one ofthe fst curent switch andthe second ‘curren sith are in the om sate nd Te His power ste isin the of sate Optional, at east one ofthe fis current swith and the second erent switch ae inthe on state afer the fist power Ste has changed tothe of state ‘Optionally, the atleast one of the Bt current switch and the second current switch rem inthe om state whilst the first power switch is changed from the on slate 0 the off ‘Optionally, the LED circuit comprises one of more LED strings. wherein cach LED string Comprises one or more LEDs. ‘According to a seeond aspect of the dselosure thee is providel a method of operating ight emitting diode (LED) ‘eu of the type comprising a fist LED, fist cumtent Sitch and one or more parasitic eapacitances, the method comprising enabling, via the fist current switch current 10 fw through the fst LED when the ist current swith isin ‘an on sate and dscharzng, via the frst curent site, the fone oe more paraiie capacitances when the fist current Ssvteh is in the an state thus peeventing parasite eurent flow trough th first LED when the fist LED isin an olf state, wherein the parasitic curent flow i result ofthe one ‘oF aire parsiti capocitance, According to a thinl aspect of the diselosure there is provided a controler for preventing parasite curent flow 4 through a first LED when the fist LED is in an off sta ‘wherein the parasitic current How isa result f ene or more parasite capacitances, wherein the coatoller is aranged to ‘control the switching of a fst current switch; wherein the fist current switch is coupled tothe fst LED and arranged to enable a current flow through the fist LED when the fist ‘cre site sn aon state a the fist erent swith i ‘mange to dischange the one oF more parasitic capacitances ‘when the first current vith i in the on sate RIFF DESCRIPTION OF THE DRAWINGS. Te disclosures described in further detail below by way ‘of example al with reference to the seeompanying dea ings, in whieh FIG. Lisa schematic diagram of a muipexed LED array in coordance with the prorat FIG. 2isa schematic diagram of a muliploed LED array with parasite eapacitances showa, in accordance with the Priorat FIG. 3 is an ilstration of a 7 segment LED display, showing an illumination sequence 10 demonstrate ghost images TG. 4 is a typical timing soquence of the switching ‘operation ofthe multiplexed LED ary of FIG. Vand FIG. in accordance with the prior art IG. 5 isa timing sequence of the switching operation of the multiplexed LED amay of FIG. Vand FIG. 2 in soso dance with a fist embodiment ofthe present disclose FIG. 6 isa timing sequence ofthe switching operation of the mulipiexed LED array of FIG. Vand FIG. 2 in secor ‘dance wilh» second embodiment ofthe preset ditelosure FIG. 7 fsa timing saquence athe switching operation of the muliplexed LED aay of FIG. Vand FIG.2 in osor dance with a third embodiment of the present disclosure. FIG. 8 timing sequence ofthe switching operation of the multiplexed LED array of FIG. Vand FIG. 2 in seor- ‘dance wit the thied embodiment of the present disclosure TIG.9is a timing sequence of the switching operation of the multiplexed LED amy of FIG. Vand FIG. 2 in soso ‘dance with the second embodiment ofthe present disclosure. FIG. 10s timing soquence ofthe switching operation of the muliplexed LED aray of FIG. Vand FIG. 2 in seeor- ‘dance with the fst embodiment of the present disclosure IG. 11 shows simulation results ofa timing sequence of the switching operation ofthe multiplexed LED array of FIG, Hand FIG. 2 that results in the occurence of upper host images FIG. 12 shows simulation sults ofa ining seseace of the switching operation ofthe multiplexed LED aera of FIG. Land FIG. 2 that results i the occurrence of lowe host images IG. 13 shows simulation resus ofa timing sequence of the switching operation of the multiplexed LED seray of FIG, 1 and FIG. 2 in secordanee withthe thin! embodiment ‘of the present diselosur, that resus ia the removal of ghost images TIG, 14 isa schematic diagram ofa controller coupled to 2 multiplexed LED anay. FIG. 18 is flowchart for a metbod of operating alight ‘emiting diode (CED) circuit in the prevent disclosure, DETAILED DESCRIPTION ‘he multiplexed LED array 100 comprises a plurality of LED strings, as shown in FIG, 1. The plurality of LED strings comprises fist LED string 102, 4 second LED US 11,373,568 B2 5 string 14, anda thin LED sing 106. Bach ofthe plurality COFLED strings 102, 104, 106 compses a plurality of LEDS The is LED sing 102 comprises fist LED 198, a second LEED 10 and third LED 112, which ave aso labelled 11, 21 and 131, respectively. The second LED string 104 ‘comprises fourit LED 114, a filh LED 116 and a sixth TED 18, which are also Inbellal L12, [22 and 32, respectively. The third LED string 106 comprises a event CRD 120, an eight LED 122 anda ninth LED 124, which are also labelled 35 L13, 123 and L33, spectively The LEDs inthe array 100 are selectively operated under ‘contol of set of switch elements, These switch elements preferably comprise a fist set of power switches (PL, P2, PS in this example), which are coupled with the anodes ofthe [LEDs and 2 second set of eurent switches (G1, G2, G3 ia this example). which are coupled with the eanodes of the LEDs. Inthe example shown in FIG. 1, the first second and third LEDs 108, 110, 112 eich have cathode terminal eoupled 0 4 ist current switch 126 a first commer hel. The fourth, fh and sixth LEDs M4, cathode terminal couple toa sscond curent switch 128 at a second common cathode node ne2. The seventh, cighth and ninth LEDs 120,122, 124 each have a cahose terminal coupled to a third current site 130 at a third ‘common cathode node ne3. The frst, second and third ‘curren switches 126, 128, 130 ae also labelled G1, G2 and G3. respectively. Te frst, fourth and seventh LEDs 108, 114, 120 cach ‘ave an ancde terminal couple toa fist power switeh 132 At frst common anode node tal, The second, fifth and ighth LEDs 110, 116, 122 each have an anode terminal ‘coupled to a second power swite 134 ata second common anode node naz. The thied, sixth and nina TDs 112, 18, 124 cach have an anode tenninal coupled wo a third power sovtch 136 at third common anode node na3, The fis, Second and thd power switches 132, 134, 136 are also Iabelid PA, P2 and P3, respectively The fis, second, ad thied power switches 182, 134, 136 are arranged to couple the plurality of LEDs to a supply voltage VS (cither diretly or indirectly), when the power Svtehes 132, 134, 186 closed. The soppy volage VS is apable of supporting a current required for operation of the TEDs As shown in FIG. 2, a fist parasitic capacitor 200 tas @ fist terminal coupled tothe Rist common anode node nal and sccond terminal coupled to ground. second paresitc ‘ipacitor 202 has «first teminal coupled to the second ‘common anode node 2 apd a secon teeminal coupled to ‘ground. A third pari capacitor 204 thas fis erminal ‘coupled to the tind common anode node na and a second terminal coupled to ground, ‘The first terminal ofthe fist parasitic capacitor 200 is at fst anode vokage S1; the fist terminal of the second 202 i aa second sod voltage S2: and the tind parasiie capacitor 204 is at third anode voltage S3 '\ founh parisiic capacitor 206 has a fst terminal coupes to the first common cathode nade ne and second terminal coupled 10 ground. ith parasite capacitor 208 Ts a firs terminal coupled wo the second common cathode ode ne? and 2 second erninsl coupled 1 ground. sixth parasite capacitor 210 has a first terminal coupled to the third common cathode node ne3 snd a second terminal ‘couples to round “The est terminal ofthe fount parasitic captor 206 is ata fist cathode voltage Dts the fist terminal ofthe fifth 6 parasitic capacitor 208 is a « sovond cathode voltage D2; and te first terminal ofthe sixth parasite epacitor 210 is ata thd cathade volage D3. The first second, third, fourth fh and sith parasitic

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