electronics

Article
A Design Methodology of High-Efficiency Dimmable Current
Sink for Current-Regulated Drivers
Ibrahim Abuishmais * , Fadi R. Shahroury and Hani Ahmad

Department of Electrical Engineering, Princess Sumaya University for Technology, Amman 11941, Jordan
* Correspondence: i.abuishmais@psut.edu.jo

Abstract: This paper proposes a high-efficiency and dimmable current sink topology along with
a design methodology for low node processes. The design methodology is demonstrated using a
boost-based WLED driver application. In this work, the focus is on current regulation rather than
voltage regulation. Therefore, the proposed topology exploits a smaller and faster NMOS pass device,
replacing the conventional PMOS-based LDO arrangement. An amplifier-boosted pass-transistor
current sink topology combined with a 5-bit programmable degenerated source resistor is being
utilized for high-efficiency and brightness control. The realized WLED driver validates the proposed
topology and the design methodology utilizing 40 nm CMOS TSMC technology. The design takes
advantage of the programmability of the resistor to enhance the system’s power efficiency. This
programmable resistor enables dimmability via current segmentation with a 1 mA step for a total of
25 mA. For a 500 mV voltage ripple at the DC-DC converter output driving 6 WLEDs with a 3.2 V
forward voltage drop each, a worst-case current ripple of 200 µA and simulated efficiency of 97.6% is
achieved for optimum pass-transistor size.

Keywords: current sink; WLED driver; programmable resistor; high efficiency; design methodology

Citation: Abuishmais, I.; Shahroury, 1. Introduction

F.R.; Ahmad, H. A Design
LED-based systems such as smartphones, TVs and other consumer electronic appli-
Methodology of High-Efficiency
cations are becoming very popular. These systems require high efficiency and accurate
Dimmable Current Sink for Current-
Regulated Drivers. Electronics 2022,
brightness control. Thus, current drivers are ubiquitous. With the increase in performance
11, 2566. https://doi.org/10.3390/
requirements, namely, efficiency, current accuracy and dimmability, which are needed in
electronics11162566 many applications, an optimized current sink driver solution is vital [1–4]. Modern IC
chips are rich with digital content favoring lower node processes [5,6]. Moreover, lower
Received: 4 July 2022
node processes yield both lower area and power loss. However, designing a current sink
Accepted: 12 August 2022
driver using a lower node process is challenging due to the lower output impedance of the
Published: 17 August 2022
MOS device, i.e., ro [7,8]. Due to the popularity of the current sink, a systematic, scalable
Publisher’s Note: MDPI stays neutral and easy-to-follow design methodology is needed [9–14].
with regard to jurisdictional claims in Figure 1 depicts a typical application of a current sink driver as part of an LED driver.
published maps and institutional affil- Here the current sink driver ensures that the desired current level passes through the LED
iations. string [15,16]. The DC-DC converter produces an output voltage that is suitable for the load
from a given input voltage. Due to the switching nature of the converter, a ripple voltage
superimposed over a regulated output average voltage is produced. Consequently, the
LED current is being affected by this ripple resulting in a ripple current that passes through
Copyright: © 2022 by the authors.
the LEDs. A simple current sink driver could be implemented using a sensing resistor [17],
Licensee MDPI, Basel, Switzerland.
as shown in Figure 2. In this topology, the resulting LED current is prone to ripple in the
This article is an open access article
output voltage, i.e., ∆ILED = ∆Vout /Rsense [18]. Furthermore, the varying forward voltage
distributed under the terms and
conditions of the Creative Commons
of the LEDs leads to an imbalanced current among strings in multi-string arrangements,
Attribution (CC BY) license (https://
even in an equal number of LEDs per string [19].
creativecommons.org/licenses/by/
4.0/).

Electronics 2022, 11, 2566. https://doi.org/10.3390/electronics11162566 https://www.mdpi.com/journal/electronics

Electronics 2022, 11, x FOR PEER REVIEW 2 of 1
Electronics 2022, 11, x FOR PEER REVIEW 2 of 14
Electronics 2022, 11, 2566 2 of 13

VOut
VOut

DC-DC
DC-DC
Converter
Converter
Vin
Vin

current sink
current sink
driver
driver

Figure 1. A typical application of the current sink driver in LED drivers.

Figure1.1.AAtypical
Figure typical application
application of the
of the current
current sink sink
driverdriver
in LEDindrivers.
LED drivers.

VVOut
Out DVout
DVout
Vin
V in

DC-DC
DC-DC
Converter
Converter
IILED
LED DILED
DI LED

EA
EA RSense
R
Vref Sense
Vref
Compensator
Compensator

Figure2.2.AAsensing
Figure sensing resistor
resistor current
current sinksink driver.
driver.
Figure 2. A sensing resistor current sink driver.
Therefore,
Therefore, a more robust
a more current
robust sink driver
current topology
sink driver is neededistoneeded
topology suppress tothe current the cur
suppress
rippleTherefore,
effect on thea more robust
sensing point.current sink driver
In the solution topology
proposed in [20],is shown
neededintoFigure
suppress
3, an the cur-
rent ripple effect on the sensing point. In the solution proposed in [20], shown in Figure
rent ripple effect on the sensing point. In the solution proposed
error amplifier and PMOS pass-transistor are introduced between the DC-DC converter in [20], shown in Figure
3, an error amplifier and PMOS pass-transistor are introduced between the DC-DC con
3, an error
output amplifier
and the andThe
LED string. PMOS errorpass-transistor
amplifier forces the areLED
introduced
current tobetween the DC-DC
be insensitive to a con-
verter
total output and the
forward LED string. The error amplifier forces the LED current to be insen
verter outputvoltage
and the drop
LEDacross the LED
string. The in any amplifier
error given string. Thisthe
forces is achieved by forcing
LED current to be insen-
sitive to a total forward voltage drop across the LED in any given string. This is achieved
the voltage
sitive over the
to a total sensing
forward resistordrop
voltage to equal
across the LEDVxin
a reference f ) . The
(reany PMOS
given passThis
string. device’s
is achieved
by forcing
presence the voltage
between the DC-DCover the sensing
output and the LED resistor
stringto equalvoltage
output reduces 𝑉
a reference the .
voltageThe PMOS
𝑥(𝑟𝑒𝑓). The
by forcing the voltage over the sensing resistor to equal a reference 𝑉𝑥(𝑟𝑒𝑓) PMOS
ripple at the output node, hence, the resulting current ripple. This topology
pass device’s presence between the DC-DC output and the LED string output voltage re requires a high
pass device’s
voltage
presence
amplifier andripple
between
PMOSat device,
the DC-DC
deeming
output andtothe
it impractical
LEDon string output voltage re-
duces the voltage the output node, hence, the ingrate
resulting the same ripple.
current chip. This to
duces the voltage ripple at the output node, hence, the resulting current ripple. This to-
pology requires a high voltage amplifier and PMOS device, deeming it impractical to in
pology requires a high voltage amplifier and PMOS device, deeming it impractical to in-
grate on the same chip.
grate on the same chip.
 Electronics 2022, 11, x FOR PEER REVIEW
Electronics 2022, 11, 2566 3 of 13 3 of 1
Electronics 2022, 11, x FOR PEER REVIEW 3 of 14

VOut DVout VLED DVLED

DC-DC VOut DVout VLED DVLED
DC-DC
Converter
Converter
Vin
Vin ILED DILED
ILED DILED

Compensator
Compensator
& Vx
& Vx
PWM EA
PWM EA Vx(ref)
Vx(ref) RsensRsens

Figure
Figure 3. Dimmable
Figure 3.3.Dimmable
currentDimmable current
sink driver
current sink
based
sink driver
on PMOS
driver based
based on PMOS
device with
on PMOS device
withwith
boosting
device boosting
amplifier.
boosting amplifier.
amplifier.

Thecircuit
The circuit inThe
Figurecircuit
4 isinin
an Figure 4 is
anan
alternative
Figure 4 is alternative
option
alternative option
foroption for for
realizing realizing
a current
realizing a current
sink
a current[21]. sink
[21]. [21].
sinkThis This Th
topology
topology features similar
topology features
features similar
advantages
similar advantages
as as as
the previous
advantages thethe previous
solution
previous in solution
overcoming
solution in overcoming
the LEDs’
in overcoming the LED
the LEDs’
forward voltageforward
forward voltage
voltage
variation and variation
variation and
minimizing and minimizing
minimizing
the current the current
theripple.
current ripple.
ripple.
Here, Here,
Here,
the the current
the current
current is directl
is directly
is directly
regulated
regulated usingregulated
an NMOS using
using ananNMOS
instead NMOS instead
of a PMOSinsteadof of
a PMOS
a PMOS
pass-transistor. pass-transistor. Thus,
pass-transistor.
Thus, making it making
Thus,
more it more
making
suitable suit- sui
it more
able for current-sensitive
able fordevices
for current-sensitive current-sensitive devices
such as LED devicessuch
withsuch as LED with current-dependent
as LED with current-dependent
current-dependent brightness. More-
brightness. More
brightness. Moreover,
over,
the low voltageover, the
error low
lowvoltage
theamplifier
voltage error
and amplifier
error
the NMOSand
amplifier thethe
and
device NMOS
NMOS
might device might
device
easily easily
be might be integrated
easily
integrated be the
on on o
integrated
the same chip.
the same chip.
same chip.

Vin
V VVOut
in
Out
DVDV
out
out
DC-DC
DC-DC
Converter
Converter

ILED
ILED

Compensator Vx DVx
Compensator
& PWM Vx DVx
& PWM Vref
Vx(ref) Vref Vds
Vx(ref) Vds
VRsens DVRsens
VRsens DVRsens
Rsens
Rsens

Figurecurrent
Figure 4. Dimmable 4. Dimmable currentusing
sink driver sink driver using
booting booting and
amplifier amplifier
NMOS anddevice.
NMOS device.

Figure
Table 1 summarizes4. Dimmable
Table current
1 summarizes thesink
the strengths driver
strengths
and using booting
of theamplifier
and weaknesses
weaknesses of the and
reviewed NMOSrelevant
reviewed
relevant device. art men-
art men-
tioned above. The current sink driver size, sensitivity to ripple, easiness of integration and and
tioned above. The current sink driver size, sensitivity to ripple, easiness of integration
systemTable 1 summarizes
complexity are the the strengths
metrics used toand weaknesses
compare citedoftopologies.
the reviewedThisrelevant art men
system complexity are the metrics used to compare the cited the
topologies. comparison
This comparison
tionedthe
favors above. The current sinktopology
NMOS-device-based driver size,
based sensitivity to ripple,
on the chosen easiness
critical metricsoflisted
integration an
favors the NMOS-device-based topology based on the chosen critical metrics listed in thein the
system complexity are the metrics used to compare the cited topologies. This compariso
summary table. This topology is modified in this work to achieve a programmable current
favors the NMOS-device-based topology based on the chosen critical metrics listed in th
sink driver by utilizing a programmable resistor to enable current dimmability and enhance
system efficiency. This work proposes a design methodology for this solution and utilizes a
WLED driver application example for demonstration. The proposed methodology guides
Electronics 2022, 11, 2566 4 of 13

and assists the designer to reach an acceptable solution given different power efficiency,
size and gain-bandwidth-product (GBP) conflicting factors. This methodology applies to
any process node size and helps reduce product design life cycle.

Table 1. Strengths and weaknesses of the reviewed current sink driver topologies.

Sensitivity to
Topology Size (1) Efficiency (1) Integrability Complexity
Current Ripple (2)
Sensing resistor
Small Low Hard Simple Very sensitive
current sink driver
PMOS-based
Large Moderate Very hard Complex Sensitive
current sink driver
NMOS-based
Medium High Easy Moderate Less sensitive
current sink driver
(1) for the same ∆ILED requirement. (2) absolute accuracy.

This paper is organized as follows: the programmable resistor current sink topology is
described in Section 2. The design methodology and an application example are discussed
in Section 3. Finally, concluding remarks are provided in Section 4.

2. Programmable Resistor Current Sink Topology

The proposed topology with a programmable resistor bank is depicted in Figure 5.
The circuit consists of an N number of LED strings; each has an amplifier-boosted pass-
transistor (M1) and a digitally-programmable integrated resistor. The Vout represents
the output voltage of the DC-DC converter. There are two options to realize current
dimmability/brightness control; programmable Vre f or programmable resistor. This work
uses a 5-bit programmable resistor bank to control the LED current with 25 segments of a
1 mA resolution step. Note that the Vre f is set to a constant voltage value of 150 mV [22,23].
Electronics 2022, 11, x FOR PEER REVIEW
Here, the efficiency improvement is realized by a programmable resistor instead of reference5 of 14

voltage programmability.

Vin
DC-DC VOut
Converter iout (t)

ILED DIout
+

Vx
VFD

Compensator ILED
& PWM

Vx(ref) VOut DVout

Vref δ Vx

M1 VDS VFD
Vx (t)
Vx DVout
a0 VDS
VRsen
a4
VRsen

Figure 5. Dimmable current sink driver using amplifier-boosted NMOS device and a programmable resistor.

Figure 5. Dimmable current sink driver using amplifier-boosted NMOS device and a programmable
resistor.

The current sink’s power loss comprises three components; the boosting amplifier
quiescent current, pass-transistor device, and sensing resistor. The boosting amplifier
power loss can be ignored as its quiescent current is much lower than the string’s current.
The power consumption in the pass-transistor is given as:
 Electronics 2022, 11, 2566 5 of 13

The current sink’s power loss comprises three components; the boosting amplifier
quiescent current, pass-transistor device, and sensing resistor. The boosting amplifier
power loss can be ignored as its quiescent current is much lower than the string’s current.
The power consumption in the pass-transistor is given as:

Ploss(n− MOS) = VDS × ILED (1)

Here the VDS is proportional to the current passing through the string and inversely
proportional to the device aspect ratio (i.e., W/L). Therefore, in dimmable designs, the
maximum LED current dictates the device’s size based on the power consumption budget.
This portion of power loss is comparable in both designs: fixed sensing resistor and
programmable resistor. The power loss in the sensing resistor is given by:

Ploss( Rsens) = VRsens × ILED (2)

If the ILED is controlled by changing the Vre f , the power loss will vary linearly with
ILED because the boosting amplifier forces VRsens to equal Vre f However, in the case where
ILED is controlled by changing the sensing-resistor value, the power loss in the sensing
resistor will be independent of ILED value and only dependent on the preset reference6 of 14
Electronics 2022, 11, x FOR PEER REVIEW
voltage level. So, for designs that require dimmability, the latter solution is more power-
efficient. The previous observation is illustrated in Figure 6.

Figure 6. 6.
Figure Power loss
Power and
loss andreference
referencecomparison
comparison for
for current
current sink driver designs
sink driver designswith
withfixed-
fixed-and
and pro-
grammable-sensing resistors.
programmable-sensing resistors.

DueIt isto
worth mentioning
the finite that there
bandwidth is a trade-off
of the between
DC-DC stage efficiency𝑉and
controller, accuracy. In-
𝑜𝑢𝑡 contains a ripple
creasing the drain-to-source voltage (V ), decreases the transistor’s
(∆𝑉𝑜 ) in addition to the DC component. This ripple is dominated by a fundamental
DS output resistance fre-
(ro ) and, consequently, degrades the current accuracy for a specific channel length of the
quency that matches the converter’s switching frequency (𝑓𝑠𝑤 ). An ideal current sink
pass-transistor. It is easier to design the boosting amplifier for a fixed reference voltage
driver should be able to force a ripple-free LED DC current, regardless of the voltage rip-
rather than a variable value, as the former requires a lower input common-mode range for
ple. Practically,
an identical gain ∆𝑉 [24].the current components by imposing current ripple ∆𝐼 due to
𝑜 affects
target
the finite output resistance of the current driver. The output resistance of the proposed
circuit is approximated by:
𝑅𝑜𝑢𝑡 = 𝐴𝑖 ∙ [𝐴 + 1] ∙ 𝑅𝑠𝑒𝑛𝑠 + 𝑅𝑠𝑒𝑛𝑠 + 𝑟𝑜 ≈ 𝐴𝑖 ∙ [𝐴 + 1] ∙ 𝑅𝑠𝑒𝑛𝑠 (3)
where 𝐴𝑖 is the intrinsic gain of the pass-transistor 𝑀1 (expressed as: 𝑔𝑚 × 𝑟𝑜 ), 𝑟𝑜 is the
small-signal AC resistance of the pass-transistor operating in saturation and A is the
boosting amplifier open-loop gain.
The higher the 𝑅𝑜𝑢𝑡 of the current sink, the higher the current accuracy. This can be
achieved by increasing the intrinsic gain and/or the boosting amplifier gain. For a fixed
device’s current and channel length, maximizing 𝐴𝑖 would require increasing device
Electronics 2022, 11, 2566 6 of 13

Due to the finite bandwidth of the DC-DC stage controller, Vout contains a ripple
(∆Vo ) in addition to the DC component. This ripple is dominated by a fundamental
frequency that matches the converter’s switching frequency ( f sw ). An ideal current sink
driver should be able to force a ripple-free LED DC current, regardless of the voltage ripple.
Practically, ∆Vo affects the current components by imposing current ripple ∆I due to the
finite output resistance of the current driver. The output resistance of the proposed circuit
is approximated by:

Rout = Ai ·[ A + 1]· Rsens + Rsens + ro ≈ Ai ·[ A + 1]· Rsens (3)

where Ai is the intrinsic gain of the pass-transistor M1 (expressed as: gm × ro ), ro is the

small-signal AC resistance of the pass-transistor operating in saturation and A is the
boosting amplifier open-loop gain.
The higher the Rout of the current sink, the higher the current accuracy. This can be
achieved by increasing the intrinsic gain and/or the boosting amplifier gain. For a fixed
device’s current and channel length, maximizing Ai would require increasing device width
(W) or the VDS . The latter option is not selected since it leads to higher power dissipation.
Consequently, the optimal device width is chosen to achieve the desired Ai value. However,
the boosting amplifier DC gain (A) is limited by the maximum achievable GBP. A maximum
gain can be achieved for a specific maximum bandwidth, which is dictated by the switching
frequency. The gain is determined by the GBP requirement and the bandwidth.

3. Design Methodology and an Application Example Simulation

The proposed design methodology is introduced in this section and illustrated via a
WLED driver example simulation.

3.1. Design Methodology

The flowchart depicted in Figure 7 summarizes the design steps of the proposed
circuit. Adhering to this methodology helps to achieve high Rout , optimal size and power
dissipation for a given GBP of the boosting amplifier.
The maximum output voltage ripple of the DC-DC converter and the ripple current
design target decide the minimum required Rout of the current driver. The minimum
needed Rout is calculated at the maximum LED string current (ILED( MAX ) ). The design
starts with choosing the channel length L that is twice the minimum process node Lmin .
The corresponding sensing resistance value (Rsens = Vre f /ILED( MAX ) ) can now be
selected. The boosting amplifier DC gain (A) can be determined depending on the switching
frequency of the DC-DC converter and the amplifier’s GBP. Having determined A and
Rsens , the approximate intrinsic gain value of the pass-transistor (Ai ) can be estimated from
Equation (3). Depending on the power budget target, the optimum drain-source voltage
(VDSopti ) in step 5 can be calculated using the following Equation (4)

∆Vout
 
Ploss( MAX ) = ILED( MAX ) VDSopti + VRsens + (4)
2

A family of curves relating the intrinsic gain Ai and the size of the pass-transistor
versus VDS are developed at different δ, where δ is the difference between the VGS and
VDS , as shown in Figure 8. These curves are developed by sweeping VDS and adjusting
the device size using the gm /ID method while keeping the device’s drain current constant
ILED( MAX ) [25].
Electronics 2022,
Electronics 11,11,
2022, 2566
x FOR PEER REVIEW 7 of 14 7 of 13

DC-DC specifications

Vo
Io Minimum Rout
fsw

Pick channel length

{(2+n) x Lmin }, n = 0, 1, 2 ...

Determine External
resistance value at ILED(MAX)

Determine the boosting

amplifier DC gain (A)

Determine minimum Ai(min)

using Equation (3)
δ3
δ2
Ai

δ1
δ3 > δ2 > δ1
Vds
Find VDSopti using Equation (4)
Select δ knowing Vds_opti & Ai

NO YES
Ai Ai(min)

δ1 δ3 > δ2 > δ1
W

δ2
δ3

Vds
Select W knowing
VDSopti & δ

The device is too YES

large

No

End

Figure 7. A Flowchart of the proposed design methodology.

 𝑜𝑢𝑡
𝑃𝑙𝑜𝑠𝑠(𝑀𝐴𝑋) = 𝐼𝐿𝐸𝐷(𝑀𝐴𝑋) [ 𝑉𝐷𝑆𝑜𝑝𝑡𝑖 + 𝑉𝑅𝑠𝑒𝑛𝑠 + ] (4)
2
A family of curves relating the intrinsic gain 𝐴𝑖 and the size of the pass-transistor
versus 𝑉𝐷𝑆 are developed at different δ, where δ is the difference between the 𝑉𝐺𝑆 and
𝑉𝐷𝑆 , as shown in Figure 8. These curves are developed by sweeping 𝑉𝐷𝑆 and adjusting
Electronics 2022, 11, 2566 8 of 13
the device size using the 𝑔𝑚 /𝐼𝐷 method while keeping the device’s drain current constant
𝐼𝐿𝐸𝐷(𝑀𝐴𝑋) [25].

δ Vds

Vgs

Figure
Figure 8.
8. Pass-transistor testbench for developing charts in
in steps
steps 66 and
and 7.
7.

A suitable value of δ that satisfies satisfies V𝑉DSopti andA𝐴i 𝑖isisfound

𝐷𝑆𝑜𝑝𝑡𝑖 and foundusing
usingthe thedeveloped
developedfamily
fam-
curves
ily curvesin step 6. If6.the
in step appropriate
If the appropriate intrinsic gain
intrinsic is not
gain met,
is not a new
met, a new longer
longer device’s channel
device’s chan-
should
nel shouldbe selected
be selected thenthenthe the
procedure
procedure repeats. For For
repeats. the the
selected Ai value
selected 𝐴𝑖 valueand and
using δ and
using δ
V
Electronics 2022, 11, x FOR PEER REVIEW
and determined previously, the transistor width W is extracted
𝑉𝐷𝑆𝑜𝑝𝑡𝑖 determined previously, the transistor width W is extracted from the curves in
DSopti from the curves in
9 step
of 14 7.
This
step 7. chart
Thisischart
developed by sweeping
is developed VDS at different
by sweeping δ, keeping
𝑉𝐷𝑆 at different a constant
δ, keeping device current
a constant device
using the
current using g /I
m the D 𝑔𝑚 /𝐼𝐷 method. If the picked device size is prohibitively the
method. If the picked device size is prohibitively large, procedure
large, the pro-
returns toDesign
Table returns
cedure 2. step 1to and
stepincrements
specification the channel
1 andofincrements
the WLED example.length. length.
the channel A detailed description
A detailed of the design
description of the
procedure
design procedure of the boosting
ofParameteramplifieramplifier
the boosting is foundisinfound
[26,27].inThis design
[26,27]. This methodology
design includes
methodology
Values
the most critical
includes the most design parameters
critical design that benefit system-level
parameters metrics
that benefit system-level (i.e., efficiency, size effi-
metrics (i.e., and
controllability). Input
Furthermore,voltage (a)
this methodology might seamlessly 3.2–4.2
apply Vto any system-level
ciency, size and controllability). Furthermore, this methodology might seamlessly apply
converter WLED string
architecture current a current sink driver.
encompassing 1–25 mA (dimmable)
to any system-level converter architecture encompassing a current sink driver.
Current resolution 1 mA
3.2. WLED DesignCurrent Exampleripple <1%
3.2. WLED Design Example
String arrangement
This section illustrates the design methodology using a WLED design example de- 6 WLEDs
This section
WLED9. illustrates
forward the design
voltage drop methodology using a WLED design example de-
3.2 Vsink
picted in Figure Picking this popular system that uses a current driver solution
picted in Figure 9. Picking this popular system that uses a current sink driver solution
highlights the Outputsystem-level voltage ripple
need for a rubout design methodology. <2.5%
Figure 9 shows a boost
highlights the system-level
Op-amp quiescentneed for a rubout design methodology. Figure 9 shows a boost
converter followed by a WLEDcurrentstring and current sink driver. The 100following
µA design exam-
converter followed Switching by a WLED
frequency string and current sink driver.
(𝑓𝑠𝑤 ) part to validate the proposed The
1 MHz following design ex-
ple focuses on the current sink driver solution functionality
ample focuses on the
and verify the design methodology.current
GBP sink driver part to validate the proposed
The chosen design specifications 100 MHz solution function-
are listed in Table 2.
ality and verify
This data isEfficiency the
based on(of design methodology.
thecurrent driver)
work presented The chosen design
in [8,19]. The TSMC 40 >97%specifications
nm CMOS technologyare listed in is
Table 2. This
(a) battery data
level. is based on the work presented
utilized in the ADS CAD tool to implement and simulate the design. in [8,19]. The TSMC 40 nm CMOS tech-
nology is utilized in the ADS CAD tool to implement and simulate the design.
Vin
Boost Converter
VOut

L D
LED string #1

LED string #n

S C

PWM
Minimum Vx#1
Compensator voltage
COM selector Vx#n

Vx(ref) Vref Vref

Ramp EA EA

VRsens#1 VRsens#n

a0 a0

Programmable a4 a4
current sink drivers

Figure 9. Boost-based WLED driver example.

Figure 9. Boost-based WLED driver example.

According to the depicted design methodology in Figure 7 and DC-DC converter pa-
rameters, the minimum output resistance of the current driver that satisfies the current
ripple for the given output voltage ripple of the converter is calculated as:
Electronics 2022, 11, 2566 9 of 13

Table 2. Design specification of the WLED example.

Parameter Values
Input voltage (a) 3.2–4.2 V
WLED string current 1–25 mA (dimmable)
Current resolution 1 mA
Current ripple <1%
String arrangement 6 WLEDs
WLED forward voltage drop 3.2 V
Output voltage ripple <2.5%
Op-amp quiescent current 100 µA
Switching frequency ( f sw ) 1 MHz
GBP 100 MHz
Efficiency (of current driver) >97%
(a) battery level.

According to the depicted design methodology in Figure 7 and DC-DC converter

parameters, the minimum output resistance of the current driver that satisfies the current
ripple for the given output voltage ripple of the converter is calculated as:

∆V 2.5% ∗ 20
Rout = = = 2.5 kΩ (5)
∆I 1% ∗ 25 m
Knowing that the string output voltage is the voltage drop across 6 WLEDs and the
voltage drop across the current sink driver, approximated here by 600 mV, then;

Vout = 6 × 3.2 V + 600 mV ≈ 20 V (6)

The boosting amplifier open-loop gain is determined by the target GBP and the
switching frequency:
GBP 100 MHz
A= = = 100 (7)
Fsw 1 MHz
The minimum sensing resistance value must be determined to calculate the required
intrinsic gain. A low voltage of 150 mV is selected as a reference voltage (Vre f ), leading to
a 6 Ω minimum sensing resistor value at ILEDMax . Consequently, the intrinsic gain value
according to Equation (3) should be higher than:

ROut 2.5 k
Ai ≥ = = 4.125 (8)
[( A + 1) × Rsens ] [(101 × 6)]

Following the efficiency requirement, the voltage drop across the current sink driver
is determined as:
Vout × ILEDMax
Vx = (1 − 0.97) × = 600 mV (9)
ILEDMax
The VDSopti as illustrated in Figure 5, can be estimated by:

∆V
VDSopti = Vx − + Vre f = 600 mV − 250 mV − 150 mV = 200 mV (10)
2
Figures 10 and 11 show the Ai and transistor’s size versus VDS for different δ at a fixed
current of 25 mA, respectively. These curves are developed for a channel length of 80 nm.
The target Ai value at the optimum VDS found in Equation (10) can be achieved at two
points (δ = 450 mV and 400 mV). Here, the optimum δ that satisfies both the intrinsic gain
and minimizes the pass-transistor size is 450 mV. The device’s size is determined using
Figure 11 to be W = 405 µm. It is noteworthy that the device’s size decreases with VDS . For
higher efficiency, a lower drain-source voltage is preferred. However, the advantage in
the size reduction diminishes as the VDS increases. Therefore, there is a design trade-off
between the system efficiency and the device’s area.
 gain and minimizes the pass-transistor size is 450 mV. The device’s size is determined
using Figure 11 to be W = 405 µ m. It is noteworthy that the device’s size decreases with
𝑉𝐷𝑆 . For higher efficiency, a lower drain-source voltage is preferred. However, the ad-
vantage in the size reduction diminishes as the 𝑉𝐷𝑆 increases. Therefore, there is a design
trade-off between the system efficiency and the device’s area.
Electronics 2022, 11, 2566 10 of 13

10

9 d= 400 mV
d= 450 mV
8
d= 500 mV
7

6
Ai
5

0
Electronics 2022, 11, x FOR PEER REVIEW 11 of 14
100 150 200 250 300 350

VDS[mV]
Figure 10. Intrinsic gain Ai vs. VDS at different δ for a fixed drain current of 25 mA.
Figure 10. Intrinsic gain 𝐴𝑖 vs. 𝑉𝐷𝑆 at different δ for a fixed drain current of 25 mA.
2500

d= 400 mV
d= 450 mV
2000
d= 500 mV
W [mm]

1500

1000

500

0
100 150 200 250 300 350

VDS[mV]
Figure 11. Transistor width vs. VDS at different δ for a fixed drain current of 25 mA.
Figure 11. Transistor width vs. 𝑉𝐷𝑆 at different δ for a fixed drain current of 25 mA.
3.3. Simulation Results
3.3. Simulation
ThisResults
section presents the simulation results for the demonstration example based on the
This sectiondesign
proposed methodology
presents using
the simulation the ADS
results CAD
for the tool. Figure 12
demonstration shows different
example based onstring
currents, with ripple zoomed, at three levels. Note that the LED
the proposed design methodology using the ADS CAD tool. Figure 12 shows differentcurrent has 25 segments
stringwith 1 mAwith
currents, segment
ripplestep each. Figure
zoomed, at three12 clearly
levels. shows
Note thatthat the worst-case
the LED current hasripple value is
25 seg-
mentsatwith
the highest current step
1 mA segment leveleach.
(25 mA) as anticipated
Figure duringthat
12 clearly shows the design The ∆I was
process. ripple
the worst-case
value 206 thefor
is atµA the worst
highest case.
current The(25
level ripple
mA) value drops to during
as anticipated 2.3 µA the
at the lowest
design current
process. level of
The
1 mA.
ΔI was 206 µA for the worst case. The ripple value drops to 2.3 µ A at the lowest current
level of 1 mA.

Electronics 2022, 11, 2566
This section presents the simulation results for the demonstration example based on
the proposed design methodology using the ADS CAD tool. Figure 12 shows different
string currents, with ripple zoomed, at three levels. Note that the LED current has 25 seg-
ments with 1 mA segment step each. Figure 12 clearly shows that the worst-case ripple
value is at the highest current level (25 mA) as anticipated during the design process. The11 of 13
ΔI was 206 µA for the worst case. The ripple value drops to 2.3 µ A at the lowest current
level of 1 mA.

Electronics 2022, 11, x FOR PEER REVIEW 12 of 14

The voltage waveform at the pass-transistor drain, 𝑣𝑥 (𝑡), and the sensing resistor
voltage are shown in Figure 13. The average value of 𝑉𝑥 is around 480 mV compared to
Figure
600
Figure 12.12.
mV Transientsimulation
previously
Transient simulation of WLED
calculated.
of string
stringcurrent
The reason
WLED for forfor
this
current three current
deviation
three islevels.
currentthelevels.
optimization under-
taken to reduce the power dissipation (efficiency enhancement) while keeping the current
TheΔIvoltage
ripple within waveform
the level of atthethe pass-transistor
design specifications.drain, v x (t), and
The resulting the sensing
power resistor
dissipation is
voltage
reduced arefrom
shown in Figurecalculated
theoretically 13. The average
~15 mWvalueto 12 ofmWVx at
is the
around 480 mV
maximum compared
current of 25 to
600
mA.mV previously
This calculated.
reduces current sink The reason
driver lossesfor
bythis
20%deviation is thethe
and enhances optimization
efficiency toundertaken
~97.6%.
toIn
reduce the power
a physical dissipationthe
implementation, (efficiency enhancement)
nonidealities of the actualwhile
hardwarekeeping the current
components ripple
might
∆Icompromise
within the level of the design
this simulated specifications.
efficiency result. The resulting power dissipation is reduced
from theoretically calculatedacross
The voltage waveform ~15 mW to 12 mW at the
the programmable maximum
resistor 𝑉𝑅𝑠𝑒𝑛𝑠current of 25
(𝑡) is also mA. This
displayed
reduces
in Figurecurrent
13. Its sink
valuedriver losses
is smaller thanbythe20% and enhances
calculated value of the
150 efficiency
mV due to to the~97.6%. In a
finite gain
of the boosting
physical amplifier (a
implementation, thesystematic error).ofNote
nonidealities that thehardware
the actual ripple on components
this waveformmightis
negligible compared
compromise to the efficiency
this simulated ripple in the drain voltage waveform 𝑣𝑥 (𝑡).
result.

Figure 13. The voltage waveform at the pass-transistor drain and sensing resistor voltage drop.
Figure 13. The voltage waveform at the pass-transistor drain and sensing resistor voltage drop.

4. Conclusions
This paper presented a high-efficiency current sink driver and its design methodol-
ogy for current regulating purposes. Unlike the conventional methods, this topology reg-
ulates the current directly using an NMOS pass-transistor in place of PMOS. Thus, the
proposed solution is suitable for current-sensitive devices such as LEDs with current-de-
pendent brightness. This makes the topology more suitable for any DC-DC converter-
Electronics 2022, 11, 2566 12 of 13

The voltage waveform across the programmable resistor VRsens (t) is also displayed in
Figure 13. Its value is smaller than the calculated value of 150 mV due to the finite gain
of the boosting amplifier (a systematic error). Note that the ripple on this waveform is
negligible compared to the ripple in the drain voltage waveform v x (t).

4. Conclusions
This paper presented a high-efficiency current sink driver and its design methodology
for current regulating purposes. Unlike the conventional methods, this topology regulates
the current directly using an NMOS pass-transistor in place of PMOS. Thus, the proposed
solution is suitable for current-sensitive devices such as LEDs with current-dependent
brightness. This makes the topology more suitable for any DC-DC converter-driven applica-
tion that suffers from output voltage ripple. Furthermore, the proposed solution comprises
an integrated programmable resistor bank that enables digital control with a user-defined
current resolution step. Using the programmable resistor for dimming proved superior to
the variable reference method. In addition, a systematic design methodology based on the
gm /ID method is proposed. This design methodology leads to a set of candidate solutions
for the pass-transistor size at specified efficiency and GBP design parameters. The proposed
methodology can be applied to any process node, including 40 nm CMOS technology. A
boost-based WLED driver application example is utilized to validate the proposed current
sink driver topology and its design methodology. In the design example, a 1 mA resolution
step for a total of 25 mA is implemented by the programmable resistor bank to enable
the dimmability of WLEDs. For a 500 mV voltage ripple at the DC-DC converter output
driving 6 WLEDs, with a 3.2 V forward voltage drop each, a worst-case current ripple of
200 µA and 97.6% efficiency is achieved for an optimal pass-transistor size. It is noteworthy
that the proposed current sink driver can be applied to more sophisticated systems and
topologies, including multi-string WLED designs and any variant of DC-DC converters.

Author Contributions: Conceptualization, I.A., F.R.S. and H.A.; methodology, I.A., F.R.S. and H.A.;
Simulations, F.R.S.; writing—original draft preparation, I.A., F.R.S. and H.A.; writing—review and
editing, I.A.; visualization, I.A. and F.R.S. All authors have read and agreed to the published version
of the manuscript.
Funding: This research received no external funding.
Data Availability Statement: Not applicable.
Acknowledgments: The authors would like to thank EUROPRACTICE for their kind support by
providing the technology files.
Conflicts of Interest: The authors declare no conflict of interest.

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