IEEE POWER & ENERGY SOCIETY SECTION

Received 20 November 2023, accepted 24 January 2024, date of publication 29 January 2024, date of current version 8 February 2024.
Digital Object Identifier 10.1109/ACCESS.2024.3359231

Hybrid Pulse Width Modulation for Improving

Reliability of DC-Link Capacitors of NPC
Inverter in Photovoltaic Systems
JAE-HEON CHOI1 , (Student Member, IEEE), UI-MIN CHOI 1, (Senior Member, IEEE),
AND FREDE BLAABJERG 2 , (Fellow, IEEE)
1 Department of Smart ICT Convergence Engineering, Seoul National University of Science and Technology, Seoul 01811, South Korea
2 AAU Energy, Aalborg University, 9220 Aalborg, Denmark
Corresponding author: Ui-Min Choi (uch@seoultech.ac.kr)
This work was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT)
(No. 2022R1A2C1091791); and in part by the Korea Institute of Energy Technology Evaluation and Planning (KETEP) and the
Ministry of Trade, Industry and Energy (MOTIE) of the Republic of Korea (No. RS-2023-00266248).

ABSTRACT Reliability improvement of the Photovoltaic (PV) inverter has a high potential for reducing
the cost of PV energy. The DC-link capacitor is one of the main components influencing the reliability of
PV inverter systems. Various pulse-width modulation (PWM) methods have been proposed to increase the
lifetime of the DC-link capacitor by reducing its ripple current. However, state-of-the-art PWM methods for
reducing capacitor ripple current increase the output current THD. Nevertheless, its optimal application to
achieve the target lifetime without unnecessary deterioration in output current THD has not been discussed.
This paper proposes a PWM method for improving the lifetime of the DC-link capacitor of the NPC inverter.
In addition, a mission-profile-based optimal application of the proposed PWM method with conventional
Space Vector Modulation (SVM) called a hybrid MLZSVM method is presented for achieving the target
lifetime of the DC-link capacitor with minimized negative effect on the output THD of the NPC inverter.
The proposed hybrid PWM concept is verified by the case study based on an annual mission profile of the PV
system. Finally, the feasibility and effectiveness of the proposed method are verified through experiments.

INDEX TERMS Capacitor, NPC inverter, PV inverter, PWM, reliability.

I. INTRODUCTION LCOE is defined as capital cost, operation and maintenance

The finitude of conventional fossil fuels and global warming cost, and the average annual power production [2]. Improving
due to carbon emissions lead to advances in renewable energy the reliability of renewable energy decreases operation and
technologies and industries. As of 2022, the total global maintenance costs with increases the average annual energy
renewable generation capacity reached 3.3 TW, which is an production, bringing about lower LCOE. Therefore, reliabil-
increase of 9.6 % compared to the previous year. Especially, ity plays an important role in reducing LCOE [3].
photovoltaic (PV) energy, which accounted for 99 % of solar Reliability improvement of the PV inverter has a high
energy, increased to 1046 GW by 22 % compared to the potential to improve the overall reliability of PV systems
previous year and had the highest growth rate among renew- since it is considered one of the reliability-critical parts
able energies [1]. Although its growth rate is maintained, according to previous research [4], [5] and a capacitor is one
the competitive Levelized Cost of Energy (LCOE) is still of the main causes of the wear-out failure of power electronics
demanded to substitute conventional fossil fuels effectively. systems [6]. Therefore, much research has been performed
focusing on the lifetime increase of the capacitor.
The associate editor coordinating the review of this manuscript and The three-level Neutral-Point Clamped (NPC) inverter,
approving it for publication was K. Srinivas . which is shown in Fig. 1 is widely used in PV systems owing
2024 The Authors. This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.
18752 For more information, see https://creativecommons.org/licenses/by-nc-nd/4.0/ VOLUME 12, 2024
J.-H. Choi et al.: Hybrid PWM for Improving Reliability of DC-Link Capacitors of NPC Inverter
FIGURE 1. Configuration of three-level NPC inverter.
to its advantages such as high efficiency, low total harmonic
distortion (THD) of the output current, and the use of power
devices having lower rated voltage over the conventional
two-level inverter [7], [8].
An aluminum electrolytic capacitor is typically used for
the DC-link of inverters, but there are many efforts to replace
aluminum electrolytic capacitors with different kinds of
capacitors such as film capacitors and ceramic capacitors due
to their reliability concerns. Its wear-out failure mainly occurs
due to temperature stress. The ripple current of the DC-link
capacitor increases the hot-spot temperature and results in
a lifetime reduction [9], [10], [11]. However, it is still
dominantly used in various power electronics applications
especially when the cost is sensitive and the environment is
not harsh. Therefore, many studies have been conducted to
reduce the ripple current of the DC-link capacitor by develop-
ing various PWM methods. It is possible due to the ability that
the NPC inverter has redundant switching states for various
switching combinations to generate a required output voltage.
In [12] and [13], a space vector PWM method is proposed,
where voltage vectors causing a high DC-link capacitor cur-
rent are replaced with other voltage vectors to reduce the
DC-link capacitor current. Even though the proposed method
in [13] is focused on the reduction of neutral point voltage
and common mode voltage, the principle is the same as the
method in [12]. In [14], the hybrid PWM method, which is
composed of the PWM method presented in [12] and the
medium voltage vector-based PWM has been proposed, but
this method increases the switching loss of the power devices.
The main idea of the SVPWM method proposed in [15] is
also similar to the previous methods, but the chosen voltage
vectors are different. Therefore, a further reduction of the
DC-link capacitor current can be achieved. A virtual space
vector modulation for the reduction of common mode volt-
age and neutral point voltage oscillation has been proposed
in [16]. The main purpose is a bit different, but the decrease
in neutral-point voltage leads to a lifetime improvement of
the DC-link capacitor. However, in this method, the switching
state of the power device is changed two times in a switching
cycle. Therefore, it results in a power loss increase. Further-
more, since the line-to-line voltage has a higher dv/dt, it leads
to a higher output THD. In addition, it is less effective for
the reduction in the DC-link capacitor current because this
method still uses small voltage vectors. The application of
the above-mentioned PWM methods deteriorates the output
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current THD. Nevertheless, its optimal application to achieve
the target reliability performance of the DC-link capacitor
without unnecessary negative effects on the output THD has
not been studied yet. Furthermore, in [17], the effect of
PWM methods on the reliability of DC-link capacitors in
NPC inverters has been investigated, which are NTV-CPWM,
NTV-DPWM, ZVI-PWM, and NTV2 -PWM. The results
show that the PWM methods for reducing neutral-point volt-
age variation by making the average of the neutral-point
current in a switching cycle zero such as ZVI-PWM and
NTV2 -PWM improve the lifetime of DC-link capacitors even
though they did not mainly focus on decreasing the magnitude
of the DC-link capacitor current.
This paper proposes a PWM method for improving the
lifetime of the DC-link capacitor of the NPC inverter. Fur-
thermore, a mission-profile-based optimal application of
the proposed PWM method with conventional Space Vec-
tor Modulation (SVM) called the hybrid PWM method is
presented for achieving the target lifetime of the DC-link
capacitor with the minimized negative effect on the output
THD of the NPC inverter. The effect of the conventional
SVM on the DC-link current is analyzed first. Then, a PWM
method called MLSVM based on the medium, large, and zero
voltage vectors for reducing the DC-link current of the NPC
inverter is proposed. Furthermore, its performance is ana-
lyzed by comparing it with the state-of-the-art PWM methods
for reducing the DC-link current. After that, the proposed
hybrid PWM concept is presented and verified by a case study
based on an annual mission profile of the PV system. Finally,
the feasibility and effectiveness of the proposed method are
verified through experiments.
II. EFFECT OF SPACE VECTOR MODULATION ON DC-LINK
CAPACITOR CURRENT OF NPC INVERTER
As shown in Fig. 1, the three-level NPC inverter consists
of four IGBTs, two clamping diodes, and four freewheeling
diodes. Each leg of the NPC inverter has three switching
states called [P], [O], and [N], respectively, which are deter-
mined by the operating states of four IGBTs of each leg.
Considering leg A, if Sa1 and Sa2 are on, its switching state
is [P], and thus the output pole voltage becomes VDC /2.
Switching state [O] indicates that the Sa2 and Sa3 are on.
Lastly, switching state [N] means that Sa3 and Sa4 are on.
The pole voltages are 0 and -VDC /2 when the switching states
are [O] and [N], respectively. Therefore, the NPC inverter has
27 combinations of switching states, and they have different
effects on the DC-link current.
Fig. 2 shows the space vector diagram of the NPC inverter.
The space vector diagram can be divided into six triangular
sectors, where the voltage vectors and the corresponding
switching states are represented. The voltage vectors are
classified into zero, small, medium, and large voltage vectors
according to their magnitude. The zero voltage vector is
represented as V0 , and its magnitude is zero. Small voltage
vectors are denoted by V1 - V6 and medium voltage vectors
are indicated by V7 - V12 . Magnitudes of small and medium
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 J.-H. Choi et al.: Hybrid PWM for Improving Reliability of DC-Link Capacitors of NPC Inverter
FIGURE 2. Space vector diagram and voltage vectors for generating
reference voltage vector in conventional SVM.
√
voltage vectors are VDC /3 and, VDC / 3 respectively. Finally,
large voltage vectors denoted by V13 - V18 have a magnitude
of 2·DC /3.
As shown in Fig. 1, the NPC inverter has two DC-link
capacitors called upper and lower capacitors, and the point
of the series connection of the two capacitors is defined as
the neutral point. The neutral point current can be expressed
as
IN = ICL + ICU
where ICL and ICU are lower and upper capacitor cur-
rents, respectively. Therefore, through the reduction of IN ,
a decrease in the current of DC-link capacitors is able to be
achieved.
The voltage vectors have different effects on IN since it
is determined by currents of the specific phases connected
to the neutral point as shown in Fig. 3. As shown in Fig. 3
(a) when the switching state is [ONN], which is one of the
small voltage vectors, the phase-A is connected to the neutral
point, and phase-B and phase-C are connected to the negative
DC-link. Therefore, IN is equal to the current of phase-A
(Ia ). In the case of the switching state [PON] of the medium
voltage vector, as illustrated in Fig. 3 (b), the current of phase-
B (Ib ) becomes IN . However, as shown in Fig. 3 (c), even
though the three phases are connected to the neutral point
when the switching state is [OOO], IN is zero because the
summation of the three-phase currents is zero. Finally, the
large voltage vectors such as [PNN] make IN zero because
any phases are not connected to the neutral point as shown
in Fig. 3 (d). It can be seen from the above analysis that the
small voltage vectors have the most significant effect on the
DC-link current.
In conventional SVM, the reference voltage vector Vref
is generated by the closest voltage vectors to Vref . If Vref
is located in Sector I-(b) as shown in Fig. 2, SVM selects
the closest voltage vectors V1 , V7 , and V13 to generate Vref .
In Sector 1, |Ia | is the largest current among three-phase
currents as shown in Fig. 4. It becomes IN when V1 is selected
during SVM. In Sector 2, the largest current |Ic | flows into the
neutral point due to V2 . Consequently, a large current flows
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FIGURE 3. The effect of the voltage vectors on the neutral point current.
(a) [ONN] of small voltage vector (b) [PON] medium voltage vector
(c) [OOO] of zero voltage vector (d) [PNN] of large voltage vector.
FIGURE 4. Output current according to the sectors under assumption that
(1) the power factor is 1.
into the DC-link capacitors when the small voltage vectors
are selected during SVM. It results in a lifetime reduction of
DC-link capacitors.
III. PROPOSED SPACE VECTOR MODULATION FOR
REDUCTION OF DC-LINK CURRENTS
A. VOLTAGE VECTORS BASED SPACE VECTOR
MODULATION METHOD (MLZSVM)
According to the analysis carried out in Section II, the small
voltage vectors make IN become the maximum phase current
in the conventional SVM. Therefore, a modified switching
sequence for reducing the DC-link ripple current is required
for the reliability improvement of the NPC inverter through
the lifetime increase of the DC-link capacitor. The main idea
of the proposed method is to replace the small voltage vector
with the adjacent large and zero voltage vectors so that Vref is
generated by using medium, large, and zero voltage vectors.
It is named Medium-Large-Zero SVM (MLZSVM) in this
paper.
The proposed MLZSVM can be applied by dividing each
sector of the space vector diagram into two sub-regions (a)
and (b). If Vref is located in Sector 1-(b) as shown in Fig. 5,
in conventional SVM, the switching sequence is [ONN]-
[PNN]-[PON]-[POO]-[PON]-[PNN]-[ONN] as shown in
Fig 6 (a). However, in the proposed MLZSVM, the zero
voltage vector V0 and large voltage vector V13 are used
instead of the small voltage vector V1 . It is possible since
the composition of V0 and V13 is equal to V1 . Therefore,
the switching sequence is established as [OOO]-[PON]-
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J.-H. Choi et al.: Hybrid PWM for Improving Reliability of DC-Link Capacitors of NPC Inverter
FIGURE 5. The voltage vectors for generating the reference voltage in
MLZSVM of Sector 1-(b).
FIGURE 6. The switching sequence and the neutral point current IN in
Sector 1-(b) under (a) conventional SVM (b) proposed MLZSVM.
[PNN]-[PON]-[OOO] as shown in Fig. 6 (b). It is seen
that IN is significantly reduced by eliminating the switching
states [ONN] and [POO] of the small voltage vector V1 .
In MLZSVM, only Ib , which is the smallest one among the
three-phase currents flows into the neutral point when the
switching state is [PON].
The dwell times of voltage vectors V0 , V7 , and V13 in Sector
1-(b) can be expressed as
" √ # lifetime of the DC-link capacitors by reducing the current of
2 3 Vref · sin (θr )
T1 = Ts
VDC
3 Vref · cos θr + π3
"
#
T2 = Ts
VDC
T0 = Ts − T1 − T2
where Ts is the switching period, T0 , T1 , and T2 are the dwell
times of V0 , V7 , and V13 , respectively (see. Fig. 6), |Vref | is
the magnitude of the reference vector, VDC is the magnitude
of the DC-link voltage, θr is the angle between Vref and large
vectors such as V13 − V18 (0◦ ≤ θr ≤ 60◦ ).
In Sector 2-(a), V0 , V7 , and V14 are selected for the pro-
posed MLZSVM, and the corresponding switching sequence
is formed as [OOO]-[PON]-[PPN]-[PON]-[OOO]. The dwell
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TABLE 1. Simulation parameters.
times of voltage vectors V0 , V7 , and V14 are calculated as
" √
2 3 Vref · cos θr + π6

#
T1 = Ts (5)
VDC
3 Vref · sin θr − π6
"
#
T2 = Ts (6)
VDC
T0 = Ts − T1 − T2 (7)
where T0 , T1 , and T2 are the dwell times of V0 , V7 , and
V14 , respectively. The above equations can be applied to
sub-regions (a) and (b) of all sectors, respectively.
B. COMPARATIVE PERFORMANCE ANALYSIS OF MLZSVM
In this section, the performance of the proposed MLZSVM is
analyzed and compared with two state-of-the-art methods for
the reduction of the ripple current of the DC-link capacitor in
terms of neutral point current and output current THD. The
simulation parameters for the analysis are listed in TABLE 1.
There are also different state-of-the-art PWM methods to
reduce neutral-point voltage variation. Their principles are
similar to NTV2 -PWM, which makes the average of the
neutral-point current in a switching cycle. Even though they
have a contribution to increasing the lifetime of the DC-link
capacitor by reducing the power loss and thus hot-spot tem-
perature, their contributions are less significant compared
with that of the PWM methods developed for improving the
(2) DC-link capacitors. Therefore, those methods are not consid-
ered in this section for comparison.
The first method called Method-I has been proposed
(3) in [12]. In this method, the nearest small voltage vector in
the conventional SVM is replaced with another small voltage
(4) vector and medium voltage vector so that the largest phase
current does not flow to the neutral point when the switching
states of the small voltage vector. For example, as shown in
Fig. 7 (a), when the reference voltage vector is located in
Sector 1-(b), the small voltage vector V1 which causes the
large capacitor current is replaced with V2 and V12 . V2 and
V12 replacing V1 allow the second largest phase current Ic to
flow to the neutral point. The switching sequence of Method-I
is [PNO]-[PNN]-[PON]-[OON]-[PON]-[PNN]-[PNO] as
shown in Fig. 8 (a).
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 J.-H. Choi et al.: Hybrid PWM for Improving Reliability of DC-Link Capacitors of NPC Inverter
FIGURE 7. The voltage vectors for generating the reference voltage under
(a) Method-I (b) Method-II.
FIGURE 8. The switching sequence and the neutral point current IN in
Sector 1-(b) (a) Method-I (b) Method-II.
The principle of Method-2 proposed in [15] is similar to
Method-1 except for choosing the voltage vectors for the
replacement of a small voltage vector as shown in Fig. 7 (b).
Method-II lets the Ib , which is the smallest one among the
three-phase currents flow to the neutral point by replacing
V1 with V6 and V7 . Therefore, the switching sequence is
[ONO]-[PNN]-[PON]-[PNN]-[ONO] as shown in Fig. 8 (b).
Fig. 9 shows the line-to-line voltages, output currents,
and upper capacitor current (ICU ) when the SVM, proposed
MLSVM, Method-I, and Method-II are applied, respectively.
It is seen that not only the proposed MLZSVM but also
Method-1 and Method-2 modify the line-to-line voltage com-
pared with conventional SVM. It results in an increase in the
output current THD. Since the proposed MLZSVM, Method-
I, and Method-II have the regions for 240 ◦ out of 360 ◦ where
dv/dt of the line-to-line voltage is VDC , there is no signifi-
cant difference in the output current THD among the PWM
methods for reducing the DC-link capacitor current. In all
cases, it increases from 1.37 % to 4.1 %. When SVM is
applied as shown in Fig. 9 (a), the RMS value of ICU is
15.1 A, and it is reduced to 2.9 A when the NPC inverter is
operated with the proposed MLZSVM as shown in Fig. 9 (b),
which is reduced by 81% compared with the SVM. When
Method-I and Method-II are applied, as shown in Figs. 9
(c) and (d), the RMS values of ICU are 11.3 A and 5.6 A,
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FIGURE 9. Simulation results of line-to-line voltages (VAB), output
currents and DC-link capacitor current under high modulation index of
0.77 (a) conventional SVM (b) MLZSVM (c) Method-I (d) Method-II.
respectively. Furthermore, in the case of the common mode
voltage, the NPC inverter has the maximum value of VDC /3
under the conventional SVM, but it is reduced to VDC /6 when
the considered three PWM methods are applied.
The power loss of the power devices is analyzed under
different PWM methods as shown in Fig. 10. The IGBT mod-
ule of F3L75R07W2E3_B11 from Infineon is used for the
power loss analysis. The required information on power loss
and thermal impedance can be obtained from the datasheet,
where the heat sink to ambient thermal resistance for each
IGBT module is set to 0.6 K/W. Under the conventional SVM,
as shown in Fig. 10 (a), Sx1,4 has the highest power loss
of 18.2 W and followed by Sx2,3 and Dx5,6 as 15.5 W and
8.2 W, respectively. The power loss of Dx1,4 and Dx2,3 is
almost zero. Compared with that under the SVM, the power
loss distribution of the power devices is not varied when the
MLZSVM, Method-I, and Method-II are applied as shown
in Figs. 10 (b), (c), and (d), respectively because the number
of switching of each device does not increase and the dwell
time of the switching state of each leg is also almost the same.
Therefore, under the proposed MLZSVM, a better cooling
system is not required, and there is no notable impact on the
reliability of the power device regarding temperature stress.
The MLZSVM can be applied regardless of the mod-
ulation index. Fig. 11 illustrates the simulation results of
conventional SVM and MLZSVM under the relatively low
modulation index of 0.49. The MLZSVM is more effective in
reducing capacitor current under the low modulation index.
The RMS value of ICU is reduced from 18.9 A to 2.3 A.
However, more deterioration in the output current THD can
be seen compared with that under the high modulation index.
Therefore, the optimal application of the MLZSVM with the
minimized negative effect on the output THD is required.
In the case of the power loss of the power device, as shown
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J.-H. Choi et al.: Hybrid PWM for Improving Reliability of DC-Link Capacitors of NPC Inverter
FIGURE 10. Power loss distribution of power devices under high
modulation index of 0.77 (a) conventional SVM (b) MLZSVM (c) Method-I
(d) Method-II.
FIGURE 11. Simulation results of line-to-line voltages (VAB ), output
currents and DC-link capacitor current under low modulation index of
0.49 (a) conventional SVM (b) MLZSVM.
FIGURE 12. Power loss distribution of power devices under the low
modulation index of 0.49 (a) conventional SVM (b) MLZSVM.
in Fig. 12, the power loss of Sx1,4 increases from 18.5 W to
19.2, while the power loss of Dx5,6 decreases from 15.2 W
to 14.5 W, with no significant change in the other devices.
However, its difference is not significant only less than 1 W.
Fig. 13 shows the transient waveform of output currents,
d-axis current (reactive power), and q-axis (active power) cur-
rent in the synchronous reference frame and corresponding
d-axis and q-axis current references and normalized voltage
reference of phase-A under the MLZSVM when the output
power changes from 10 kW to 20 kW and then the power
factor changes from 1 to 0.8. It is seen that the output currents
are controlled well without any notable distortion under the
proposed MLZSVM regardless of its operating condition.
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FIGURE 13. The transient waveforms of outputs when the output power
and power factor change under MLZSVM.
It is seen from the results that the proposed MLSVM
suppresses the DC-link capacitor current most effectively
and thus leads to the reliability improvement of the DC-link
capacitors since the main cause of wear-out failure of
an aluminum electrolytic capacitor is temperature stress
generated by power loss due to the capacitor current.
Furthermore, it does not negatively affect the efficiency
and reliability of the power devices. However, the above
three PWM methods, including the MLZSVM, increase
the output current THD compared with SVM. Therefore,
it is required to apply it effectively to achieve the target
lifetime with a minimized negative effect on the output
THD.
C. PROPOSED HYBRID MLZSVM CONCEPT
A hybrid MLZSVM method is proposed to accomplish the
required reliability of DC-link capacitors by considering
the mission profile of the PV system without the unneces-
sary deterioration of the output current THD. The hybrid
MLZSVM method utilizes MLZSVM and SVM. In each
sector, the MLZSVM is applied for a certain period called
hybrid modulation angle (θh ) symmetrically based on the
large voltage vector. Since each phase current has the max-
imum value in this region, it is the most effective way to
apply the MLZSVM to reduce the DC-link capacitor current.
For example, in Sector 1, the MLZSVM is applied during
θh symmetrically based on the large voltage vector V13 as
shown in Fig. 14, and the SVM is applied to the rest of the
area of Sector 1. The same principle is applied to the rest
of the sectors. θh is adjusted from 0 ◦ to 60 ◦ to satisfy the
desired lifetime of the DC-link capacitor. When θh is 0 ◦ , only
SVM is applied, and when θh is 60 ◦ , only the MLSVM is
applied.
Fig. 15 shows the line-to-line voltage, output currents,
and upper capacitor current (ICU ) under different θh of the
proposed hybrid MLZSVM method. As θh increases, out-
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 J.-H. Choi et al.: Hybrid PWM for Improving Reliability of DC-Link Capacitors of NPC Inverter
FIGURE 14. Space vector diagram for the proposed hybrid PWM method.
FIGURE 15. Simulation results of line-to-line voltages, output currents
and DC-link capacitor current under different θ h in the hybrid MLZSVM
method (a) SVM θh = 0 ◦ (b) θh = 20 ◦ (c) θh = 40 ◦ (d) θh = 60 ◦ .
put current THD increases from 1.37 % to 2.9 %, 3.68
%, and 4.1 % when θh are 20 ◦ , 40 ◦ , and 60 ◦ , respec-
tively. On the other hand, the RMS value of the DC-link
capacitor current decreases as θh increases from 15.1 A to
11.7 A, 8.1 A, and 2.9 A when θh is 20 ◦ , 40 ◦ , and 60 ◦ ,
respectively.
The power loss analysis is carried out based on the power
loss of the power devices and DC-link capacitors under the
different modulation schemes as summarized in TABLE 2.
The power loss of the NPC inverter is reduced when the
proposed MLZSVM is applied under the considered power
ranges, and it has lower power loss as θh increases. Further-
more, compared with Method-I and Method-II, the proposed
method also has a lower power loss. However, its difference is
not significant. Therefore, it can conclude that the proposed
MLZSVM does not negatively affect the power loss of the
inverter. However, the proposed MLZSVM increases the out-
put current THD, and it may lead to a higher power loss of
the filter inductor.
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TABLE 2. Comparison of total power loss under different modulation
schemes according to the output power.
It is seen that there is a trade-off between the RMS value
of the DC-link capacitor current and the output current
THD. Therefore, θh is needed to be properly selected so
that the required reliability performance of the capacitor is
achieved with a minimum negative impact on the output
current THD. By this strategy, the proposed MLZSVM is
applied only when necessary for the target lifetime. Thus,
the unnecessary distortion of the output current can be
minimized.
The effect of the proposed method on the neutral point
voltage is analyzed. Under the proposed MLZSVM, only the
medium voltage vectors affect the neutral point voltage. For
example, when the reference voltage vector is in Sector 1
as shown in Fig. 14, the switching state [PNO] or [PON]
charges the lower capacitor because phase-C or phase-B is
connected to the neutral point, and their currents have nega-
tive values. Conversely, the switching states [NPO] or [NOP],
which are symmetrical to [PNO] and [PON], respectively,
are selected when the reference voltage vector is in Sector 4.
These switching states discharge the lower capacitor because
phase-C and phase-B currents have positive values. Since the
amounts of charge and discharge in Sector 1 and Sector 4
are the same, and this principle applies to other sectors as
well, the MLZSVM maintains the neutral point voltage at the
same value. In the hybrid MLZSVM, since the MLZSVM is
applied for the hybrid modulation angle (θh ) symmetrically
based on the large voltage vector and the conventional SVM
is applied to the rest of the area, the two capacitor voltages
are balanced to the same value. As shown in Fig. 16, two
capacitor voltages are maintained at the same value when the
hybrid MLZSVM with different hybrid modulation angles is
applied. It obviously shows that the proposed MLZSVM does
not affect the neutral point voltage.
IV. MISSOPM PROFILE BASED OPTIMAL APPLICATION
OF HYBRID PWM
In this section, an optimal application strategy of Hybrid
PWM based on the lifetime of the DC-link capacitor con-
sidering a mission profile is presented. An annual mission
profile of the PV system shown in Fig. 17, recorded in Ari-
zona, USA, is considered for the case study. Thermal stress
is one of the main causes of wear-out failure of aluminum
electrolytic capacitors. Therefore, this case study is carried
out by focusing on the lifetime of the capacitor due to thermal
stress.
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J.-H. Choi et al.: Hybrid PWM for Improving Reliability of DC-Link Capacitors of NPC Inverter
FIGURE 16. Two DC-link capacitor voltages under SVM and MLZSVM with
different hybrid modulation angles (θh ).
FIGURE 17. Annual mission profile of PV system recorded in Arizona, USA
(a) solar irradiation (b) ambient temperature.
A. THERMAL LOADING OF DC-LINK CAPACITORS
The thermal stress of the capacitor is mainly caused by the
power loss due to the capacitor ripple current. The power loss
of the capacitor can be calculated from capacitor current and
equivalent series resistance (ESR). Since ESR is dependent
on the temperature and the frequency of the capacitor current,
it can be expressed as
Xm h i itors at different operating conditions. Then, a look-up table is
Ploss = ESR (fi , Th ) · I 2 (fi ) (8)
i=1
where Th is the hot-spot temperature of the capacitor, I (fi ) is
the RMS value of capacitor current at a specific frequency fi ,
and m is the number of frequency components.
The hot-spot temperature Th of the capacitor is obtained as
Th = Ta + Zha · Ploss
where Ta is the ambient temperature and Zha is the thermal
impedance from the hot-spot to the ambient environment.
Fig. 18 shows the power loss and the corresponding Th of
the DC-link capacitors at the rated power of 20 kW under
the proposed MLZSVM, conventional SVM, Method-I, and
Method-II, respectively. As expected from the analysis of
the DC-link capacitor current, the power loss of the DC-link
capacitor is significantly reduced when the PWM methods
for reducing the DC-link capacitor current are applied. It is
reduced from 5.3 W under the conventional SVM to 0.3 W,
3.2 W, and 1.0 W when MLZSVM, Method-I, and Method-II
are applied, respectively. The proposed DC-link capacitor
has the smallest power loss of 0.3 W under the proposed
MLZSVM and thus the lowest Th of 41.6 ◦ C.
The input power (Pin ) and the voltage of the PV inverter are
determined from the PV array model by applying the solar
irradiance and ambient temperature (Ta ), which are called
the mission profile of the PV system. After that, at differ-
ent combinations of operating conditions (i.e input power
and ambient temperature), the power loss of the capacitors
is calculated and applied to the thermal model as given
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FIGURE 18. Power loss and hot-spot temperature of DC-link capacitor at
20 kW under different PWM methods (at Prated = 20 kW, Ta = 40 ◦ C).
FIGURE 19. Hot-spot temperature profile of DC-link capacitor under the
given mission profile.
in (8) and (9) to obtain the hot-spot temperature (Th ) of capac-
built regarding Th in connection with Pin and Ta . Finally, the
thermal loadings of capacitors during the mission profile are
acquired through a look-up table when Pin and Ta are given.
This approach is helpful to handle long-term simulations (i.e.
annual mission profile).
Fig. 19 shows the hot-spot temperature profiles of the
(9) DC-link capacitor under the given mission profile. A lower
thermal loading is seen as θh increases.
B. ACCUMULATED DAMAGE OF DC-LINK CAPACITORS
The obtained thermal loading, which is Th is put into the
lifetime model of the capacitor given as
 −n
V T0 −Th
L = L0 · · 2 10 (10)
V0
where L0 , V0, and T0 are the rated lifetime, rated voltage,
and rated temperature of the capacitor, respectively. V is the
operating voltage of the capacitor. The related parameters
of the lifetime model used in this case study can be found
in [18] and [19]. Then, the accumulated damage (AD) of the
capacitor during the given annual mission profile is obtained
based on the Palmgren-Miner rule [20] as
Xk ti
AD =
(11)
i=1 Lf
i
where ti is the time duration in a certain condition and (Lf )i
is the corresponding time-to-failure at a certain temperature
and voltage conditions calculated from (10). If the damage is
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 J.-H. Choi et al.: Hybrid PWM for Improving Reliability of DC-Link Capacitors of NPC Inverter
FIGURE 20. Accumulated damages of the capacitor during an annual
mission profile when the proposed hybrid MLZSVM with different θh are
applied, respectively.
FIGURE 21. Unreliability functions of DC-link capacitor according to
voltage modulation methods.
FIGURE 22. Unreliability functions of DC-link capacitor under different θ h
in the hybrid MLZSVM method.
accumulated such that AD = 1 (or 100 %), it is considered
that the capacitor is reached its end-of-life [19].
Fig. 20 shows the accumulated damages of the capaci-
tor during the annual mission profile when the SVM and
proposed hybrid MLZSVM with different θh are applied,
respectively. It is seen that the proposed method decreases the
accumulated damage significantly. Therefore, the lifetime of
the capacitor is expected to increase.
C. SYSTLE-LEVEL RELIABILITY ANALYSIS OF DC-LINK
CAPACITOR
The time to end-of-life of the individual capacitors could vary
within a range due to the tolerance in physical parameters
that occur during the manufacturing process and differences
in the experienced stress applied to each component even
in the same operating environment. Therefore, the reliability
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FIGURE 23. Experimental results of the collector-emitter voltages of
power devices under (a) conventional SVM (b) MLZSVM.
analysis of the capacitor needs to consider the lifetime model
based on a statistical analysis of lifetime distribution. How-
ever, lifetime models with statistical properties are rarely
given. Therefore, a statistical approach based on the Monte
Carlo analysis is employed in this study to have the lifetime
distributions of the capacitors. The Monte Carlo simulation is
implemented with a population of 10,000 samples, by consid-
ering a 5 % variation with a normal distribution in the lifetime
model parameters and equivalent thermal stress parameters
according to previous research. More detailed information for
performing the Monte Carlo simulation can be found in [21],
[22], and [23]. As a result of the Monte Carlo simulation, the
lifetime distribution of individual capacitors is obtained.
From the lifetime distribution, the Weibull probability
density function f (t) is obtained as
 β−1  β
β t − ηt
f (t) = · ·e (12)
η η
where t is the operating time of the capacitor. β and η are the
shape and scale parameters, respectively, which are decided
by the lifetime distribution. Then, the cumulative distribution
function F(t) called unreliability function of the capacitor is
Z t
F(t) = f (t) dt (13)
0
Since the failure of any of the capacitors leads to the failure
of the entire inverter system, the unreliability function of the
entire system Fsys (t)considering all DC-link capacitors can be
calculated as
Yn
Fsys (t) = 1 − (1 − Fk (t)) (14)
k=1
where n is the number of DC-link capacitors, and Fk (t)is the
unreliability function of the kth capacitor in the system.
From the unreliability function, the time when a certain
percentage of a population is failed can be obtained. It is
referred to as the percentile lifetime (Bx lifetime), which can
be used as a reliability metric containing statistical informa-
tion on the failure rate. For example, B10 lifetime means the
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J.-H. Choi et al.: Hybrid PWM for Improving Reliability of DC-Link Capacitors of NPC Inverter

FIGURE 24. Experimental results of the output current in time and frequency domains, line-to-line
voltage, and capacitor current in time and frequency domains under the proposed hybrid MLZSVM
with different θh (a) θh = 0◦ (SVM), (b) θh = 20◦ , (c) θh = 40◦ , (d) θh = 60◦ .

time by which failure in 10 % of a population occurs. Namely,
the reliability is 0.9 at that time.
Fig. 21 shows the unreliability function of the DC-link
capacitor under the given mission profile with different PWM
methods when they are applied in all regions. As expected
from the analysis results of the DC-link capacitor (See Fig. 9),
the proposed MLZSVM has the longest lifetime due to the
best ability to reduce the DC-link capacitor current. Under the
assumption that the target B10 lifetime of the DC-link capaci-
tor is 30 years, the proposed MLZSVM and Method-II satisfy
the target lifetime as 38 years and 34.4 years, respectively,
whereas the conventional SVM and Method-I cannot meet
the requirement as 14.3 years and 22.8 years, respectively.
D. OPTIMAL APPLICATION STRATEGY OF HYBRID
MLZSVM
The B10 lifetime of 38 years is achieved when the pro-
posed MLZSVM is applied to all regions. It means that
the applied region can be reduced through the proposed
hybrid MLZSVM strategy to satisfy the target B10 lifetime
of 30 years, which results in a decrease in the output current
THD.
Fig. 22 shows the unreliability functions of the DC-link
capacitor under different θh in the hybrid MLZSVM method.
θh of 0 ◦ means that the conventional SVM is applied to all
regions. A target B10 lifetime of 30 years can be satisfied
when θh is 40 ◦ , where the output current THD is 3.68 % as

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 J.-H. Choi et al.: Hybrid PWM for Improving Reliability of DC-Link Capacitors of NPC Inverter
analyzed in section C of III. Therefore, the improved output
THD can be achieved compared with when the MLZSVM is
applied in all regions (i.e. θh = 60 ◦ ), where the output current
THD is 4.1 %. In the case when the hybrid PWM concept is
applied with Method-II, the required θh is 50 ◦ to meet the B10
lifetime of 30 years, and the output current THD is 3.92%.
Method-1 is not considered since it cannot satisfy the target
lifetime of 30 years. It is seen from the above result that the
proposed hybrid MLZSVM method is the most effective for
satisfying the target lifetime when the output current THD is
considered at the same time. Furthermore, the unnecessary
deterioration in output current THD can be curbed through
the hybrid PWM strategy.
In this paper, the hybrid modulation angle (θh ) has been
chosen by mainly focusing on the lifetime of the PV inverter
so that a B10 lifetime of 30 years is achieved under the given
mission profile of the PV system.
The required θh could be different depending on the target
lifetime of PV inverters, the mission profile of PV systems,
and also how the DC-link is designed. Therefore, they should
be considered for determining θh as performed in this paper.
In the case that the specific mission profile of the PV inverter
is not available, the worst-case mission profile could be con-
sidered to guarantee the lifetime of the DC-link capacitors.
Furthermore, since the θh affects not only the reliability of
the DC-link capacitor but also the power quality, there is
a trade-off between them. It means that the power qual-
ity or filter size can be a limiting factor for selecting the
hybrid modulation angle. Therefore, it should be determined
properly by considering the requirements of the target appli-
cations for reliability and power quality. This principle can be
extended to other applications.
V. EXPERIMENTAL RESULTS
Experiments are carried out to verify the feasibility and
effectiveness of the proposed hybrid MLZSVM under the
following conditions: DC-link voltage (VDC ): 400 V, switch-
ing frequency (fsw ): 10 kHz, output frequency (fout ): 60 Hz,
DC-link capacitors (CDC ): 3300 µF, Load (R-L): 20 , and
1.5 mH.
Fig. 23 shows the collector-emitter voltage (i.e. voltage
stress) of each power device of phase-A under the SVM and
the MLZSVM. Regardless of the modulation schemes, the
collector-emitter voltage of the power devices is 200 V which
is half of the DC-link voltage. There is no difference in the
applied voltage stress on the power devices between SVM
and MLZSVM.
Fig. 24 shows experimental results of the output current in
time and frequency domains, line-to-line voltage, and upper
capacitor current in time and frequency domains under the
proposed hybrid MLZSVM with different θh of 0 ◦ , 20 ◦ , 40 ◦ ,
and 60 ◦ , respectively. It is seen that the output current is pro-
duced without any distortion in all cases. Thus, the proposed
hybrid MLZSVM method is applicable to three-level NPC
inverters for DC-link capacitor current reduction. However,
it is also seen that the ripple current, especially at 10 kHz
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increases as θh increases. It means the increase in output
current THD as θh increases in the hybrid MLZSVM method.
The RMS value of the upper capacitor current (ICU ) is 5.9 A
under the conventional SVM, and it decreases when the
regions where MLZSVM is applied (θh ) increase as 4.5 A,
3.2 A, and 1.3 A when θh is 20 ◦ , 40 ◦ , and 60 ◦ , respectively.
The decrease in ICU can also be seen from its FFT analysis.
Especially, the capacitor current at 10 kHz notably decreases
as θh increases. The different effects on the reduction of the
DC-link capacitor current depending on θh are also clearly
seen from the experimental results. The reduction of the
DC-link capacitor current results in lower power loss and
thus lower Th . Consequently, the lifetime of the capacitor
increases. The trade-off between the capacitor current and
output current THD is also confirmed.
The experimental results clearly show the feasibility
and effectiveness of the proposed method and its optimal
application for lifetime improvement without unnecessary
deterioration in output current THD.
VI. CONCLUSION
This paper proposes the MLZSVM method for increasing the
lifetime of the DC-link capacitor of the NPC inverter. The
proposed method has a better ability to reduce the DC-link
capacitor current compared with the state-of-the-art PWM
methods considered in this paper developed for the same
purpose. Therefore, the DC-link capacitor has the longest
lifetime under the proposed MLZSVM. In the case study,
when the proposed method is applied in all regions, the B10
lifetime is 38 years which is about 2.7 times longer than that
under the conventional SVM, which is 14.3 years. Further-
more, a mission-profile-based optimal application strategy of
the proposed MLZSVM called the hybrid MLZSVM strategy
is presented. Through the proposed hybrid MLZSVM, the
MLZSVM is applied to the specific regions only as necessary
to achieve the target lifetime of the DC-link capacitor, which
prevents unnecessary deterioration in output current THD.
In the case study, the required hybrid modulation angle (θh )
is 40 ◦ to satisfy a target B10 lifetime of 30 years which
is smaller than that when the hybrid PWM method with
Method-II is applied, where the required θh is 50 ◦ . Through
the proposed hybrid MLZSVM, less distortion in the output
current can be achieved, which is 3.68 % compared with the
hybrid PWM modulation with Method-II and the case where
the proposed hybrid PWM strategy is not applied, which are
3.92 % and 4.1 %, respectively. Finally, the feasibility and
effectiveness of the proposed hybrid MLZSVM method can
be verified through the experiments. The proposed method
also be applied to different cases for different target lifetimes
under different mission profiles of PV systems.
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VOLUME 12, 2024
JAE-HEON CHOI (Student Member, IEEE)
received the B.S. degree in electronic and IT media
engineering from the Seoul National University
of Science and Technology, Seoul, South Korea,
in 2021, where he is currently pursuing the M.S.
degree.
His research interests include the reliability of
power electronic components and systems, power
electronics in renewable energy generation, and
multilevel converters.
UI-MIN CHOI (Senior Member, IEEE) received
the B.S. and M.S. degrees from Ajou Univer-
sity, Suwon, South Korea, in 2011 and 2013,
respectively, and the Ph.D. degree in electrical
engineering from Aalborg University, Aalborg,
Denmark, in 2016.
From 2016 to 2018, he was a Postdoctoral
Researcher with the Department of Energy Tech-
nology, Aalborg University. In 2018, he joined
the Department of Smart ICT Convergence Engi-
neering, Seoul National University of Science and Technology, Seoul,
South Korea, where he is currently an Assistant Professor. He was a
Partner Researcher with Grundfos Holding A/S, Bjerringbro, Denmark,
from 2014 to 2016. His research interests include the reliability of power
electronic components and systems, power electronics in renewable energy
generation, and multilevel converters.
Dr. Choi received the IEEE Power Electronics Transactions Second Prize
Paper Award, in 2017. He is serving as an Associate Editor for IEEE OPEN
JOURNAL OF POWER ELECTRONICS.
FREDE BLAABJERG (Fellow, IEEE) received
the Ph.D. degree in electrical engineering from
Aalborg University, in 1995.
He was with ABB-Scandia, Randers, Denmark,
from 1987 to 1988. He was an Assistant Profes-
sor with AAU Energy, in 1992, where he was an
Associate Professor, in 1996, and a Full Professor
of power electronics and drives, in 1998. Since
2017, he has been a Villum Investigator. He is hon-
oris causa with University Politehnica Timisoara
(UPT), Romania, in 2017, and Tallinn Technical University (TTU), Estonia,
in 2018. He has published more than 600 journal articles in the fields of
power electronics and its applications. He is the coauthor of eight mono-
graphs and an editor of 14 books on power electronics and its applications,
such as the Series (four volumes) Control of Power Electronic Converters and
Systems (Academic Press/Elsevier). His current research interests include
power electronics and its applications, such as in wind turbines, PV systems,
reliability, Power-2-X, power quality, and adjustable speed drives.
Dr. Blaabjerg has received the 38 IEEE Prize Paper Awards, the IEEE
PELS Distinguished Service Award, in 2009, the EPE-PEMC Council
Award, in 2010, the IEEE William E. Newell Power Electronics Award,
in 2014, the Villum Kann Rasmussen Research Award, in 2014, the Global
Energy Prize, in 2019, and the 2020 IEEE Edison Medal. He was the Editor-
in-Chief of IEEE TRANSACTIONS ON POWER ELECTRONICS, from 2006 to 2012.
He was a Distinguished Lecturer of the IEEE Power Electronics Society,
from 2005 to 2007, and the IEEE Industry Applications Society, from 2010 to
2011 and from 2017 to 2018. From 2019 to 2020, he served as the President
for the IEEE Power Electronics Society. He has been the Vice-President of
the Danish Academy of Technical Sciences. From 2014 to 2021, he was
nominated by Thomson Reuters to be among the 250 most cited researchers
in engineering in the world.
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