Class Agenda

CSCI E-93, Spring 2019:
Computer Architecture
Agenda for 7-May-2019
Prof. James L. Frankel
Harvard University
Version of 4:11 PM 7-May-2019
Copyright © 2019 James L. Frankel. All rights reserved.
Pre-Class 1/29/2019
• Photos of class members, course staff, AV staff
First Class Meeting on 1/29/2019
• Our class web site is located at URL:
http://sites.fas.harvard.edu/~cscie287/spring2019/
• Distance students: Please participate in the live stream and ask

questions verbally using HELIX/Zoom in the Room’s audio/video link
• In addition, questions may be asked textually using HELIX/Zoom in
the Room’s Chat facility
• Do not use Canvas’ Chat facility – we will *not* be monitoring Canvas chat
Syllabus Review
• Review of Syllabus
• Staff Introductions
• Required and optional books
• Order books
• Contemporary Logic Design, 2/e; Katz & Borriello
• Computer Organization and Design: The Hardware/Software Interface, 5/e; Patterson
& Hennessy
• The Designer's Guide to VHDL, 3/e; Ashenden
• Students who will not be coming to class for the midterm exam should
make arrangements now for a proctor
Required Readings
• Refer to the Approximate Schedule section of the course website for
required readings to be completed before each class meeting
Section
• Section meets immediately before class
• 6:45-7:45 PM in 1 Story Street, Room 307
• Very important
• Discusses concepts & issues that are not covered in class
• Great forum for a more interactive dialog
• Is live streamed and also recorded
Altera/Terasic DE2-70/DE2-115 Hardware
• Show class the hardware
• Distance students should order the hardware now
• Terasic DE2-115 FPGA kit
• Available from Terasic (http://www.terasic.com.tw/en/)
• Academic pricing is available ($595 usual; $309 academic)
• Screen shot that shows that you’re registered in the course is sufficient to get the academic
pricing
• In addition to Terasic FPGA board, order USB to serial adapter & serial cable
• Possible static dissipative devices: mat, strap, ground point
• For local students, on February 19, 2019 during class, we will lend you the
hardware for the semester
• No static dissipative devices are included
• All borrowed hardware must be returned at the end of the semester
Piazza Poll about Altera DE2 Hardware
• All students must complete the Piazza poll “Hardware survey” (to be
created shortly) about purchasing vs. borrowing hardware
• We will have hardware available only for students who complete the
poll with the answer, “I plan to borrow and will be on campus the
days hardware is loaned and returned”
Say Hello!, Student Locations, Harvard Key,
Using nice
• Submit a video using Say Hello! in Canvas
• Please post your primary location using Student Locations facility in

Canvas
• Ensure that your Harvard Key is established
• Ensure that you have an account on the nice computers

• Login to nice.harvard.edu using SSH/SFTP (SecureCRT & SecureFX)
g.harvard.edu e-mail Address, Problem Set 0
• Ensure that you have a g.harvard.edu e-mail address
• Complete Problem Set 0

• Establish a GitHub account
• Install git as described on the section web site
• Modify the course questionnaire with your personal answers
• Fix warnings and errors in fix-this-program on the nice computers
• Write the word count program
• Create a branch named “problem-set-0“, create a merge request, add the
appropriate comment
Class Discussion Group: Piazza
• Ask questions in Piazza so the whole class can benefit from the
answers
• Personal questions should be sent to the course staff via e-mail
• If appropriate, include all three course staff members in e-mail to allow the
fastest reply
Lying to Students
• I will lie to you this semester
Lying to Students
• I will lie to you this semester
• There are too many details to give the whole truth
• That is the only way we can make reasonable progress through the material
• By the end of the semester, all lies will be fully corrected

Non-academic Class Activities
• Encourage a student community
• Class dinner after each class meeting
• Sailing outing in the Spring/Summer after the class has ended

Today’s New Material
• Cover Binary Logic Levels & Boolean Logic slides
Pre-Class 2/5/2019
Second Class Meeting on 2/5/2019
• Questions?
• From last class?
• From PS0?
• From section?
• Anything else?
• Reminder: Students who will not be coming to class for the midterm
exam should make arrangements now for a proctor
• Midterm will be three hours long
• Must start the exam from 8:00 PM ET on Tuesday, March 12, 2019 to 8:00 PM
ET on Wednesday, March 13, 2019
Reminder about Section
• Section meets immediately before class
• 6:45-7:45 PM in 1 Story Street, Room 307
• Very important
• Discusses concepts & issues that are not covered in class
• Great forum for a more interactive dialog
• Is live streamed and also recorded
Problem Sets
• Problem Set 0 was due this past Sunday night
• Go over Problem Set 1

• Due at midnight on this coming Sunday, February 10, 2019
Altera/Terasic DE2-70/DE2-115 Hardware
• Distance students should order the hardware now
• Terasic DE2-115 FPGA kit
• Available from Terasic (http://www.terasic.com.tw/en/)
• Academic pricing is available ($595 usual; $309 academic)
• Screen shot that shows that you’re registered in the course is sufficient to get the academic pricing
• In addition to Terasic FPGA board, order USB to serial adapter & serial cable
• Possible static dissipative devices: mat, strap, ground point
• For local students, on February 19, 2019 during class, we will lend you the hardware for
the semester
• No static dissipative devices are included
• All borrowed hardware must be returned at the end of the semester
• You must be present in the last class meeting (on May 14, 2019) to return the hardware
• There will be one more opportunity to return hardware after the due date (on May 17, 2019)
• Please respond to the PollEv survey (sent through Piazza) about picking up FPGA hardware in person
Say Hello! in Canvas
• Please submit a Say Hello! video in Canvas
Enroll in Piazza
• Enroll in Piazza
• Important questions are answered in that forum
• Ask questions in Piazza so the whole class can benefit from the
answers
• Personal questions should be sent to the course staff via e-mail
• If appropriate, include all three course staff members in e-mail to allow the
fastest reply
New Material for this Week
• Finish covering Boolean Logic slides
• Start with the XNOR Gate Observations slide
• Cover new slides

• Boolean Logic Continued
• Advanced Boolean Logic
• Laws and Theorems of Boolean Logic
• Computer Logic
• [Place Values delayed until later]
Pre-Class 2/14/2019
Third Class Meeting on 2/14/2019
• Happy Valentines Day!
• Questions?
• From PS0, PS1, or PS2?
• From section?
• Anything else?
• Reminder: Students who will not be coming to class for the midterm exam
should have already made arrangements for a proctor
• Must start the exam from 8:00 PM ET on Tuesday, March 12, 2019 to 8:00 PM ET on
Wednesday, March 13, 2019
Problem Sets
• Problem Set 1 was due this past Sunday night
• Problem Set 2 was presented in section yesterday

• Due at midnight on Sunday, February 24, 2019
Comments on Problem Set 2
• Your instruction set description and block diagram will become the basis
for the Principles of Operation documentation for your final project
• Your submission for PS2 will be continuously revised throughout the
semester
• Certainly make your best effort to have a complete and correct
submissions, but don’t worry if you still have open questions
• These will be resolved as the semester progresses
• Your best source for information needed to complete PS2 is from lecture,
course slides, section, and readings
• Please note the readings associated with class meetings in the syllabus
• Quick review of Computer Logic
• [Place Values delayed until later]
• [Numeric Encodings delayed until later]
• [Gray Codes & Karnaugh Maps delayed until later]
• [Canonical Form, Minterms & Maxterms delayed until later]
• [Dealing with Time in Combinational Circuits delayed until later]
• MIPS Instruction Set
• MIPS Datapath - Single Memory - No Pipelining
• MIPS Coding Snippets
• MIPS Assembly Language
Pre-Class 2/19/2019
Fourth Class Meeting on 2/19/2019
• Questions?
• From section?
• Anything else?
• Reminder: Students who will not be coming to class for the midterm
exam should have already made arrangements for a proctor
• Must start the exam from 8:00 PM ET on Tuesday, March 12, 2019 to 8:00 PM
ET on Wednesday, March 13, 2019
Problem Sets
• Problem Set 2 will be due on Sunday, February 24, 2019
• Finish covering MIPS Instruction Set slides
• Start with the Load Word Instruction slide

• MIPS Datapath - Single Memory - No Pipelining
• MIPS Coding Snippets
• MIPS Assembly Language
• Place Values
• [Numeric Encodings]
• [Gray Codes & Karnaugh Maps]
• [Canonical Form, Minterms & Maxterms]
• [Dealing with Time in Combinational Circuits]
Coming Attractions
• VHDL and using the Altera DE2 hardware
Distribute Altera DE2 Hardware
Pre-Class 2/26/2019
Fifth Class Meeting on 2/26/2019
• Questions?
• From previous classes?
• From section?
• From readings?
• Anything else?
Problem Sets
• Problem Set 2 was due last Sunday, February 24, 2019
• Problem Set 3 will be due on Sunday, March 10, 2019

Present Problem Set 3
• VHDL Counter
• Book Problems
• Final Program in High-level Language
• A word to the wise: Complete PS3 before the midterm exam

Midterm Exam
• Two weeks until the midterm exam on Tuesday, March 12, 2019
• Cover new material
• Numeric Encodings
• Gray Codes & Karnaugh Maps
• Canonical Form, Minterms & Maxterms
• Dealing with Time in Combinational Circuits
Finite Automata
• Finite State Machines
VHDL and Using the DE2 Hardware
• VHDL through the Process Example (reg.vhd) slide
Pre-Class 3/5/2019
Sixth Class Meeting on 3/5/2019
• Questions?
• From problem sets?
• From section?
• From readings?
• Anything else?
Problem Sets
• Problem Set 3 will be due this coming Sunday, March 10, 2019
• Problem Set 4 will be due on Sunday, March 31, 2019

• There are three weeks to complete PS4 because of Spring Break
Questions on Problem Set 3?
• VHDL Counter
• Book Problems
• Final Program in High-level Language
• A word to the wise: Complete PS3 before the midterm exam

• Assembler
• Final program in your assembly language
• Show the Altera Memory Initialization File (.mif) format

• http://sites.fas.harvard.edu/~cscie287/spring2019/def_mif.htm
• For the DE2-70, the value for the DEPTH parameter must be 16384, the WIDTH parameter must be 16
• For the DE2-115, the value for the DEPTH parameter must be 32768, the WIDTH parameter must still be 16
• These constraints are necessary because the memory system we are providing allows only the low 32K bytes
of memory to be initialized in the DE2-70 and the low 64K bytes of memory in the DE2-115
• Assembly language features

• http://sites.fas.harvard.edu/~cscie287/spring2019/slides/Assembler%20Concepts.txt
Memory-mapped I/O Interface
• http://sites.fas.harvard.edu/~cscie287/spring2019/io_interface.txt
PS4: Final Program in Assembly Language
• Parts 2 through 9 of PS4 detail subroutines to be written in your
assembly language to accomplish the required final program
• All programs must be acceptable to your assembler and produce a

correct .mif file
• Unfortunately, you will not be able to run and test your final program
under emulation until PS5 is complete
Midterm Exam
• Our midterm exam is next week, Tuesday, March 12, 2019 from 8 PM
to 11 PM in our usual classroom
• Ask any questions about the midterm exam today or on Piazza before
noon ET on the day of the exam
• Section will be meeting at its usual time next week, but there will be no
discussion of the midterm exam in fairness to distance students
• Also, there will be no questions during the exam – also in fairness to distance
students
Midterm Exam Material
• All material covered in class through and including today’s class
meeting
• Problem sets through PS3
• All readings on the syllabus through and including today’s readings
Slide Deck Material that is Midterm Eligible
• Binary Logic Levels • MIPS Instruction Set
• Boolean Logic • MIPS Datapath - Single Memory - No
• Boolean Logic Continued Pipelining
• Advanced Boolean Logic • MIPS Coding Snippets
• Laws and Theorems of Boolean Logic • MIPS Assembly Language
• Computer Logic • Hazards and Glitches
• Place Values • Endianness
• Numeric Encodings • Finite State Machines
• Gray Codes & Karnaugh Maps • VHDL
• Canonical Form, Minterms & • VHDL Looping
Maxterms • Assembler Concepts (a.k.a. Some
• Dealing with Time in Combinational Assembly Is Required)
Circuits • Criteria for Final Project Proposal
Types of Midterm Questions
• Similar to book questions
• Short answer
• Programming
• Hardware design
• Usually there is a question that requires the students to think outside

the box and create something new that is applicable to their final
projects
Midterm Directions
• Read each question very carefully
• The question should include all necessary information
• Present any truth tables in the format and order requested
• The point values in the exam are equal to the number of minutes that a
student who would score highly might take to complete the question
• The exam in lengthy – don’t be concerned if you don’t complete everything
• Initially, spend approximately the number of minutes on each question that
the question is worth, then return to the question later to complete them
as available time permits
Show the DE2-70 User Manual
• Do not program the Flash memory
• That is, ensure that the slide switch is always in the RUN position (not in the
PROG position)
• Table 5.1 on Page 34: Slide (Toggle) Switches

• Table 5.2 on Page 35: Pushbutton Switches
• Table 5.3 on Page 35: LEDs
• Table 5.4 on Pages 36-38: Seven-segment Displays
• Table 5.5 on Page 39: Clocks
VHDL and Using the DE2 Hardware
• VHDL continuing from the Process Example (reg.vhd) slide
• Show VHDL programs (on the class web site at Hardware Related
References -> VHDL Programs)
• 4-bit comparator versions
• Invert segment versions
• Debounce switch
• Rotate segments
• Identify segments
• VHDL Looping
• Hazards and Glitches
• Endianness
Pre-Class 3/12/2019
Seventh Class Meeting on 3/12/2019
• Midterm Exam
• 8 PM ET – 11 PM ET
Spring Break 3/19/2019
Pre-Class 3/26/2019
Eighth Class Meeting on 3/26/2019
• Questions?
• From midterm exam?
• From problem sets 1-4?
• From section?
• From readings?
• Memory-mapped I/O?
• Altera Memory Initialization File (.mif) format?
• Unresolved from Piazza?
• Anything else?
Spring Break
• I trust that everyone had a relaxing and/or productive Spring Break!
John Hennessy’s MIT Distinguished Lecturer
Series Talk
• He presented evidence that we are now really at the end of seeing
large performance increases in conventional architectures
• He argued that Domain-Specific Architectures are the way of the
future
• Example: Google’s Tensor Processing Unit (TPU) for TensorFlow
State of Midterm Exam Grading
• We’ve not quite finished the midterm exam grading
Problem Sets
• Problem Set 4 will be due on this coming Sunday, March 31, 2019
• There are three weeks to complete PS4 because of Spring Break
• The Preliminary Final Project Problem Set (ALU) will be due on

Sunday, April 7, 2019
• Problem Set 5 will be due on Sunday, April 14, 2019

Present the Preliminary Final Project Problem
Set (ALU)
• ALU for your CPU in VHDL
• Must be based on a bit-slice ALU component
• Should be implemented using combinational logic

• In VHDL, a process should not be required
Present Solutions to Midterm Exam
Question 6: Logic Design for ALU Bit-Slice
• Solution One: Structured around a single full adder in each bit slice
• Solution Two: Using a truth table approach
• Operations are:
• result  a + b
• result  b
• result  ~ b
• result  b + 1
• result  – b
• result  a – b
Logic Design for ALU Bit-Slice: Based on Full
Adder (1 of 2)
• Operations are:
• result  b
• result  ~ b
• Complete a design around a full adder

Logic Design for ALU Bit-Slice: Based on Full
Adder (2 of 2)
• Inputs are:
• A, B, Cin, KeepA, InvertB
• Outputs are
• S, Cout
• Encapsulation of ALU Bit-Slice
• Table detailing Function Encoding for each operation
• Full Adder truth table and gate-level implementation
• Overall connections for a 4-bit wide ALU
• Operations are:
• result  b
• result  ~ b
Logic Design for ALU Bit-Slice: Using a Truth
Table Approach (1 of 2)
• Operations are:
• result  a + b Function = 0
• result  b Function = 1
• result  ~ b Function = 2
• result  b + 1 Function = 3
• result  – b Function = 4
• result  a – b Function = 5
• Complete a design using a truth table approach

Logic Design for ALU Bit-Slice: Using a Truth
Table Approach (2 of 2)
• Inputs are:
• A, B, Cin, F2, F1, F0
• Outputs are
• S, Cout
• Encapsulation of ALU Bit-Slice
• Table detailing Function Encoding for each operation
• Truth Table
• Gate-level implementation
• Overall connections for a 4-bit wide ALU
• Operations are:
• result  a + b Function = 0
• result  b Function = 1
• result  ~ b Function = 2
• result  b + 1 Function = 3
• result  – b Function = 4
• result  a – b Function = 5
• Emulator/Simulator
• Now, you’ll finally be able to test your code written for PS4!
• Your emulator may also serve as a software model for the correct
implementation of instructions in your CPU
• Corrections/modifications to:
• ISA (Instruction Set Architecture)
• Block Diagram
• Principles of Operation documentation
• Assembler
Emulator Implementation (1 of 3)
• Your emulator need not implement your architecture in the same way
that your hardware/VHDL/FPGA will implement your architecture
• Architecture identical
• All aspects that an assembly language programmer could see and all aspects that are
described in your Principles of Operation documentation
• Not organizationally identical
• Does not need to implement instructions/sequencer in the same way that the hardware
will implement these aspects
• Our memory subsystem is little endian
• You must implement I/O to the serial (RS-232) ports
• Your emulator need not implement the PS/2 and LCD ports and their
status/control bits
• It is acceptable to assume that serial (RS-232) input and output are

always ready
• If you implement this approach, any attempt to read a character will
stall until a character is typed (if the input is buffered as a line, the
input operation will stall until a complete line is typed)
• Extra credit will be awarded for simulating the input ready bit
• You must implement some form of tracing
• Minimally: display the PC of each emulated instruction before executing it
• A multitude of extra credit options:

• Display all registers before executing each instruction
• Display only those registers that were modified before executing each instruction
• Update registers in a separate window pane or area
• Color to indicate modification
• Display of disassembly of each instruction before execution
• Single stepping
• Breakpoints
• Watch points for memory data locations
• …
• Pipelining/MIPS Multicycle Data Path through Right to Left Data Paths are
Problematic slide
Pre-Class 4/2/2019
Ninth Class Meeting on 4/2/2019
• Questions?
• From Preliminary Final Project problem set?
• From section?
• From readings?
• Anything else?
State of Midterm Exam Grading
• We’ve finished grading the midterm exams and we’re returning them
today
• If you took the midterm exam as a distance student, we’ll be e-

mailing your corrected/graded exams to you
• Summary of midterm grades

Problem Sets
• Problem Set 4 was due this past Sunday, March 31, 2019
• The Preliminary Final Project Problem Set (ALU) will be due this
coming Sunday, April 7, 2019

Preliminary Final Project Problem Set (ALU)

Problem Set 5
• Block Diagram
• Assembler
• Pipelining/MIPS Multicycle Data Path continuing from the Right to Left Data
Paths are Problematic slide
• Shifters
• PDP-8 instruction set
• PDP-11 instruction set
Pre-Class 4/9/2019
Tenth Class Meeting on 4/9/2019
• Questions?
• From section?
• From readings?
• PDP-8 instruction set?
• Anything else?
Midterm Exam Grading
• Return remaining midterm exams
• All distance students should have already received their graded

midterm exams
Problem Sets
• The Preliminary Final Project Problem Set (ALU) was due this past
Sunday, April 7, 2019

Preliminary Final Project Problem Set (ALU)

Problem Set 5
• Block Diagram
• Assembler
• Problem 1 (Counts toward Problem Set grade): Detailed description of
what happens on each cycle and for each clock edge for all
instructions
• Problem 2 (Counts toward Final Project grade): VHDL code to interact

with the memory subsystem
PS6: Problem 1
• See Clocking slides
• Present how clocking will work in the final project

• Clock goes everywhere always
• Enables are turned on by the controller FSM
• Usual clocking scheme

• Progress from one FSM state to another on clock rising edge
• While in an FSM state, assert appropriate enables and control lines (e.g., ALU
function, MUX control)
• While clock is high signals propagate through the data paths
• Clock registers on clock falling edge
PS6: Problem 2 (1 of 2)
• Present the memory interaction protocol from
http://sites.fas.harvard.edu/~cscie287/spring2019/processor_memory_interface.txt
• Additional signals are shown in
http://sites.fas.harvard.edu/~cscie287/spring2019/MemorySubsystemSummary%2020141118.pdf
• These include:
• clock_hold – stops sysclk1 & sysclk2
• clock_step – if clock_hold is already asserted, a rising edge on clock_step will generate a
single full clock cycle
• clock_divide_limit – a 20-bit std_logic_vector to slow sysclk1 & sysclk2
• sysclk1 – use this clock for your processor
• sysclk2 – 180° out of phase from sysclk1; can be used for your processor
• serial_character_ready – used only if the CPU implements a hardware serial port interrupt
• ps2_character_ready – used only if the CPU implements a hardware PS/2 port interrupt
• In addition, there are many signals that need to be connected directly to pins
PS6: Problem 2 (2 of 2)
• The memory subsystem VHDL code is available on the class web site
• For DE2-70:
• http://sites.fas.harvard.edu/~cscie287/spring2019/tools/Memory%20Subsystem%20VHDL%2020141118%20cscie93_DE2-70.zip
• See the DE2-70 Top-Level Shell File in the Memory Subsystem Summary
document
• For DE2-115:
• http://sites.fas.harvard.edu/~cscie287/spring2019/tools/Memory%20Subsystem%20VHDL%2020141118%20cscie93_DE2-115.zip
• See the DE2-115 Top-Level Shell File in the Memory Subsystem Summary
document
Question 1: Timing Waveforms, Hazards, and
Glitches
• 𝑓 𝐴, 𝐵, 𝐶, 𝐷 = 𝑚(6, 7, 8, 9, 12, 13, 14, 15)
• 1a: Schematic using AND, OR, and INVERTER (i.e., NOT) gates in sum-
of-products form
• 1b: Timing waveform graph
• 1c: Karnaugh map, or K-Map
• 1d: Does this circuit exhibit a hazard? What is the evidence for or
against the presence of a hazard? If there is a hazard, what kind of
hazard is it?
Question 7: Finite State Machine (FSM) for E-ZPass
• Mealy FSM – Output associated with transitions (edges/arcs)
• Inputs:
• C: car present
• D: dime
• Q: quarter
• T: transponder
• Output: G: Gate
• Solution One: States for idle, 0¢ (carPresent), 10¢, 20¢, 25¢, 30¢, ≥35¢
• Solution Two: Realize that there is no difference between the 25¢ & 30¢
states, so they are combined into a single 25¢or30¢ state
Midterm, FSM
• Inputs represented by CDQT
• Issues are:
• Self loops
• Covering all possible inputs
• No conflicts on inputs
• Must be Mealy
• Include state assignment table
• Identify start state
• PDP-8 instruction set slides
• Opcode 6 is for In-Out Transfer instructions
• Present condition codes and how they are combined for comparisons
Pre-Class 4/16/2019
Eleventh Class Meeting on 4/16/2019
• Questions?
• From section?
• From readings?
• Interface to the memory subsystem?
• Anything else?
Midterm Exam Grading
• Return remaining midterm exams
• All distance students should have already received their graded

midterm exams
Problem Sets
• Problem Set 5 was due this past Sunday, April 14, 2019

Problem Set 5
• Pretty cool to see your assembly language program running?
• Block Diagram
• Assembler
Problem Set 6
• Problem 1 has been revised

instructions

Issue with Generated sysclk1
• clock_divide_limit will slow down the effective rate of the generated clocks
• If this value is non-zero, the generated clocks will be gated to zero for this number of
cycles in between clock pulses
• If this value is zero (or left unmapped), the clocks are not gated
• It is currently *not* a square wave, but we will be trying to correct this

• There have been issues trying to create a square wave that works with out FPGA
clock routing
• If we can’t correct this issue, then the best approach is to take two cycles
to: (1) set control lines in the first cycle, then (2) enable registers that
should be loaded in the next cycle
• There is no need to use both clock edges if this approach is used
clock_divide_limit LSB
• Reminder: DO NOT SET THE LEAST SIGNIFICANT BIT of the
clock_divide_limit
Question 2: Floating-Point Representation
• Using IEEE 754 32-bit (i.e., float) floating-point representation, what would
be the representation of 3.37510 (i.e., 3.375 in decimal) as a normalized
float? Express your answer as a single hexadecimal number representing
the 32-bit float.
• As a reminder, an IEEE 754 32-bit float has three fields: a sign bit, an
exponent value, and the significand digits
• The sign bit is the most-significant bit, followed by the exponent value, and with the
significand bits in the least-significant bits
• The radix is 2, the exponent field is 8 bits wide, the significand field is 23 bits wide
• The exponent is expressed with a bias of 127
• The representation does use a hidden bit – that is, there is an assumed 1 bit to the
left of the binary point
Question 3: MIPS Instruction Set (1 of 2)
• In the MIPS instruction set, branch instructions use a version of the I-Type
instruction format. The 16-bit immediate field is treated as an offset. To
determine the branch target address, that immediate field is shifted left
two bits and sign-extended to 32-bits then added to the address of the
word following the branch instruction.
• The BEQ instruction is encoded with four fields, as follows from most-
significant to least-significant bit position
• (1) A 6-bit opcode field of 0001002 (i.e., 000100 in binary)
• (2) a 5-bit rs field
• (3) a 5-bit rt field, and finally
• (4) a 16-bit offset field
• The BEQ instruction has an assembly language format of:
beq rs, rt, target
Question 3: MIPS Instruction Set (2 of 2)
• Given the following program fragment,
loop: addiu $19, $17, 1
addiu $18, $18, -1
beq $18, $0, loop
• What is the encoded representation of the beq instruction? Express
your answer as a single hexadecimal number representing the 32-bit
instruction word.
Question 4: Laws and Theorems of Boolean
Algebra
• Compute the complement of 𝑋 + 𝑌𝑍 (that is, X + ~(YZ))
• Simplify the resulting formula
• Apply only one law or theorem at a time and identify which law or theorem
has been applied
Question 5: Boolean Simplification
• Given the following formula, arrive at a minimized form in sum-of-
product notation
• Use Karnaugh maps (K-maps) to perform the minimization
• Show your work using Karnaugh maps
• 𝑓 𝐴, 𝐵, 𝐶, 𝐷 = 𝑚(0, 2, 4, 6)
• Caching slides through Set Associative Caches slide
Pre-Class 4/23/2019
Twelfth Class Meeting on 4/23/2019
• Questions?
• From section?
• From readings?
• Anything else?
Problem Sets
• Problem Set 6 will be due this coming Sunday, April 28, 2019
Problem Set 6
instructions

Final Project
• Produce VHDL code for your entire processor design
• This includes the data path, the ALU, the memory interface, and the sequencing logic
• The final design should be implemented using the Altera DE2-70 or DE2-
115 system in conjunction with the furnished memory subsystem
• The culmination of your final project is to run the assembly language code
that you wrote for your processor in Problem Set 4, Parts 2 through 9
under your processor on the FPGA
• In addition, you are welcome to write, run, and demonstrate additional interesting
programs running on your hardware
• You should describe and demonstrate the special feature(s) that you
implemented
Final Project Class Meeting
• Final class meeting is on Tuesday, May 14, 2019 from 6:45 PM to
~11:00 PM, as necessary
• This is three weeks from today
• Students will present their final project to the class and answer
questions
• Students will create a pre-recorded ten minute video to be shown in class that
shows their final project
• Five minutes are reserved for a Q & A session
Final Project Presentation
• Included in your presentation should be slides that show your:
• block diagram
• clocking scheme
• sequencing logic
• interesting design aspects of your logic
• your instruction set
• assembler
• emulator
• special feature(s)
• a demo of your project running with the memory subsystem
• Show a small number of programs running on your hardware that
demonstrate the capabilities of your hardware (including any novel
features you have implemented)
Final Project Logistics
• Local students will participate in the question and answer session in
person
• The Q&A sessions for all distance students will take place over a web
conferencing application
• Distance students should send their web conferencing ID to the
course staff in advance of the final class meeting
Final Project Code & Document Submission
• By 2 PM ET on Friday, May 17th, each class member should submit
(with git tag term-project) a Final Project report which will include:
• the slides used during your presentation
• an overview of the processor
• an up-to-date copy of the processor block diagram
• an up-to-date copy of your processor's instruction set (i.e., your Principles of
Operation manual)
• VHDL code for the complete design
• a current copy of the source code for your assembler
• a current copy of the source code for your emulator
• documented sample programs for your processor
Returning Hardware
• Students who borrowed hardware will need to return their hardware
during the last class meeting on Tuesday night, May 14th
• Alternatively, students who want to keep their hardware until the
final project submission deadline of 2 PM ET on Friday, May 17th, will
need to make special arrangements prior to the final class meeting to
return their hardware
Issue with Generated sysclk1
• clock_divide_limit will slow down the effective rate of the generated clocks
• If this value is non-zero, the generated clocks will be gated to zero for this number of
cycles in between clock pulses
• If this value is zero (or left unmapped), the clocks are not gated
• It is currently *not* a square wave, but we will be trying to correct this

• There have been issues trying to create a square wave that works with out FPGA
clock routing
• If we can’t correct this issue, then the best approach is to take two cycles
to: (1) set control lines in the first cycle, then (2) enable registers that
should be loaded in the next cycle
• There is no need to use both clock edges if this approach is used
clock_divide_limit LSB
• Reminder: DO NOT SET THE LEAST SIGNIFICANT BIT of the
clock_divide_limit
Altera Hardware Reminders (1 of 2)
• For DE2-70: Application Note 2: DE2-70 Can't place multiple pins
assigned to pin location Pin_AD25: AN2 DE2-70 Can't place multiple
pins assigned to pin location Pin_AD25.txt
• For DE2-115: Application Note 1: Dealing with DE2-115 Current
Strength and Slew Rate: AN1 DE2-115 Current Strength and Slew
Rate.txt
• Device and Pin Options: Reserve all unused pins: As input tri-stated
Altera Hardware Reminders (2 of 2)
• Read the documentation for the memory subsystem that needs to be
compiled with student projects
• cscie93.sdc: this file specifies some clock and timing information for the Altera
TimeQuest Timing Analyzer
• To enable an accurate timing analysis, and avoid warnings about undefined clocks, you should
include this file in your project as well
• DE2-70 Only: Once you have included our VHDL files in your project, in order to
successfully compile your project you will need to add the following to your project’s
.qsf file:
• set_parameter -name CYCLONEII_SAFE_WRITE "\"RESTRUCTURE\"“
• This line can be added anywhere among the existing set_global_assignment lines
• Without this line, your compilation will fail with memory configuration errors from the
memory compiler
• See Other suggestions under Configuring your Quartus II Project
mem_reset
• When mem_reset is asserted to the memory subsystem, no sysclk1 or
sysclk2 clock pulses are generated
• Therefore, your use of mem_reset to reset your FSMs to their initial
states must be asynchronous to the clock (i.e., because you will not
received a clock pulse when mem_reset is asserted, you cannot use a
usual state transition that checks for mem_reset to cause your FSMs
to be in their initial (idle/reset) state
• So, you should use mem_reset to reset your FSMs, but check for
mem_reset before you wait for the (rising) edge of the clock (sysclk1)
Sample FSM Reset VHDL Code
stateMachine: process(mem_reset, sysclk1) is
variable newState: StateType;
begin
if mem_reset = '1' then
newState := state_reset;
elsif rising_edge(sysclk1) then
case presentState is
when state_reset =>
if mem_dataready_inv = '1' then
...
Demo of PS6 VHDL Solution
• Caching slides
• Continue from Set Associative Caches slide
• Serial Communication slides
• Virtual Memory slides
• Through Two-Level Page Table slide
Pre-Class 4/30/2019
Thirteenth Class Meeting on 4/30/2019
• Questions?
• Section?
• Final Project?
• Previous classes?
• Any problem sets?
• Preliminary Final Project problem set?
• Readings?
• Midterm exam?
• PDP-8 or PDP-11 instruction set?
• Anything else?
Problem Sets
• Problem Set 6 was due this past Sunday, April 28, 2019
• Final class meeting is on Tuesday, May 14, 2019 from 6:30 PM to
~11:00 PM, as necessary
• This is two weeks from today
• Sign up for presentation slots during class next week
questions
Operation manual)
Returning Hardware
New Final Project Clocking Scheme
• Present Final Project Clocking Scheme slides
• Virtual Memory slides
• Continue from Two-Level Page Table slide
• VLSI Design
• Processor Photomicrographs (See https://en.wikipedia.org/wiki/Transistor_count)
• Intel 4004 (4-bit CPU, 1971, 2,300 transistors)
• Intel 80386DX, i387, 486, 486DX2
• Intel i960 Cobra (32-bit CPU, 1984)
Pre-Class 5/7/2019
Fourteenth Class Meeting on 5/7/2019
• Questions?
• Remaining from Section?
• Final Project?
• Final Project Presentation?
• Previous classes?
• Any problem sets?
• Preliminary Final Project problem set?
• Readings?
• Serial port/terminal emulation?
• Anything else?
Course Evaluations
• Please complete the course evaluations sent from the Extension
School
Problem Sets
• All Problem Sets were already due
• Final class meeting is next week – on Tuesday, May 14, 2019 from
6:30 PM to ~11:00 PM, as necessary
• This is one week from today
• Sign up for presentation slots now!
questions
Dinner After Final Presentations
• We will go out for dinner at the Border Café after the final
presentations
• Significant others are invited to join us

Sailing Trip during the Summer
• I’ll let the class know when the boat is ready and possible date(s) via
e-mail
• Day outing
• Meet in the morning on the North Shore
• Pick up lunch
• Sail during the day
• Dinner together in the evening
Operation manual)
Returning Hardware
• We will be available to accept returns of hardware on Tuesday evening/night,
May 21st, 2019 in Science Center, Room 101e from 6:30 PM ET to 8:30 PM ET
• Demo of Logic Analyzer & Oscilloscope
• Output of logic analyzer fed to video feed?
• Magnetic core memory functionality
• Slides: Magnetic Core Memory 01 through 05
• Show & Tell of core memory
• Show & Tell of raw wafer, etched wafer, chip in DIP carrier
• Use microscope or close-up camera?
• Dependency analysis
• Slides: Dependencies, Instruction Scheduling, Optimization, and Parallelism
• SIMD computer organization
• Sketch on whiteboard
• Data Flow architecture
• A Preliminary Architecture for a Basic Data-Flow Processor, Jack B. Dennis & David P. Misunas
• Network connectivity
• Slides: Parallel Systems

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CSCI E-93, Spring 2019:

• Distance students: Please participate in the live stream and ask

• Please post your primary location using Student Locations facility in

• Ensure that your Harvard Key is established

• Ensure that you have an account on the nice computers

• Complete Problem Set 0

• By the end of the semester, all lies will be fully corrected

• Class dinner after each class meeting

• Sailing outing in the Spring/Summer after the class has ended

• Go over Problem Set 1

• Cover new slides

• Problem Set 2 was presented in section yesterday

• Cover new slides

• Problem Set 3 will be due on Sunday, March 10, 2019

• A word to the wise: Complete PS3 before the midterm exam

• Problem Set 4 will be due on Sunday, March 31, 2019

• A word to the wise: Complete PS3 before the midterm exam

• Show the Altera Memory Initialization File (.mif) format

• Assembly language features

• All programs must be acceptable to your assembler and produce a

• Usually there is a question that requires the students to think outside

• Present any truth tables in the format and order requested

• Table 5.1 on Page 34: Slide (Toggle) Switches

• The Preliminary Final Project Problem Set (ALU) will be due on

• Problem Set 5 will be due on Sunday, April 14, 2019

• Should be implemented using combinational logic

• Complete a design around a full adder

• Complete a design using a truth table approach

• It is acceptable to assume that serial (RS-232) input and output are

• A multitude of extra credit options:

• If you took the midterm exam as a distance student, we’ll be e-

• Summary of midterm grades

• Problem Set 5 will be due on Sunday, April 14, 2019

• Should be implemented using combinational logic

• All distance students should have already received their graded

• Problem Set 5 will be due on Sunday, April 14, 2019

• Problem Set 6 will be due on Sunday, April 28, 2019

• Should be implemented using combinational logic

• Problem 2 (Counts toward Final Project grade): VHDL code to interact

• Present how clocking will work in the final project

• Usual clocking scheme

• All distance students should have already received their graded

• Problem Set 6 will be due on Sunday, April 28, 2019

• Problem 1 (Counts toward Problem Set grade): Detailed description of

• Problem 2 (Counts toward Final Project grade): VHDL code to interact

• It is currently *not* a square wave, but we will be trying to correct this

• Problem 2 (Counts toward Final Project grade): VHDL code to interact

• It is currently *not* a square wave, but we will be trying to correct this

• Significant others are invited to join us

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• It is currently not a square wave, but we will be trying to correct this

• It is currently not a square wave, but we will be trying to correct this