CE246

Digital Systems
Design
Dr. Michael Walton

School of Computer Science and Electronic Engineering

University of Essex
Introduction

• Lecturer – Dr. Michael Walton

• Assisted in Labs by: Billy Baker

• These are classes and not LECTURES; so, the goal is to drive you to the right
direction.

• All relevant material available on Moodle.

• Acknowledgements: Dr. Steve Sangwine and Dr. Liang Hu

Learning Outcomes
• Understand the building blocks of complex digital
systems such as registers, counters and memory.
• Describe the implementation technologies used in
various types of digital systems.
• Design digital systems building blocks at gate level.
• Design systems using combinational and sequential
logic as appropriate and showing an appreciation of
timing issues.
Module contents
Introduction to digital systems design

Combinational circuit design

Sequential circuit design

Design of control and sequencing logic

Digital system timing

Implementation technologies for digital systems

Pre-requisites
• Familiar with the basics of digital circuits, including gates, flip-flops, registers, binary
number systems, Boolean algebra, and the distinction between combinational and
sequential circuits.
• If you are not confident, REVISE THEM - read material in Floyd's book (see the reading list
on Moodle).
• You have used Multisim before (in Year 1), you will be using it differently in this module
- cannot use standard TTL and CMOS components in your FPGA design, you must use the
correct FPGA gates and other components, and test them on the FPGA board in
hardware.

• Do not underestimate the work required on this module.

Structure
• Classes – 10 hours (one per week from week 2-11).
• Labs - 20 hours (2 hours each week from week 2-11) – Thursday 16:00 – 18:00.
• Weeks 2-3 mixed (with permission), then physical only – Lab 8.

• Week 4/5: Competence test in lab (30 mins).

• Week 7: Progress test on Moodle (30 minutes).
• Revision lecture: Over summer.
• Remember: Lab-based course so attending labs is very important!
• Classes will be recorded, so you have the option to listen again.

• Academic hour: Thursday 12:00 – 13:00 Please confirm before.

• Can use “Help Forum” on Moodle to post questions or have a discussion about a topic.
Assessment
• Coursework – 50%, Final exam – 50%
• Further distribution of coursework:
• Design Report 25% -
• Due date: 04-02-2022 (check FASER for exact deadlines);
• Assess your design work and ability to write a professional formal report, including ability to express technical
ideas in correct English (Please refer to the report format requirements available from week 3).
• CAD Competence Test 10% -
• Week 4 or 5 in Lab (30 minutes).
• Progress MCQ Test 10% -
• Week 7 on Moodle (30 minutes) – Tuesday between 10:00 – 11:00 am (check timetable);
• Assess understanding of the lab work and digital design concepts covered up to that point.
• Logbook 5% -
• Summary of activities in each lab (from week 2).
• Final exam:
• 2 hours - over summer; based on what you learned in the laboratory, backed up by the classes;
• Past papers on Moodle.
How to get a good grade?
• Attend all the labs and classes.
• The notes are not a substitute to attendance. If you missed a class:
(i) Read class notes
(ii) ask for additional notes from peers
(iii) read material online
(iv) watch recorded class on ‘ListenAgain’.
• Follow the material and ask questions if not understood.
• Write and submit coursework on time.
• If your marks are low, understand your mistakes.
• Attend competence and progress tests.
• Attend revision lecture.
 Course Overview
• CE264 is a course about digital systems design, and is a COURSEWORK-based course.
• It has to be learned by doing design and learning by doing is the main mode of learning
on this module.
• You will use National Instruments Multisim and Xilinx Vivado CAD software to design a
digital system for implementation on an FPGA board.

• Remember: “Learning by doing ”.

Lab work
• There are four parts to the laboratory work:

• A tutorial in which you will learn how to enter and build a trivial design, and download it
to the Basys3 board for testing (week 2).

• Stage 1 – a guided design in which you will learn how to enter a hierarchical design
composed of blocks that you have designed by yourself, with strong guidance on how to
design the blocks (weeks 3-4)

Note: Lab briefs with detailed instructions for each stage would be issued before start of
the respective stage. Please read carefully.
Lab work..
• Stage 2 – a design in which you will create a hierarchical block that generates a VGA
video raster. You will need this block for Stage 3. Although you will be given guidance
here, this stage is not a tutorial and you will have to start designing for yourself (weeks 5-
7).

• Stage 3 – an open-ended design with minimal guidance, based on a specification. You will
need to design a system, using the VGA block that you designed and implemented in
Stage 2, and much more (weeks 8-11).

Note: You only have 20 lab-hours, so make sure your progress on the tutorials and Stage 1
is sufficiently rapid. (If it isn’t, you will need to put in extra time outside the laboratory
sessions and/or change the way you are working to work more effectively or efficiently.)
Tools
• Circuit design
Multisim
Online tutorial: http://www.ni.com/tutorial/10710/en/

• FPGA design solution (IDE, compilation, optimization, …)

Xilinx Vivado
http://www.xilinx.com/support/download.html

Already installed in lab PCs and available on csee horizon.

Implementation board
• We will NOT use breadboard, but FPGA
board BASYS3

• Please download and study the datasheet of

theDigilent Basys3 implementation board:
http://www.digilentinc.com/Products/Detail.cfm?Prod=BASYS3
https://reference.digilentinc.com/basys3:basys3
Module design
• Intermediate module in digital electronics: CE162 → CE264 → CE339
• Educationally, we need to use schematics (Multisim) to provide a transition from CE162
to design
• Industrial engineers don’t design with schematics, they use hardware description
languages and design software e.g. Vivado directly
• Xilinx Vivado software is industrial grade CAD software. It isn’t trivial to use, and it is
designed on the assumption that its users are engineers
• In this module, you will learn how to design using Multisim and Vivado, and you will
learn about hardware description languages when you take CE339 next year
Warning: do not use Multisim for simulation, we should do it using testbench in Vivado,
another way is to direct test signals using instruments e.g. oscilloscopes
Useful online resources
• Digilent Website: http://store.digilentinc.com
• Basys3 webpage:
http://store.digilentinc.com/basys-3-artix-7-fpga- trainer-board-recommended-for-
introductoryusers/
• Basys3 Schematic: https://reference.digilentinc.com/_media/basys3:basys3_sch.pdf
• Basys3 Reference Manual: https://reference.digilentinc.com/_media/basys3:basys3_rm.pdf
• Basys3 Resource Centre: https://reference.digilentinc.com/basys3:basys3
• Basys3 Master XDC (constraints) file:
https://reference.digilentinc.com/_media/basys3:basys3_master.zip
• Xilinx Artix-7 FPGA family:
http://www.xilinx.com/products/silicon- devices/fpga/artix- 7.html
 • Scenario 1
Two students (A and B) are struggling with part of
their CE264 design work, and cannot understand

Plagiarism how to implement a widget divider that uses 7-bit

accounting. They discuss this problem with each
other then see on another student (C’s) screen that
and she has used a decade counter and a pair of cross-
coupled toggle flip-flops. They copy this idea and

Academic later submit their design reports on a design based

on this approach.

Offences • Have they done anything wrong?

• What if the design by student C is actually a really
bad way to implement the circuit, and no-one else
has done it that way?
Solution
• A and B have committed an offence if they do not acknowledge or reference the work of
C. They should also have spoken to C. If C’s design is not a very good way to implement
the circuit, it is more likely that the plagiarism will be detected.
 • Scenario 2
Plagiarism Student D is puzzled by part of his design, and in an
attempt to understand how to implement it, he posts
and a message to an Internet discussion group asking
about the problem. A very helpful reply is posted by
an engineer in South Korea, and D realises that the
Academic Korean engineer’s idea is just what is needed. D uses
this idea in his design.
Offences.. • Has D done anything wrong?
Solution
• D has done nothing wrong, provided s/he references the discussion with the Korean
engineer (a reference with a URL/hyperlink to the discussion itself would be
appropriate). If it is not referenced, an academic offence has been committed.
 • Scenario 3
Plagiarism Student E, like D, has a problem with part of her
design, and posts a contract bid on an Internet
and design site. A Russian engineer produces a design for
her, which she submits as her own work, and pays
Academic the Russian US$200 for his work.
• What does E need to do in her report to avoid an
Offences.. academic offence allegation?
Solution
• This is called contract cheating and is always an offence.
Further steps
• Week 3 onwards:
• Classes – discussion on technical content related to
the module.
• Labs – working on respective stages.

• Tutorial?
Thank
you