VLSI Guide: Floor Planning and Power Planning Interview Questions

5/11/2020 Floor Planning and Power Planning Interview Questions ~ VLSI Guide
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HOM E P HY SICAL D ESIGN FL OW
D ESIGN SETUP FL O OR P L ANNING
P L ACEM ENT CL O CK TR EE SY NTHESIS
R OUTING SIGNOFF SIGNAL INTEGR ITY
JOB OP ENINGS INTER VIEW QUESTIONS
VID EO TUTOR IAL S
Floor Planning and Power Planning

Interview Questions
https://www.vlsiguide.com/p/floor-planning-interview-questions.html 1/24
1. What is Floor planning?

2. How can you say a oor plan is good?
3. Is timing information mandatory for oor planning?
4. What are the inputs for oor planning stage?
5. What are the outputs from oor planning?
6. What are the oor planning control parameters?
7. Differentiate Static and Dynamic power? What are
the different techniques to save static and dynamic
power?
8. What do you mean by Aspect ratio?
9. What is Sanity check?
10. What is cell delay?
11. What is net delay?
12. What are the difference between standard cell and
macro?
13. Do static and dynamic power have any relation with
power supply?
14. What is core utilization?
15. What is total chip utilization?
16. What is Pre-routing? Why do you need to do it before
placement?
17. What is core limited and pad limited design?
18. Can macro be placed between core and die boundary
or in I/O pad?
19. How is macro placement done in oor planning?
What are the guidelines for macro placement?
20. What is placement blockage? What are the different

types of placement blockages?
21. What is Halo? How it is useful?
22. Can we rotate the macro in lower technologies?
23. What do you mean by Flylines? How it is useful in
oorplanning?
24. What is core utilization percentage?
25. What are the datas getting from synthesis team?
How do you validate them?
26. What is mean by wire bond and ip chip?
27. What is the need for sanity checks?
28. Can area recovery be done by downsizing the cells at
path with positive slack?
29. How to reduce congestion?
30. What are the inputs requred for oor planning?
Explain each?
31. What is Power planning?
32. Why do we use alternate routing approach HVH
/VHV (Horizontal-Vertical-Horizontal)/(Vertical-
Horizontal-Vertical)?
33. What is the main reason to use ip chip over wire
bond package?
34. How to nd out the minimum spacing between two
macros?
35. What are the steps to be taken care while doing oor
planning?
36. Why power stripes routed in the top metal layers?
37. What would you do in order to not use certain cells

from the library?
17 comments:
Sandeep 30 July 2019 at 11:29
Can you please post answers ..
Reply
ersadaf 10 September 2019 at 11:41

Q37> Set don’t use attribute on those library cells.
Reply
Q36> Power routes generally conduct a lot of current.

In order to reduce effect of IR drop, we need to make
these routes less resistive. Top metal layers are
thicker and offer lesser resistance. This helps to
reduce IR drop.
Reply
Q35> Following are the steps to be taken care while

doing oor planning.
1. Die Size Estimation
2. Pin/pad location
3. Hard macro placement
4. Placement and routing
5. Location and area of the soft macros and its pin
locations
6. Number of power pads and its location
Reply
Q34>
The distance between macro
= (no. of pins of macros*pitch*2)/no. of available
routing layers
Metal pitch = Metal Width + Metal Space
Reply
Replies
Madhu P 17 October 2019 at 08:00

the pitch varies for different metal layers.
which metal layer pitch we need to
consider? for e.g: in layerstack with 8
metal layers with 5 1x, 2 2x and 1 ultra

thick metal, width and space is different
for each of these categories.
Reply
This comment has been removed by the author.

Reply
Q33> Flip-chip assembly and wire bonding are the

principal methods for interconnecting ICs.
Following are the Process Advantages of Flip-Chip
Design
1. Device Speed
2. Power and Ground Distribution
3. I/O Density with Area Array
4. Package Size /Form Factor
5. Low Stress over active Area
6. Reliability
Reply
Q32>
1. No. of routing resources is increases.
2. To avoid crosstalk
3. To reduce RC value
Reply
Q31> Power Planning is used to distribute power to

each part of design equally.
Reply
Q30> Inputs are

1. Synthesized Netlist
2. SDC
3. Floor control parameters
4. Physical Partitioning information of design
Reply
Q29> Following are the congestion reduction

techniques
1. Placement Blockage
2. Module Constraints( Fence, Region, Guide)
3. Macro Padding ( Halos)

4. Cell Padding ( help to remove pin density)
5. Scan Chain Re-ordering
Reply
Q28>
Yes, Area recovery can be done by downsizing cells at
path with positive slack. Also deleting unwanted
buffers will also help in area recovery
Q27>
The main reason for using Sanity check is used to
checking/qualifying the design for further acceptance
at each stages of the physical implementation.
It quali es the netlist in terms of timing, checks the
issues related to library les, constraints les etc.
Following are the sanity checks carried out in
physical design ow:
(a) check_library: It performs consistency checks
between logical and physical libraries.
(b) check_timing: This is to check any unconstrained
paths present in the design. check whether the
pins/ports has it's corresponding I/O delays and also
checks for the clock de nition exists for all op pins.
(c) check_design: This check is to report problems
like undriven input ports, unloaded output ports,
nets/ports with multiple drivers, unloaded nets, pins

mismatch, cells or instances with out I/O pins/ports
etc.
Reply
Q26>
Flip-chip assembly and wire bonding are the
principal methods for interconnecting ICs.
Q24>
Core utilization = (standard cell area+ macro cells
area)/ total core area
A core utilization of 0.8 means that 80% of the area is
available for placement of cells, whereas 20% is left
free for routing.
Q23>
Flylines means check net connections from macro to
macro and macro to standard cells. If there is more
connection from macro to macro, place those macros
nearer to each other preferably nearer to core
boundaries.
Q22>
In advanced Technology Nodes Macro Orientation is
xed since the Poly Orientation can’t vary, so there
will be restrictions in Macro Orientation.
Q21>
Halo (Keep-out Region) is a region around boundary
of xed macro in desig in which no other macro or
std cells can be placed. Placement of cells out of such
region avoids congestion.
Reply
Q20>
In order to avoid placement in some areas, they are
used.
There are 3 types of Placement blockages
(a) Soft Blockage: allows only buffer & inverters to
optimizes/ meet the timing. Used for Timing purpose
only. Advantages is that Area is less, Timing is ease
& less transition time.
(b) Hard Blockage: Won't allow any cell. Used for
Routing purpose only. Advantages is used to avoid
congestion. Disadvatages is Area is wastage.
(c) Partial Blockage: Some % of all celss can be used.
No of available tracks can be increased uisng this.
Advantages is to meet timing, routing easy & less IR
drop.
Q19> Macro placement can be done using Macro

guidelines.
1. Based on Flylines analysis (connections) between

macros.
2. Macro should be near to core boundaries.
3. Communicating macros should be placed nearer.
4. Macro cell pin direction should be towards std cell
direction.
5. Two Macros in between, we can placed/add soft
bloackages
6. MAcros alignment should be follow
7. Criss Cross connection is not allowed.
8. Notches( edges) is avoided,
9. Orientation is not allowed.
Reply
Q18>
Yes. Core is de ned as the inner block, which
contains the standard cells and macros. There is
another outer block which covers the inner block.
The I/O pins are placed on the outer block.
Q17>
1. Pad Limited Design :
A design is called Pad limited design when there are
large number of pad cells determining the die size
2. Core Limited Design :
A design is called Core limited design when the large
number of standard cells and macros determine the
die size.
Q16>
Prerouting means routing of PG nets. Power Planning
also called Pre-routing as the Power Network
Synthesis (PNS) is done before actual signal (net)
routing and clock routing.
For Area optimization, pre-routing is need to do it
before placement(Flip Chip Concept)
Q15>
Total utilization T(F) of oorplan F is derived using
the following equation
T(F) = (A(m) + A(p) + A(s) ) / A
where A(m) = Area occupied by macros,
A(p) = Area occupied by Pads/ Pad llers
A(s) = Area occupied by Standard Cells
Reply

Q14>
Core Utilization = (Stdcell area + Macro Cell Area)/ (
Total Core Area)
Q13>
Yes.
Static Power: The charge power consumed when gate
is in ideal/ xed state (0 or 1). (Leakage Current)

Dynamic Power: The charge power consumed when
gate is in switching state. (Short Circuit Current)
Q12>
Macros are intellectual properties that you can use in
your design. You do not need to design it. For
example, memories, processor core, serdes, PLL etc.
A macro can be hard or soft macro.
A standard cell is a group of transistor and
interconnect structures that provides a boolean logic
function (e.g., AND,OR, inverters) or a storage
function ( ip op or latch).
Q11>
Net delay is the amount of delay from the output of a
cell to the input of the next cell in a timing path. This
delay is caused by the parasitic capacitance of the
interconnection between the two cells, combined
with net resistance and the limited drive strength of
the cell driving the net.
Q10>
Cell Delay is the amount of delay from input to
output of a logic gate in a path. PT calculates the cell
delay from delay tables provided in the technology
library for the cell.
Q9>
Sanity Checks mainly checks the quality of netlist in

terms of timing. It also consists of checking the
issues related to Library les, Timing constraints, IOs
and Optimization Directives.
Q8>
Aspect Ratio gives/ decide the shape of block.
Aspect Ratio = Vertical Resources/ Horizontal
Resources
Q7>
Static Power: The charge power consumed when gate
is in ideal/ xed state (0 or 1). (Leakage Current)
Dynamic Power: The charge power consumed when
gate is in switching state. (Short Circuit Current)
Static power(SP) = Leakage current * supply voltage
Leakage current = is (e ^qv/KT - 1)
where is= reverse saturation current
V = Diode voltage
K = Boltzman constant
T= Temperature
Dynamic power consumption of CMOS circuitry is
given by the formula:
DP = C * V2 * f
where P is the power, C is the effective switch
capacitance, V is the supply voltage, and f is the
frequency of operation.
How to reduce dynamic power?
1) reduce power supply voltage Vdd
2) reduce voltage swing in all nodes

3) reduce the switching probabilty (transition factor)
4) reduce load capacitance
Q6>
Floor planning control parameters are:
Aspect Ratio & Core Utilization
Q5>
Outputs of Floor Planning are:
1. Die/ Block Area
2. I/O pad placed
3. Macro placed
Q4>
Inputs for oor planning stage are
1. Synthezed Netlist
2. SDC
3. Floorplanning control parametes
4. Physical partioningv information of design
Q3>
Yes. For Sanity check purpose we need timing
information.
Q2>
1. Minimize chip area
2. Making routing easy
3. Reduce IR drop across design
Q1>
Floorplanning is process placing macros in chip/ core
area.
Reply
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5/11/2020 Floor Planning and Power Planning Interview Questions ~ VLSI Guide

HOM E P HY SICAL D ESIGN FL OW

D ESIGN SETUP FL O OR P L ANNING

P L ACEM ENT CL O CK TR EE SY NTHESIS

R OUTING SIGNOFF SIGNAL INTEGR ITY

JOB OP ENINGS INTER VIEW QUESTIONS

VID EO TUTOR IAL S

Floor Planning and Power Planning

1. What is Floor planning?

20. What is placement blockage? What are the different

37. What would you do in order to not use certain cells

ersadaf 10 September 2019 at 11:41

ersadaf 10 September 2019 at 11:43

Q36> Power routes generally conduct a lot of current.

ersadaf 10 September 2019 at 11:49

Q35> Following are the steps to be taken care while

ersadaf 10 September 2019 at 11:52

Metal pitch = Metal Width + Metal Space

Madhu P 17 October 2019 at 08:00

metal layers with 5 1x, 2 2x and 1 ultra

ersadaf 10 September 2019 at 12:03

This comment has been removed by the author.

ersadaf 10 September 2019 at 12:06

Q33> Flip-chip assembly and wire bonding are the

ersadaf 10 September 2019 at 12:26

ersadaf 10 September 2019 at 14:29

Q31> Power Planning is used to distribute power to

ersadaf 10 September 2019 at 14:31

Q30> Inputs are

ersadaf 10 September 2019 at 14:34

Q29> Following are the congestion reduction

3. Macro Padding ( Halos)

ersadaf 10 September 2019 at 16:09

nets/ports with multiple drivers, unloaded nets, pins

ersadaf 10 September 2019 at 16:10

ersadaf 10 September 2019 at 16:10

Q19> Macro placement can be done using Macro

1. Based on Flylines analysis (connections) between

ersadaf 10 September 2019 at 16:10

ersadaf 10 September 2019 at 16:11

is in ideal/ xed state (0 or 1). (Leakage Current)

Sanity Checks mainly checks the quality of netlist in

2) reduce voltage swing in all nodes

3. Reduce IR drop across design

Enter your comment...

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Physical Design Sanity Checks

Sign Off Checks

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Static and Dynamic Power Dissipation

Introduction to Low Power Design

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