Lecture 1: Course Outline & Introduction

DIGITAL LOGIC DESIGN

(ECCE 210)
Course Outline & Introduction

Dr. Baker Mohammad

ECCE 210 Digital Logic Design Slide 1

 Lecture 1: Course Outline & Introduction

Course Descriptions
• Data representation in digital computers
• Boolean algebra
• Minimization and implementation of logic functions.
• Design of combinational circuits
• Programmable devices (PLA, PAL, FPGA), multiplexers, decoders,
memory and tri-state devices.
• Basic ALU design
• Elements of sequential circuits: latches, flip-flops and counters.
• Design of synchronous sequential machines
• Introduction to CAD and hardware description languages

 What around you isn’t a computer or was created via computer?

 ECCE 210: First step on your career path

ECCE 210 Digital Logic Design Slide 2

 Lecture 1: Course Outline & Introduction

SYLLABUS
• Number Systems
• Boolean Algebra; K-map & Tabular Minimization Methods
• Combinational Circuit Design; Arithmetic Logic Circuits,
• Computer Aided design (CAD) Tools
• Hardware Description Languages (HDL)
• Sequential Logic Design
• Programmable Logic Devices; PAL, PLA, FPGA
• Memory Devices; RAM, ROM, SRAM
• CMOS Logic Family

ECCE 210 Digital Logic Design Slide 3

 Lecture 1: Course Outline & Introduction

Learning outcomes
1 Recognize data in different digital formats, convert from one format to another and perform basic
mathematical operations.
2
Analyze and Synthesis a logic circuit, set-up its truth table and describe its functionality.
3
Assess logic functions using Boolean algebra, and Karnaugh maps
4
Recommend combinational logic circuits and sub-systems of medium complexity using combinational-circuit
building blocks.

5
Describe simple synchronous sequential circuits and finite state machines.
6
Describe the general architecture and functionality of memory devices.
7
Define basic digital circuits using a hardware description language
8

Simulate logic circuits at component-level using digital simulation tools with schematic capture. Utilize
test/measurement equipment to debug/verify functionality
9
Write laboratory reports, interpret and appraise the experimental results.

ECCE 210 Digital Logic Design Slide 4

 Lecture 1: Course Outline & Introduction

Course and Lab Topics

ECCE 210 Digital Logic Design Slide 5

 Lecture 1: Course Outline & Introduction

TEXTBOOK & REFERENCES

• Textbook
– Fundamentals of Digital Logic with Verilog
Design, S. Brown and Z. Vranesic, McGraw-
Hill
• References
– Digital Systems: Principles & Applications,
R.J. Tocci & N.S. Widmer, Prentice Hall
– Logic and Computer Design Fundamentals,
M. Morris Mano & C. R. Kime, Prentice Hall
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ECCE 210 Digital Logic Design Slide 6
 Lecture 1: Course Outline & Introduction

ASSESSMENT
• Exam 1 Week 5 10%
• Midterm Week 10 20%
• Exam 2 Week 13 10%

• Final Examination 40%

• Lab experiments/project/report 20%
• 10%
• See Black Board for exact dates for

ECCE 210 Digital Logic Design Slide 7

 Lecture 1: Course Outline & Introduction

GRADING

• 90 –100%A
• 80 – 89% B
• 70 –79% C
• 60 – 69% D
• Below 60% F
• All grades are assigned on an individual basis.

Note: Above numerical values are representative of the particular grade band.

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ECCE 210 Digital Logic Design Slide 8
 Lecture 1: Course Outline & Introduction

COURSE POLICIES (1/5)

• Punctuality:
– Don’t be late!
– Cell Phones:
• Please turn your cell phone off before coming to
class!
• Lecturing Time:
– Efficient use of lecturing time
– Please do not discuss things with your

9
ECCE 210 Digital Logic Design Slide 9
 Lecture 1: Course Outline & Introduction

COURSE POLICIES (2/5)

• Academic Dishonesty:
– Any academic dishonesty will not be
tolerated, please consult the KU Code of
Academic Integrity.
• All lab reports should be completed entirely on
your own
• You are allowed to discuss general concepts and
ideas
• But you should not discuss lab assignments

10
ECCE 210 Digital Logic Design Slide 10
 Lecture 1: Course Outline & Introduction

COURSE POLICIES (3/5)

• Reading:
– Be prepared, read over material BEFORE
class.
• Re grading:
– All requests for re grading will be dealt with
in accordance with the relevant KU
policies.

11
ECCE 210 Digital Logic Design Slide 11
 Lecture 1: Course Outline & Introduction

COURSE POLICIES (4/5)

• Lab 1 (Starts Week # 3 of the semester)
• Labs must be finished on-time. Late labs will
not be accepted.
• Lab schedule subject to change
• A lab report required for all lab assignments,
including tutorials
• Due at the beginning of the following lab
period after the lab is due (unless otherwise
instructed).
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ECCE 210 Digital Logic Design Slide 12
 Lecture 1: Course Outline & Introduction

COURSE POLICIES (5/5)

• Use specified lab report format (A Microsoft Word
template will be provide to you)
• Pre-Lab is 20%, individual performance in Lab 20%,
report is 60% of each lab score
• Students should work in groups of two for laboratory
assignments
– Option of working on their own if computing
resources permit
• Choose your lab partner during the first lab and inform
your Instructor of your Selection
– Your lab partner will remain the same for the rest of
the semester – We will assign groups .....
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ECCE 210 Digital Logic Design Slide 13
 Lecture 1: Course Outline & Introduction

Information Delivery
• Presentation in class is the main channel
of information, including knowledge,
schedule announcements.
• Lecture notes and labscripts will be posted
on course website.
• Tutorials for vivado and Verilog will be
posted on lab website

ECCE 210 Digital Logic Design Slide 14

 Lecture 1: Course Outline & Introduction

Course management
• When Sunday, Tuesday, Thursday 9am
• Where TBD
• Instructors

Dr. Baker Mohammad

Office C04020- orange -> 4th floor -> office 20
Email baker.mohammad@kustar.ac.ae

Phone 02-5018513

ECCE 210 Digital Logic Design Slide 15

 Lecture 1: Course Outline & Introduction

Introduction to Logic Design

Location in course
textbook

Chapter 1

ECCE 210 Digital Logic Design Slide 16

 Lecture 1: Course Outline & Introduction

Learning objectives
• Be aware where logic circuits are in our
daily life.
• To know how logic circuits are
implemented in real world.
• To get familiar with the concept of design
process in industry.
• Understand the purpose of ECCE 210

ECCE 210 Digital Logic Design Slide 17

 Lecture 1: Course Outline & Introduction

Logic circuits are everywhere

• Computers
re
• Health Care
w he
• Mobile phones
e r y
• Security (monitoring, screening, encryption)
r e ev
• Audio visual systems
s a
• Electronic games
ni c
•
tr
Automobiles
o
•
• l ec
Missile guidance systems
E
Airplanes and space shuttles

ECCE 210 Digital Logic Design Slide 18

 Lecture 1: Course Outline & Introduction

Electronics/Computing Evolution
Bell’s Law: New class of Computing every
decade
 Device density(Moors Law)
 Volume increases
 Price Decrease

ECCE 210 Digital Logic Design Slide 19

 Lecture 1: Course Outline & Introduction

History: Invention of the Transistor

• Vacuum tubes ruled in first half of 20th

century: Large, expensive, power-hungry,
unreliable
• 1947: 1st point contact transistor at Bell Labs
– John Bardeen and Walter Brattain at Bell Labs
– Read the book titled Crystal Fire
by Riordan, Hoddeson

http://www.nobelprize.org/educational/physics/integrated_circuit/history/
ECCE 210 Digital Logic Design Slide 20
 Lecture 1: Course Outline & Introduction

Moore’s Law
• 1965: Gordon Moore plotted the number of
transistors on each chip
– Fit straight line on semilog scale
– Transistor counts have doubled every 18 months
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates

ECCE 210 Digital Logic Design Slide 21

 Lecture 1: Course Outline & Introduction

Transistor count is doubling every 18 months Moors Law

Manufactures are
now moving to multi
core devices.

ECCE 210 Digital Logic Design Slide 22

 Lecture 1: Course Outline & Introduction

Digital hardware
• Technology evolution
 Before 1960s, transistors and resistors as individual parts
 Integrated circuits: a number of transistors on a single chip (SSI,
MSI)
 By 1970, a microprocessor on a single chip
 In the early 1990s, a few million transistors on a chip (VLSI)
 By the late 1990s, 10 million transistors on a chip
 After 2019 Billion of transistors on single chip
• Moore’s law
 The number of transistors on a chip will double every 1.5 to 2
years. (from 1980 to 2010)
 Lower cost
 High speed
 Low Power

ECCE 210 Digital Logic Design Slide 23

 Lecture 1: Course Outline & Introduction

Digital hardware
• Implemented:
 On a single chip
 Multiple chips on a PCB (printed circuit board)
• Available chips that may be used
 Standard chips: <100 transistors, simple function,
fixed functionality.
 PLD (programmable logic devices): larger size,
general structure, user defines the function by
programming PLD.
 Custom design (no chip available): manufacturing a
chip on semiconductor material directly based on
logic function, area efficient, high speed, low cost for
high volum

ECCE 210 Digital Logic Design Slide 24

 Lecture 1: Course Outline & Introduction

Digital hardware
• Comparison

Advantages Drawbacks examples

Standard Simple, cheap Area inefficient, 74LS04
fixed function
chips
PLD Programmable, Area inefficient, not FPGA
A wide range of sizes, high speed
short time to market
Custom Area efficient, Expensive (high Microprocessor,
High speed, fixed cost), DSP, ASIC
design Long time to market

ECCE 210 Digital Logic Design Slide 25

 Lecture 1: Course Outline & Introduction

How to design a digital circuit with

millions of transistors
• A good designer should
Understand the specifications of the product
Convert the specifications to logic problems
Grasp principles of logic design ( ECCE 210)
Skillfully use of CAD tools
Understand VLSI (Delay, Power, ..)
Process Technology and Fabrication

ECCE 210 Digital Logic Design Slide 26

 Lecture 1: Course Outline & Introduction

Process for design a digital circuit

with millions of transistors
Basic design loop
1) Generate initial design,
manual efforts
2) Simulation, extensively
use CAD tools.
3) If errors, redesign
Iterative Process

ECCE 210 Digital Logic Design Slide 27

 Design Abstraction Levels

SYSTEM

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CIRCUIT
Vin Vout

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ECCE 625 Introduction.28

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Digital Design Abstraction Levels
iphone 4 PCB board

SOC-Chip

Module adder(a,b,cin,sum,cout)
MODULE
Input a,b,cin;
+
Output sum, cout;
GATE

CIRCUIT/
Physical Design

DEVICE
G
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n+ n+

30
 Lecture 1: Course Outline & Introduction

Cell Phone Digital System

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ECCE 210 Digital Logic Design Slide 31
 Lecture 1: Course Outline & Introduction

Block Level schematic ofLSOC

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ECCE 210 Digital Logic Design Slide 32

 Lecture 1: Course Outline & Introduction

Chip/die photo
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ECCE 210 Digital Logic Design Slide 33

 Lecture 1: Course Outline & Introduction

Summary
• Syllabus
– Why this course?
– What we will learn
– Outcomes of this course
– Grading policy
• Introduction to logic design
– Life needs digital
– History of digital circuits
– Design methodology

ECCE 210 Digital Logic Design Slide 34

 Lecture 1: Course Outline & Introduction

Backup/extra

ECCE 210 Digital Logic Design Slide 35

 Lecture 1: Course Outline & Introduction

Chip Design Main Functions

System Level
(Architecture) Register
Transfer Manufacturin
Language g (FAB)
RTL
Spec in word
doc or
system C Synthesis and
Si Validation
verification

Block Level
Design (u-
Architecture) Physical
System
Design
validation

ECCE 210 Digital Logic Design Slide 36

 Lecture 1: Course Outline & Introduction

A PCB in a computer system

ECCE 210 Digital Logic Design Slide 37

 Lecture 1: Course Outline & Introduction

Design concept
A

Partition
B

Design one block Design one block

C

Design interconnection between blocks

Functional simulation of complete system

No
Correct?
Yes D

Physical mapping

Timing simulation

No
Correct?
Yes

Implementation Figure 1.6. Design flow for logic circuits.

ECCE 210 Digital Logic Design Slide 38