CHAPTER 30

HOT AIR LEVELING

Sherry Goodell
Teledyne Electronic Technologies, Halco
Londonderry, New Hampshire

30. 1 INTRODUCTION

Hot air solder leveling (HAL) is a reliable technique for ensuring printed wiring board (PWB)
solderability during fabrication and through assembly. HAL provides protection of solderable
surfaces from corrosion and contamination with the application of eutectic solder (SnPb) or
alternative solder compositions (no lead) to the exposed solderable surface on a PWB. HAL
provides protection of the entire copper surface of a panel or selective areas for product types
such as solder mask over bare copper (SMOBC). With SMOBC product, solder mask covers
copper surfaces not requiring solder connections at assembly and leaves solderable sites
exposed. Typical shelf life for PWBs coated with HAL is 12 months under normal storage
conditions.

30.2 HISTORY

HAL has existed in various forms since the mid 1970s. Several beneficial features of HAL are
excellent shelf life, shorter solder wetting times at assembly, high mechanical durability, and the
formation of an intermetallic bond prior to the PWB assembly process. HAL as we know it
today has evolved from early processes known as roll tinning whereby a very thin layer of
solder was transferred to the panel from hot tinned rolls. This was followed by early vertical
processes that typically immersed PWBs vertically into a molten solder pot before the excess
solder was removed with high-pressure air. The vertical process has been refined over the years
and has overcome many of its initial problems of cosmetics and blocked holes. Horizontal HAL
was introduced in the late 1970s and by the mid 1980s offered many benefits and increased
capabilities over the vertical processes. The 1990s have continued to be a time of PWB
development requiring improved process capability. Fine-pitch products from 0.015 to 0.050 in
(0.4 to 1.25 mm) have challenged the process, with very acceptable results being achieved.
Current challenges include 0.008 to 0.01 in (0.2 to 0.25 mm) pitch features. Horizontal HAL
has addressed concerns related to vertical HAL. These include improved solder thickness
control, uniformity, reduced thermal shock, reduced copper dissolution, and a reduced
intermetallic compound (IMC) layer.

30.3 PROCESS FLOW

Panels presented for HAL typically have solder mask applied over the surface of all areas of the
PWB that will not receive solder; that is, conductors, ground shields, and other areas
nonessential for component assembly. If the entire panel requires solder, there will be no solder
mask applied before HAL. This is the exception rather than the rule. The process flow at HAL
consists of a preclean cycle, preheating, flux coating, solder coating, leveling with hot air knives,
cooling, and a postclean section (Figs. 30.1 through 30.3). The vertical and horizontal
processes are essentially the same sequence, except the vertical process is usually not an in-line
process and may not include the preheat and cool-down sections.

FIGURE 30.1 Process flow

Preclean Preheat Flux Solder Air knife Cool Down Postclean

Conveyor direction

30.3.1 Preclean

The Preclean employs a microetch, water rinse, and hot air dry. Some lines have an additional
acid rinse following the microetch chamber, prior to the water rinse. The microetch is typically
required to remove 0.75 to 1.0 mm (30 to 40 in) of copper to ensure that organic surface
contaminants are sufficiently removed. Available chemistries offer a variety of surface
topographies and process compatibilities. Many variables from prior manufacturing steps affect
the requirements and effectiveness of preclean, such as solder mask and solder strip. These will
be discussed in more detail in Sec. 30.4.1. The preferred method of preclean is an in-line
conveyorized system. The chemistries are sprayed onto the panel and transported at a
controlled rate to achieve a consistent etch and production rate. The horizontal process requires
these controls for best results. Many vertical lines use off-line batch cleaning. This is
accomplished by a horizontal precleaner or by immersing the panels in a tank of chemistry,
repeating the procedure for rinsing, and followed by a hot air dryer. Many process variables are
introduced with this process, and time between preclean and solder coat is typically not
controlled. Reoxidation of the panel is inevitable, which reduces solderability.

30.3.2 Preheat

Preheating varies with the equipment being used. A preheater serves two main functions: it
reduces thermal shock and helps prevent blocked or reduced holes. Efficient use of preheat
minimizes thermal shock to the PWB when immersed in the molten solder. Some vertical
processes do not use preheat. However, solder dwell times are increased to compensate,
especially with thicker panels over 0.062 in (1.6 mm). Typically, the panel is heated by
additional dwell time in molten solder at 490°F to 510°F (254°C to 266°C). Some horizontal
and vertical processes use convection ovens to prebake the panels as a preheat. The most
common horizontal system uses an infrared (IR) conveyorized preheater in line with variable
intensity and speed to control heating. The exit temperature should be monitored for process
control and product consistency. A typical 0.062 in (1.6 mm) thick panel temperature exiting
preheat should be 291°F to 345°F (144°C to 174°C) when measured at the surface. Efficient
heat transfer to the core of the PWB is important when processing panels of high aspect ratios
or inner layer connections that serve as heat sinks. Applying heat at a preheat stage allows for
reduced dwell times in the solder. Solder being cleared from the holes is more easily
accomplished when panel temperature is elevated. Recent horizontal processes have revealed
that preheating prior to applying flux to the panel is more beneficial than preheating after flux
coat. Postflux preheating causes the flux to lose some of its active ingredients and, with a
conveyorized IR preheater, it is a safety concern for potential combustion. With flux application
after preheating the panel, these concerns are minimized. Common process options used are:

1. Flux, heat, coat

2. Heat, flux, coat
3. Batch heat, coat
4. Batch heat followed by no. 1 or no. 2 (Note that this sometimes is used for thick
backplanes or multilayers.)

30.3.3 Flux

Flux application may vary somewhat by immersion or coating brush/nap rolls. Many solder-
leveling fluxes are available. The viscosity and acidity requirements are very much product-,
process-, and equipment-dependent. Horizontal HAL typically requires a much lower viscosity
flux than the vertical processes. The reduced dwell time in the molten solder of the horizontal
process requires the flux to disperse quickly to allow for adequate solder wetting. Flux selection
must take into consideration requirements such as surface insulation resistance (SIR), ionics, and
uniformity as well as product characteristics that affect flux performance. Product characteristics
include coverage issues, solder mask type, base materials such as nickel/gold, and no-lead
solder alloys.

30.3.4 Solder Coating

Solder coating is accomplished by total immersion of the PWB in molten solder. A glycol-based
oil blanket, with chemistry compatible to the flux, limits dross formation on the solder. In
horizontal equipment, it protects dross formation on any moving parts that would otherwise be
exposed to the atmosphere. In the most commonly used horizontal equipment today, PWBs are
conveyorized on a level plane through the solder by tapered rolls that hold the panel flat for a
solder dwell time of two seconds. Other horizontal systems use various conveyor mechanisms
to transport panels through the solder. These range from rolls to mesh conveyors, with some
systems using conveyors that are angled. The panels are bent slightly as they are processed
through the solder.

In all HAL, the previously applied flux is displaced by the solder. An intermetallic (IMC) bond
(Cu6Sns) is formed between the base copper and the solder. The horizontal soldering process
should be complete in less than two seconds if there are no contaminates interfering with the
direct contact of the solder to the copper. The vertical process dwell times vary from the top of
the panel to the bottom of the panel with PWB thickness. Some types of copper contamination
can be displaced with additional time in the molten solder. Increasing solder dwell times must be
considered carefully, as this also increases the thickness of the IMC layer. The IMC layer is not
a solderable surface and must have sufficient eutectic solder thickness overcoating after leveling
to ensure solderability.

30.3.5 Leveling

Leveling actually takes place directly after solder coat. With molten solder coating the PWB, it
is passed through pressurized hot air knives to remove excess solder and level the remaining
deposits, as well as to clear the holes of excess solder. The air is supplied via commercial
compressors through a heat source and then to the air knife. Typical air temperatures are 400°F
to 500°F (204°C to 260°C) at the knife. Air pressures range from 12 to 30 psi dynamic,
depending on the equipment used, board thickness, hole aspect ratio, and knife distance from
the PWB.

Leveling results are controlled by air knife configurations and setup parameters. Critical
parameters include panel-off contact (distance from panel to air knife), air knife angle, dynamic
air pressures (in psi), panel SMT feature orientation, and speed through the air knife. The
vertical HAL process is at a major disadvantage at this stage. Panel fixturing limits off-contact
distances and, due to the panel being vertical, produces a natural tendency for solder to sag or
puddle on the lower edge of a component pad, surface mount pad, or plated through-hole
(PTH), which can affect hole size.

Once the molten solder is leveled, it must solidify before cleaning. Solidification takes only a few
seconds. Cool-down takes on different forms for different applications. Some applications
require only that the solder solidify during cool-down, but others require the panel to reach a
certain temperature to prevent panel warpage or thermal shock when entering postclean liquids.
The horizontal process can accommodate these variations in line using an air table concept. The
panel floats on a bed of air. Most vertical processes require the panel to be manually removed
from the solder coat fixture and racked on an accumulator or placed on an off-line cool-down
module.

30.3.6 Postclean

Postclean is the final stage of the HAL process. Customer and application requirements cover a
wide range at this stage. Depending largely on product type and application, postclean can be a
simple removal of flux residuals to very tight specifications for ionic contamination levels
(IONICS) and surface insulation resistance (SIR) requirements. The most common variables at
postclean are the chemistries used and their concentrations. Water quality, water with a
detergent, water with board cleaners, and solvents used along with flood, high pressure, and
brush chambers affect the final results. Telecommunications applications typically have the
highest standards of cleanliness. The water rinse can be tap or DI. Variables that apply to
chambers are bath temperature, water flow rates and recirculation (conductivity sensors), and
contact time.

30.4 CAPABILITIES

30.4.1 Preclean

Preclean operations at HAL are intended for, and capable of, oxidation removal from the
surface of the base copper metal. Preclean requirements and success are dependent on the
product supplied for HAL. Contaminants remaining from uncontrolled or incomplete processing
at prior processes will not be removed in a mild microetch and will impair the solder coating
results. Figure 30.4 shows the common sources of contamination and a simple oxide disclosure
test procedure for testing copper cleanliness and solderability troubleshooting after each of these
processes.

Common variables at preclean are:

• Type of chemistry

• Concentration of active ingredients (oxidizer, acid)

• Copper concentration of etchant

• Temperature

• Contact time

Several of these are shown with typical microetch ranges used and the effect each has on
process results. Table 30.1 shows the most common chemistries used. Pre-clean bath life is
often dictated by copper concentrations. One method of controlling copper concentrations in
the bath is use of a bleed-and-feed system. This adds fresh chemistry by using a controller that
analyzes for copper concentration using a copper colorimeter.

FIGURE 30.4 Contamination and oxide disclosure (courtesy of Pratta).

Tank 1 20% ebonol C-50

Tank 2 80% water (ambient temperature)
Procedure: Dip panel into tank 1.
Soak two minutes.
Rinse in tank 2.
 Air dry.
Inspect for uniform blackening.

• Uneven blackening indicates that an organic is hindering the coat of this blackening
material.
• Once the organic is cured to the copper, it is nearly impossible to remove by
conventional pre-cleaning in microetches.
• The test is nondestructive.
• Remove blackened surface by conventional precleaning.

TABLE 30.1 The Most Common Preclean Chemistries

Chemistry Etch rate*

Ferric chloride 30-70 µin
Sodium persulfate 30-70 µin
Peroxide sulfuric 30-70 µin
* Actual etch rate required varies with product.

There are many theories as to the effect different preclean chemistries have on solder
distribution. One study evaluated hydrogen peroxide/sulfuric acid, sodium persulfate, potassium
monopersulfate, and ferric chloride. Approximately 60 µin (1.5 µm) of copper was removed
from each sample. The micrographs in Figs. 30.5 through 30.14 show the copper surface
topography by SEM at 1,000x and 2,000x magnification. Table 30.2 shows the solder
distribution on the surface after HAL. Microetch chemistry shows no strong effect on solder
distribution across surface mount pads, even though there are noticeable differences in the
copper surface topography produced by the different chemistries.

Adequate copper preparation is essential for preferred results at solder coat. Any organic
residue remaining on the surface will delay or prohibit solder coating in that area. The preclean
operation at HAL is not intended to or capable of removing contaminants on the surface as a
result of incomplete processing at prior operations. An easy oxide test can be done at each
operation to identify the source of contamination. The procedure is shown in Figure 30.4, with
common sources of contamination shown in the troubleshooting guide.

TABLE 30.2 Preclean Solder Distribution Effects (courtesy of Pratta)*

Measuring points Ferric chloride Sodium persulfate Peroxide/sulfuric

1 0 0 0
2 52 55 58
3 52 50 65
4 105 100 125
 5 280 300 265
6 255 280 250
7 0 0 0
X 148.8 157.0 152.6

* The thickness of solder and its distribution across the pads did not change significantly with
the different microetch chemistries, as shown by the solder thickness graphs of average
measurements. All measurements are in microinches.

30.4.2 Preheat

A minimum PWB surface temperature is required for IMC formation and soldering to take
place. A process balanced for preheat and dwell time is needed. Pre-heat at HAL is intended to
heat the core of the PWB to prevent blocked or reduced holes and minimize thermal shock.
While prevention of blocked and reduced holes can be a process variable, the minimization of
thermal shock can be a function of board integrity.

Some HAL processes do not include preheat. The holes are heated by increasing the soak
(dwell) times in the molten solder. This substitute is effective in allowing air to clear most holes at
the air .knife, provided the panel is not too thick and the holes are not too small (aspect ratio).
Excessive soak time can be detrimental to the PWB quality, causing conditions such as
delamination and high IMC thickness, which can be detrimental to solderability at assembly.

Thermal shock has always been a concern associated with the HAL process. Controlled use of
preheat minimizes the thermal shock subjected on a PWB (Fig. 30.15). Vertical processes that
use a preheat and then stage the panels prior to solder coat cannot control the temperature in
which a panel enters the solder. The panel is preheated but cools for an undetermined time at
uncontrolled temperature conditions. Therefore, process controls are lost.

30.4.3 Flux

Flux can be applied by immersion, rolls, or spray. Complete coverage and uniform coating are
important. Flux selection can be difficult and confusing, depending on the products being
processed and the equipment being used. The proper flux selection will provide adequate
lubrication to the panel, promote coverage, wetting of the solder and, when applicable, be
compatible with oil blankets on the solder. When cleanliness requirements are measured, the
flux must also be readily removed without leaving residuals.

The type of chemistry is sometimes dictated by the customer. Some applications require rosin-
based fluxes or other specialty fluxes. However, the most common fluxes used are water
soluble, glycol-based. These give the best results and are easier to remove after HAL without
solvents.
Fluxes used for HAL are typically acid-activated using HC1 or HBr. Some citric and other
acids are being evaluated. Concentrations vary and are somewhat product dependent. Highly
active fluxes increase effectiveness to break down flash oxidation on copper to promote solder
coverage. Lower flux activity tends to provide cleaner soldered boards with less corrosive ionic
salts and residues.

The last variable to be discussed here is flux viscosity. This too is very much product and
process dependent. Higher-viscosity fluxes provide better laminate and solder mask protection
(lubricity) from solder sticking. Lower viscosity fluxes promote faster solder wetting and
coverage as well as better rinsing in the postcleaner.

During operation, flux properties may vary with each system. Some equipment types use flux
recirculators that expose flux to preheated panels. This repeated exposure to heat will alter the
original flux viscosity and volatile content. Flux level, viscosity, and volatile content can be
controlled with the use of a flux-replenishing system. A replenishing system will contain
electronics and sensors to balance the flux reservoir by addition of replacement flux or
replenisher flux, which is a high-volatile version of the original flux.

30.4.4 Solder Coating

Solder coating is the actual application of solder. Solder coating should be accomplished in as
little time as required to provide adequate solder wetting with a thin layer of IMC. This is
normally accomplished in less than two seconds with in-line preheating. IMC is the tin and
copper migration that creates the metallic bond between the copper feature and surface solder.
While a layer of IMC is essential to the process, it should be kept as thin as possible (Fig.
30.16). The IMC layer will continue to grow as copper migrates toward the surface, The rate of
growth is slow during normal storage conditions; however, growth is rapidly accelerated with
each thermal cycle the panel experiences. Table 30.3 shows a comparison of IMC thicknesses
typically obtained using a horizontal process and a vertical process. Although the solder dwell
times are both considered to be two seconds, in a vertical process, the leading edge of the panel
going into the solder is also the trailing edge on withdrawal. This varies the dwell time across the
panel and the IMC thickness. The horizontal process removes this variable as the first end in is
the first end out, yielding a uniform dwell time across the panel. Panel size or thickness has no
effect.

TABLE 30.3 IMC Thickness Comparison by Process

Horizontal vs. Average Maximum

Vertical µin µm µin µm
Horizontal 6.0 0.15 15.3 0.38
(1 pass)
Horizontal 10.8 0.27 39.9 1.00
 (2 pass)
Vertical A 15.0 0.37 51.0 1.27
(1 pass)
Vertical B 12.5 0.31 48.0 1.20
(1 pass)
Vertical C 17.5 0.44 75.0 1.88
(1 pass)
Vertical D 13.0 0.33 49.0 1.20
(1 pass)

IMC thickness becomes important when surface mount thickness specifications are addressed.
Horizontal HAL with a two-second solder dwell time shows an average of 6 µin (0.152 µm).
The vertical process shows an average range of 12.6 to 17.6 µin (0.31 to 0.44 µm), depending
on equipment used. The maximum IMC thickness shown is approximately 20 µin (0.5 µm) for
the horizontal process and over 70 µin (1.75 µm) on the vertical process. The high range of
IMC thickness on the vertical process is due to the variation of dwell time across the panel. As
shown in Fig. 30.17, the IMC thickness almost doubles with exposure to a second cycle since
the IMC layer itself is not eutectic SnPb and is nonsolderable at assembly. A sufficient layer of
eutectic solder over the IMC layer is necessary to ensure solderability. Minimum solder
thickness specifications typically take this into consideration and specify minimums sufficient to
match the number of assembly thermal cycles required.

30.4.5 Leveling

Solder leveling is the removal of excess solder from the PWB. Capabilities of leveling vary
greatly with equipment and process controls. The following capabilities are based on horizontal
processing using a Unicote® system. Figure 30.18 shows some comparison data from other
systems. The horizontal systems are the latest generation of HAL and therefore show much
improved capability. The above capabilities are based on a uniform two-second dwell time and
a specific process system using the Unicote® machine. These capabilities may vary with other
HAL processes.

30.4.6 Postclean

Postclean is the removal of processing fluids from the surface of the PWB. The primary concern
is removal of any flux from the surface of the PWB after leveling. Typical postclean operations
have a detergent wash followed by a water rinse.

Because HAL fluxes are water soluble, this is adequate for general cleaning applications.

Some applications require more stringent cleanliness standards. These require measurements of
ionic contamination levels as well as surface insulation resistance.
Typical SIR requirements are 3 x 109 f2 at 24 hours, 95°F (35°C) and 85 percent RH after
HAL. Typical ionic requirements are 6.5 µg/cm2. Several proprietary chemistries are available
to help achieve these requirements. Many factors contribute to ionic and SIR levels, and often
an entire process must be reviewed. The use of DI water and extended length of rinse chambers
is sometimes required (Tables 30.4 through 30.7).

Surface insulation resistance after HAL

Dept: Screening --- without s/m

HAL X with s/m Type s/m: Deso
Temperature: 95° F to 104°F
(35°C to 40°C)
RH: 85% min.
Time: 24 hours
Test conditions: Volts: 50
No. test points: 32
IRA: 7.4 × 103
R. min.: 4.0 × 103

TABLE 30.4 Combination Pattern vs. Entire Board* (courtesy of Pratta)

Date Process Pattern Average P/F Log no.

12
08/02/94 PI/SS/DI CD GH 1.00 pass 370 comb only: DI No HAL
08/03/94 PI/HAL CD GH 25510 pass 376 comb only: DI 90°F std.
10
08/05/94 PI/HAL CD GH 3.37 pass 378 comb only: DI 125°F
08/07/94 PI/HAL CD GH 7.569 pass 382 comb only: DI 90°F new sox
10
08/12/94 PI/HAL ABCDEFGH 7.32 pass 385 comb only: 125°F new sox
12
08/02/94 PI/SS AB EF 1.00 pass 369 comb only: no DI no HAL
10
08/03/94 PI/HAL AB EF 1.93 pass 374 comb only: no DI 90°F std.
08/05/94 PI/HAL AB EF 0.539 pass 377 comb only: no DI 125°F
08/07/94 PI/HAL AB EF 1.949 fail 381 comb only: no DI 90°F new sox
11
08/02/94 PI/SS/DI CD GH 7.65 pass 372 entire board: DI no HAL
10
08/03/94 PI/HAL CD GH 5.98 pass 374 entire board: DI 90°F
10
08/05/94 PI/HAL CD GH 4.66 pass 380 entire board: DI 125°F
10
08/07/94 PI/HAL CD GH 2.02 pass 384 entire board: DI 90°F new sox
11
08/02/94 PI/SS AB EF 8.47 pass 371 entire board: no DI no HAL
08/03/94 PI/HAL AB EF 4.199 pass 373 entire board: no DI 90°F
08/05/94 PI/HAL AB EF 4.389 pass 379 entire board: no DI 125°F
08/07/94 PI/HAL AB EF 8.149 pass 383 entire board: no DI 90°F new sox

* Comb only = no mask over remaining board for lots with mask in honeycomb area. Typical
honeycomb pattern on both types.
 Entire board = mask covering legs and honeycomb.

TABLE 30.5 SIR Test Results--Finish A Solder Mask*

Reading no. Resistance (Ω Ω) Log10 of resistance

9
1 6.00 9.7781513
9
2 7.00 9.845098
3 7.409 9.8692317
9
4 6.00 9.7781513
10
5 9.00 10.945243
6 6.509 9.8129134
9
7 9.70 9.9867717
9
8 6.10 9.7853298
9
9 9.50 9.9777236
10 9.809 9.9912261
10
11 1.30 10.113943
10
12 1.80 10.255273
10
13 1.60 10.20412
10
14 1.40 10.146128
10
15 1.30 10.113943
10
16 1.40 10.146128
9
17 5.90 9.770852
9
18 7.50 9.8750613
9
19 6.70 9.8260748
20 3.909 9.5910646
9
21 8.80 9.9444827
9
22 8,90 9,94939
9
23 8.80 9.9444827
24 8.109 9.908485
9
25 3.30 9.5185139
9
26 2.80 9.447158
9
27 2.20 9.3424227
28 1.209 9.0791812
9
29 5.70 9.7558749
9
30 6.70 9.8260748
9
31 6.10 9.7853298
32 6.309 9.7993405
10 average of longs 7565151221
Minimum resistance (Ω) 9.07918125
Maximum resistance (Ω) 10.9542425
 Process sampled Finish B--Vacrel
Date sampled 09/13/94
Line width (25 mil nominal) 25
Line spacing (50 mil nominal) 50
Pass/fail pass
* Courtesy of Pratta

TABLE 30.6 SIR Test Results--Finish B Solder Mask*

Reading no. Resistance (El) Log10 of resistance

1 6.2010 10.792392
2 8.3010 10.919078
3 6.9010 10.838849
4 1.2010 11.079181
5 5.0010 10.69897
6 3.8010 10.579784
7 4.5010 10.653213
8
8 8.70 8.9395193
9 2.1010 10.322219
10 3.7010 10,568202
11 4.3010 10.633468
12 7.5010 10.875061
13 1.9010 10.278754
14 1.5010 10.176091
15 4.0010 9.60260
16 4.7010 10.672098
17 2.7010 10.431364
18 3.1010 10.491362
19 2.4010 10.380211
20 2.0010 10.30103
21 4.3010 10.633468
22 2.6010 10.414973
23 1.8010 10.255273
24 1.6010 10.20412
25 6.6010 10.819544
26 7.9010 10.897627
27 5.6010 10.748188
28 4.8010 10.681241
29 7.2010 10.857332
30 6.4010 10.80618
31 4.7010 10.672098
 32 8.0010 10.90309
10 average of longs 3.42921 o
Minimum resistance (Ω) 8.93951925
Maximum resistance (Ω) 11.0791812
Process sampled Finish A--Probimer 52
Date sampled 09/13/94
Line width (25 mil nominal) 25
Line spacing (50 mil nominal) 50
Pass/fail pass
* Courtesy of Pratta

30.5 TROUBLESHOOTING

Please refer to Appendix 1 for a troubleshooting guide.

30.6 INDUSTRY STANDARD SPECIFICATION GUIDELINES

These specification guidelines have been compiled to establish and standardize achievable
solder thickness requirements and measurement techniques. All information, requirements, and
techniques given are based on the results of extensive testing and production through the
component assembly process. The coating of eutectic solder (Sn63) was applied on copper
surfaces of the printed wiring board using the Unicote® horizontal process for the evaluations.

30.6.1 Terminology

The following definitions are to clarify terms used in these guidelines:

Mean Average thickness for a given number of thickness readings

Crest Highest point for a given feature (pad)

Center Middle of a feature (pad); some geometries will have crests at the
center, some may not

Data group Data collected to show thickness deviation within a single feature size or
different feature sizes at given measurement locations

Coplanarity Levelness from pad to pad over entire board, or within certain feature
size groups
Measure the crests of all features as one data group. Measure the
centers (minimum) of all features as your second data group. Do
not mix data groups. This will show two planes
 Uniformity Levelness from pad to pad within a single feature
Measure one geometry only (i.e.: all 0.025 in (0.64 mm) pitch quad
flat packs (QFPs). Measure crests in one data group. Measure
centers (minimum) in a separate data group. Note that for QFPs,
measure North, East, South, West in rotation or patterns North,
South, East West to show any directional dependency. Do not mix
data groups. Repeat procedure for each geometry required by
customer. If only one geometry is measured, it will be the most
critical feature.

Distribution Levelness within a pad

To determine the range of solder thickness over a feature (pad), a
minimum of five points should be measured over the feature.
Distance to edge of pad should be 0.010 in (0.25 mm) minimum.
The number of data points required will usually be determined by
the end user, but a minimum of 24 data points per data group is
recommended.

TABLE 30.7 SIR after HAL

Hours 24 hours Hours 24 hours

3 3
A l&2 4.7 x 10 E l&2 8.0 x10
3 3
2&3 4.3 x 10 2&3 7.2 x 10
3 3
3&4 5.0 x 10 3&4 8.4 x 10
3 3
4&5 4.0 × 10 4&5 8.4 x 10

3 4
B l&2 5.1 x 10 F l&2 1.1 × 10
3 4
2&3 4.4 × 10 2&3 1.5 ×10
3 4
3&4 5.0 × 10 3&4 1.3 x 10
3 4
4&5 5.9 x 10 4&5 1.6 × 10

3 4
C l&2 6.0 x 10 G l&2 1.5 x 10
3 4
2&3 6.0 x 10 2&3 1.4 x 10
3 4
3&4 5.5 x 10 3&4 1.6 x 10
3 3
4&5 5.4 × 10 4&5 1.2 ×10

3 4
D l&2 6.2 x 10 H l&2 1.0 x 10
3 3
2&3 6.4 x 10 2&3 7.6 x 10
3 3
3&4 5.0 × 10 3&4 5.2 x 10
3 3
4&5 5.6 × 10 4&5 7.8 x 10
30.6.2 Process Variables

Copper surface The copper surface must be clean, free of organic contaminates, and
oxidation that restrict solder distribution within a feature or prevent solder from adhering to
the copper (see Secs. 30.3.1 and 30.4.1). Other metal surfaces to be soldered have the
same requirements; however, they are not covered in this document.

Feature geometry The geometry of a feature will affect the thickness results at a given setup.
Large features tend to be thinner than small features on the same side of the panel.

30.6.3 Equipment and Setup

Grouping data The most meaningful data is obtained when it is grouped, usually by geometry
and measurement location. When establishing process control and checking machine setup,
only one feature size should be measured per data group. This method of grouping will
provide thickness results that relate to assembly placement by component [i.e. 0.025 in
(0.64 mm) pitch QFPs versus 0.100 in (2.54 mm) pitch or 1206 chip sites]. This also
allows the tightest uniformity control when setting up the equipment and establishing process
control. Using this method, a three sigma process can be accomplished as discussed later.

• Other methods of grouping data can be meaningful tools for gathering information or
confirming ranges like entire panel coplanarity. However, it is important that the value of
these be understood and used as inspection tools rather than setup and control
procedures. Because this is a geometrically dependent process, combined data will
have a larger process window and will vary with board technology.

30.6.4 Most Critical Feature

The most critical feature, usually defined by the end user, represents the feature with the tightest
solder thickness requirement. This is usually the finest pitch or smallest SMD feature on the
panel, and it has a tight tolerance at assembly. The most critical feature will be used for
establishing the thickness and uniformity as described previously. Remaining features may be
thinner or thicker, depending on panel geometry, feature size, and orientation on card.

30.6.5 Method of Measurement

Measurements are typically taken using X-ray fluorescence (XRF) equipment. There are many
XRF equipment manufacturers, and each instrument has specific, unique features. We will
discuss general requirements here, and all examples will be based on the Seiko XRF Model
STX 3000.
The goal is for the collimator diameter or width to be less than one-half of the pad width.
Measurement times will vary with equipment manufacturer and thickness of calibration range. It
is important to test and gain confidence in the equipment used. Measurements taken outside the
calibration thickness range will result in false readings.

Panel orientation is important, especially for fine-pitch QFP features. Many XRF units are
capable of measuring small features in only one direction. When measuring small features (i.e.
0.020 in [0.51 mm] pitch and finer), compare east/west measurements with north/south
measurements. Rotate panel 90° and repeat measurements. Monitor for differences in result. If
a large difference is detected, the accuracy of one direction should be verified by cross section
and panel rotated as necessary for accuracy. Collimator size is important, especially on small
features (Table 30.8). The larger collimators are more accurate at shorter measurement times.
The larger the collimator, the larger the sample area. However, it is important to ensure that the
collimator (or sample area) does not extend beyond the area to be measured. Alignment
accuracy of machine and operator must be considered. The feature must be focused properly in
the z-axis to ensure accuracy. If these conditions are not met, the accuracy is greatly
compensated.

TABLE 30.8 Typical Collimators Used

Feature size Collimator

>0.025 in (0.64 mm) 0.008 in (0.20 mm) circular
0.015 to 0.025 in (0.33 to 0.64 mm) 0.004 in (0.10 mm) circular
0.005 to 0.015 in (0.13 to 0.38 mm) 0.001 x 0.016 in (0.02 mm × 0.41 mm) rectangular

Measurement times are determined by collimator size, thickness range, and calibration. It is
important that the proper calibration is used for the thickness range being measured. Calibration
curves should be reviewed to determine the best one for the product. Many XRF models
calculate the suggested times for accuracy. As a rule, the smaller the collimator, the longer the
measurement time. Typical times will range between 10 to 30 seconds. Inadequate
measurement times will result in false readings.

30.6.6 Thickness Capability Specification

If the criteria for measuring uniformity and most critical feature is followed, then a process
window of 70 µin (1.75µm) minimum and 800 µin (20 µm) maximum at crests on surface
features is achievable on standard SMT panels. For 20 mil (0.5 mm) pitch and greater, panels
were processed through both the HSL-175 and HSL-350. For panels with less than 20 mil
pitch, panels were processed through HSL-175 (Table 30.9).

Critical feature. For 0.020 in (0.5 mm) pitch or greater QFP geometries, a nominal thickness
of 250 to 500 µin (6.25 to 12.5 µm) with 3 sigma deviation is achievable.

For 0.015 in (0.4 mm) pitch and small QFP geometries, a nominal thickness specification will
vary by customer assembly practices. Ranges we have run successfully to date include the
following:

TABLE 30.9 Process Windows at Crest (Panel Uniformity)

1. 20 mil (0.5 mm) pitch 70 to 800 µin (1.75 to 30 µm)

2. 15 mil (0.4 mm) pitch 70 to 1500 µin (1.75 to 37.5 µm)
3 sigma deviation Mean ± [(3) (std. dev.)] = window range

1. Mean thickness 400 to 600 µin (10 to 15 µm)

3 sigma minimum of 100 µin (2.5 µm)
3 sigma maximum of 1000 µin (25 µm)

2. Mean thickness 500 to 800 µin (12.5 to 20 µm)

3 sigma minimum of 200 µin (5 µm)
3 sigma maximum of 1200 µin (30 µm)

Other features Chip sizes up to Standard 1206

Crest measurement: Mean average between 100-600 µin (2.5-15.0 µm)

Minimum average at center: HSL-350: 30 µin (0.75 µm)
HSL-175: 70 µin (1.75 µm)

Other features Plated holes

Maximum hole reduction 0.003 in (0.76 mm) max.
from copper: 0.001-0.002 in (0.025-0.051 mm) typical

30.6.7 Intermetallic Compounds

Intermetallic compound (IMC) growth can be minimized, depending on process parameters

used. Typical IMC growth is 6 to 12 µin (0.152 to 0.30 µm) average.

30.7 EFFECTS OF CONTAMINANTS IN EUTECTIC SOLDER

Soldering processes, by nature, are considered complicated and involved due to the various
factors that must be maintained and monitored. Most of these factors are indigenous to the
process, such as pot temperature, dwell times, and contamination levels. Items such as
temperature and dwell times are readily measured, adjusted, and understood, making them
some of the more comfortable aspects of the soldering process. Solder contamination, on the
other hand, tends to be a less understood phenomenon. To accurately determine trace
contamination levels in solder requires very specific analytical equipment and precise analytical
methods. Most solder suppliers provide multi-element analysis beyond tin, lead, and copper.
Once levels of contaminants have been determined, interpretation of these results may require
assistance based on your particular problem.

Typically, copper contamination and tin concentration were targeted as the gauges of the
relative health of a solder bath. This was born of the fact that varying levels of other trace
contaminants were considered normal and, as they could not be removed anyway, would not be
productive in terms of process impact. With the advent of electrolytic-grade solders, there is
now a need to better understand the potential effects of these trace contaminants on solder
performance.

30.7.1 Copper

Copper, being the most typical contaminant, is probably the best understood in soldering
circles. Manifesting itself as an intermetallic along with tin, it is necessary to deal with it. A
normal by-product of the formation of the solder bond on the board surface, it migrates
outward from the board into the solder pot, where it typically becomes soluble and
homogeneous. There are two forms of this material, Cu3Sn and CusSn6, of which the latter is
more prevalent. There will come a point in the lifetime of any solder bath where the solubility of
the copper/tin intermetallic will be at or near the saturation point. Boards processed under these
conditions [approximately 0.30 percent by weight at 470°F (243°C)] will show a pronounced
gritty appearance. The reason for this is that the intermetallic, being less dense than molten
tin/lead, will migrate to the top of the deposit where the characteristic dendritic crystalline
structure will create the gritty surface.

This poses a problem, both in terms of esthetics and in solderability. The presence of a
concentrated copper in the relatively small volume of solder located on a pad will raise the
thermal demand requirement on a local level, compromising the reflow characteristics of the
solder deposit.

30.7.2 Gold

Gold is another typical contaminant of a solder bath if it is being used to process boards that
have been previously tab plated. AuSn4 is another intermetallic that will form if solder is allowed
to contact gold-plated surfaces. Utmost caution must be taken to avoid this occurrence,
because gold is approximately six times more soluble than copper and can be even more
detrimental to the solder joint. Gold contamination will be visible as a frostiness of the solder
deposit with an accompanying embrittlement of the solder joint. A joint produced under these
conditions can be prone to failure under thermal cycling or high vibration environments.
Adequate protection of the gold from solder contact or elimination of pre-gold plating are the
keys to controlling gold contamination. It can not be removed by any user-available methods--
only by sophisticated metal treatment systems or solder bath replacement.
30.7.3 Tin

Variation of tin concentration can have a pronounced effect on solder performance, but there is
a reasonable window in which to operate that is not difficult to maintain. Typically, most
processes will run well between 61.5 and 63.5 percent tin concentrations. The danger in running
above or below this range is the change in melting points and subsequent variation in surface
tension characteristics. Surface mount processing poses particular problems primarily in that
surfaces devoid of a hole demonstrate low surface-energy characteristics. As such, they resist
the efforts of fluxes and solder to achieve lower free-energy states and wet the copper surface.
Sufficient deviation from the eutectic alloy ratio can affect later reflow performance in high-
speed, low-temperature soldering applications.

An important factor to consider when examining the soldering of a board or a given area is that,
although a pot might exceed the melting point of the solder deposit, there is a heat sink effect of
the board and flux that will lower the overall amount of energy transferred to the board,
decreasing the ability to melt the solder deposit. The physical scale we are dealing with in terms
of thermodynamics is small enough to deviate from what we would consider correct and to
force us to reevaluate our way of troubleshooting and investigating problems.

30.7.4 Antimony

The element antimony as an intentional addition to solder alloys has become the subject of much
debate. The rationale behind the addition is prevention of tin decomposition. This
decomposition, commonly referred to as tin pest, is in actuality a phenomenon associated with
pure tin rather than its alloys. In fact, any significant level of contamination of tin will inhibit the
allotropic transformation of beta-phase tin to alpha-phase tin. Antimony was initially chosen
because it was not known at the time to adversely affect the soldering process.

The soldering technology of that time did not include the manufacturing of printed circuit boards
and did not anticipate stricter technical requirements. Today, we know that antimony has a
pronounced effect on the wetting function of solders onto copper. Previously, specifications
indicated that levels up to and including 0.50 percent by weight were allowable but, with the
advent of SMT, negative effects on wetting are being noted at significantly lower levels. Again,
surface tension and flee surface energy criteria are illuminating deficiencies in established norms
of material specification. Revisions of the specifications for incoming material purchases are
being modified to allow the stricter requirements of this new technology to be satisfied.

30.7.5 Trace Materials

Up to this point, we have examined the effects of contaminants typical to the soldering process
as either a natural by-product or as an intentional addition. We will now turn our attention to
elements that are indigenous to the solder material itself by virtue of the procedures used to
produce it. As tin and lead are products of ore-refining procedures, there are bound to be
varying levels of trace or residual materials in the finished solder product. These trace
contaminants have the potential to disrupt the soldering process, depending on which ones are
present and in what quantity.

One group of elements that pose a problem consists of aluminum (A1), cadmium (Cd), and zinc
(Zn). These elements exhibit common characteristics in that they all increase the amount of
drossing of the solder by contributing to the accelerated oxidation of the tin component. Not
only oxidation, but dewetting, grittiness, and dull or frosty solder deposits result from the
presence of any of these materials.

30.7.5.1 Iron and nickel. Iron and nickel are similar in that they both can cause a
deterioration of the solder deposit that is akin to that of copper contamination. Both of these
materials are surface active so that a grittiness and dullness of the solder will result if these
materials are present in sufficient quantity.

Additionally, like copper, these materials can be removed from the functioning solder pot to a
limited degree. This is accomplished by cooling the solder pot to near eutectic temperatures and
allowing the low-density intermetallic to rise to the surface of the solder pot.

30.7.5.2 Silver. Silver, like gold, produces a dullness on the solder deposit that will rapidly
change to a sluggish cold appearance if allowed to reach high concentration levels.

30.7.5.3 Arsenic and phosphorous. Arsenic and phosphorous are grouped together due to
their similar effects on wetting. Relatively small amounts of these materials will significantly
increase the time required to establish a sound solder joint and will compromise the integrity of
the copper-to-solder adherence.

30.7.5.4 Sulfur. Sulfur is possibly the most critical of the contaminants, as it is chemically
reactive with both the tin and lead components of solder and has the ability to degrade wetting
severely at only parts per million levels. Every effort should be made to avoid this contaminant,
which is best accomplished by stringent checks on incoming material quality.

30.7.5.5 Bismuth and indium. Bismuth and indium are both common contaminants that are
not typically associated with any particular negative impact on soldering or solderability. In fact,
these materials have been intentionally added to solder used in touch-up and repair applications,
as they can assist in wetting and will allow for low-temperature soldering. However, caution
must be observed in considering these special formulations for mass soldering applications. The
benefits of these materials can be realized only in small-site applications, as there is a significant
degree of brittleness associated with these joints, which would not be acceptable in mass circuit
board applications.

30.7.5.6 Stand-alone contaminants. Bismuth and indium are the last elements discussed, for
an important reason. As indicated, no negative aspects regarding soldering and solderability are
associated with them. But this applies only when each is considered as a stand-alone
contaminant.

Provided that bismuth is the only contaminant present, and all other factors are nominal, there
should not be any soldering problems. In the presence, e.g., of zinc, the situation may change
radically. Intrude copper now, and the situation will deteriorate further. The point here is that
combinations of any of the materials will have unpredictable results. Some combinations will be
more benign than others, but the fact still exists that there is no guide or reference that can assist
in knowing what combinations in what ratios are acceptable.

For this reason, it is advisable to minimize trace materials and promote process controls that
allow for control of the levels of materials that are natural and yet detrimental to the process.

Table 30.10 provides a listing of elements and prudent limits on contaminants based on the
quality of available solder. These limits will be reflected for both incoming materials and process
operation.

TABLE 30.10 Solder Contamination Limits*

Element Incoming material In-process
specifications specifications
Copper (Cu) 0.001 0.300
Iron (Fe) 0.002 0.004
Silver (Ag) 0.0005 0.010
Antimony (Sb) 0.01 0.100
Arsenic (As) 0.005 0.020
Bismuth (Bi) 0.002 0.010
Cadmium (Cd) 0.0005 0.002
Nickel (Ni) 0.001 0.005
Gold (Au) 0.0005 0.045
Aluminum (AI) 0.0005 0.002
Indium (In) 0.002 0.010
Zinc (Zn) 0.0005 0.003
Sulfur (S) 0.001
Tin (Sn) 63.3 62.8-63.5
*All values are in percent by weight. Lead in balance.

ACKNOWLEDGMENTS

The author would like to extend thanks to the following individuals:

John Adams, Quality Assurance Manager, Altron, 1 Jewel Drive, Wilmington, MA

 01887-3390
Jack Fellman, R&D Director, Pratta Electronic Materials, Inc., 111 Zachary Road,
Manchester, NH 03109
Joe Webb, Applications Development Manager, Dexter Electronic Materials, 144 Harvey
Road, Manchester, NH 03103
Brian Raymond, Process Engineer, Hadco Derry, Manchester Road, Route 28,
Derry, NH 03038
Martin W. Jawitz, Editor in Chief, and McGraw-Hill, Publisher, “Printed Circuit Board
Materials Handbook”, 1997.
 APPENDIX 1
TROUBLESHOOTING GUIDE

Problem Cause Corrective Action

Snow Lack of Lubricity 1. Increase oil circulation

(solder smear) 2. Check solder flow
3. Check solder agitation
4. Change flux
5. Reduce preheat
6. Decrease air pressure
7. Check solder mask cure
8. Reduce solder dwell

Dirt/mud Lack of lubricity 1. Same as snow

Dirty oil 1. Change oil

2. Clean parts in contact with oil

Thin solder Excessive air pressure 1. Decrease air pressure

(swept look)

Contaminated copper 1. Check etch rate

2. Check for proper rinse
3. Check dryer
4. Check spray nozzles
5. Do oxide test (Fig. 30.4)
6. Check for solder mask
7. Check for incomplete solder
stripping
8. Decrease preheat
9. Increase dwell time
10. Use more active flux

Reduce air knife orifice 1. Clean air knife orifice

2. Repair or replace air knife if
worn

Mixed geometries on 1. Reference Specification

panel Guidelines, Sec. 30.7

Thick solder Insufficient air pressure 1. Increase air pressure

 Air knife orifice too wide 1. Repair or replace air knife
or worn

Air leak in air hose or 1. Replace hoses and tighten or

connection replace connections as needed

Partially blocked air knife 1. Clean air knife orifice

Scratches on Mechanical contact with 1. Isolate unit causing scratches,

panel panel remove and/or repair problem
area

Broken link(s) or burrs on 1. Inspect belts and conveyors for

mesh conveyor belts damage, replace or repair as
required

Handling 1. Instruct operators on correct

handling techniques

Cold solder Insufficient heat 1. Check preheat, increase if needed

2. Check solder flow, increase as
needed
3. Check air/air knife temperature
(425°F [218°C] typical)
4. Check solder temperature
(450°F-500°F [232°C-260°C]
typical)

Excessive solder contami- 1. Check solder analysis, maximum

nation copper allowed typically is 0.3%
(see Sec. 30.7)
2. Skim, dump, or dilute solder in
pot to reduce contaminant level

Touch marks Insufficient cool-down time 1. Increase cool-down time after air
on solder knife and before postclean
2. Check alignment and nip line for
mechanical contact with panel
after the air knife and before the
postclean wash

Exposed copper Insufficient preclean 1. Check etch rate

 2. Check rinse chambers; clean bath,
clean nozzles, bath levels, and/or
spray pressure

Excessive preheat 1. Reduce surface temperature of

panel during preheat

Flux 1. Replenish or replace old spent

flux with fresh flux
2. Replace with lower viscosity
and/or higher acid flux (see Sec.
30.4.3)

Contaminated oil 1. Replace oil

Low solder flow 1. Increase per manufacturer's

instructions

Low flow in fluxer 1. Increase flow or level in fluxer

per manufacturer's instructions

Contamination on copper 1. Inspect for visible contamination

surface using 10x or 30x magnification
2. Using cupric chloride test (Fig.
30.4) or black oxide, test for
contamination
3. Identify source and clean copper
surface

Dewetting Contaminated copper 1. Check etch rate

2. Check for proper rinse
3. Check dryer
4. Check spray nozzles
5. Do oxide test (Fig. 30.4)
6. Check for solder mask
7. Check for incomplete solder
stripping
8. Decrease preheat
9. Increase dwell time
10. Use more active flux

High organics in copper 1. Check copper plating parameters

from plating