Lecture (05)

Arithmatic /logic
operations and flags
By:
Dr. Ahmed ElShafee

1 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

Format of DOS programs
• All programs must have a code and a stack.
– Code is the part of the program that contains the instructions of the
program.
– Stack is an area in the RAM used by the system to store return
addresses, and by the programmer to store temporarily data. It is a Last
In First Out (LIFO) buffer.
• Programs can also have a data area, where all data (variables) is
stored.
• There are two basic types of programs:
– Commands (.COM). The data and the stack of the program are part of
the Code segment. The stack is always located at the end of the
segment. The first 256 bytes of the segment are reserved.
– Executable (.EXE). The code and stack and data of the program are
located in different segments.
2 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
Format of the .COM programs
.MODEL SMALL
CSEG SEGMENT PARA 'CODE’ ;Start a Code segment
ASSUME CS:CSEG, DS:CSEG, SS:CSEG
ORG 100H ;Reserve first 256 locations
START: JMP MAIN ;Skip data area
{Place the data of the program here}
MAIN PROC NEAR ;Beginning of main procedure
{Place the code of the
program here}
RET ;Get return DOS address
MAIN ENDP ;End of main procedure
CSEG ENDS ;End of the segment
END START ;End of the program
3 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
Format of the .COM programs
.MODEL SMALL
.CODE
ORG 100H ;Reserve first 256 locations
START: JMP MAIN ;Skip data area
{Place the data of the program here}
MAIN PROC NEAR ;Beginning of main procedure

{Place the code of the

program here}

RET ;Get return DOS address

MAIN ENDP ;End of main procedure
END START ;End of the program
4 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
Example 01; hello world; masm
CSEG SEGMENT PARA ‘CODE’ ;Start a Code segment
ASSUME CS:CSEG, DS:CSEG, SS:CSEG
ORG 100H ;Reserve first 256 locations
START: JMP MAIN ;Skip data area
MSG DB "Hello World 01",'$‘
MAIN PROC NEAR ;Beginning of main procedure
LEA DX,MSG
MOV AH,9
INT 21H
INT 20H
RET
MAIN ENDP ;End of main procedure
CSEG ENDS ;End of the segment
END START ;End of the program

5 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

Example 02; hello world; masm
.MODEL SMALL
.CODE
ORG 100H ;Reserve first 256 locations
START: JMP MAIN ;Skip data area
MSG DB "Hello World 01",'$‘
MAIN PROC NEAR ;Beginning of main procedure
LEA DX,MSG
MOV AH,9
INT 21H
INT 20H
RET
MAIN ENDP ;End of main procedure
END START ;End of the program

6 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

7 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
Compiling and linking
Masm 01.asm
ML –AT 01.obj

01.com

8 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

•

9 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

The Flag Register
31 21 20 19 18 17 16 14 13 12 11 10 9 8 7 6 4 2 0
IOP IOP
ID VIP VIF AC VM RF NT O D I T S Z A P C
1 0

8088/8086
80286
80386
80486
Pentium

• A (Auxiliary) [half carry]

• C (carry): [result exceeds the size of destination]
• O (overflow): [something went wrong]
• P (Parity) [even number of ones]
• S (sign): [MSB =1]
• Z (zero): [==0]
Carry Flag
• 1. The carry flag is set if the addition of two numbers causes a
carry out of the most significant (leftmost) bits added.
• 1111 + 0001 = 0000 (carry flag is turned on)
• 2. The carry (borrow) flag is also set if the subtraction of two
numbers requires a borrow into the most significant
(leftmost) bits subtracted.
• 0000 - 0001 = 1111 (carry flag is turned on) Otherwise, the
carry flag is turned off (zero).

11 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

Overflow Flag
• 1. If the sum of two numbers with the sign bits off yields a
result number with the sign bit on, the "overflow" flag is
turned on.
0100 + 0100 = 1000 (overflow flag is turned on)
• 2. If the sum of two numbers with the sign bits on yields a
result number with the sign bit off, the "overflow" flag is
turned on.
1000 + 1000 = 0000
(overflow flag is turned on) Otherwise, the overflow flag is
turned off.

12 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

13 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
Arithmetic and Logic
Instructions
• Addition: (Flags affected: A,C,O,P,S,Z)
– ADD AL,BL ; AL  AL + BL , BL unchanged
• Register addressing mode
– ADD CX,DI ; CX  CX + DI , DI unchanged
• Register addressing mode
– ADD AH,45H ; AH  AH + 45H
• Immediate addressing mode
– ADD [BX],AL ; [BX]  [BX] + AL
• Register indirect addressing mode
– ADD CX,[BX] ; CX  CX + [BX]
– ADD AL,CX ; INVALID

14 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

 Add with Carry: (Flags affected: A,C,O,P,S,Z)
– ADC AH,BH ; AH  AH + BH + Carry
• Register addressing mode
– ADC AX,CX ; AX  AX + CX + Carry
• Register addressing mode
– ADC AL,[BX+SI] ; AL  AL + [BX+SI] + Carry
• Register indirect addressing mode

15 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

 Subtraction: (Flags affected: A,C,O,P,S,Z)
– SUB AL,BL ; AL  AL - BL ;BL unchanged
• Register addressing mode
– SUB CX,DI ; CX  CX - DI ;DI unchanged
• Register addressing mode
– SUB AH,45H ; AH  AH - 45H
• Immediate addressing mode
– SUB BL,ARRAY ; BL  BL - [ARRAY]
• Direct Addressing mode
– SUB [BX],AL ; [BX]  [BX] – AL
• Register indirect addressing mode
16 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
– SUB AL,CX ; INVALID
 Subtract with Borrow: (Flags affected: A,C,O,P,S,Z)
– SBB AH,BH ; AH  AH - BH – Carry
• Register addressing mode
– SBB AX,CX ; AX  AX - CX – Carry
• Register addressing mode
– SBB AL,[BX+SI] ; AL  AL - [BX+SI] – Carry
• Register indirect addressing mode

17 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

 Increment: (Flags affected: A,O,P,S,Z)
– INC AL ; AL  AL + 1
– INC SP ; SP  SP + 1
– INC COUNT1 ; [COUNT1]  [COUNT1] + 1
– INC BYTE PTR[BX] ; [BX]  [BX] + 1
– INC WORD PTR[BX] ; [BX]  [BX] + 1

18 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

Example 01
•org 100h org 100h
jmp start jmp start
db 0feh,00h db 0feh,00h
start: start:
mov bx,0102h mov bx,0102h
INC BYTE PTR[BX] INC BYTE PTR[BX]
INC BYTE PTR[BX] INC WORD PTR[BX]

ret ret

19 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

20 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
21 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
 Decrement: (Flags affected: A,O,P,S,Z)
– DEC AL ; AL  AL - 1
– DEC SP ; SP  SP - 1
– DEC COUNT1 ; [COUNT1]  [COUNT1] - 1
– DEC BYTE PTR[BX] ; [BX]  [BX] - 1
– DEC WORD PTR[BX] ; [BX]  [BX] - 1

22 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

Example 02
•org 100h org 100h
jmp start jmp start
db 001h,00h db 01h,00h
start: start:
mov bx,0102h mov bx,0102h
dec BYTE PTR[BX] dec BYTE PTR[BX]
dec BYTE PTR[BX] dec WORD PTR[BX]

ret ret

23 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

24 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
25 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
Example 03
• What will be the values of the carry, overflow, sign and zero
flags after the execution of each of the following instructions:
– MOV DX,0
– DEC DX
– MOV AX,720H
– SUB AX, 0E6H
– MOV DX,0
– DEC DX

26 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

• Instruction AX DX Flags
H L H L C Z S O
MOV DX,0
DEC DX
MOV AX,720H
SUB AX, 0E6H

27 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

• Instruction AX DX Flags
H L H L C Z S O
MOV DX,0 00 00 0 0 0 0
DEC DX FF FF 0 0 1 0
MOV AX,720H 07 20 - - - -
SUB AX, 0E6H 06 3A 0 0 0 0

28 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

 Example 04
MOV AX,847AH
Fill up the trace table given below.
SUB CX,CX
MOV BX,5CE8H CS:0108H 02
ADD AL,BH CS:0106H E8
ADC AH,BL CS:0107H 5C
MOV CL,AL Cs:010CH 8A
CS:010DH C8
ADD CH,BL
MOV SI,0108H
SUB BL,[SI]
SBB BH,[SI+4]
ADD AL,[010CH]
MOV AX,[0106H]
INC AL
DEC BX
ADD CX,[SI+4]

29 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

 AX BX CX SI Flags
Instruction
H L H L H L C Z S O
MOV AX,847AH
SUB CX,CX
MOV
• BX,5CE8H
ADD AL,BH
ADC AH,BL
MOV CL,AL
ADD CH,BL
MOV SI,0108H
SUB BL,[SI] (02)
SBB BH,[SI+4] (8A)
ADD AL,[010CH]
(8A)
MOV AX,[0106H]
(5CE8)
INC AL
DEC30 BX Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
ADD CX,[SI+4]
 AX BX CX SI Flags
Instruction
H L H C L H L Z S O
MOV AX,847AH 84 7A - - - -
SUB CX,CX 00 00 0 1 0 0
MOV BX,5CE8H 5C E8 - - - -
•
ADD AL,BH D6 0 0 1 1
ADC AH,BL 6C 1 0 0 1
MOV CL,AL D6 - - - -
ADD CH,BL E8 0 0 1 0
MOV SI,0108H 0108 - - - -
SUB BL,[SI] (02) E6 0 0 1 0
SBB BH,[SI+4] (8A) D2 1 0 1 1
ADD AL,[010CH] 60 1 0 0 1
(8A)
MOV AX,[0106H] 5C E8 - - - -
(5CE8)
INC AL E9 - 0 1 0
DEC BX D2 E5 - 0 1 0
31 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
ADD CX,[SI+4] (C88A) B1 60 1 0 1 0
32 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
• G. Multiplication: (Flags affected: C,O, (A,P,S,Z are
undefined))
Unsigned multiplication:
– MUL CL ; AX  AL * CL
– MUL CX ; DX,AX  AX * CX
– MUL BYTE PTR [BX] ; AX  AL * [BX]
– MUL WORD PTR [SI] ; DX,AX  AX * [SI]

33 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

 • Signed multiplication (2's complement):
– IMUL BL ; AX  AL * BL
– IMUL BX ; DX,AX  AX * BX
– IMUL BYTE PTR [BX] ; AX  AL * [BX]
– IMUL WORD PTR [SI] ; DX,AX  AX * [SI]

34 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

Example 05
org 100h
jmp start

start:
mov al,15h
mov cl,15h
mul cl
mov al,00h
mul cl
ret

35 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

36 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
37 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
 Division: (Flags affected: A,C,O,P,S,Z (all undefined))
Unsigned Division:
– DIV CL ; AL  Quotient of AX/CL
; AH  Remainder of AX/CL
– DIV CX ; AX  Quotient of DX,AX/CX
; DX  Remainder of DX,AX/CX

38 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

 Signed Division:
– IDIV CL ; AL  Quotient of AX/CL
; AH  Remainder of AX/CL
– IDIV CX ; AX  Quotient of DX,AX/CX
; DX  Remainder of DX,AX/CX

39 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

• In short, the carry flag is used to indicate that an arithmetic
operation has resulted in a carry out of the most significant
bit. This means that the operation has produced an unsigned
result that is too large to be represented in the given number
of bits. For example, if you’re adding two 8-bit numbers and
the result is 9-bits, the carry flag will be set.
• The overflow flag, on the other hand, is used to indicate that
an arithmetic operation has resulted in a signed number that
is too small or too big to be represented in the given number
of bits. Hence, we can call a carry flag the inverse of an
overflow flag.

40 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

Example 06
org 100h
jmp start

start:
mov ax,1234h
mov cl,15h
div cl
mov ax,0000h
div cl
ret

41 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

•

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43 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
Example 07
org 100h
Fill up the trace table given below.
MOV AX,42C1H
SUB DX,DX
MOV BX,2456H
MUL BL
MUL BX
MOV AX,0A42H
MOV CH,32H
DIV CH
MOV SI,0103H
MUL BYTE PTR [SI]
MOV AX,[0109H]
MUL AH
MOV BL,0F0
DIV BL
ret
44 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
 AX BX CX DX Flags
Instruction SI
H L H L H L H L C Z S O
MOV AX,42C1H
SUB DX,DX
MOV BX,2456H
MUL •BL
MUL BX
MOV
AX,0A42H
MOV CH,32H
DIV CH
MOV SI,0103H
MUL BYTE PTR
[SI] (2B)
MOV
AX,[0109H]
(F7E3)
MUL AH
MOV BL,0F0H
DIV BL
45 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
 AX BX CX DX Flags
Instruction SI
H L H L H L H L C Z S O
MOV AX,42C1H 42 C1
SUB DX,DX 00 00 0 1 0 0
MOV BX,2456H 24 56
MUL •BL 40 D6 1 1
MUL BX DF E4 09 33 1 1
MOV
0A 42
AX,0A42H
MOV CH,32H 32
DIV CH 1A 34
MOV SI,0103H 103
MUL BYTE PTR
08 BC 1 1
[SI] (2B)
MOV
AX,[0109H] F7 E3
(F7E3)
MUL AH DB 05 1 1
MOV BL,0F0H F0
DIV BL 95 D9
46 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
 BCD and ASCII Arithmetic:
– DAA ; Decimal Adjust for Addition
– DAS ; Decimal Adjust for Subtraction
– AAA ; ASCII Adjust for Addition
– AAS ; ASCII Adjust for Subtraction
– AAM ; ASCII Adjust for Multiplication
– AAD ; ASCII Adjust for Division

47 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

Example 08
org 100h
mov al,08
mov bl,07
add al,bl
daTa
mov al,08
mov bl,07
add al,bl
aaa
ret

48 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

49 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
 C U Next Week,…

50 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1