Lecture (04)

By:
Dr. Ahmed ElShafee

1 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

Segmentation
• Segmentation is used to allow
relocation of programs, i.e.
programs can be loaded on
different memory areas and still
run correctly.
• Segmentation is used in the
8088/8086 microprocessors to
allow the generation of 20-bit
addresses using 16-bit registers.

2 Dr. Ahmed ElShafee, NileU : Fall 2022, Microprocessor System Design

• In the Real Mode Operation a 20-bit
address (effective address) is
obtained by shifting the segment
address 4 bits to the left (X10H) and
then adding the offset address
• The offset address is specified in the
program. The segment address is
specified by the operating system
whenever the program is loaded.
• The code segment holds the machine
codes of the program. The
Instruction Pointer specifies the
3
offset address in the code segment.
Dr. Ahmed ElShafee, NileU : Fall 2022, Microprocessor System Design
• The data segment holds the data
used by the program. Most data
references are specified in the data
segment.
• The stack segment holds the stack of
the program. The offset address in
the stack segment is specified with
the registers SP and BP.
• The extra segment is used as a data
segment by some data movement
instructions.
4 Dr. Ahmed ElShafee, NileU : Fall 2022, Microprocessor System Design
Example
If DS =1600H find the maximum area occupied by
the data segment. Find also the effective address, if
the offset address is 1F00H.

5 Dr. Ahmed ElShafee, NileU : Fall 2022, Microprocessor System Design

Solution
Starting address = DS X 10H = 1600H X 10H
= 16000H
Ending address = Starting address + FFFF
= 16000H + FFFFH = 25FFFH
Effective address = Segment:Offset = 1600:1F00
= Segment address X 10H + Offset
= 1600H X 10H + 1F00H
= 16000H + 1F00H = 17F00H

6 Dr. Ahmed ElShafee, NileU : Fall 2022, Microprocessor System Design

The Memory Map of a Personal
Computers
• Transient Program Area (TPA): Holds
the operating system (interrupt
vectors, DOS BIOS, devices drivers,
Command.com) and application
programs.

7 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

• System Area: Holds the ROM BIOS,
the video buffer area, and the BASIC
language ROM.

8 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

• Extended Memory: Memory above
the 1M conventional memory found
in AT compatible computers . Its size
depends on the RAM installed on the
motherboard, and is limited by the
size of the processor’s address bus.

9 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

Addressing Modes
• Addressing mode refers to the way the data needed by
an instruction is specified.

10 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

 %eax

Moving Data: IA32 %ecx

• Moving Data %edx

• mov Des, src:
%ebx

• Operand Types %esi

– Immediate: Constant integer data %edi
• Example: 0x400, -533
%esp
– Register: One of 8 integer registers
• Example: eax, edx %ebp

• But esp and ebp reserved for special use

• Others have special uses for particular instructions
– Memory: 4 consecutive bytes of memory at address given by register
• Simplest example: ([eax])
• Various other “address modes”

11 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

mov Operand Combinations
• operand Src C Analog
Src,Dest

Reg mov eax, 0x4 temp = 0x4;

Imm
Mem mov [eax], -147 *p = -147;

Reg Mov edx, eax temp2 = temp1;

mov Reg
Mem mov [edx], eax *p = temp;

Mem mem Mov edx,offset var temp = var;

Reg Mov edx, [eax] temp = *p;
Direct – reg indirect
Cannot do memory-memory transfer with a single instruction

12 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

int _tmain(int argc, _TCHAR* argv[]) printf("x1=%d\n",x1);
{ printf("x2=%d\n\n",x2); Example
unsigned int printf("y1=%d\n",y1); 05
x1,x2,x3,y1,y2,y3,z1,z2,z3,address_z3; printf("y2=%d\n\n",y2);
y1=147; printf("z1=%d\n",z1);
•
y2=258; printf("z2=%d\n",z2);
z1=741; printf("z3::0x%x:%d\n\n",address_z3,z3);
_asm printf("Press any key to continue,...");
{ char ch = getch();
//immediate addressing mode return 0;
mov eax,123 }
mov x1, eax// just to print
mov x2,456
// reg trans mode
mov eax, y1
mov y2, eax
// mem trans mode
mov eax, z1
mov z2,eax

lea ebx,z3
mov address_z3,ebx
mov edx,789
mov 13
[ebx],edx Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
}
Simple Memory Addressing Modes
•
• Normal (R) Mem[Reg[R]]
– Register R specifies memory address

mov eax, [ecx]

• Displacement D(R) Mem[Reg[R]+D]

– Register R specifies start of memory region
– Constant displacement D specifies offset

mov edx, 8[ebp]

14 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

int _tmain(int argc, _TCHAR* argv[])
{ Example
unsigned int src_arr[4]={12,34,56,78}; 06
unsigned int x1,x2,x3,x4;
unsigned int des_arr[4]; mov edx,x1
_asm• mov 12[ebx],edx
{ }
lea ebx,src_arr printf("x1=%d\n",x1);
mov edx,[ebx] printf("x2=%d\n",x2);
mov x1,edx printf("x3=%d\n",x3);
mov edx,4[ebx] printf("x4=%d\n",x4);
mov x2,edx printf("des_arr[0]=%d\n",des_arr[0]);
mov edx,8[ebx] printf("des_arr[1]=%d\n",des_arr[1]);
mov x3,edx printf("des_arr[2]=%d\n",des_arr[2]);
mov edx,12[ebx] printf("des_arr[3]=%d\n",des_arr[3]);
mov x4,edx printf("Press any key to continue,...");
char ch = getch();
lea ebx,des_arr return 0;
mov edx,x4 }
mov [ebx],edx
mov edx,x3
mov 4[ebx],edx
mov edx,x2
mov 8[ebx],edx
15 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
1> Immediate Addressing Mode
• The data needed is specified as a number in the machine
code of a program. The data is specified by the
programmer:
– as a numeric operand in the instruction,
e.g. MOV AL,87H ;AL  87H
MOV CX,34A6H ;CX  34A6H
MOV BL,8C2H ;Invalid (Data Mismatch)

– or as a label. The actual value is determined by the assembler.

e.g. MOV BX,OFFSET VAL3 ;BX  Address of VAL3
MOV AH,CON1 ;AH  CON1
16 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
Example 07
org 100h

jmp start
VAL1 EQU 39H
VAL2 DB 37
start:
nop
MOV BX,OFFSET VAL2
MOV AH,VAL1
END start

17 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

18 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
Example 08
ORG 100H
STRT: JMP MAIN
CON1 EQU 6CH
CON2 EQU 245AH
DAT1 DB 2FH,48H
DAT2 DB 4 DUP (0)
DAT3 DW 37AH
MAIN PROC NEAR
MOV SI,2310H
MOV BX,OFFSET DAT1
MOV AL,CON1
MOV CX,CON2
MOV AX,283CH
MOV AX,OFFSET DAT3
ENDP MAIN
19 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
END start
ORG 100H Label Address Data
STRT: JMP MAIN
CON1 EQU 6CH
CON2 EQU 245AH
DAT1
• DB 2FH,48H
DAT2 DB 4 DUP (0)
DAT3 DW 37AH

AX BX CX
SI
MAIN PROC NEAR AH AL BH BL CH CL
MOV SI,2310H
MOV BX,OFFSET DAT1
MOV AL,CON1
MOV CX,CON2
MOV AX,283CH
MOV AX,OFFSET DAT3
ENDP MAIN
20
END start Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
ORG 100H Label Address Data
STRT: JMP MAIN start 0100-0101 CODE
CON1 EQU 6CH DAT1 0102-0103 2F48
CON2 EQU 245AH DAT2 0104-0107 00000000
• DB 2FH,48H
DAT1 DAT3 0108-0109 7A03
DAT2 DB 4 DUP (0)
DAT3 DW 37AH

AX BX CX
SI
MAIN PROC NEAR AH AL BH BL CH CL
MOV SI,2310H NC NC NC NC NC NC 2310
MOV BX,OFFSET DAT1 NC NC 01 02 NC NC NC
MOV AL,CON1 6C
MOV CX,CON2 24 5A
MOV AX,283CH 28 3C
MOV AX,OFFSET DAT3 01 08
ENDP MAIN
21 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
END start
22 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
2> Register Addressing Mode
• Both of the operands are the contents of registers.
e.g. MOV AL,BH ;AL  BH
MOV BX,CX ;BX  CX
MOV AX,DL ;Invalid (Data Mismatch)

23 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

Example 09
ORG 100H MOV BX,CX
STRT: JMP MAIN MOV AL,DH
DATA1 DW 3620H MOV CX,AX
DATA2 DW 0EEA5H MOV AH,AL
DATA3 DW 9089H MOV SI,DX
DATA4 DW 73F6H ENDP MAIN
DATA5 DW 2006H END start
MAIN PROC NEAR
MOV AX,DATA1
MOV BX,DATA2
MOV CX,DATA3
MOV DX,DATA4
MOV SI,DATA5

24 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

•

AX BX CX DX
SI
AH AL BH BL CH CL DH DL
MAIN PROC NEAR 36 20 EE A5 90 89 73 F6 2006
MOV BX,CX
MOV AL,DH
MOV CX,AX
MOV AH,AL
MOV SI,DX

25 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

 DATA1 DW 3620H
DATA2 DW 0EEA5H
DATA3 DW 9089H
DATA4 DW 73F6H
DATA5 DW 2006H

AX BX CX DX
SI
AH AL BH BL CH CL DH DL
MAIN PROC NEAR 36 20 EE A5 90 89 73 F6 2006
MOV BX,CX 90 89
MOV AL,DH 36 73
MOV CX,AX 36 73
MOV AH,AL 73
MOV SI,DX 73F6

26 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

27 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
3> Memory Direct Addressing
Mode
• One of the operands is the contents of the memory location that is
specified directly in the instruction.
e.g. MOV AL,[1008H] ;AL  [1008H]
MOV BX,VALUE ;BX  [VALUE]

28 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

Example 10
ORG 100H
STRT: JMP MAIN
DB ?
FRST DB 0C1H
VAL1 DW 8756H
ARR1 DB 9FH,0A6H,75H,8CH
MAIN PROC NEAR
MOV AL,[0104H]
MOV BX,[0108H]
MOV CH,FRST
MOV DX,VAL1
MOV AH,ARR1
MOV CL,ARR1+3
ENDP MAIN
END start
29 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
ORG• 100H Label Address Data
STRT: JMP MAIN FRST 0103
DB ? VAL1 0104
FRST DB 0C1H 0105
VAL1 DW 8756H ARR1 0106
ARR1 DB 9FH,0A6H,75H,8CH 0107
0108
0109

30 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

•ORG 100H Label Address Data
STRT: JMP MAIN FRST 0103 C1
DB ? VAL1 0104 56
FRST DB 0C1H 0105 87
VAL1 DW 8756H ARR1 0106 9F
ARR1 DB 9FH,0A6H,75H,8CH 0107 A6
0108 75
0109 8C

31 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

 Label Address Data
FRST 0103 C1
VAL1 0104 56
0105 87
• ARR1 0106 9F
0107 A6
0108 75
0109 8C

AX BX CX DX
SI
MAIN PROC NEAR AH AL BH BL CH CL CH CL
MOV AL,[0104H]
MOV BX,[0108H]
MOV CH,FRST
MOV DX,VAL1
MOV AH,ARR1
MOV CL,ARR1+3
32 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
 Label Address Data
FRST 0103 C1
VAL1 0104 56
0105 87
• ARR1 0106 9F
0107 A6
0108 75
0109 8C

AX BX CX DX
SI
MAIN PROC NEAR AH AL BH BL CH CL CH CL
MOV AL,[0104H] 56
MOV BX,[0108H] 8C 75
MOV CH,FRST C1
MOV DX,VAL1 87 56
MOV AH,ARR1 9F
MOV CL,ARR1+3 8C
33 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
34 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
4> memory Register Indirect
Addressing Mode
• One of the operands is the contents of the memory location that is specified by a
register, or a combination of registers and an offset, in the instruction.
 Index: Use of SI or DI to specify a memory location.
e.g. MOV AL,[SI] ;AL  [SI]

- Base: Use of BX or BP to specify a memory location.

e.g. MOV AH,[BP] ;AL  [BP]
- Base Relative: Use of BX or BP in combination with an offset to
specify a memory location.
e.g. MOV AL,[BX+ 2] ;AL  [BX + 2]
- Base Relative plus Index: Use of BX or BP in combination with an
index register (SI or DI) and an offset to specify a memory location.
e.g. MOV AL,[BX+SI+8] ;AL  [BX+SI+8]
MOV BX,ARR[BX+DI] ;BX  ARR[BX+DI]

35 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

Example 11
ORG 100H
STRT: JMP MAIN MOV AL,[BX]
DAT1 DB 2FH,48H MOV AH,DAT2[SI]
DAT2 DB 12H,10H,18H MOV AL,DAT1[DI]
DAT3 DW 7A5H MOV AL,[BX+SI]
DAT4 DW 37H MOV AH,[BX+DI+3]
DAT5 DB 10H ENDP MAIN
MAIN PROC NEAR END start
MOV AX,7745H
MOV BX,0104H
MOV DI,0001
MOV SI,0002

36 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

ORG 100H Label Address Data
STRT: JMP MAIN 0100
DAT1 DB 2FH,48H 0101
• DB 12H,10H,18H
DAT2 0102
DAT3 DW 7A5H 0103
DAT4 DW 37H 0104
DAT5 DB 10H 0105
0106
0107
0108
0109
010A
010B

37 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

ORG 100H Label Address Data
STRT: JMP MAIN START 0100
DAT1 DB 2FH,48H 0101
• DB 12H,10H,18H
DAT2 DAT1 0102 2FH
DAT3 DW 7A5H 0103 48H
DAT4 DW 37H DAT2 0104 12H
DAT5 DB 10H 0105 10H
0106 18H
DAT3 0107 0A5H
0108 07H
DAT4 0109 37H
010A 00H
DAT5 010B 10H

38 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

 Address Data
DAT1 0102 2FH
0103 48H
DAT2 0104 12H
0105 10H
0106 18H
DAT3 0107 0A5H
• DAT4
0108
0109
07H
37H
010A 00H
DAT5 010B 10H

AX BX CX DX
SI di
MAIN PROC NEAR AH AL BH BL CH CL DH DL
MOV AX,7745H
MOV BX,0104H
MOV DI,0001
MOV SI,0002
MOV AL,[BX]
MOV AH,DAT2[SI]
MOV AL,DAT1[DI]
MOV AL,[BX+SI]
39 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
MOV AH,[BX+DI+3]
 Address Data
DAT1 0102 2FH
0103 48H
DAT2 0104 12H
0105 10H
0106 18H
DAT3 0107 0A5H
• DAT4
0108
0109
07H
37H
010A 00H
DAT5 010B 10H

AX BX CX DX
SI di
MAIN PROC NEAR AH AL BH BL CH CL DH DL
MOV AX,7745H 77 45
MOV BX,0104H 01 04
MOV DI,0001 0001
MOV SI,0002 0002
MOV AL,[BX] 12
MOV AH,DAT2[SI] 18
MOV AL,DAT1[DI] 48
MOV AL,[BX+SI] 18
40 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
MOV AH,[BX+DI+3] 07H
41 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
Example 12
ORG 100H MOV AL,Data1
STRT: JMP MAIN MOV AH,BL
blank db 3 DUP (?) MOV AL,Data2+3
MOV AX,Data3
Data1 db 4FH
MOV AL,Data2[SI]
Data2 db 8CH,5AH,0ACH,93H MOV AL,[BX+1]
Data3 dW 4F59H,7EA3H MOV AL,[SI+102H]
Data4 db MOV AL,[BX+SI-1]
0F4H,09H,8AH,5CH,6AH MOV AL,Data4[SI+2]
MAIN PROC NEAR MOV AL,Data2[SI+5]
MOV AX,Data3+1
MOV AX,2F8AH
ENDP MAIN
MOV BX,OFFSET Data4 END start
MOV SI,3

42 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

ORG 100H Label Address Data
STRT: JMP MAIN 0100
blank db 3 DUP (?) 0101
Data1 db 4FH 0102
Data2 db 8CH,5AH,0ACH,93H 0103
•
Data3 dW 4F59H,7EA3H 0104
Data4 db 0F4H,09H,8AH,5CH,6AH 0105
0106
0107
0108
0109
010A
010B
010C
010D
010E
010F
0110
0111
0112
43 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
ORG 100H Label Address Data
STRT: JMP MAIN blank 0100
blank db 3 DUP (?) 0101
Data1 db 4FH 0102
Data2 db 8CH,5AH,0ACH,93H 0103
•
Data3 dW 4F59H,7EA3H 0104
Data4 db 0F4H,09H,8AH,5CH,6AH Data1 0105 4F
Data2 0106 8C
0107 5A
0108 AC
0109 93
Data3 010A 59
010B 4F
010C A3
010D 7E
Data4 010E F4
010F 09
0110 8A
0111 5C
0112 6A
44 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1
 Addres Dat
Label
AX BX Addr s a
SI ess blank 0100
MAIN PROC NEAR AH AL BH BL Mode 0101
MOV AX,2F8AH 0102
•
MOV BX,OFFSET Data4 0103
0104
MOV SI,3
Data1 0105 4F
MOV AL,Data1 Data2 0106 8C
MOV AH,BL 0107 5A
MOV AL,Data2+3 0108 AC
MOV AX,Data3 0109 93
Data3 010A 59
MOV AL,Data2[SI]
010B 4F
MOV AL,[BX+1] 010C A3
MOV AL,[SI+102H] 010D 7E
MOV AL,[BX+SI-1] Data4 010E F4
MOV AL,Data4[SI+2] 010F 09
0110 8A
MOV AL,Data2[SI+5]
0111 5C
MOV
45
AX,Data3+1 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1 0112 6A
 Addres Dat
AX BX Label
s a
SI Address Mode
MAIN PROC NEAR AH AL BH BL blank 0100
MOV AX,2F8AH 2F 8A immediate 0101
MOV BX,OFFSET Data4 01 0E immediate 0102
•
MOV SI,3 0003 immediate
0103
0104
MOV AL,Data1 4F Direct
Data1 0105 4F
MOV AH,BL 0E Reg.
Data2 0106 8C
MOV AL,Data2+3 93 Direct 0107 5A
MOV AX,Data3 4F 59 Direct 0108 AC
0109 93
MOV AL,Data2[SI] 93 Reg. Ind.
Data3 010A 59
MOV AL,[BX+1] 09 Reg. Ind.
010B 4F
MOV AL,[SI+102H] 4F Reg. Ind.
010C A3
MOV AL,[BX+SI-1] 8A Reg. Ind. 010D 7E
MOV AL,Data4[SI+2] B8 Reg. Ind. Data4 010E F4
MOV AL,Data2[SI+5] F4 Reg. Ind. 010F 09
0110 8A
MOV AX,Data3+1 A3 4F Direct
0111 5C
46 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1 0112 6A
•

47 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1

 C U Next week,..

48 Dr. Ahmed ElShafee, ACU : Fall 2022, Microprocessors 1