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Lab #10
1-Design and Implementation of a Sequence Detector using
Mealy/Moore Machine
1.2-Objective:
This experiment is to design a Sequence detector using Mealy/Moore models of Finite State
Machine (FSM) and implement the design on FPGA.

1.3-Pre-Lab:
Background theory:
The most general model of a sequential circuit has inputs, outputs, and internal states. It is
customary to distinguish between two models of sequential circuits: the Mealy model and the
Moore model. They differ only in the way the output is generated. The two models of a
sequential circuit are commonly referred to as a finite state machine, abbreviated FSM.
In the Mealy model, the output is a function of both the present state and the input as shown
in Figure 10.1. the outputs may change if the inputs change during the clock cycle. the output
of the Mealy machine is the value that is present immediately before the active edge of the
clock.

In the Moore model, the output is a function of only the present state. A circuit may have
both types of outputs as shown in Figure 10.2. The outputs of the sequential circuit are
synchronized with the clock because they depend only on flip-flop outputs that are
synchronized with the clock.
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1.4-In Lab Tasks:

Design and Implementation of a Sequence Detector using Mealy Machine
1.4.1-In Lab Task # 01
State diagram (Mealy), State table, State Equations and
Circuit Diagram:

Figure:1.4.2:
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1.5-In-Lab Task 2:
HDL implementation for Mealy machine on FPGA
Step 1:
Write the HDL (Verilog) structural description for Mealy based sequence detector
for the given sequence.

1.5.1-D flipflop Verilog code

Figure:1.5.5: Verilog code

1.5.2-Mealy Verilog code:

Figure:1.5.6: Verilog code

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1.5.3-Test pattrens :

Figure:1.5.7: Verilog code

Figure:1.5.7.1:Verilog code

1.5.4-Main:
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Figure:1.5.8: Verilog code

1.6-Implementation on FPGA:

Figure:1.6.1: give button in FPGA on Xilinx software

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Figure: Implementation on FPGA

1.7-Post Lab Tasks:

Using State diagram-based Behavioral model, write a Verilog description of Mealy based
sequence detector for the given sequence.
o Make a stimulus for the given task.
o Record the simulation output waveforms in observations.
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Figure:1.7.1: Verilog code

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Figure:1.7.2: Test Bench code

Test Bench:

Figure:1.7.3: Test Bench

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Conclusion and Discussion:

Discussion:
In this lab we discuss

How we make a sequence detector using mealy\moore models of finite state machines(FSM)

Also discuss how we implement on FPGA.

Proof of the Objective:

Conclusion:
We conclude that we detect the sequence detector using sequential circuit and combinational circuits.
For example in this lab we use d flip-flop and some gates for the detection of the sequence. A Sequence
detector using Mealy/Moore models of Finite State Machine (FSM) and implement the design
on Verilog. In task 1 we design the sequence detector by making the state diagram first then
using this we make state table then with the of state table we make the equations and then
make the circuit on paper. Then we implement the model using the behavioral modeling after
this we made the test bench and then verify the results by observing the outputs.