Synthesis of Digital Systems

Minor Exam 1
25 August 2019, 9:30 to 10:30 AM
20 Marks

1. [8 Marks] We have two types of adders, both of which take inputs from registers that
operate with a clock.
a. In a MULTI-CYCLED ADDER, the result of the addition appears on the output after
three cycles; the input needs to be held stable for the three cycles.
b. In a PIPELINED ADDER, the result of the addition also appears on the output after
three cycles, but a new input can be provided to the adder every cycle, so that a new
output appears on the output every cycle in the steady state (with a 3-cycle delay).

Write VHDL models for both the above adders. Both models should have ONE
process, with the clock signal in the sensitivity list.

2. [8 Marks] Consider the resolution function used below for resolving contention between
multiple signals of type std_ulogic. Note several features of this code: (1) range of s is not
mentioned; (2) loop iteration count is not mentioned; it is derived from the size of s; and (3)
the resolution is performed through a matrix lookup instead of through IF statements. What
is the advantage of writing the code in this style? Justify all three features identified above.

FUNCTION resolved (s : std_ulogic_vector ) RETURN std_ulogic IS

VARIABLE result : std_ulogic := ‘-'; -- weakest state default
BEGIN
IF (s'LENGTH = 1) THEN RETURN s(s'LOW);
ELSE -- Iterate through all inputs
FOR i IN s'RANGE LOOP
result := resolution_table (result, s(i));
END LOOP; -- Return the resultant value
RETURN result;
END IF;
END resolved;

3. [4 Marks] In High Level Synthesis, multiplexers may be inferred at the inputs of function
units when they are shared by different operations. Consider a 2-input adder, which is
shared by n operations occurring in different clock cycles. This results in m-to-1 multiplexers
at the adder inputs. What is the relation between n and m? Justify.