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Test 2 Applications CID 2021

Total working time: 115 minutes

The figure below describes a small processor capable of executing 3 instructions: LOADC, which
loads a constant into one register, ADD, which gathers the values stored in two registers and saves the
result in a third, and SUB, which makes the difference between two registers and saves the result in a third.

To know what to do, a processor needs an instruction, a string of bits that encodes
information about:
• instruction type: field opcode = instruction [7: 6]. This field will be 2'b00 for
LOADC, 2'b10 for ADD and 2'b11 for SUB, regardless of operands.
• the address of the register to which the result will be written: the field dest = instruction [5: 4].
• the address of the register in which the first operand for the arithmetic instructions is stored:
the field addr1 = instruction [3: 2].
• the address of the register in which the second operand for the arithmetic instructions is
stored: the field addr2 = instruction [1: 0].
• date to be uploaded to the registry in case of LOADC: data = instruction [3: 0]
Example: instruction = 8'b10110001 => opcode = 2'b10 (ADD), dest = 2'b11, addr1 = 2'b00, addr2 = 2'b01
=> Reg [3] = Reg [0] + Reg [1]

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1) Circuit implementation (15p - HDL):
Obs: Use the templates listed with to implement GREEN below, so that you follow
exactly the names of the signals on the interfaces and the names of the modules.
All signals with the reset function are synchronous and active in 0 (hence they are called nreset)

a) Implementation INSTR_REG: this module consists of an 8-bit register with synchronous

reset active in 0 and write enable active in 1, which saves the value of the input signal
instruction when we is 1. The outputs of the module are buses that extract groups of bits from this
register: opcode, addr1, addr2, dest and date according to the above information.
b) Implementation MUX: multiplexer with two 4-bit inputs and a selection bit that will select the
output date of INSTR_REG when the selection is 0 and the output result of ALU, when the selection
is 1.
c) Implementation REGFILE: 4x4 RAM (4 4-bit locations) without reset with two read
address buses (addr1 and addr2) and one for writing (dest). outputs op1 and
op2 will be the data read asynchronously from this memory from the addresses addr1, respectively addr2.
The write operation is synchronous and will consist of writing the data coming on data_in at the address
dest. Also, the writing is conditioned by the signal we, active in 1.
d) Implementation ALU: arithmetic-logical unit that performs the operations ADD (op1 + op2)
and SUB (op1 - op2). Any carry / borrow is ignored.
e) Implementation CONTROL: automatic with 3 states that control the operation of the circuit through
the write enable signals of INSTR_REG and REGFILE and through the selection signal of MUX. The 3
states are:
• FETCH: reset status specific to all instructions, in which the instruction is loaded in
INSTR_REG, during which time writing to REGFILE is blocked). The following states
can be LDC or EXEC depending on the instruction entry [7: 6], which represents the
specific opcode for each instruction.
• LDC: in this state from FETCH if instruction [7: 6] is equal to the specific LOADC
opcode. This state leads to the constant loaddate in REGFILE, while the loading of
a new instruction is blocked. The following status is mandatory FETCH.
• EXEC: in this state from FETCH if instruction [7: 6] is equal to the specific ADD and
SUB opcode. This condition causes the result to loadresult in REGFILE, while the
loading of a new instruction is blocked. The following status is mandatory FETCH.

f) Implementation PROCESSOR: how all the sub-modules described above are instantiated and
connected according to the scheme.
Upload all hardware descriptions (Verilog file or files) of the above modules to the assignment
HDL, following the port name indications and the module below (the drawing does not contain
all the names of the ports and modules):
PROCESSOR module (nreset, clock, instruction, result);
INSTR_REG module (nreset, clock, instruction, we, opcode, addr1, addr2, dest, data); MUX
module (in0, in1, sel, out);
REGFILE module (op1, op2, addr1, addr2, dest, data_in, we, clock); ALU
module (op1, op2, opcode, result);
CONTROL module (clock, nreset, op, we_instruction, seldata, we_regfile);
NB: Do not load the testbench here, in HDL, but in SIM. Loading it into HDL can cause errors in the
automatic evaluation.

The scores on the respective modules are divided: as follows: PROCESSOR: 2p / CONTROL:
6p / MUX: 1p / REGFILE: 2p / ALU: 2p / INSTR_REG: 2p.

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2) PROCESSOR circuit test mode (10p - SIM):
Implement a test module PROCESSOR_TB by which you generate at the input of the tested module
a sequence of instructions so as to perform the following algorithm:
• Load a constant in REGFILE at address 0.
• Load in REGFILE at address 1 a constant different from that at address 0.
• Calculate the sum of the two constants by ADD (REGFILE [0] + REGFILE [1]) and put the
result in REGFILE at address 2.
• Calculate the difference of the two constants by SUB (REGFILE [0] - REGFILE [1]) and put the
result in REGFILE at address 3.
Obs: The instructions need two clock cycles to be fully executed, so they must follow
each other every two clock cycles.

Upload on moodle PROCESSOR_TB.v also a printscreen with the obtained waveform, from which to observe the
variation in time of the state of the automaton and of the registers, in the assignment card

3) Answer in writing on an A4 page and upload a single picture (eg, taken with your mobile phone)
with the answers in the assignment ARG (5p - ARG):
a) What is the connection between the number of selection bits of a multiplexer and the number of inputs?
b) What are the parameters of a ROM memory, what do they mean (eg if you are told that it is a ROM memory of
MxN) and how do we calculate the storage capacity (in bits) according to them?
c) Draw the graph of the CONTROL machine, also highlighting the output values for each state.
d) What type of automaton is CONTROL? Mealy or Moore? Why?
e) If the PROCESSOR should recognize a total of 10 different instructions, what is the minimum number of
bits of the opcode to be able to encode all these instructions?