International Journal of Electronics

ISSN: 0020-7217 (Print) 1362-3060 (Online) Journal homepage: https://www.tandfonline.com/loi/tetn20

Speed enhancement techniques for Clock-Delayed

Dual Keeper Domino logic style

A. Anita Angeline & V.S. Kanchana Bhaaskaran

To cite this article: A. Anita Angeline & V.S. Kanchana Bhaaskaran (2020): Speed enhancement
techniques for Clock-Delayed Dual Keeper Domino logic style, International Journal of Electronics,
DOI: 10.1080/00207217.2020.1726486

To link to this article: https://doi.org/10.1080/00207217.2020.1726486

Accepted author version posted online: 04

Feb 2020.
Published online: 20 Feb 2020.

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INTERNATIONAL JOURNAL OF ELECTRONICS
https://doi.org/10.1080/00207217.2020.1726486

Speed enhancement techniques for Clock-Delayed Dual

Keeper Domino logic style
A. Anita Angeline and V.S. Kanchana Bhaaskaran
School of Electronics Engineering, VIT, Chennai, India

ABSTRACT ARTICLE HISTORY

Domino circuit topology for high-speed operation, robustness and Received 12 July 2019
lower power consumption is quintessential in design of digital systems. Accepted 1 January 2020
In this paper, various high speed and robust mechanisms are proposed KEYWORDS
to enhance the speed of Clock-Delayed Dual Keeper Domino (CDDK) Domino logic circuit; high
circuit. Delayed enabling of keeper circuit in CDDK domino circuit speed techniques; noise gain
reduces contention between keeper circuit and Pull-Down network margin; robustness; process
(PDN). The speed of transition at the dynamic node of the CDDK variation tolerance
domino circuit is enhanced through imposing techniques namely (i)
controlled clock delay time in enabling the keeper transistor, (ii) keeper
control signal voltage swing variation, (iii) sizing of keeper transistors
and (iv) deploying an additional conditional discharge path. The robust-
ness of CDDK circuit is increased by upsizing the keeper transistor
without degrading the speed by stack arrangement of dual keeper
transistors. The simulation of enhancement techniques has been per-
formed using Cadence® Virtuoso ADEL and ADEXL environments
employing UMC 90nm technology library. The simulation results of
wide fan-in 64-input OR gate demonstrate that CDDK technique with
additional discharge path offer 38% increase in speed and CDDK tech-
nique with keeper transistor upsizing offers 52% increase in noise gain
margin without speed degradation while comparing with the conven-
tional domino logic circuit.

1. Introduction
Domino logic circuits are widely in use due to their reduced transistor count, high-speed
performance and reduced logical effort (Ding & Mazumder, 2004). Realisation of wide fan-
in gates using domino logic circuit style is normally preferred as in the Pull-Up Network
(PUN); they evade stacking of transistors and are extensively used in design of Static
Random Access Memory (SRAM) pre-decoders, tag comparators and programmable
encoders (Asyaei & Ebrahimi, 2018; Nasserian, Kafi-Kangi, Maymandi-Nejad, & Moradi,
2016; Peiravi & Asyaei, 2012a). The domino logic circuit design with reduced transistor
count and the evaluation being performed only by N-type Metal Oxide Semiconductor
(NMOS) transistors makes it a preferable circuit style compared to static Complementary
Metal Oxide Semiconductonductor (CMOS) circuit in terms of chip area and speed
performance. However, it offers low noise gain margin due to leakage current and charge

CONTACT V.S. Kanchana Bhaaskaran vskanchana@ieee.org School of Electronics Engineering, VIT, Chennai
TN-600 127, India
© 2020 Informa UK Limited, trading as Taylor & Francis Group
2 A. A. ANGELINE AND V. S. K. BHAASKARAN

sharing which occur in the internal nodes. In addition, the dynamic power consumption is
increased because of redundant switching at output node for every pre-charge operation,
even for consecutive identical inputs.
In conventional domino logic circuit, the PUN comprises of a single pre-charge PMOS
transistor and pull-down network (PDN) consists of NMOS evaluation transistors, with a static
inverter connected at the dynamic node D as shown in Figure 1. The keeper transistor MK
protects the dynamic node against leakage current and charge sharing. The keeper ratio
K stated as
WKeeper
K¼ (1)
WPDN

where WKeeper is the keeper transistor width and WPDN is the evaluation transistor’s width in the
PDN. The upsizing of keeper transistor MK improves the robustness of the circuit, by trading off
the speed performance (Moradi et al., 2013). This has been addressed by various researchers to
design high speed, robust domino logic circuit topologies for reduced power consumption
(Alvandpour et al., 2002; Angeline & Bhaaskaran, 2018; Anis, Allam, & Elmasry, 2002; Anita
Angeline & Kanchana Bhaaskaran, 2019; Anita Angeline & Kanchana Bhaaskaran, 2019; Asyaei,
2015; Asyaei & Moradi, 2018; Garg & Gupta, 2018; Jeyasingh, Bhat, & Amrutur, 2009; Lih,
Tzartzanis, & Walker, 2006; Moradi et al., 2013; Palumbo, Pennisi, & Alioto, 2012; Peiravi &
Asyaei, 2012b). This had led to design of various other domino logic structures with modifica-
tion in the keeper circuit or the PDN of the conventional domino logic circuit style (Alvandpour
et al., 2002; Anis et al., 2002; Asyaei, 2015; Asyaei & Moradi, 2018; Jeyasingh et al., 2009; Lih et al.,
2006; Palumbo et al., 2012; Peiravi & Asyaei, 2012b).
The controlling of the keeper circuit is based on anyone of the following
approaches such as: (i) delayed enabling of the keeper circuit, (ii) abrupt keeper
control mechanism, (iii) keeper control signal with voltage swing variation, (iv) keeper

VDD

CLK
MP MK

OUT
D
Inputs PDN

MN

Figure 1. Conventional domino logic circuit.

 INTERNATIONAL JOURNAL OF ELECTRONICS 3

mechanisms with process variation tolerance and (v) bias voltage variation of the
keeper device. The various other topologies based on PDN modification have also
been proposed in the literature, in which an additional discharge path is augmented.
This results in increased operating speed and reduction of leakage current mechan-
isms (Garg & Gupta, 2018; Moradi et al., 2013).
Figure 2(a) depict the high-speed domino (HSD) logic (Anis et al., 2002) in which the keeper
control circuit is enabled after a small delay. This cause the dynamic node to remain in floating
condition during that initial delay time. This can however result in increased power consump-
tion. In leakage current replica (LCR) keeper technique shown in Figure 2(b), the strength of the
keeper device is controlled by an analog current mirror circuit, which is dependent on the
leakage current of PDN (Lih et al., 2006). On the other hand, it is to be noted that for wider fan-
in circuits, this technique incurs increased power dissipation with reduced robustness. An
additional keeper transistor along with the conventional keeper transistor reduces the loop
gain and decreases the delay variability in grounded PMOS keeper structure shown in Figure 2
(c) (Palumbo et al., 2012). An additional discharge path is controlled by output voltage and foot
node voltage in foot-driven stacked transistor domino logic (FDSTDL) as depicted in Figure 2
(d). This reduces the delay in discharge of the dynamic node and accelerates the transitions in
the output node (Garg & Gupta, 2018). Clock-delayed dual keeper (CDDK) domino circuit
structure has also been proposed in the same line of research with modifications in keeper
circuit for decreasing the contention during the beginning of evaluation phase(Angeline &
Bhaaskaran, 2018; Anita Angeline & Kanchana Bhaaskaran, 2019).
CDDK circuit operates on the principle of delayed enabling of keeper circuit, which
comprises of dual PMOS keeper transistors in series. This feature of delayed enabling of
keeper circuit reduces the contention current between the keeper transistor and PDN.
Hence, if the PDN evaluates a TRUE condition, it facilitates faster discharge of the dynamic
nodal charge through PDN, which enhances the operating speed of circuit. In domino
logic circuits, the feedback loop gain and process parameter variations contribute to
considerable amount of delay variability (Alioto, Palumbo, & Pennisi, 2009; Dadgour &
Banerjee, 2009). These issues accentuate the necessity of identifying suitable enhance-
ment techniques, which can offer high-speed performance with reduced delay variability
under statistical process parameter variations of the keeper circuit.
This paper proposes the following four high-speed enhancement techniques on CDDK
circuit to enhance the speed performance by alleviating the contention current problem.

(1) Controlled clock delay time in enabling the keeper transistor

(2) Keeper control signal with voltage swing variation
(3) Keeper transistor sizing
(4) Additional conditional discharge path

Also, reduced delay variability is ensured in all the techniques for repeated runs. The
high-speed techniques of CDDK domino circuits have been simulated and analysed for
speed, power consumption, noise gain margin and delay variability factor using wide fan-in
benchmark circuits. UMC 90nm technology node library using Cadence Virtuoso® ADEL and
ADEXL environments has been utilised for design and simulation of enhancement techni-
ques on CDDK domino circuit. Delay variability is observed using Monte–Carlo analysis for
2000 runs under statistical variations of process parameters. The organisation of the paper is
 4
A. A. ANGELINE AND V. S. K. BHAASKARAN

Figure 2. Existing domino logic circuit styles (Anis et al., 2002; Lih et al., 2006; Lih et al., 2006; Palumbo et al., 2012; Garg & Gupta, 2018).
(a) High-Speed Domino Logic, (b) Leakage current Replica Keeper Domino Logic, (C) Grounded PMOS keeper, (d) Foot-Driven staked Transistor Domino Logic.
 INTERNATIONAL JOURNAL OF ELECTRONICS 5

as follows: Section 2 elaborates the operation of CDDK domino circuit. Section 3 focuses on
the principle and operation of various high-speed techniques of CDDK domino circuit. The
simulation results are discussed in Section 4 and Section 5 concludes the paper.

2. Clock-Delayed Dual Keeper (CDDK) domino circuit

Figure 3 depicts CDDK circuit comprising pre-charge transistor MP and keeper transistors
MK1 and MK2 in series. The MK2 keeper device is controlled by the delayed inverted clock
CLK_DI which is introduced by inverter I2 on CLK signal (Angeline & Bhaaskaran, 2018;
Anita Angeline & Kanchana Bhaaskaran, 2019). While the CLK is LOW (pre-charge phase),
the transistor MP conducts and makes the dynamic node to be HIGH. Consequently, the
output becomes LOW. While the CLK is HIGH (evaluation phase), the PDN evaluates for the
inputs. The evaluation phase is deterred as follows. The inverter I2 introduces a delay on
CLK signal as characterised by the inverter device size. This makes the keeper transistor
MK2 to be cut-off initially for a brief duration, due to delayed inverted clock signal CLK_DI

Figure 3. Clock-delayed domino keeper circuit topology.

6 A. A. ANGELINE AND V. S. K. BHAASKARAN

that is still HIGH. The inverter I2 is optimally sized such that it is sufficient to offer
a momentary delay in disabling the keeper device MK1, only during the beginning of
the evaluation phase and reduce the contention current between the keeper circuit and
the PDN. Thus, if the PDN evaluates a TRUE condition, the keeper circuit being cut-off
prevents replenishing the dynamic node to HIGH state through keeper circuit and this
feature facilitates faster discharge of the dynamic node charge and the output signal OUT
becomes HIGH. If the PDN evaluates a FALSE condition, the dynamic node is still retained
at VDD, as the keeper transistor MK2 is enabled after the delay incurred by the inverter I2
circuit. During the brief period of MK2 cut-off time and during the beginning of the
evaluation phase, the dynamic node D is self-sufficient in retaining the dynamic nodal
charge (acquired through pre-charge operation). Thus, the additional keeper transistor
MK2, in series along with the conventional keeper transistor MK1, reduces the contention
and thereby results in increased operating speed. Table 1 depicts the transistor’s states of
CDDK circuit during various phases of operation.
In the domino keeper structure, the positive feedback loop gain T decreases as transcon-
ductance offered by the keeper transistor gmK1 is reduced as stated in Equation (2) (Palumbo
et al., 2012). Here, Ainv is the inverter gain and ZX is the total impedance of dynamic node.

T ¼ Ainv gmK1 Z X (2)

In CDDK domino circuit, the keeper transistor MK2 behaves as a closed switch offering
a resistance R during evaluation phase. This reduced resistance accounts for source de-
generation of keeper transistor Mk1 in the feedback circuit (Palumbo et al., 2012). This
reduces the effective trans-conductance Gm;eff of the keeper device K1 in the feedback
loop as expressed by

GmK1
Gm;eff ¼ (3)
ð1 þ GmK1 ÞR

It is observed that the reduced resistance R offered by keeper transistor MK2 reduces the
feedback keeper circuit loop gain by a factor of ð1 þ GmK1 ÞR. Similarly, during the begin-
ning of the evaluation phase, the keeper transistor MK2 is completely cut-off and offers
infinite resistance. This makes ð1 þ GmK1 ÞR factor to be increased which in-turn
decreases the trans-conductance of keeper device. Simultaneously, the feedback loop
gain of CDDK domino circuit is reduced which decreases the delay variability.
The enhancement techniques of CDDK domino circuit proposed in the following
sections focus on enhancing the speed of operation without much compromise in area
consumption and robustness of the circuit.

Table 1. CDDK domino circuit transistor’s states during various phases of operation.
Transistors operation
Phase of operation MP MK1 MK2 Dynamic Node Output
Pre-charge phase ON ON ON H L
Beginning of evaluation phase OFF ON OFF H L
Evaluation phase Inputs = TRUE OFF OFF OFF L H
Inputs = FALSE OFF ON ON H L
H- high L- low
 INTERNATIONAL JOURNAL OF ELECTRONICS 7

3. High-speed techniques
The CDDK domino circuit topology with dual keeper transistors offers various degrees of
freedom to enhance the speed metrics and robustness of the circuit. The subsequent
sections detail the principle of speed-enhancement techniques proposed for CDDK
domino circuit and its operation.

3.1. Controlled clock delay time in enabling the keeper transistor

The brief time delay elapsed in enabling the keeper circuit of CDDK domino circuit greatly
decreases the contention current between PDN and the keeper circuit. This increases the
operating speed. However, extended delay in enabling the keeper circuit could slow down
the speed of operation. Hence, the delay offered during initial evaluation phase needs to be
just sufficient enough for proper discharge of the dynamic node. The delay to be introduced
depends on the number of pull-down paths. Hence, for wide fan-in circuits, it is sufficient to
have a lesser delay compared to that of the circuits with lower number of fan-ins.
The keeper transistor MK2 of CDDK domino circuit is enabled only when the keeper
control signal is LOW. Thus, if the keeper control signal transits to LOW abruptly (which is
the output of the inverter I2), the keeper circuit will replenish charge to the dynamic node
in a faster pace. By considering charging path as a first-order linear RC-network, the
propagation delay (tPHL) of inverter I2 is proportional to the pull-down resistance of the
inverter I2 and load capacitance expressed by the RC network formed by

tPHL α 0:69 Rn CL (4)

Here, Rn is the resistance offered by the NMOS transistor and is given as Rn αLn =Wn , Wn is the
width and Ln is the channel length of NMOS transistor. In CDDK domino circuit, the load
capacitance CL is the capacitance exerted at the gate of keeper device CGK2. Hence, sizing of
NMOS transistor in inverter I2 plays a vital role in controlling the delay time of keeper enabling
circuit as depicted in Figure 3.
This embarks on having the Wn of the I2 to be greater which facilitates faster HIGH-to-
LOW transition of the CLK_DI signal, which is provided as the keeper control signal for MK2
keeper device. This makes the MK2 keeper device to be conducting at the earliest.
However, the retaining of the dynamic node at HIGH condition depends on MK1 device
which is determined by the PDN condition. Thus, the contention is alleviated during the
beginning of evaluation phase, by MK1 keeper device being cut-off and for the rest of the
evaluation phase it is determined by the MK2 keeper device.

3.2. Varied voltage swing at keeper control

The inverter is connected to a HIGH supply voltage VDD2 instead of power supply rail of
the inverter I2 being VDD1 as depicted on Figure 1. This enables the keeper control signal
to attain LOW logic condition in a faster pace as stated in Equation (5).
CL VDD2 CL VDD1
< (5)
Wn
Ln μn Cox ðVDD2  Vtn Þ2 Wn
Ln μn Cox ðVDD1  Vtn Þ2
8 A. A. ANGELINE AND V. S. K. BHAASKARAN

Hence, during the evaluation phase when clock signal CLK transits from LOW to HIGH,
initially the keeper circuit is disabled due to the delay incurred by the inverter I2. The
keeper control signal makes a faster transition from HIGH to LOW, after the delay elapsed,
due to increase in VDD. This facilitates in retaining the dynamic node instantly depending
on MK1 condition, which is controlled by the output signal. The keeper control signal for
MK1 is LOW, if dynamic node is not discharged (inputs being LOW) during evaluation
phase. Hence, the keeper circuit with MK1 and MK2 conducts and the dynamic node is
replenished to compensate for leakage current and charge sharing.
Increasing the supply voltage indiscriminately has a positive impact on performance
on the gate. In addition, it makes the gate increasingly insensitive to variations in device
parameters such as transistor threshold voltage and mobility of charge carriers. However,
it is absolutely detrimental to energy dissipation.

3.3. Keeper transistor sizing

The effective aspect ratios of the two keeper transistors MK1 and MK2 present in CDDK
domino circuit are sized such that it is equivalent to the aspect ratio of single keeper
transistor MK in the case of conventional domino logic structure as shown in Equation (6).
This feature of CDDK domino circuit offers great freedom in sizing the MK1 and MK2
transistors for increased robustness.

1 1 1
¼ þ (6)
ðW=LÞK ðW=LÞK1 ðW=LÞK2

During evaluation phase, since MK2 is enabled only after a momentary delay, the upsizing
of MK2 does not increase the contention current and discharge speed of dynamic node.
Similarly, the upsizing of MK1 increases the robustness and this does not have any
considerable impact on the discharge speed. Thus, delayed enabling of the upsized
dual keeper transistors of CDDK domino circuit offers two-fold advantage of increasing
the robustness of the circuit without speed performance degradation.
To elaborate, the conventional domino logic has its keeper circuit being ON during the
beginning of the evaluation phase and the drain capacitance CK of the keeper transistor MK is
contributed primarily by the following components, namely, 1) the keeper transistor’s gate to
drain capacitance CGCD_K = CoxWL/2 and 2) the drain diffusion capacitance of keeper transistor
MK specified by the sidewall junction capacitance as Cdiff α Cjsw ð2Ls þ W Þ where Cdiff is the
diffusion capacitance, Cjsw is the sidewall junction capacitance, W is the width of the transistor
and Ls is the length of the transistor. On the other hand, in CDDK domino circuit, the
capacitance CK1 exerted at dynamic node of MK1 is the gate-to-drain capacitance CGCD_K1 and
is equivalent to zero (Palumbo et al., 2012), since the keeper circuit is initially cut-off during the
evaluation phase. Also, the drain diffusion capacitance of keeper transistor MK1 is less than that
of keeper transistor MK as given by Cdiff α Cjsw ðLs þ W Þ: These factors result in reduced net
capacitance at the dynamic node while using MK1 – MK2 transistor configuration in CDDK
domino. Hence, it can be stated that CK1 < CK . Thus, the total dynamic nodal capacitance Cdyn of
CDDK domino circuit is less than the dynamic nodal capacitance of conventional domino logic
gate, which speed up the logic transitions at the dynamic node. The total dynamic nodal
capacitance Cdyn of CDDK domino circuit is stated as in Equation (7).
 INTERNATIONAL JOURNAL OF ELECTRONICS 9

Cdyn ¼ f ðCPre ; CK1 ; CPDN ; CInv P ; CInv N Þ (7)

Here, Cdyn is the total capacitance at dynamic node and it depends on CPre , the drain
capacitance of the pre-charge transistor CPDN , the source diffusion capacitance exerted by
PDN and CK or CK1, the effective keeper transistor capacitance and the sum of effective
gate capacitances of static inverter CInv P and CInv N which is contributed by the NMOS and
PMOS transistor’s gate capacitances namely CInv P and CInv N . The capacitive load impact
due to the capacitances CPre and the PDN is identical in both conventional domino logic
and CDDK domino logic. Hence, achieving CK1 < CK during the initial evaluation phase
greatly reduces the net dynamic node capacitance Cdyn. This makes the dynamic node to
be pre-charged in a faster manner with reduced time delay TD and stated as
Cdyn VDD
TD ¼ (8)
2IDsat
where IDsat is the pre-charging current.

3.4. Additional conditional discharge path

During evaluation, due to PDN input conditions, when the dynamic node is to be
discharged, it incurs the path delay imposed by PDN. Hence, CDDK domino circuit is
incorporated with an additional discharge path which facilitates faster discharge of
dynamic node. Figure 4 depicts the CDDK domino circuit, comprising the additional

Figure 4. CDDK domino circuit with additional conditional discharge path.

10 A. A. ANGELINE AND V. S. K. BHAASKARAN

discharge path with MN1 and MN2 devices controlled by the footer node voltage Vfoot and
the clock CLK, respectively.
During pre-charge phase, when the CLK is LOW, since MN2 is cut-off, the additional
discharge path is cut-off. During initial evaluation phase, if the PDN is TRUE, the Vfoot
attains HIGH and enables MN1 and the clock CLK enables MN2. This paves way for faster
discharge of the dynamic node through MN1 and MN2.
The sizing of both the footer transistor Mf and the devices in the PDN determines Vfoot,
which is set to be slightly above Vth of the MN1. Upsizing the evaluation transistors of PDN
increases the Vfoot and upsizing the footer transistor decreases the Vfoot. Hence, the sizing
of the PDN transistors and the footer device are done in such a way that Vfoot  Vth MN1 , to
enable the additional discharge path, while the PDN evaluates TRUE condition.

4. Enhanced robustness
The robustness of the circuit can be enhanced by upsizing the keeper transistor and by
deploying countermeasures against leakage current mechanism and by avoiding issues due
to charge sharing. In CDDK domino circuit technique, the availability of two keeper devices
offers flexibility in upsizing the keeper transistors and increase robustness as discussed in
Section 3.4. The upsizing of keeper devices increases the noise margin of the circuit. Hence,
the devices MK1 and MK2 can be upsized without incurring any additional penalty on speed
performance. It is to be noted that it does not affect the speed performance since the
keeper circuit is completely cut-off during the initial evaluation phase.

5. Simulation results and discussion

The proposed enhancement techniques are validated through design of wide fan-in
designs using Cadence® with UMC 90nm technology library with supply voltage of 1V.
The keeper transistors are also set to their minimum process width, so chosen to reduce
the nodal capacitance values. The speed metric simulation results of 128-input OR gate
with various other existing domino logic circuits under same input conditions is depicted
in Figure 5. It demonstrates that CDDK domino circuit style offers higher speed compared
with the existing styles of domino logic circuits.

Figure 5. Delay analysis of various domino logic topologies.

 INTERNATIONAL JOURNAL OF ELECTRONICS 11

Figure 6. Delay and power delay product of CDDK domino circuit-enhanced techniques.

Figure 6(a) depicts the increase in speed by adopting various high-speed techniques in
the CDDK domino circuit under various fan-in conditions. It is observed that CDDK
domino style with additional discharge path offers high speed of operation when com-
pared with the other enhancement techniques.
The CDDK domino circuit with controlled delay time of keeper control signal
exhibits high speed of operation without penalty in area and power consumption as
depicted in Figure 5(b).
Unity Noise Gain (UNG) metric defines the robustness of the domino logic circuit
(Moradi et al., 2013). The noise gain margin is defined as the DC voltage, which when
applied to all inputs, produces an output voltage with the same amplitude, as stated in
Equation (9).
12 A. A. ANGELINE AND V. S. K. BHAASKARAN

Figure 7. Delay and UNGM variation due to keeper transistor sizing.

UNG ¼ fðVin ; Vnoise Þ ¼ VOut g (9)

Figure 7 demonstrates the increase in noise gain margin on upsizing the keeper transis-
tors without degradation in the speed performance. This makes the CDDK domino circuit
technique a better choice for improving the robustness without compromising the speed
performance.
Variations in the process parameters lead to undesirable changes in the delay char-
acteristics of a circuit. Hence, to evaluate the robustness of CDDK domino circuit enhance-
ment techniques, Monte–Carlo analysis is performed for 2000 runs on a 64-input OR gate.
The various process parameters such as mobility and threshold voltage are subjected to
statistical variations of 3σ value and analysed as depicted in Figure 8. Figure 8(a,b)
demonstrate the statistical distribution imposed on the mobility and threshold voltage
of keeper circuit devices. Figure 8(c–f) demonstrate the effect of process parameter
variations on the three circuits with enhancement techniques. The reduced mean, stan-
dard deviation and variability factor of the enhancement techniques are depicted in
Table 2.
The reduced variability factor demonstrates good robustness of the proposed styles
with increased speed. Hence, the proposed styles of CDDK domino circuit-enhancement
techniques are better choices for lower technology nodes due to the circuits employing
reduced variability factor.

6. Conclusion
Four CDDK domino enhancement techniques with increased robustness are proposed
and simulated using UMC 90nm technology node using various wide fan-in circuits. The
keeper transistors arrangement and delayed enabling of CDDK keeper circuit enhance the
performance and robustness without any trade-offs. Furthermore, the on-circuit
 INTERNATIONAL JOURNAL OF ELECTRONICS 13

Figure 8. Delay variation in CDDK domino techniques for statistical variations of process parameters
on a 64-input OR gate.

Table 2. Variability factor of CDDK domino circuit under statistical process parameter variations.
Mean (ps) Standard deviation (ps) Variability factor
Domino logic technique (µ) (σ) (σ/µ)
Conventional Domino logic 207.35 3.75 1.81%
CDDK domino circuit 183.3 3.13 1.71%
CDDK with varied voltage swing of keeper control signal 172.72 3 1.74%
CDDK domino circuit with additional discharge path 158.5 3.45 2.18%

enhancement techniques on CDDK circuit pave way for additional flexibility in increasing
the performance. The simulation of 64-input OR gate using CDDK domino circuit techni-
que with additional discharge path proves to offer high speed of operation with
14 A. A. ANGELINE AND V. S. K. BHAASKARAN

a reduced delay value of 164.5 ps. The upsizing of the keeper transistor improves the
robustness of the circuit without degrading the speed performance. These techniques
with decreased loop gain offered by the CDDK circuit also proves to offer reduced delay
variability factor of 1.71% which validates the designs to be process variation tolerant and
more suitable for lower technology node-based dynamic circuits.

Disclosure statement
No potential conflict of interest was reported by the authors.

ORCID
A. Anita Angeline http://orcid.org/0000-0002-5603-0976
V.S. Kanchana Bhaaskaran http://orcid.org/0000-0002-3819-1952

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