®

OPA2111

Dual Low Noise Precision

Difet ® OPERATIONAL AMPLIFIER

FEATURES APPLICATIONS
● LOW NOISE: 100% Tested, 8nV/√Hz max at ● PRECISION INSTRUMENTATION
10kHz ● DATA ACQUISITION
● LOW BIAS CURRENT: 4pA max ● TEST EQUIPMENT
● LOW OFFSET: 500µV max ● PROFESSIONAL AUDIO EQUIPMENT
● LOW DRIFT: 2.8µV/°C ● MEDICAL EQUIPMENT
● HIGH OPEN-LOOP GAIN: 114dB min ● DETECTOR ARRAYS
● HIGH COMMON-MODE REJECTION:
96dB min

DESCRIPTION
The OPA2111 is a high precision monolithic +VCC
dielectrically isolated FET (Difet ) operational ampli-
fier. Outstanding performance characteristics allow its 8

use in the most critical instrumentation applications.

Noise, bias current, voltage offset, drift, open-loop
gain, common-mode rejection, and power supply re- –In
jection are superior to BIFET® amplifiers.
Very low bias current is obtained by dielectric isola-
tion with on-chip guarding. +In
Noise-Free
Cascode*
Laser trimming of thin-film resistors gives very low
offset and drift. Extremely low noise is achieved with
Output
patented circuit design techniques. A cascode design
allows high precision input specifications and reduced
susceptibility to flicker noise. –VCC

Standard dual op amp pin configuration allows up- 4

*Patented
grading of existing designs to higher performance
OPA2111 Simplified Circuit
levels. (Each Amplifier)

BIFET® National Semiconductor Corp., Difet ® Burr-Brown Corp.

International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

© 1984 Burr-Brown Corporation PDS-540E Printed in U.S.A. October, 1993

SBOS140
SPECIFICATIONS
ELECTRICAL
At VCC = ±15VDC and TA = +25°C unless otherwise noted

. OPA2111AM OPA2111BM OPA2111SM OPA2111KM, KP

PARAMETER CONDITION MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
INPUT NOISE
Voltage, fO = 10Hz 100% Tested 40 80 30 60 40 80 40 nV/√Hz
fO = 100Hz 100% Tested 15 40 11 30 15 40 15 nV/√Hz
fO = 1kHz 100% Tested 8 15 7 12 8 15 8 nV/√Hz
fO = 10kHz (1) 6 8 6 8 6 8 6 nV/√Hz
fB = 10Hz to 10kHz (1) 0.7 1.2 0.6 1 0.7 1.2 0.7 µVrms
fB = 0.1Hz to 10Hz (1) 1.6 3.3 1.2 2.5 1.6 3.3 1.6 µVp-p
Current, fB = 0.1Hz to 10Hz (1) 15 24 12 19 15 24 15 fAp-p
fO = 0.1Hz to 20kHz (1) 0.8 1.3 0.6 1 0.8 1 0.8 fA/√Hz

OFFSET VOLTAGE(2)
Input Offset Voltage VCM = 0VDC ±0.1 ±0.75 ±0.05 ±0.5 ±0.1 ±0.75 ±0.3 ±2 mV
Average Drift TA = TMIN to TMAX ±2 ±6 ±0.5 ±2.8 ±2 ±6 ±8 ±15 µV/°C
Match ±1 ±0.5 2 2 µV/°C
Supply Rejection 90 110 96 110 90 110 86 110 dB
±3 ±31 ±3 ±16 ±3 ±31 ±3 ±50 µV/V
Channel Separation 100Hz, R L = 2kΩ 136 136 136 136 dB

BIAS CURRENT(2)
Input Bias Current VCM = 0VDC ±2 ±8 ±1.2 ±4 ±2 ±8 ±3 ±15 pA
Match ±1 ±0.5 ±1 2 pA

OFFSET CURRENT(2)
Input Offset Current VCM = 0VDC ±1.2 ±6 ±0.6 ±3 ±1.2 ±6 ±3 ±12 pA

IMPEDANCE
Differential 1013 || 1 1013 || 1 1013 || 1 1013 || 1 Ω || pF
Common-Mode 1014 || 3 1014 || 3 1014 || 3 1014 || 3 Ω || pF

VOLTAGE RANGE
Common-Mode Input Range ±10 ±11 ±10 ±11 ±10 ±11 ±10 ±11 V
Common-Mode Rejection VIN = ±10VDC 90 110 96 110 90 110 82 110 dB

OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain RL ≥ 2kΩ 110 125 114 125 110 125 106 125 dB
Match 3 2 3 3 dB

FREQUENCY RESPONSE
Unity Gain, Small Signal 2 2 2 2 MHz
Full Power Response 20Vp-p, RL = 2kΩ 16 32 16 32 16 32 32 kHz
Slew Rate VO = ±10V, RL = 2kΩ 1 2 1 2 1 2 2 V/µs
Settling Time, 0.1% Gain = –1, RL = 2kΩ 6 6 6 6 µs
0.01% 10V Step 10 10 10 10 µs
Overload Recovery,
50% Overdrive(3) Gain = –1 5 5 5 5 µs

RATED OUTPUT
Voltage Output RL = 2kΩ ±10 ±11 ±10 ±11 ±10 ±11 ±10 ±11 V
Current Output VO = ±10VDC ±5 ±10 ±5 ±10 ±5 ±10 ±5 ±10 mA
Output Resistance DC, Open-Loop 100 100 100 100 Ω
Load Capacitance Stability Gain = +1 1000 1000 1000 1000 pF
Short Circuit Current 10 40 10 40 10 40 10 40 mA

POWER SUPPLY
Rated Voltage ±15 ±15 ±15 ±15 VDC
Voltage Range, Derated
Performance ±5 ±18 ±5 ±18 ±5 ±18 ±5 ±18 VDC
Current, Quiescent IO = 0mADC 5 7 5 7 5 7 5 9 mA

TEMPERATURE RANGE
Specification Ambient Temp. –25 +85 –25 +85 –55 +125 0 +70 °C
Operating “M” Package Ambient Temp. –55 +125 –55 +125 –55 +125 –55 +125 °C
“P” Package –40 +85 °C
Storage “M” Package Ambient Temp. –65 +150 –65 +150 –65 +150 –65 +150 °C
“P” Package –40 +85 °C
θ Junction-Ambient 200 200 200 200(4) °C/W
NOTES: (1) Sample tested—this parameter is guaranteed. (2) Offset voltage, offset current, and bias current are measured with the units fully warmed up. (3) Overload
recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. (4) Typical θJ-A =
150°C/W for plastic DIP.

OPA2111 2
ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS)
At VCC = ±15VDC and TA = TMIN to TMAX unless otherwise noted.

OPA2111AM OPA2111BM OPA2111SM OPA2111KM, KP

PARAMETER CONDITION MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

TEMPERATURE RANGE
Specification Range Ambient Temp. –25 +85 –25 +85 –55 +125 0 +70 °C
INPUT OFFSET VOLTAGE(1)
Input Offset Voltage VCM = 0VDC ±0.22 ±1.2 ±0.08 ±0.75 ±0.3 ±1.5 ±0.9 ±5 mV
Average Drift ±2 ±6 ±0.5 ±2.8 ±2 ±6 ±8 ±15 µV/°C
Match 1 0.5 2 2 µV/°C
Supply Rejection 86 100 90 100 86 100 82 100 dB
±10 ±50 ±10 ±32 ±10 ±50 ±10 ±80 µV/V

BIAS CURRENT(1)
Input Bias Current VCM = 0VDC ±125 ±1nA ±75 ±500 ±2nA ±16.3nA ±125 ±500 pA
Match 60 30 1nA pA

OFFSET CURRENT(1)
Input Offset Current VCM = 0VDC ±75 ±750 ±38 ±375 ±1.3nA ±12nA ±75 ±375 pA

VOLTAGE RANGE
Common-Mode Input Range ±10 ±11 ±10 ±11 ±10 ±11 ±10 ±11 V
Common-Mode Rejection VIN = ±10VDC 86 100 90 100 86 100 80 100 dB

OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain RL ≥ 2kΩ 106 120 110 120 106 120 100 120 dB
Match 5 3 5 5 dB

RATED OUTPUT
Voltage Output RL = 2kΩ ±10.5 ±11 ±10.5 ±11 ±10.5 ±11 ±10.5 ±11 V
Current Output VO = ±10VDC ±5 ±10 ±5 ±10 ±5 ±10 ±5 ±10 mA
Short Circuit Current VO = 0VDC 10 40 10 40 10 40 10 40 mA

POWER SUPPLY

Current, Quiescent IO = 0mADC 5 8 5 8 5 8 5 10 mA

NOTES: (1) Offset voltage, offset current, and bias current are measured with the units fully warmed up.

CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS

Top View DIP Supply ........................................................................................... ±18VDC
Internal Power Dissipation (TJ ≤ +175°C) .................................... 500mW
Differential Input Voltage ............................................................ Total VCC
Out A 1 8 +VCC Input Voltage Range .......................................................................... ±VCC
Storage Temperature Range: “M” Package .................. –65°C to +150°C
A “P” Package .................... –40°C to +85°C
–In A 2 7 Out B Operating Temperature Range: “M” Package ............... –55°C to +125°C
“P” Package ................. –40°C to +85°C
B
+In A 3 6 –In B Lead Temperature (soldering, 10s) ............................................... +300°C
Output Short Circuit to Ground (+25°C) ................................. Continuous
Junction Temperature .................................................................... +175°C
–VCC 4 5 +In B

PACKAGE INFORMATION
PACKAGE DRAWING
MODEL PACKAGE NUMBER(1)
OPA2111AM TO-99 001
Top View TO-99
OPA2111BM TO-99 001
+VCC and Case OPA2111KM TO-99 001
8 OPA2111SM TO-99 001
Out A 1 7 Out B OPA2111KP 8-Pin Plastic DIP 006

NOTE: (1) For detailed drawing and dimension table, please see end of data
A B
sheet, or Appendix D of Burr-Brown IC Data Book.
–In A 2 6 –In B

ORDERING INFORMATION
+In A 3 5 +In B
4 OFFSET
–VCC TEMPERATURE VOLTAGE,
MODEL PACKAGE RANGE max (mV) 1–24

OPA2111AM TO-99 –25°C to +85°C ±0.75 $12.50

OPA2111BM TO-99 –25°C to +85°C ±0.5 21.60
OPA2111KM TO-99 0°C to +70°C ±2 25.55
OPA2111SM TO-99 –55°C to +125°C ±0.75
OPA2111KP 8-Pin Plastic DIP 0°C to +70°C ±2

3 OPA2111
DICE INFORMATION

PAD FUNCTION
1 Out A
2 –In A
3 +In A
4 –VS
5 +In B
6 –In B
7 Out B
8 +VS
NC No Connection
Substrate Bias: No Connection

MECHANICAL INFORMATION
MILS (0.001") MILLIMETERS
Die Size 138 x 84 ±5 3.51 x 2.13 ±0.13
Die Thickness 20 ±3 0.51 ±0.08
Min. Pad Size 4x4 0.10 x 0.10
OPA2111AD DIE TOPOGRAPHY
Backing None
Transistor Count 102

TYPICAL PERFORMANCE CURVES

TA = +25°C, and VCC = ±15VDC unless otherwise noted.

VOLTAGE AND CURRENT NOISE SPECTRAL

INPUT CURRENT NOISE SPECTRAL DENSITY DENSITY vs TEMPERATURE
100 12 100

fO = 1kHz
Current Noise (fA/ Hz)

Voltage Noise (nV/ Hz)

Current Noise (fA/ Hz)

10 10
10

8 1

1
BM 6 0.1

0.1 4
0.01
1 10 100 1k 10k 100k 1M –75 –50 –25 0 25 50 75 100 125
Frequency (Hz) Temperature (°C)

OPA2111 4
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, and VCC = ±15VDC unless otherwise noted.

TOTAL(1) INPUT VOLTAGE NOISE SPECTRAL

DENSITY vs SOURCE RESISTANCE INPUT OFFSET VOLTAGE WARM-UP DRIFT
1k 40
RS = 10MΩ

Offset Voltage Change (µV)

Voltage Noise (nV/ Hz)

RS = 1MΩ 20
100
RS = 100kΩ
0

BM
10 RS = 100Ω
–20
NOTE: (1) Includes contribution
from source resistance.

1 –40
0.1 1 10 100 1k 10k 100k 0 1 2 3 4 5 6
Frequency (Hz) Time From Power Turn-On (Minutes)

BIAS AND OFFSET CURRENT

INPUT VOLTAGE NOISE SPECTRAL DENSITY vs TEMPERATURE
1k 1k 1k

100 100
Voltage Noise (nV/ Hz)

Offset Current (pA)

Bias Current (pA)

100
10 10

AM, SM
BM 1 1
10

0.1 0.1

1 0.01 0.01
1 10 100 1k 10k 100k 1M –50 –25 0 25 50 75 100 125
Frequency (Hz) Ambient Temperature (°C)

TOTAL(1) INPUT VOLTAGE NOISE (PEAK-TO-PEAK) POWER SUPPLY REJECTION

vs SOURCE RESISTANCE vs FREQUENCY
1k 140

120
Power Supply Rejection (dB)

NOTE: (1) Includes contribution

Voltage Noise (µVp-p)

from source resistance. 100

100
80

60
10 BM
fB = 0.1Hz to 10Hz 40

20

1 0
4
10 10 5 10
6
10
7
10
8
10
9
10
10
1 10 100 1k 10k 100k 1M 10M
Source Resistance (Ω) Frequency (Hz)

5 OPA2111
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, and VCC = ±15VDC unless otherwise noted.

TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY COMMON-MODE REJECTION

AT 1kHz vs SOURCE RESISTANCE vs INPUT COMMON-MODE VOLTAGE
1k 120

EO

Common-Mode Rejection (dB)

Voltage Noise, EO (nV/ Hz)

110

100 RS BM
100

OPA2111 +
90
Resistor
10

80
Resistor Noise Only

1 70
100 1k 10k 100k 1M 10M 100M –15 –10 –5 0 5 10 15
Source Resistance (Ω) Common-Mode Voltage (V)

INPUT OFFSET VOLTAGE CHANGE GAIN-BANDWIDTH AND SLEW RATE

DUE TO THERMAL SHOCK vs TEMPERATURE
150 4 4

AM
Offset Voltage Change (µV)

Gain Bandwidth (MHz)

75 3 3

Slew Rate (V/µs)

BM

0 25°C 85°C 2 2
TA = 25°C to TA = 85°C
Air Environment
–75 1 1

–150 0 0
–1 0 1 2 3 4 5 –75 –50 –25 0 25 50 75 100 125
Time From Thermal Shock (Minutes) Ambient Temperature (°C)

BIAS AND OFFSET CURRENT

vs INPUT COMMON-MODE VOLTAGE OPEN-LOOP GAIN vs TEMPERATURE
10 10 140

Bias Current 130

Offset Current (pA)
Bias Current (pA)

Voltage Gain (dB)

1 1

Offset Current 120

0.1 0.1
110

0.01 0.01 100

–15 –10 –5 0 5 10 15 –75 –50 –25 0 25 50 75 100 125
Common-Mode Voltage (V) Ambient Temperature (°C)

OPA2111 6
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VCC = ±15VDC unless otherwise noted.

COMMON-MODE REJECTION
vs FREQUENCY LARGE SIGNAL TRANSIENT RESPONSE
140

120
Common-Mode Rejection (dB)

15

100

Output Voltage (V)

80
0
60

40

20 –15

0
1 10 100 1k 10k 100k 1M 10M 0 25 50
Frequency (Hz) Time (µs)

OPEN-LOOP FREQUENCY RESPONSE SETTLING TIME vs CLOSED-LOOP GAIN

140 100

120 –45
80
Phase Shift (Degrees)

100
Voltage Gain (dB)

Settling Time (µs)

Gain
φ 60
80 –90

60 Phase 0.01% 0.1%

Margin 40
40 ≈ 65° –135
20
20

0 –180 0
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k
Frequency (Hz) Closed-Loop Gain (V/V)

GAIN-BANDWIDTH AND SLEW RATE

vs SUPPLY VOLTAGE CHANNEL SEPARATION vs FREQUENCY
3 3 150

RL = ∞
140
Channel Separation (dB)
Gain Bandwidth (MHz)

Slew Rate (V/µs)

2 2 RL = 2kΩ
130
RL = 560Ω
120
1 1

110

0 0 100
0 5 10 15 20 10 100 1k 10k 100k
Supply Voltage (±VCC ) Frequency (Hz)

7 OPA2111
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VCC = ±15VDC unless otherwise noted.

MAXIMUM UNDISTORTED OUTPUT

VOLTAGE vs FREQUENCY SUPPLY CURRENT vs TEMPERATURE
30 8

6
Output Voltage (Vp-p)

Supply Current (mA)

20

10
2

0 0
1k 10k 100k 1M –75 –50 –25 0 25 50 75 100 125
Frequency (Hz) Ambient Temperature (°C)

TOTAL HARMONIC DISTORTION

SMALL SIGNAL TRANSIENT RESPONSE vs FREQUENCY
60 1
10kΩ
Total Harmonic Distortion (%)

40 10kΩ EO = 7V
EO
Output Voltage (mV)

20 0.1
2kΩ
0
EO =
–20 0.01 700mV

–40 THD + Noise

Residual Test Limit
–60 0.001
0 1 2 3 4 5 0.1 1 10 100 1K 10K 100K
Time (µs) Frequency (Hz)

APPLICATIONS INFORMATION
OFFSET VOLTAGE ADJUSTMENT INPUT PROTECTION
The OPA2111 offset voltage is laser-trimmed and will Conventional monolithic FET operational amplifiers require
require no further trim for most applications. external current-limiting resistors to protect their inputs
Offset voltage can be trimmed by summing (see Figure 1). against destructive currents that can flow when input FET
With this trim method there will be no degradation of input gate-to-substrate isolation diodes are forward-biased. Most
offset drift. BIFET amplifiers can be destroyed by the loss of –VCC.
Because of its dielectric isolation, no special protection is
needed on the OPA2111. Of course, the differential and
common-mode voltage limits should be observed. Static
In 1/2 OPA2111
damage can cause subtle changes in amplifier input charac-
Out
teristics without necessarily destroying the device. In preci-
–15V sion operational amplifiers (both bipolar and FET types),
150kΩ ±2mV this may cause a noticeable degradation of offset voltage and
OffsetTrim
drift.
100kΩ
20Ω +15V
Static protection is recommended when handling any preci-
sion IC operational amplifier.

FIGURE 1. Offset Voltage Trim.

OPA2111 8
GUARDING AND SHIELDING APPLICATIONS CIRCUITS
As in any situation where high impedances are involved, Figures 5 through 13 are circuit diagrams of various appli-
careful shielding is required to reduce “hum” pickup in input cations for the OPA2111.
leads. If large feedback resistors are used, they should also
be shielded along with the external input circuitry.
Leakage currents across printed circuit boards can easily 1k
exceed the bias current of the OPA2111. To avoid leakage EO
OP-27 + Resistor

Voltage Noise Spectral Density (EO)

OPA2111 + Resistor
problems, it is recommended that the signal input lead of the

Typical at 1kHz (nV/ Hz)

Resistor Noise Only
OPA2111 be wired to a Teflon standoff. If the OPA2111 is
100 RS
to be soldered directly into a printed circuit board, utmost
care must be used in planning the board layout. A “guard”
pattern should completely surround the high impedance
input leads and should be connected to a low impedance 10 EO = eN2 + (iNRS)2 + 4kTRS
point which is at the signal input potential (see Figure 2).
OPA2111 + Resistor
Resistor Noise Only
OP-27 + Resistor BM
NOISE: FET vs BIPOLAR 1
100 1k 10k 100k 1M 10M
Low noise circuit design requires careful analysis of all
Source Resistance, RS (Ω)
noise sources. External noise sources can dominate in many
cases, so consider the effect of source resistance on overall
operational amplifier noise performance. At low source FIGURE 3. Voltage Noise Spectral Density vs Source
impedances, the low voltage noise of a bipolar operational Resistance.
amplifier is superior, but at higher impedances the high
current noise of a bipolar amplifier becomes a serious
liability. Above about 15kΩ the OPA2111 will have lower 80
total noise than an OP-27 (see Figure 3).
TA = 25°C; curves taken from
60 LF156/157
manufacturers' published
Input Bias Current (pA)

BIAS CURRENT CHANGE typical data

vs COMMON-MODE VOLTAGE 40

The input bias currents of most popular BIFET® opera-

20 LF155
tional amplifiers are affected by common-mode voltage
(Figure 4). Higher input FET gate-to-drain voltage causes AD547 OPA2111
leakage and ionization (bias) currents to increase. Due to its 0

cascode input stage, the extremely low bias current of the OP-15/16/17 “Perfect Bias Current Cancellation”
–20
OPA2111 is not compromised by common-mode voltage.
–15 –10 –5 0 5 10 15
Common-Mode Voltage (VDC)

Non-Inverting Buffer
FIGURE 4. Input Bias Currrent vs Common-Mode Voltage.

2 2
1 Out 1 Out
A A 1MΩ

In
3
In 3 In Operate 10kΩ 2
1/2
1 Out
OPA2111BM
Zero 3
Inverting TO-99 Bottom View
100kΩ
4
In 2 Gain = –100
Out 3 5
1
100Ω
Polypropylene VOS ≤ 5µV
A 2 6
100kΩ
1µF Drift ≤ 0.028µV/°C
3 Zero Droop ≤ 2µV/s
Referred to Input
1 7
8 6
1/2
7
OPA2111BM
Board layout for input guarding: guard top and bottom of board. 5
Alternate: use Teflon® standoff for sensitive input pins.

Teflon® E. I. Du Pont de Nemours & Co.

FIGURE 2. Connection of Input Guard. FIGURE 5. Auto-Zero Amplifier.

9 OPA2111
 <1pF to prevent gain peaking 100Ω 10kΩ

1000MΩ 1/2 OPA2111BM

2
1
+15V 3 Out
Pin Photodiode Guard 5.34MΩ(1) 5.34MΩ(1)
UDT Pin-040A
0.1µF 1/2 OPA2111BM
2 In
8 Output 1000pF 5 2kΩ
1 Q
1/2 OPA2111 7
3
4 0.1µF 6
5 x 108V/W 2.67MΩ(1)

0.01µF
1000MΩ 500pF 500pF
–15V
Circuit must be well shielded.
NOTE: (1) For 50Hz use 3.16MΩ and 6.37Ω.
Gain = 101
FIGURE 6. Sensitive Photodiode Amplifier.
FIGURE 7. High Impedance 60Hz Reject Filter with Gain.

10.5kΩ 0.03µF

0.01µF

73.2Ω Right

365Ω
2
365kΩ 1µF Output
1
1/2 OPA2111
3
L
Input 0.01µF 100kΩ
RT CT

10.5kΩ 0.03µF

0.01µF

73.2Ω Left

365Ω
6
365Ω 1µF Output
7
1/2 OPA2111
5
R
Input 100kΩ
0.01µF
RT CT
G = 26dB Midband

FIGURE 8. RIAA Equalized Stereo Preamplifier.

OPA2111 10
 IB = ±4pA max
1/2 OPA2111BM Gain = 100
3
CMRR ≈ 106dB
–In 1
RIN ≈ 1013Ω
2
RF
5kΩ 25kΩ 25kΩ
2 5

RG
101Ω
RF
6
5kΩ 25kΩ
3 Output

Burr-Brown
1/2 OPA2111BM
6 25kΩ INA105
7 Differential
Amplifier
5
1
+In
Differential Voltage Gain = 1 + 2RF /RG

FIGURE 9. FET Input Instrumentation Amplifier.

10kΩ

≈10pF

(1)

1MΩ 1/2
OPA2111AM
IN914 6
1/2 Output
OPA2111AM 7
2 (1)
(1) 5
1
3
IN914 Droop ≈ 0.5mV/s
Input 2N4117A

0.01µF
NOTE: (1) Reverse polarity for Polystyrene
negative peak detection.

FIGURE 10. Low-Droop Positive Peak Detector.

6.3MΩ 944kΩ 6.3MΩ 7.8MΩ

2 6
1.6MΩ
1 7
1.6MΩ 1.6MΩ 1/2 OPA2111 1.6MΩ 1/2 OPA2111
3 5 Out
In
0.01µF 0.01µF 0.01µF 0.01µF
NPO NPO NPO NPO

NOTE: Lower value resistors will have lower AV = 2.6

thermal noise but capacitors must fO = 10Hz
be scaled larger. –24dB/Octave

FIGURE 11. 10Hz Fourth-Order Butterworth Low-Pass Filter.

11 OPA2111
 100Ω 10kΩ

2
10kΩ
Input 1
1/2OPA2111
3

100Ω 10kΩ Since signal voltage sums directly with N

but amplifier noise voltage sums as N,
6 signal-to-noise ratio improves by N.
10kΩ
7
1/2OPA2111
5
AV = –1010
en = 1.9nV/ Hz typ(1) at 10kHz
100Ω 10kΩ
BW = 30kHz typ
GBW = 30.3 MHz typ
2 VOS = ±16µV typ(1)
10kΩ ∆VOS/∆T = ±0.16µV/°C typ(1)
1
1/2OPA2111
3 IB = 40pA max
ZIN = 1012Ω || 30pF

100Ω 10kΩ
NOTE: (1) Theoretical performance
achievable from OPA2111BM
6
10kΩ with uncorrelated random
7 distribution of parameters.
1/2OPA2111
5

100Ω 10kΩ

2
10kΩ 10kΩ
1
1/2OPA2111
3
2 Output
6
OPA37
3

1/2OPA2111

N = 10
5 each OPA2111BM

FIGURE 12. ‘N’ Stage Parallel-Input Amplifier.

OPA2111 12
 1/2 OPA2111

E1 A1 1
–In
R2
INA106
10kΩ 10kΩ 100kΩ
2 5

R1
202Ω
R2 6
10kΩ 10kΩ
3 EO
Output
1/2 OPA2111
100kΩ
AV = 10
A2
1
E2
+In

EO = 10(1 + 2 R2/R1)(E2 – E1) = 1000(E2 – E1)

Using the INA106 for an output difference amplifier extends the input common-mode
range of an instrumentation amplifier to ±10V. A conventional IA with a unity-gain difference
amplifier has an input common-mode range limited to ±5V for an output swing of ±10V. This
is because a unity-gain difference amp needs ±5V at the input for 10V at the output,
allowing only 5V additional for common-mode.

FIGURE 13. Precision Instrumentation Amplifier.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

13 OPA2111
 PACKAGE OPTION ADDENDUM

www.ti.com 16-Apr-2009

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
OPA2111AM NRND TO-99 LMC 8 20 Green (RoHS & AU N / A for Pkg Type
no Sb/Br)
OPA2111BM NRND TO-99 LMC 8 20 Green (RoHS & AU N / A for Pkg Type
no Sb/Br)
OPA2111KM NRND TO-99 LMC 8 20 Green (RoHS & AU N / A for Pkg Type
no Sb/Br)
OPA2111KP ACTIVE PDIP P 8 50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA2111KPG4 ACTIVE PDIP P 8 50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1
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