Dell - Latitude - 5480 - CDP70 - LA-E141P R0.2 2016-07-01 PDF

5 4 3 2 1
COMPAL CONFIDENTIAL
MODEL NAME : CDP70
D D
PCB NO : LA-E141P
BOM P/N :
GPIO MAP: Dell GPIO map EC16 062416 Compal Only
Breckenridge 14 UMA
Kabylake H
2016-07-01
C
REV : 0.2 (X01) C
@ : Nopop Component
EMI@ : EMI Component
@EMI@ : EMI Nopop Component
ESD@ : ESD Component
@ESD@ : ESD Nopop Component
RF@ : RF Component
B
@RF@ : RF Nopop Component B
XDP@ : XDP Component

CONN@ : Connector Component
MB PCB
Part Number Description
DAB0001R000 PCB 1SC LA-E141P REV0 MB UMA 1
Layout Dell logo
A A
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
COPYRIGHT 2016 Issued Date 2016/01/01 Deciphered Date 2017/01/01 Title
ALL RIGHT RESERVED Cover Sheet
REV: X01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
PWB: K6NHT DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
LA-E141P 0.2
Date: Friday, July 01, 2016 Sheet 1 of 61

5 4 3 2 1
USB2.0[2]
USB3.0 Conn
USB3.0[3] (Ext Port 3) P43
USB2.0[3]
PAGE 16~24
SATA [2]
SPI
PCIE[17]
Card reader Intel Jacksonville

WGI219LM M.2,3042 Key B M.2,3030 Key A
RTS5242 P34 P33 WWAN/LTE WLAN+BT/WIGIG
/HCA/SSD P35
SD4.0 Transformer USB2.0[8]
SATA-0A
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS USB3.0 SSIC PCIE SATA DESTINATION USB PORT# DESTINATION
S3# S4# S5# A# PLANE PLANE PLANE PLANE
State USB3.0-1 JUSB3-->Rear 1 JUSB3-->Rear
USB3.0-2 SSIC-1 JNGFF2-->M2 3042(LTE) 2 JUSB1-->Right

S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON
USB3.0-3 SSIC-2 JUSB1-->Right 3 JUSB2 ->Left
D S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF D
USB3.0-4 JUSB2-->Left 4 Type C
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF USB3.0-5 NA 5 NA
USB3.0-6 NA 6 JNGFF1--> M.2 3030(BT)

S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF
USB3.0-7 PCIE-1 JNGFF1-->M.2 3030(WIGIG) 7 NA
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
USB3.0-8 PCIE-2 JNGFF1-->M.2 3030(WLAN) 8 JNGFF2-->M2 3042(WWAN)
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF USB3.0-9 PCIE-3 Card Reader 9 JEDP1-->Touch Screen
USB3.0-10 PCIE-4 LOM 10 JUSH1-->USH

S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
PCIE-5 11 JEDP1-->Camera
NA
PM TABLE PCIE-6 NA
12
C
+5V_ALW PCIE-7 C
+3.3V_ALW USH H BIO

PCIE-8
+3.3V_ALW_DSW +3.3V_SUS +5V_RUN
+3.3V_ALW_PCH +1.2V_MEM +3.3V_RUN
PCIE-9 SATA-0A
power
plane +RTC_CELL +1.0V_VCCST +0.6V_DDR_VTT PCIE-10 SATA-1A M.2 Socket 3 (Key M)
+1.8V_PRIM +2.5V_MEM +1.2V_RUN M.2 2280 SSD
+1.0V_PRIM +VCC_CORE
PCIE-11 (PCIex4 or SATA) VIDEO DESTINATION
+1.0V_PRIM_CORE +VCC_GT PCIE-12 eDP LCD
+5V_ALW2 +1.0VS_VCCIO
State PCIE-13 SATA-0B NA
+3.3V_ALW2 +VCC_SA DDI-B JHDMI1
+3.3V_RTC_LDO +1.8V_RUN PCIE-14 SATA-1B NA
+1.0V_MPHYGT DDI-C Type-C
PCIE-15 SATA-2 JSATA1-->HDD SATA
S0 ON ON ON
PCIE-16 SATA-3 NA M.2 3030 (WiGig)
B
S3 ON ON OFF PCIE-17 SATA-4 M.2 3042 (HCA or QCA LTE) SSD Cache DDI-D DeMux 1 B
NA MB VGA
S5 S4/AC ON OFF OFF
PCIE-18 SATA-5
PCIE-19 NA
S5 S4/AC doesn't exist OFF OFF OFF
PCIE-20 NA
A A
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2016/01/01 Deciphered Date 2017/01/01
Port Assignment
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
LA-E141P 0.2
Date: Wednesday, June 29, 2016 Sheet 3 of 61

5 4 3 2 1
5 4 3 2 1
SIO_SLP_SUS# CPU PWR

SIO_SLP_S4#
SIO_SLP_S4# TPS22961 PCH PWR
+1.2V_MEM (UZ26) +VCC_SFR_OC
GT3 PWR
SY8210A
(PU200) Peripheral Device PWR
0.6V_DDR_VTT_ON RUN_ON
TPS22961 SIO_SLP_S0# TYPE-C Power
Barrel Type-C +0.6V_DDR_VTT (UZ19) +1.0V_VCCSTG
D
ADAPTER ADAPTER GPU PWR D
SIO_SLP_S4#
TPS22961
(UZ21) +1.0V_VCCST
SIO_SLP_SUS#
SYX198D
(PU301) +1.0V_PRIM
RUN_ON
CHARGER TPS62134C
ISL88738 +PWR_SRC +5V_ALW (PU401) +1.0VS_VCCIO
ALWON
(PU801) SY8288C
(PU102) TPS62134D SIO_SLP_SUS#
(PU402) +1.0V_PRIM_CORE
+5V_ALW2
RUN_ON 3.3V_TS_EN
EM5209 LP2301
(UZ4) +5V_RUN (QV8) +5V_TSP
BATTERY AUD_PWR_EN
EM5209
(@UZ5) +5V_RUN_AUDIO
USB_PWR_SHR_EN#
SY8288B +3.3V_RTC_LDO SLGC55544C
(PU100) (UI3) +5V_USB_CHG_PWR
ALWON
C C
USB_PWR_EN1#
+3.3V_ALW2 SY6288
(UI1) +USB_EX2_PWR
USB_PWR_EN2#
+3.3V_ALW SY6288
(UI2) +USB_EX3_PWR
SIO_SLP_SUS# RUN_ON
AP3402KTTR AOZ1336
(PU501) +1.8V_PRIM (UZ8) +1.8V_RUN
SIO_SLP_LAN#
ISL95857 ISL95857 ISL95857 AO6405
(PU602) (PU604) (PU603) (QV1) +3.3V_LAN
EM5209
(UZ2) AUX_EN_WOWL
IMVP_VR_ON
IMVP_VR_ON
IMVP_VR_ON
+3.3V_WLAN
EN_INVPWR
@SIO_SLP_WLAN#
SIO_SLP_SUS#
+3.3V_ALW_PCH
EM5209 @PCH_ALW_ON
(UZ3) RUN_ON 3.3V_CAM_EN#
+VCC_SA +VCC_GT +VCC_CORE +BL_PWR_SRC LP2301A
+3.3V_RUN (QZ1) +3.3V_CAM
3.3V_WWAN_EN
B
EM5209 AUD_PWR_EN
B
(UZ4) +3.3V_WWAN EM5209

(@UZ5) +3.3V_RUN_AUDIO
ENVCC_PCH
G524B1T11U
(UV24) +LCDVDD
TYPE-C
TBT_PWR_EN
AOZ1336
(UT13) +3.3V_TBT
+5V_ALW
TPS65982
(UT5) +TBT_VBUS(5V~20V) TPS22967 CV2_ON
+PP_HV(5V~20V) (UZ18) +3.3V_CV2
USH/B
SIO_SLP_S4#
AP7175SP
(PU503) +2.5V_MEM
for DDR4
+5V_ALW
AP2204 AP2112K
(UT8) (UT7) +3.3V_TBT_SX
+5V_TBT_VBUS
A A
Title
Power Rails
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
1K 2.2K
SMBUS Address [0x9a]
1K
+3.3V_ALW_PCH 2.2K
+3.3V_RUN
AW44 MEM_SMBCLK 202
MEM_SMBDATA
DMN66D0LDW-7
BB43 200 DIMMA
DMN66D0LDW-7
499
202
D
PCH D
499
+3.3V_ALW_PCH 200 DIMMB
AY44 SML0_SMBCLK 28
SML0_SMBDATA 31 LOM
BB39
AW45 AW42 53
51 XDP
1K
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
1K
1
E11 D8 2.2K LNG2DMTR
4
+3.3V_TP
03 03 2.2K
02 C12 DAT_TP_SIO_I2C_CLK 9
02 E10 CLK_TP_SIO_I2C_DAT 8 TP
@2.2K 2.2K
+3.3V_ALW +3.3V_CV2
@2.2K 2.2K
C
01 B3 USH_SMBCLK M9 C
E5 USH_SMBDAT USH
01 L9
2.2K USH/B
00 D7 2.2K
00 E7
2.2K +3.3V_ALW +3.3V_TBT_FLASH
KBC 2.2K
C3 UPD1_SMBCLK UPD1_SMBCLK_Q B5
04 DMN66D0LDW-7
B4 UPD1_SMBDAT PD &
UPD1_SMBDAT_Q A5
04 DMN66D0LDW-7 FW reflash
MEC 5105
F7
05
B6
05
06 A12
B 06 N10 B
2.2K
+3.3V_ALW
2.2K
07 M4 EXPANDER_GPU_SMCLK
M7 EXPANDER_GPU_SMDATA EXPANDER
07
08 C5
08 C8
09 F6
09 E9 2.2K
Charger
+3.3V_ALW
2.2K
10
100 ohm 7
N2 PBAT_CHARGER_SMBCLK
A
100 ohm 6
BATTERY A
10 M3 PBAT_CHARGER_SMBDAT CONN
Title
SMbus Block Diagram
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
D D
UC1C SKYLAKE_HALO
Rev_1.0
E25 B25
D25 PEG_RXP[0] PEG_TXP[0] A25
PEG_RXN[0] PEG_TXN[0]
E24 B24
F24 PEG_RXP[1] PEG_TXP[1] C24
E23 B23
E22 B22
E21 B21
E20 B20
E19 B19
E18 B18
C F18 PEG_RXP[7] PEG_TXP[7] C18 C
D17 A17
E17 PEG_RXP[8] PEG_TXP[8] B17
F16 C16
D15 A15
F14 C14
D13 A13
F12 C12
D11 A11
F10 C10
PEG_COMP G2
PEG_RCOMP
B B
DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0
<17> DMI_CRX_PTX_P0 DMI_RXP[0] DMI_TXP[0] DMI_CTX_PRX_P0 <17>
DMI_CRX_PTX_N0 E8 A8 DMI_CTX_PRX_N0
<17> DMI_CRX_PTX_N0 DMI_RXN[0] DMI_TXN[0] DMI_CTX_PRX_N0 <17>
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
DMI_CRX_PTX_N1 F6 B6 DMI_CTX_PRX_N1
DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2
DMI_CRX_PTX_N2 E5 A5 DMI_CTX_PRX_N2
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
DMI_CRX_PTX_N3 J9 B4 DMI_CTX_PRX_N3
3 OF 14
SKL-H_BGA1440
+1.0VS_VCCIO
1 2 PEG_COMP
RC2 24.9_0402_1%
Trace width=5 mils

,Spacing=15mil
Max length= 600 mils.
A A
Title
KBL-H (1/8)
A
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM +1.0V_PRIM_XDP
1 2
+3.3V_ALW_PCH @ RC216 0_0603_1%
XDP@ RC133
1.5K_0402_5%
CPU XDP +1.0V_PRIM_XDP
1
+1.0V_PRIM_XDP XDP@
+1.0V_PRIM_XDP XDP_PRSNT_PIN1 1 2 CFG3
RC121 1K_0402_5% +1.0V_PRIM_XDP CPU_XDP_HOOK6 1 2
1 2 XDP@ RC115 2.2K_0402_5%
2
@ RC122 0_0402_5%
SYS_PWROK_R +3.3V_ALW_PCH
0.1U_0402_25V6
0.1U_0402_25V6
JXDP1
1 1 1 2
CPU_XDP_PREQ# 3 GND0 GND1
0.1U_0402_25V6
@ CC28
@ CC29
D 1 4 CFG17 D
CPU_XDP_PRDY# 5 OBSFN_A0 OBSFN_C0 XDP_DBRESET#
@ CC33
6 CFG16 1 2
Place near JXDP1.47 7 OBSFN_A1 OBSFN_C1 8 XDP@ RC137 1.5K_0402_5%
2 2 CFG0 9 GND2 GND3 10 CFG8
2 CFG1 11 OBSDATA_A0 OBSDATA_C0 12 CFG9
13 OBSDATA_A1 OBSDATA_C1 14
CFG2 15 GND4 GND5 16 CFG10 +1.0V_VCCSTG
CFG3 17 OBSDATA_A2 OBSDATA_C2 18 CFG11
19 OBSDATA_A3 OBSDATA_C3 20
Place near JXDP1 XDP_OBS0_R 21 GND6 GND7 22 CFG19 CPU_XDP_TDO 1 2
+3.3V_ALW XDP_OBS1_R 23 OBSFN_B0 OBSFN_D0 24 CFG18 RC135 51_0402_5%
25 OBSFN_B1 OBSFN_D1 26
CFG4 27 GND8 GND9 28 CFG12 CPU_XDP_TRST# 1 2
29 OBSDATA_B0 OBSDATA_D0
1
1.5K_0402_5%
XDP@ RC241
CFG5 30 CFG13 @ RC136 51_0402_5%

31 OBSDATA_B1 OBSDATA_D1 32
CFG6 33 GND10 GND11 34 CFG14 CPU_XDP_TCLK 1 2
CFG7 35 OBSDATA_B2 OBSDATA_D2 36 CFG15 RC139 51_0402_5%
<20,44> PCH_RSMRST#_AND
37 OBSDATA_B3 OBSDATA_D3 38
39 GND12 GND13
2
XDP@ RC124 1 2 1K_0402_5% H_VCCST_PWRGD_XDP 40 PCH_XDP_CLK_DP

T191 @ PAD~D PCH_XDP_CLK_DP <18>
SIO_PWRBTN# SIO_PWRBTN# 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42 PCH_XDP_CLK_DN
<20,37> SIO_PWRBTN# PCH_XDP_CLK_DN <18>
FIVR_EN @ RC217 1 2 0_0402_5% 43 HOOK1 ITPCLK#/HOOK5 44 XDP_DBRESET#
FIVR_EN_R 45 VCC_OBS_AB VCC_OBS_CD CPU_XDP_HOOK6 ITP_PMODE_CPU
0.1U_0402_25V6
XDP@ CC269
CFG0 XDP@ RC126 1 2 1K_0402_5% 46 1 2 ITP_PMODE_CPU <20>

SYS_PWROK_R 47 HOOK2 RESET#/HOOK6 XDP_DBRESET#
0.1U_0402_25V6
XDP@ CC32
XDP@ RC128 1 2 1K_0402_5% 48 XDP@ RC144 0_0402_5%
1 Place near JXDP1.41 <19> PCH_SPI_D0
@ RC129 1 2 0_0402_5% 49 HOOK3 DBR#/HOOK7 50
1
<20,37> SYS_PWROK XDP_DBRESET# <17>
51 GND14 GND15 52 CPU_XDP_TDO
<14,15,20,41> DDR_XDP_WAN_SMBDAT
53 SDA TD0 54 CPU_XDP_TRST#
CPU_XDP_TRST# <22>
2 <14,15,20,41> DDR_XDP_WAN_SMBCLK 55 SCL TRST# 56 CPU_XDP_TDI 2
<20> PCH_JTAG_TCK CPU_XDP_TCLK 57 TCK1 TDI 58 CPU_XDP_TMS
59 TCK0 TMS 60 CPU_XDP_PRS 1 2 PCH_SPI_D2_XDP
GND16 Not link CIS GND17 PCH_SPI_D2_XDP <19>
XDP@ RC127 1K_0402_5%
SAMTE_BSH-030-01-L-D-A CONN@
CFG0
Stall reset sequence after PCU
1
C C
PLL lock until de-asserted
+1.0V_PRIM_XDP @
CPU_XDP_TMS 1 2 RC321
PCH_JTAG_TMS <20>
RC228 0_0402_5% 1K_0402_5% No Stall 1
1 2 CPU_XDP_PREQ# CPU_XDP_TDO H_VCCST_PWRGD_XDP CPU_XDP_TRST# CPU_XDP_TDI 1 2
PCH_JTAG_TDI <20>
2
@ RC138 51_0402_5% RC229 0_0402_5%
CPU_XDP_TDO 1
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
+1.0VS_VCCIO
2
PCH_JTAG_TDO <20> Stall 0
RC230 0_0402_5%
1
CPU_XDP_TCLK 1 2
PCH_JTAGX <20>
RC143 0_0402_5%
1 2 FIVR_EN_R CPU_XDP_PRDY# 1 2
PCH_XDP_PRDY# <22>
2
CC306
CC307
CC308
RC132 150_0402_5% @ RC314 0_0402_5% CFG2
CPU_XDP_PREQ#1 2
PCH_XDP_PREQ# <22>
1
+1.0V_VCCSTG @ RC315 0_0402_5% PEG LANE REVERSAL
@
1 2 H_PROCHOT#
RC181
1K_0402_5%* NORMAL 1
RC83 1K_0402_5% ESD request,Place near JXDP1 side.
2
+1.0V_VCCST
LANE
REVERSED 0
1 2 H_THERMTRIP#
RC80 1K_0402_5%
1 2 PCH_JTAGX
@ RC166 1K_0402_5% CFG4
1 2 VCCST_PWRGD eDP enable
1
RC71 1K_0402_5%
1 2 H_CATERR# SKYLAKE_HALO
UC1E
@ RC79 49.9_0402_1%
PCH_CPU_BCLK_R_D
Rev_1.0 RC322 Disabled 1
B31 BN25 CFG0 1K_0402_5%
+1.0V_VCCST <18> PCH_CPU_BCLK_R_D PCH_CPU_BCLK_R_D# BCLKP CFG[0]
A32 BN27 CFG1
<18> PCH_CPU_BCLK_R_D# BCLKN CFG[1]
2
CFG[2]
BN26 CFG2 Enabled 0
1 2 FIVR_EN PCH_CPU_PCIBCLK_R_D D35 BN28 CFG3
<18> PCH_CPU_PCIBCLK_R_D PCH_CPU_PCIBCLK_R_D# PCI_BCLKP CFG[3]
@ RC218 150_0402_5% C36 BR20 CFG4
<18> PCH_CPU_PCIBCLK_R_D# PCI_BCLKN CFG[4] BM20 CFG5
B 1 2 FIVR_EN CPU_24MHZ_R_D E31 CFG[5] BT20 CFG6 B
<18> CPU_24MHZ_R_D CPU_24MHZ_R_D# D31 CLK24P CFG[6] BP20
@ RC219 10K_0402_5% CFG7
<18> CPU_24MHZ_R_D# CLK24N CFG[7] BR23 CFG8 CFG5
CFG[8] BR22 CFG9
CFG[9]
1
BT23 CFG10 PCI Express* Bifurcation
+1.0V_VCCST CFG[10] BT22 CFG11 @ [6:5]
CFG[11] BM19 CFG12 RC323
CFG[12] BR19 CFG13 1K_0402_5%
CFG[13]
CFG[14]
BP19 CFG14 1x8, 2x4 00
2
1
1
56.2_0402_1%
100_0402_5%
CPU_VIDALERT# BH31 BT19 CFG15

VR_SVID_CLK VIDALERT# CFG[15]
RC152
RC157
<54> VR_SVID_CLK BH32

VR_SVID_DATA VIDSCK
H_PROCHOT# H_PROCHOT#_R
BH29
VIDSOUT CFG[17]
BN23 CFG17 Reserved 01
1 2 BR30 BP23 CFG16 CFG6
<37,54,57> H_PROCHOT# RC84 499_0402_1% PROCHOT# CFG[16] BP22 CFG19
CFG[19]
2
1
VR_SVID_DATA DDR_VTT_CTRL BT13 BN22 CFG18 2x8 10
<54> VR_SVID_DATA <14> DDR_VTT_CTRL DDR_VTT_CNTL CFG[18]
VR_SVID_ALERT# BR27 XDP_OBS0 @ RC239 1 2 0_0402_5% XDP_OBS0_R RC324
<54> VR_SVID_ALERT# BPM#[0] XDP_OBS1 @ RC240
BT27 1 2 0_0402_5% XDP_OBS1_R 1K_0402_5% 1x16 11
BPM#[1]
1
220_0402_5%
BM31
BPM#[2]
2
RC153
VCCST_PWRGD 1 2 VCCST_PWRGD_CPU H13 BT30

<37,38> VCCST_PWRGD VCCST_PWRGD BPM#[3]
RC78 60.4_0402_1%
H_PWRGD BT31
VR_SVID_DATA <20> H_PWRGD PLTRST_CPU# PROCPWRGD CPU_XDP_TDO
BP35 BT28 @
<16> PLTRST_CPU# RESET# PROC_TDO PAD~D T184
2
H_PM_SYNC BM34 BL32 CPU_XDP_TDI

<16> H_PM_SYNC PM_SYNC PROC_TDI PAD~D @ T185
H_PM_DOWN 1 2 H_PM_DOWN_R BP31 BP28 CPU_XDP_TMS
<16> H_PM_DOWN PM_DOWN PROC_TMS PAD~D @ T180
CPU_VIDALERT# H_PECI RC168 20_0402_5% BT34 BR28 CPU_XDP_TCLK CFG7
<16,37> H_PECI PECI PROC_TCK PAD~D @ T181
H_THERMTRIP# 1 2 H_THERMTRIP#_R J31
<14,15,16,38> H_THERMTRIP# THERMTRIP#
1
RC169 0_0402_5% BP30 CPU_XDP_TRST# PEG Training
H_SKTOCC# PROC_TRST# CPU_XDP_PREQ# PAD~D @ T179
1 2 BR33 BL30 @
SKL_CNL# SKTOCC# PROC_PREQ# CPU_XDP_PRDY# PAD~D @ T190
RC3191 2 0_0402_5% BN1 BP27
PAD~D @ T189
RC325 (default) PEG Train
PROC_SELECT# PROC_PRDY#
@ RC171 0_0402_5%
H_CATERR#
1K_0402_5% immediately following 1
BM30 RESET# de-assertion
CATERR#
2
BT25
CFG_RCOMP PEG Wait for BIOS for
training 0
A H_PWRGD VCCST_PWRGD H_THERMTRIP# H_PROCHOT# 5 OF 14 1 A
RF Request RC114
100P_0402_50V8J
ESD@
100P_0402_50V8J
ESD@
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
SKL-H_BGA1440 49.9_0402_1%
1
VR_SVID_CLK 1 2
CC300
CC301
@RF@ CC325 33P_0402_50V8J

2
2
CC323
CC324
Place close CPU side
Title
ESD Request:place near CPU side
KBL-H (2/8)
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
<14> DDR_A_DQS#[0..7]
<14> DDR_A_DQS[0..7]
<15> DDR_B_DQS#[0..7]
<15> DDR_B_DQS[0..7]
D D
UC1A SKYLAKE_HALO UC1B SKYLAKE_HALO

Rev_1.0 Interleave / Non-Interleaved Rev_1.0
<14> DDR_A_D[0..15] DDR_A_D0 DDR_A_CLK0 <14> DDR_A_D[16..31] DDR_A_D16 DDR_B_CLK0
BR6 AG1 BT11 AM9
DDR_A_D1 DDR0_DQ[0] DDR0_CKP[0] DDR_A_CLK#0 DDR_A_CLK0 <14> DDR_A_D17 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKP[0] DDR_B_CLK#0 DDR_B_CLK0 <15>
BT6 AG2 BR11 AN9
DDR_A_D2 DDR0_DQ[1] DDR0_CKN[0] DDR_A_CLK#1 DDR_A_CLK#0 <14> DDR_A_D18 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[0] DDR_B_CLK#1 DDR_B_CLK#0 <15>
BP3 AK1 BT8 AM8
DDR_A_D3 DDR0_DQ[2] DDR0_CKN[1] DDR_A_CLK1 DDR_A_CLK#1 <14> DDR_A_D19 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKN[1] DDR_B_CLK1 DDR_B_CLK#1 <15>
BR3 AK2 BR8 AM7
DDR_A_D4 DDR0_DQ[3] DDR0_CKP[1] DDR_A_CLK1 <14> DDR_A_D20 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <15>
BN5 AL3 BP11 AM11
DDR_A_D5 BP6 DDR0_DQ[4] DDR0_CLKP[2] AK3 DDR_A_D21 BN11 DDR1_DQ[4]/DDR0_DQ[20] DDR1_CLKP[2] AM10
DDR_A_D6 BP2 DDR0_DQ[5] DDR0_CLKN[2] AL2 DDR_A_D22 BP8 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CLKN[2] AJ10
DDR_A_D7 BN3 DDR0_DQ[6] DDR0_CLKP[3] AL1 DDR_A_D23 BN8 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CLKP[3] AJ11
DDR_A_D8 BL4 DDR0_DQ[7] DDR0_CLKN[3] DDR_A_D24 BL12 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CLKN[3]
DDR_A_D9 BL5 DDR0_DQ[8] AT1 DDR_A_CKE0 DDR_A_D25 BL11 DDR1_DQ[8]/DDR0_DQ[24] AT8 DDR_B_CKE0
DDR_A_D10 DDR0_DQ[9] DDR0_CKE[0] DDR_A_CKE1 DDR_A_CKE0 <14> DDR_A_D26 DDR1_DQ[9]/DDR0_DQ[25] DDR1_CKE[0] DDR_B_CKE1 DDR_B_CKE0 <15>
BL2 AT2 BL8 AT10
DDR_A_D11 DDR0_DQ[10] DDR0_CKE[1] DDR_A_CKE1 <14> DDR_A_D27 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CKE[1] DDR_B_CKE1 <15>
BM1 AT3 BJ8 AT7
DDR_A_D12 BK4 DDR0_DQ[11] DDR0_CKE[2] AT5 DDR_A_D28 BJ11 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CKE[2] AT11
DDR_A_D13 BK5 DDR0_DQ[12] DDR0_CKE[3] DDR_A_D29 BJ10 DDR1_DQ[12]/DDR0_DQ[28] DDR1_CKE[3]
DDR_A_D14 BK1 DDR0_DQ[13] AD5 DDR_A_CS#0 DDR_A_D30 BL7 DDR1_DQ[13]/DDR0_DQ[29] AF11 DDR_B_CS#0
DDR_A_D15 DDR0_DQ[14] DDR0_CS#[0] DDR_A_CS#1 DDR_A_CS#0 <14> DDR_A_D31 DDR1_DQ[14]/DDR0_DQ[30] DDR1_CS#[0] DDR_B_CS#1 DDR_B_CS#0 <15>
BK2 AE2 BJ7 AE7
DDR0_DQ[15] DDR0_CS#[1] DDR_A_CS#1 <14> <14> DDR_A_D[48..63] DDR_A_D48 DDR1_DQ[15]/DDR0_DQ[31] DDR1_CS#[1] DDR_B_CS#1 <15>
AD2 BG11 AF10
DDR0_CS#[2] AE5 DDR_A_D49 BG10 DDR1_DQ[16]/DDR0_DQ[48] DDR1_CS#[2] AE10
<14> DDR_A_D[32..47] Interleave / Non-Interleaved
DDR_A_D32 BG4 DDR0_CS#[3] DDR_A_D50 BG8 DDR1_DQ[17]/DDR0_DQ[49] DDR1_CS#[3]
DDR_A_D33 BG5 DDR0_DQ[16]/DDR0_DQ[32] AD3 DDR_A_ODT0 DDR_A_D51 BF8 DDR1_DQ[18]/DDR0_DQ[50] AF7 DDR_B_ODT0
DDR_A_D34 DDR0_DQ[17]/DDR0_DQ[33] DDR0_ODT[0] DDR_A_ODT1 DDR_A_ODT0 <14> DDR_A_D52 DDR1_DQ[19]/DDR0_DQ[51] DDR1_ODT[0] DDR_B_ODT1 DDR_B_ODT0 <15>
BF4 AE4 BF11 AE8
DDR_A_D35 DDR0_DQ[18]/DDR0_DQ[34] DDR0_ODT[1] DDR_A_ODT1 <14> DDR_A_D53 DDR1_DQ[20]/DDR0_DQ[52] DDR1_ODT[1] DDR_B_ODT1 <15>
BF5 AE1 BF10 AE9
DDR_A_D36 BG2 DDR0_DQ[19]/DDR0_DQ[35] DDR0_ODT[2] AD4 DDR_A_D54 BG7 DDR1_DQ[21]/DDR0_DQ[53] DDR1_ODT[2] AE11
DDR_A_D37 BG1 DDR0_DQ[20]/DDR0_DQ[36] DDR0_ODT[3] DDR_A_D55 BF7 DDR1_DQ[22]/DDR0_DQ[54] DDR1_ODT[3]
DDR_A_D38 BF1 DDR0_DQ[21]/DDR0_DQ[37] DDR3L / LPDDR3 / DDR4 DDR_A_D56 BB11 DDR1_DQ[23]/DDR0_DQ[55] DDR3L / LPDDR3 / DDR4
DDR_A_D39 DDR0_DQ[22]/DDR0_DQ[38] DDR_A_BA0 DDR_A_D57 DDR1_DQ[24]/DDR0_DQ[56] DDR_B_MA16 DDR_B_MA[0..16] <15>
BF2 AH5 BC11 AH10
C DDR_A_D40 DDR0_DQ[23]/DDR0_DQ[39] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_BA1 DDR_A_BA0 <14> DDR_A_D58 DDR1_DQ[25]/DDR0_DQ[57] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_MA14 C
BD2 AH1 BB8 AH11
DDR_A_D41 DDR0_DQ[24]/DDR0_DQ[40] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_BG0 DDR_A_BA1 <14> DDR_A_D59 DDR1_DQ[26]/DDR0_DQ[58] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_MA15
BD1 AU1 BC8 AF8
DDR_A_D42 DDR0_DQ[25]/DDR0_DQ[41] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_BG0 <14> DDR_A_D60 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
BC4 BC10
DDR_A_D43 DDR0_DQ[26]/DDR0_DQ[42] DDR_A_MA16 DDR_A_MA[0..16] <14> DDR_A_D61 DDR1_DQ[28]/DDR0_DQ[60] DDR_B_BA0
BC5 AH4 BB10 AH8
DDR_A_D44 DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_MA14 DDR_A_D62 DDR1_DQ[29]/DDR0_DQ[61] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_BA1 DDR_B_BA0 <15>
BD5 AG4 BC7 AH9
DDR_A_D45 DDR0_DQ[28]/DDR0_DQ[44] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_MA15 DDR_A_D63 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_BG0 DDR_B_BA1 <15>
BD4 AD1 BB7 AR9
DDR_A_D46 DDR0_DQ[29]/DDR0_DQ[45] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] <15> DDR_B_D[16..31] DDR_B_D16 DDR1_DQ[31]/DDR0_DQ[63] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_BG0 <15>
BC1 AA11
DDR_A_D47 BC2 DDR0_DQ[30]/DDR0_DQ[46] AH3 DDR_A_MA0 DDR_B_D17 AA10 DDR1_DQ[32]/DDR1_DQ[16] AJ9 DDR_B_MA0
<15> DDR_B_D[0..15] DDR_B_D0 DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_A_MA1 DDR_B_D18 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR_B_MA1
AB1 AP4 AC11 AK6
DDR_B_D1 AB2 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AN4 DDR_A_MA2 DDR_B_D19 AC10 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] AK5 DDR_B_MA2
DDR_B_D2 AA4 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AP5 DDR_A_MA3 DDR_B_D20 AA7 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] AL5 DDR_B_MA3
DDR_B_D3 AA5 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[3] AP2 DDR_A_MA4 DDR_B_D21 AA8 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] AL6 DDR_B_MA4
DDR_B_D4 AB5 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[4] AP1 DDR_A_MA5 DDR_B_D22 AC8 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] AM6 DDR_B_MA5
DDR_B_D5 AB4 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] AP3 DDR_A_MA6 DDR_B_D23 AC7 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AN7 DDR_B_MA6
DDR_B_D6 AA2 DDR0_DQ[37]/DDR1_DQ[5] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AN1 DDR_A_MA7 DDR_B_D24 W8 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] AN10 DDR_B_MA7
DDR_B_D7 AA1 DDR0_DQ[38]/DDR1_DQ[6] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AN3 DDR_A_MA8 DDR_B_D25 W7 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AN8 DDR_B_MA8
DDR_B_D8 V5 DDR0_DQ[39]/DDR1_DQ[7] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AT4 DDR_A_MA9 DDR_B_D26 V10 DDR1_DQ[41]/DDR1_DQ[25] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AR11 DDR_B_MA9
DDR_B_D9 V2 DDR0_DQ[40]/DDR1_DQ[8] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] AH2 DDR_A_MA10 DDR_B_D27 V11 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] AH7 DDR_B_MA10
DDR_B_D10 U1 DDR0_DQ[41]/DDR1_DQ[9] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] AN2 DDR_A_MA11 DDR_B_D28 W11 DDR1_DQ[43]/DDR1_DQ[27] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AN11 DDR_B_MA11
DDR_B_D11 U2 DDR0_DQ[42]/DDR1_DQ[10] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] AU4 DDR_A_MA12 DDR_B_D29 W10 DDR1_DQ[44]/DDR1_DQ[28] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AR10 DDR_B_MA12
DDR_B_D12 V1 DDR0_DQ[43]/DDR1_DQ[11] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] AE3 DDR_A_MA13 DDR_B_D30 V7 DDR1_DQ[45]/DDR1_DQ[29] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AF9 DDR_B_MA13
DDR_B_D13 V4 DDR0_DQ[44]/DDR1_DQ[12] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU2 DDR_A_BG1 DDR_B_D31 V8 DDR1_DQ[46]/DDR1_DQ[30] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AR7 DDR_B_BG1
DDR_B_D14 DDR0_DQ[45]/DDR1_DQ[13] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_ACT# DDR_A_BG1 <14> DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_ACT# DDR_B_BG1 <15>
U5 AU3 AT9
DDR_B_D15 DDR0_DQ[46]/DDR1_DQ[14] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR_A_ACT# <14> <15> DDR_B_D[48..63] DDR_B_D48 DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_ACT# <15>
U4 R11
<15> DDR_B_D[32..47] DDR_B_D32 DDR0_DQ[47]/DDR1_DQ[15] DDR_A_PARITY DDR_B_D49 DDR1_DQ[48]
R2 AG3 P11
DDR_B_D33 DDR0_DQ[48]/DDR1_DQ[32] DDR0_PAR DDR_A_ALERT# DDR_A_PARITY <14> DDR_B_D50 DDR1_DQ[49] DDR_B_PARITY
P5 AU5 P7 AJ7
DDR_B_D34 DDR0_DQ[49]/DDR1_DQ[33] DDR0_ALERT# DDR_A_ALERT# <14> DDR_B_D51 DDR1_DQ[50] DDR1_PAR DDR_B_ALERT# DDR_B_PARITY <15>
R4 R8 AR8
DDR_B_D35 DDR0_DQ[50]/DDR1_DQ[34] DDR_A_DQS#0 DDR_B_D52 DDR1_DQ[51] DDR1_ALERT# DDR_B_ALERT# <15>
P4 BR5 R10
DDR_B_D36 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[0] DDR_A_DQS#1 DDR_A_DQS#0 <14> DDR_B_D53 DDR1_DQ[52]
R5 BL3 P10 Interleave / Non-Interleaved
DDR_B_D37 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[1] DDR_A_DQS#1 <14> DDR_B_D54 DDR1_DQ[53] DDR_A_DQS#2
P2 R7 BP9
DDR_B_D38 DDR0_DQ[53]/DDR1_DQ[37] DDR_B_D55 DDR1_DQ[54] DDR1_DQSN[0]/DDR0_DQSN[2] DDR_A_DQS#3 DDR_A_DQS#2 <14>
R1 Interleave / Non-Interleaved P8 BL9
DDR_B_D39 DDR0_DQ[54]/DDR1_DQ[38] DDR_A_DQS#4 DDR_B_D56 DDR1_DQ[55] DDR1_DQSN[1]/DDR0_DQSN[3] DDR_A_DQS#6 DDR_A_DQS#3 <14>
P1 BG3 L11 BG9
DDR_B_D40 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[2]/DDR0_DQSN[4] DDR_A_DQS#5 DDR_A_DQS#4 <14> DDR_B_D57 DDR1_DQ[56] DDR1_DQSN[2]/DDR0_DQSN[6] DDR_A_DQS#7 DDR_A_DQS#6 <14>
M4 BD3 M11 BC9
DDR_B_D41 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSN[3]/DDR0_DQSN[5] DDR_B_DQS0 DDR_A_DQS#5 <14> DDR_B_D58 DDR1_DQ[57] DDR1_DQSN[3]/DDR0_DQSN[7] DDR_B_DQS#2 DDR_A_DQS#7 <14>
M1 AB3 L7 AC9
DDR_B_D42 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSP[4]/DDR1_DQSP[0] DDR_B_DQS1 DDR_B_DQS0 <15> DDR_B_D59 DDR1_DQ[58] DDR1_DQSN[4]/DDR1_DQSN[2] DDR_B_DQS#3 DDR_B_DQS#2 <15>
L4 V3 M8 W9
DDR_B_D43 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] DDR_B_DQS4 DDR_B_DQS1 <15> DDR_B_D60 DDR1_DQ[59] DDR1_DQSN[5]/DDR1_DQSN[3] DDR_B_DQS#6 DDR_B_DQS#3 <15>
B L2 R3 L10 R9 B
DDR_B_D44 DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQSP[6]/DDR1_DQSP[4] DDR_B_DQS5 DDR_B_DQS4 <15> DDR_B_D61 DDR1_DQ[60] DDR1_DQSN[6] DDR_B_DQS#7 DDR_B_DQS#6 <15>
M5 M3 M10 M9
DDR_B_D45 DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_A_DQS0 DDR_B_DQS5 <15> DDR_B_D62 DDR1_DQ[61] DDR1_DQSN[7] DDR_B_DQS#7 <15>
M2 BP5 M7
DDR_B_D46 DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQSP[0] DDR_A_DQS1 DDR_A_DQS0 <14> DDR_B_D63 DDR1_DQ[62] DDR_A_DQS2
L5 BK3 L8 BR9
DDR_B_D47 DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQSP[1] DDR_A_DQS4 DDR_A_DQS1 <14> DDR1_DQ[63] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_A_DQS3 DDR_A_DQS2 <14>
L1 BF3 BJ9
DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS5 DDR_A_DQS4 <14> DDR1_DQSP[1]/DDR0_DQSP[3] DDR_A_DQS6 DDR_A_DQS3 <14>
BC3 AW11 BF9
DDR0_DQSP[3]/DDR0_DQSP[5] DDR_B_DQS#0 DDR_A_DQS5 <14> DDR1_ECC[0] DDR1_DQSP[2]/DDR0_DQSP[6] DDR_A_DQS7 DDR_A_DQS6 <14>
BA2 AA3 AY11 BB9
DDR0_ECC[0] DDR0_DQSN[4]/DDR1_DQSN[0] DDR_B_DQS#1 DDR_B_DQS#0 <15> DDR1_ECC[1] DDR1_DQSP[3]/DDR0_DQSP[7] DDR_B_DQS2 DDR_A_DQS7 <14>
BA1 U3 AY8 AA9
DDR0_ECC[1] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_B_DQS#4 DDR_B_DQS#1 <15> DDR1_ECC[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR_B_DQS3 DDR_B_DQS2 <15>
AY4 P3 AW8 V9
DDR0_ECC[2] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_B_DQS#5 DDR_B_DQS#4 <15> DDR1_ECC[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR_B_DQS6 DDR_B_DQS3 <15>
AY5 L3 AY10 P9
DDR0_ECC[3] DDR0_DQSN[7]/DDR1_DQSN[5] DDR_B_DQS#5 <15> DDR1_ECC[4] DDR1_DQSP[6] DDR_B_DQS7 DDR_B_DQS6 <15>
BA5 AW10 L9
DDR0_ECC[4] DDR1_ECC[5] DDR1_DQSP[7] DDR_B_DQS7 <15>
BA4 AY3 AY7
AY1 DDR0_ECC[5] DDR0_DQSP[8] BA3 AW7 DDR1_ECC[6] AW9
AY2 DDR0_ECC[6] DDR0_DQSN[8] DDR1_ECC[7] DDR1_DQSP[8] AY9
DDR0_ECC[7] DDR1_DQSN[8]
DDR CH - A DDR CH - B
RC5 1 2 121_0402_1% DDR_RCOMP0 G1 BN13
DDR_RCOMP1 DDR_RCOMP[0] DDR_VREF_CA +DDR_VREF_CA
RC6 1 2 75_0402_1% H1 BP13
DDR_RCOMP2 DDR_RCOMP[1] DDR0_VREF_DQ PAD~D @ T199
1 OF 14 RC7 1 2 100_0402_1% J2 2 OF 14 BR13 +DDR_VREF_B_DQ
DDR_RCOMP[2] DDR1_VREF_DQ
SKL-H_BGA1440 SKL-H_BGA1440
Trace width=12-15 mils

,Spacing=20mil
Max length= 500 mils.
A A
Title
KBL-H (3/8)
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
D D
SKYLAKE_HALO
UC1D
Rev_1.0
CPU_DP1_P0 K36 D29 EDP_TXP0
<26> CPU_DP1_P0 CPU_DP1_N0 K37 DDI1_TXP[0] EDP_TXP[0] E29 EDP_TXN0 EDP_TXP0 <32>
<26> CPU_DP1_N0 CPU_DP1_P1 J35 DDI1_TXN[0] EDP_TXN[0] F28 EDP_TXP1 EDP_TXN0 <32>
<26> CPU_DP1_P1 CPU_DP1_N1 J34 DDI1_TXP[1] EDP_TXP[1] E28 EDP_TXN1 EDP_TXP1 <32>
<26> CPU_DP1_N1 CPU_DP1_P2 H37 DDI1_TXN[1] EDP_TXN[1] B29 EDP_TXN1 <32>
<26> CPU_DP1_P2 CPU_DP1_N2 DDI1_TXP[2] EDP_TXN[2]
HDMI <26> CPU_DP1_N2
H36
DDI1_TXN[2] EDP_TXP[2]
A29
CPU_DP1_P3 J37 B28
<26> CPU_DP1_P3 CPU_DP1_N3 J38 DDI1_TXP[3] EDP_TXN[3] C28
<26> CPU_DP1_N3 DDI1_TXN[3] EDP_TXP[3]
D27 C26 EDP_AUXP
DDI1_AUXP EDP_AUXP EDP_AUXN EDP_AUXP <32>
E27 B26
DDI1_AUXN EDP_AUXN EDP_AUXN <32>
CPU_DP2_P0 H34
<28> CPU_DP2_P0 CPU_DP2_N0 H33 DDI2_TXP[0]
<28> CPU_DP2_N0 CPU_DP2_P1 F37 DDI2_TXN[0] A33
<28> CPU_DP2_P1 CPU_DP2_N1 DDI2_TXP[1] EDP_DISP_UTIL PAD~D @ T194
C G38 C
<28> CPU_DP2_N1 CPU_DP2_P2 F34 DDI2_TXN[1] +1.0VS_VCCIO
<28> CPU_DP2_P2 CPU_DP2_N2 DDI2_TXP[2] EDP_COMP
Type C <28> CPU_DP2_N2
F35
DDI2_TXN[2] EDP_RCOMP
D37
CPU_DP2_P3 E37
<28> CPU_DP2_P3 CPU_DP2_N3 E36 DDI2_TXP[3] EDP_COMP 1 2
<28> CPU_DP2_N3 DDI2_TXN[3] RC1 24.9_0402_1%
CPU_DP2_AUXP F26
<28,29> CPU_DP2_AUXP CPU_DP2_AUXN DDI2_AUXP
<28,29> CPU_DP2_AUXN E26
DDI2_AUXN
CPU_DP3_P0 C34
<25> CPU_DP3_P0 CPU_DP3_N0 D34 DDI3_TXP[0] Trace width=5 mils
<25> CPU_DP3_N0 CPU_DP3_P1 B36 DDI3_TXN[0] ,Spacing=20mil
<25> CPU_DP3_P1 CPU_DP3_N1 B34 DDI3_TXP[1] Max length= 600 mils.
<25> CPU_DP3_N1 CPU_DP3_P2 F33 DDI3_TXN[1]
<25> CPU_DP3_P2 CPU_DP3_N2 E33 DDI3_TXP[2]
<25> CPU_DP3_N2 CPU_DP3_P3 C33 DDI3_TXN[2]
<25> CPU_DP3_P3 CPU_DP3_N3 DDI3_TXP[3]
WIGIG , VGA <25> CPU_DP3_N3
B33
DDI3_TXN[3] AUD_AZACPU_SCLK
G27 AUD_AZACPU_SCLK <20>
CPU_DP3_AUXP A27 PROC_AUDIO_CLK G25 AUD_AZACPU_SDO
<25> CPU_DP3_AUXP DDI3_AUXP PROC_AUDIO_SDI AUD_AZACPU_SDO <20>
<25> CPU_DP3_AUXN CPU_DP3_AUXN B27 G29 AUD_AZACPU_SDI
DDI3_AUXN 4 OF 14 PROC_AUDIO_SDO
SKL-H_BGA1440
AUD_AZACPU_SDI 1 2AUD_AZACPU_SDI_R
AUD_AZACPU_SDI_R <20>
RC66 20_0402_5%
B B
A A
Title
KBL-H (4/8)
A
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
D D
+VCC_EDRAM UC1J SKYLAKE_HALO

Rev_1.0
3.3A
BJ17
BJ19 VCCOPC
BJ20 VCCOPC
BK17 VCCOPC
BK19 VCCOPC
BK20 VCCOPC
BL16 VCCOPC
BL17 VCCOPC
BL18 VCCOPC
BL19 VCCOPC
BL20 VCCOPC UC1K SKYLAKE_HALO
BL21 VCCOPC Rev_1.0
+VCC_EDRAM_ED2 BM17 VCCOPC
BN17 VCCOPC D1 BM33
VCCOPC PAD~D @ T1 RSVD_TP RSVD_TP T26 @ PAD~D
PAD~D @ T2 E1 BL33
RSVD_TP RSVD_TP T25 @ PAD~D
BJ23 PAD~D @ T3 E3
BJ26 RSVD E2 RSVD_TP BJ14
RSVD PAD~D @ T4 RSVD_TP RSVD_TP T28 @ PAD~D
BJ27 BJ13
RSVD RSVD_TP T27 @ PAD~D
BK23 PAD~D @ T5 BR1
BK26 RSVD BT2 RSVD_TP BK28
RSVD PAD~D @ T6 RSVD_TP RSVD T29 @ PAD~D
BK27 BJ28
RSVD RSVD T30 @ PAD~D
BL23 PAD~D @ T7 BN35
C BL24 RSVD RSVD BJ18 C
BL25 RSVD J24 VSS
RSVD PAD~D @ T9 RSVD
BL26 PAD~D @ T10 H24 BJ16
BL27 RSVD BN33 RSVD RSVD_TP BK16 T31 @ PAD~D
RSVD PAD~D @ T11 RSVD RSVD_TP T32 @ PAD~D
BL28 PAD~D @ T8 BL34
BM24 RSVD RSVD
RSVD N29 BK24
PAD~D @ T14 RSVD RSVD_TP T34 @ PAD~D
PAD~D @ T13 R14 BJ24
BL15 AE29 RSVD RSVD_TP T33 @ PAD~D
VCCOPC_SENSE PAD~D @ T15 RSVD
BM16 PAD~D @ T12 AA14 BK21
VSSOPC_SENSE RSVD RSVD BJ21 T36 @ PAD~D
BL22 A36 RSVD T35 @ PAD~D
BM22 RSVD A37 RSVD BT17
RSVD RSVD RSVD BR17 T37 @ PAD~D
PCH_2_CPU_TRIGGER H23 RSVD T38 @ PAD~D
3.2A <22> PCH_2_CPU_TRIGGER CPU_2_PCH_TRIGGER_R PROC_TRIGIN
+VCC_EOPIO
BP15 J23 BK18
BR15 VCCEOPIO PROC_TRIGOUT VSS
BT15 VCCEOPIO TP_SKL_F30 F30 BJ34
VCCEOPIO TP_SKL_E30 E30 RSVD RSVD_TP BJ33 T39 @ PAD~D
BP16 RSVD RSVD_TP T40 @ PAD~D
+VCC_EOPIO_ED2 RSVD
BR16 PAD~D @ T18
B30
BT16 RSVD C30 RSVD
RSVD PAD~D @ T19 RSVD G13
RSVD T42 @ PAD~D
G3 AJ8
PAD~D @ T21 RSVD RSVD T41 @ PAD~D
BN15 PAD~D @ T20
J3 BL31
VCCEOPIO_SENSE RSVD RSVD T44 @ PAD~D
BM15
VSSEOPIO_SENSE B2
NCTF T43 @ PAD~D
BP17 B38
RSVD NCTF T45 @ PAD~D
BN16 BP1
PAD~D @ T23
BR35 BR2
PAD~D @ T24
BR31 C1
BM14 PAD~D @ T22
BH30 C38
VCC_OPC_1P8 RSVD NCTF T49 @ PAD~D
BL14 11 OF 14
VCC_OPC_1P8
BJ35 SKL-H_BGA1440
B BJ36 RSVD B
RSVD
AT13
AW13 ZVM#
MSM#
AU13
AY13 ZVM2#
MSM2#
BT29
BR25 OPC_RCOMP
BP25 OPCE_RCOMP
OPCE_RCOMP2 CPU_2_PCH_TRIGGER 1 2 CPU_2_PCH_TRIGGER_R
<22> CPU_2_PCH_TRIGGER
10 OF 14 RC177 30_0402_5%
SKL-H_BGA1440
TP_SKL_F30 1 2
TP_SKL_E30 @ RC178 1 2 0_0402_5%
@ RC179 0_0402_5%
A A
Title
KBL-H (5/8)
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+VCC_GT
+VCC_GT
+VCC_SA +1.2V_MEM
BG34
UC1H SKYLAKE_HALO
Rev_1.0 UC1I SKYLAKE_HALO +VCCPLL_OC source PDDG page19, if don`t support DS3, contact to VDDQ directly
VCCGT AV29
Rev_1.0 12A +1.2V_MEM +VCC_SFR_OC
BG35 VCCGT J30 AA6
VCCGT AV30 VCCSA VDDQ
BG36 VCCGT K29 AE12
BH33 VCCGT K30 AF5
BH34 VCCGT K31 AF6 1 2
BH35 VCCGT K32 AG5 @ RZ119 0_0402_5%
D VCCGT AV34 VCCSA VDDQ D
BH36 VCCGT K33 AG9
BH37 VCCGT K34 AJ12
BH38 VCCGT K35 AL11 UZ26
VCCGT AW14 VCCSA VDDQ
BJ37 VCCGT L31 AP6 1
VCCGT AW31 VCCSA VDDQ VIN1
BJ38 VCCGT L32 AP7 1 2 2
VCCGT AW32 VCCSA VDDQ VIN2
BL36 VCCGT L35 AR12 CZ102 1U_0402_6.3V6K
BL37 VCCGT L36 AR6 7 6 1 2
VCCGT AW34 VCCSA VDDQ VIN thermal VOUT
BM36 VCCGT L37 AT12 CZ103 0.1U_0201_10V6K
BM37 VCCGT L38 AW6 3
VCCGT AW36 VCCSA VDDQ +5V_ALW VBIAS
BN36 VCCGT M29 AY6
VCCGT AW37 VCCSA VDDQ VCCSTG_EN
BN37 VCCGT M30 J5 1 2 4 5
VCCGT AW38 VCCSA VDDQ ON GND
BN38 VCCGT M31 J6 RZ120 0_0402_5%
VCCGT AY29 VCCSA VDDQ
BP37 VCCGT M32 K12
VCCGT AY30 VCCSA VDDQ +3.3V_ALW
BP38 VCCGT M33 K6 TPS22961DNYR_WSON8
VCCGT AY31 VCCSA VDDQ @ CZ104
BR37 VCCGT M34 L12
BT37 VCCGT M35 L6 1 2
BE38 VCCGT M36 R6
BF13 VCCGT T6 0.1U_0402_10V7K
VCCGT AY37 VDDQ
5
BF14 VCCGT W6
VCCGT AY38 VDDQ
BF29 VCCGT AG12 1
P
VCCGT BA13 +1.0VS_VCCIO VCCIO <20,37,46,51,53> SIO_SLP_SUS# B
BF30 VCCGT G15 Y12 +VCC_VDDQ_CLK
4
VCCGT BA14 VCCIO VDDQC Y
BF31 VCCGT G17 2
VCCGT BA29 VCCIO <11,20,21,37,50,53> SIO_SLP_S4# A
G
BF32 VCCGT G19 BH13 @ UZ34
VCCGT BA30 VCCIO VCCPLL_OC +VCC_SFR_OC
BF35 VCCGT G21 G11 TC7SH08FU_SSOP5
VCCGT BA31 VCCIO VCCPLL_OC
3
BF36 VCCGT H15
VCCGT BA32 VCCIO
BF37 VCCGT H16
VCCGT BA33 VCCIO
BF38 VCCGT H17 H30 +1.0V_VCCST
VCCGT BA34 VCCIO VCCST
BG29 VCCGT H19
VCCGT BA35 VCCIO
BG30 VCCGT H20 H29
VCCGT BA36 VCCIO VCCSTG +1.0V_VCCSTG
BG31 VCCGT H21
VCCGT BB13 VCCIO +VCC_FUSEPRG
BG32 VCCGT H26 G30 1 2 +1.0V_VCCSTG
VCCGT BB14 VCCIO VCCSTG
BG33 VCCGT H27 RC326 0_0603_5%
VCCGT BB31 VCCIO
BC36 VCCGT J15 H28
VCCGT BB32 VCCIO VCCPLL +1.0V_VCCSFR
BC37 VCCGT J16 J28
VCCGT BB33 VCCIO VCCPLL
BC38 VCCGT J17
C VCCGT BB34 VCCIO +VCC_SFR_OC C
BD13 VCCGT J19
VCCGT BB35 VCCIO
BD14 VCCGT J20 M38 VCC_SA_SENSE <54>
VCCGT BB36 VCCIO VCCSA_SENSE
BD29 VCCGT J21 M37
VCCGT BB37 VCCIO VSSSA_SENSE VSS_SA_SENSE <54>
BD30 VCCGT J26
VCCGT BB38 VCCIO
BD31 VCCGT J27 H14 1
2.2P_0402_50V8C
VCCGT BC29 VCCIO VCCIO_SENSE VCC_IO_SENSE <52>
BD32 VCCGT J14 VSS_IO_SENSE <52>
VCCGT BC30 VSSIO_SENSE
BD33 VCCGT
RF@ CC322
VCCGT BC31
BD34 VCCGT
VCCGT BC32 2
BD35 VCCGT
VCCGT BC35
BD36 VCCGT
VCCGT BE33
BE31 VCCGT
VCCGT BE34
BE32 VCCGT
VCCGT BE35
BE37 VCCGT 9 OF 14
VCCGT BE36
VCCGT
8 OF 14 SKL-H_BGA1440
+VCC_VDDQ_CLK +1.2V_MEM
RF Request
SKL-H_BGA1440
1 2
RC220 0_0402_5%
+1.0V_VCCSTG +1.0V_VCCST
1 2
@ RZ151 0_0402_5%
B B
+1.0V_VCCSTG source +1.0V_VCCSTG
+1.0V_VCCST source
1
+1.0V_PRIM
PJP2 +1.0V_PRIM
UZ19 PAD-OPEN1x1m
1 UZ21
2 VIN1 1 +1.0V_VCCST +1.0V_VCCSFR
VIN2 2 VIN1
VIN2
2
+5V_ALW 7 6 +1.0V_VCCSTG_C 1 2 PJP1

VIN thermal VOUT CZ106 0.1U_0402_10V7K +5V_ALW 7 6 +1.0V_VCCST_C 2 1 1 2
3 VIN thermal VOUT RC304 0_0402_5%
VBIAS
1U_0402_6.3V6K
1 3
4 5 VBIAS PAD-OPEN1x1m
ON GND 1
CZ105
1U_0402_6.3V6K
4 5 1
ON GND
CZ100
0.1U_0402_10V7K
2
CZ101
TPS22961DNYR_WSON8
2 TPS22961DNYR_WSON8
4.4mohm/6A 2
TR=12.5us@Vin=1.05V 4.4mohm/6A
+3.3V_ALW TR=12.5us@Vin=1.05V
<11,20,21,37,50,53> SIO_SLP_S4#
5
1
P
<20,21,39,52> SIO_SLP_S0# IN1 VCCSTG_EN

4
2 O
<37,38,46,52> RUN_ON IN2
G
UZ35
3
SN74AHC1G08DCKR_SC70-5
A A
1 2
@ RZ320 0_0402_5%
Title
KBL-H (6/8)
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
PLACE CAP BACKSIDE

+VCC_VDDQ_CLK +1.0V_VCCSTG +1.0V_VCCSFR +1.0V_VCCST +VCC_SFR_OC +VCC_GT +VCC_GTU
D D
UC1N SKYLAKE_HALO
Rev_1.0
10U_0603_6.3V6M~D
+VCC_CORE +VCC_CORE
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 2 2 2 2 2 2 AJ29
AJ30 VCCGT
VCCGT AF29
CC185
CC186
CC195
CC192
CC191
CC210
CC209
AJ31 VCCGTX
VCCGT AF30 UC1G SKYLAKE_HALO
AJ32 VCCGTX
2 1 1 1 1 1 1 VCCGT AF31 Rev_1.0
AJ33 VCCGTX
VCCGT AF32
AJ34 VCCGTX
VCCGT AF33 AA13 V32
AJ35 VCCGTX VCC VCC
VCCGT AF34 AA31 V33
AJ36 VCCGTX VCC VCC
VCCGT AG13 AA32 V34
AK31 VCCGTX VCC VCC
VCCGT AG14 AA33 V35
AK32 VCCGTX VCC VCC
VCCGT AG31 AA34 V36
AK33 VCCGTX VCC VCC
VCCGT AG32 AA35 V37
AK34 VCCGTX VCC VCC
VCCGT AG33 AA36 V38
AK35 VCCGTX VCC VCC
+1.0VS_VCCIO VCCGT AG34 AA37 W13
AK36 VCCGTX VCC VCC
VCCGT AG35 AA38 W14
AK37 VCCGTX VCC VCC
PLACE CAP BACKSIDE VCCGT AG36 AB29 W29
AK38 VCCGTX VCC VCC
VCCGT AH13 AB30 W30
AL13 VCCGTX VCC VCC
VCCGT AH14 AB31 W31
For SKL-H 4+2 AL29
VCCGT
VCCGTX AH29 AB32 VCC VCC W32
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
AL30 VCCGTX VCC VCC
Remove VCCOPC/VCCEOPIO/ 1 AL31 VCCGT
VCCGTX
AH30
AH31
AB35
VCC VCC
W35
1
VCCGT AB36 W36
CC189
CC188
CC187
CC272
VCCOPC_1P8 Cap AL32
AL35 VCCGT
VCCGTX AH32 AB37 VCC VCC W37
VCCGTX AJ13 AB38 VCC VCC W38
AL36 VCCGT
VCCGTX VCC VCC
2
2
VCCGT AJ14 AC13 Y29
AL37 VCCGTX VCC VCC
AL38 VCCGT AC14 Y30
VCC VCC
AM13
AM14
VCCGT
VCCGT Reserve for Soldering AC29
AC30 VCC VCC
Y31
Y32
VCCGT AC31 VCC VCC Y33
AM29 VCC VCC
AM30 VCCGT AC32 Y34
VCCGT AC33 VCC VCC Y35
AM31 VCC VCC
AM32 VCCGT AC34 Y36
VCCGT AC35 VCC VCC L14
C AM33 VCC VCC C
AM34 VCCGT AC36 P29
VCCGT AD13 VCC VCC P30
+1.0V_VCCST AM35 VCC VCC
AM36 VCCGT AD14 P31
AN13 VCC VCC
AN14 VCCGT AD32 P33
AN31 VCC VCC
AN32 VCCGT AD34 P35
1U_0402_6.3V6K
1U_0402_6.3V6K
2 2 AN33 VCC VCC

AN34 VCCGT AD36 R13
VCCGT AD37 VCC VCC R31
CC193
CC194
AN35 VCC VCC

AN36 VCCGT AD38 R32
1 1 VCCGT AE13 VCC VCC R33
AN37 VCC VCC
AN38 VCCGT AE14 R34
VCCGT AE30 VCC VCC R35
AP13 VCC VCC
AP14 VCCGT AE31 R36
VCCGT AE32 VCC VCC R37
AP29 VCC VCC
Remove to Power (+VCC_SA cap) AP30
AP31
VCCGT
VCCGT
AE35
AE36 VCC VCC
R38
T29
VCCGT AE37 VCC VCC T30
AP32 VCC VCC
AP35 VCCGT AE38 T31
VCCGT AF35 VCC VCC T32
AP36 VCC VCC
AP37 VCCGT AF36 T35
VCCGT AF37 VCC VCC T36
+1.2V_MEM AP38 VCC VCC
PLACE CAP BACKSIDE AR29 VCCGT AF38 T37
+1.2V_MEM DECOUPLING AR30 VCCGT K13 VCC
VCC
VCC
VCC
T38
AR31 VCCGT K14 U29
VCCGT L13 VCC VCC U30
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
AR32 VCC VCC

AR33 VCCGT AH38 N13 U31
1 1 1 1 1 1 1 1 1 1 VCC_GT_SENSE <54> VCC VCC
AR34 VCCGT VCCGT_SENSE AH35 N14 U32
VCCGT VSSGTX_SENSE N30 VCC VCC U33
CC161
CC170
CC164
CC168
CC163
CC166
CC171
CC165
CC172
CC167
AR35 AH37 VCC VCC

AR36 VCCGT VSSGT_SENSE AH36 VSS_GT_SENSE <54> N31 U34
2 2 2 2 2 2 2 2 2 2 VCCGT VCCGTX_SENSE N32 VCC VCC U35 +VCC_CORE
AT14 VCC VCC
AT31 VCCGT N35 U36
VCCGT N36 VCC VCC V13
AT32 VCC VCC
1
100_0402_1%
AT33 VCCGT N37 V14
VCC VCC
RC140
B
AT34 VCCGT N38 V31 B
VCCGT P13 VCC VCC P14
AT35 VCC VCC
AT36 VCCGT
AT37 VCCGT
2
AT38 VCCGT
VCCGT AG37 VCC_SENSE
AU14 VCC_SENSE VCC_SENSE <54>
VCCGT AG38 VSS_SENSE
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
AU29 VSS_SENSE VSS_SENSE <54>

AU30 VCCGT
1
AU31 VCCGT
1
100_0402_1%
AU32 VCCGT 7 OF 14
RC141
VCCGT
CC81
CC82
CC83
CC84
AU35
2
AU36 VCCGT SKL-H_BGA1440

AU37 VCCGT
AU38 VCCGT
2
VCCGT 14 OF 14
SKL-H_BGA1440
VSS_SENSE 1 2 VCC_SENSE
@ RC221 49.9_0402_1%
A A
Title
KBL-H (7/8)
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
UC1L SKYLAKE_HALO
UC1F SKYLAKE_HALO UC1M SKYLAKE_HALO
Rev_1.0
Rev_1.0 Rev_1.0
C25
Y38 K1 BB4 AK30 C17 VSS
VSS VSS VSS VSS VSS C23
Y37 J36 BB3 AK29 C13 VSS
Y14 J33 BB2 AK4 C9 VSS
Y13 J32 BB1 AJ38 BT32 VSS
Y11 J25 BA38 AJ37 BT26 VSS
VSS VSS VSS VSS VSS BM29
D Y7 J7 BA10 AJ3 BT14 VSS D
W34 J4 BA9 AJ2 BT12 VSS
W33 H35 BA8 AJ1 BT9 VSS
W12 H32 BA7 AH34 BT5 VSS
W5 H25 BA6 AH33 BR36 VSS
W4 H22 B9 AH12 BR34 VSS
W3 H18 AY34 AH6 BR29 VSS
W2 H12 AY33 AG30 BR26 VSS
VSS VSS VSS VSS VSS BL38
W1 H11 AY14 AG29 BR24 VSS
V30 G28 AY12 AG11 BR21 VSS
V29 G26 AW30 AG10 BR18 VSS
VSS VSS VSS VSS VSS BK25
U38 G22 AW5 AG6 BR7 VSS
U37 G20 AW4 AF14 BP34 VSS
U6 G18 AW3 AF13 BP33 VSS
VSS VSS VSS VSS VSS BJ30
T34 G16 AW2 AF12 BP29 VSS
T33 G14 AW1 AF4 BP26 VSS
T14 G12 AV38 AF3 BP24 VSS
T13 G10 AV37 AF2 BP21 VSS
VSS VSS VSS VSS VSS BH11
T12 G9 AU34 AF1 BP18 VSS
T11 G8 AU33 AE34 BP14 VSS
T8 G4 AU10 AD30 BN34 VSS
T7 F36 AU9 AD29 BN31 VSS
VSS VSS VSS VSS VSS BG37
VSS VSS VSS VSS VSS BF34
C T2 F25 AT30 AD9 BN21 VSS C
VSS VSS VSS VSS VSS BF6
T1 F23 AT29 AD8 BN20 VSS
VSS VSS VSS VSS VSS BE30
R30 F21 AT6 AD7 BN19 VSS
R29 F19 AR38 AD6 BN18 VSS
R12 F17 AR37 AC38 BN14 VSS
P38 F15 AR14 AC37 BN12 VSS
VSS VSS VSS VSS VSS BD38
N34 F8 AR3 AC4 BN2 VSS
N33 F5 AR2 AC3 BM38 VSS
N12 F4 AR1 AC2 BM35 VSS
N11 F3 AP34 AC1 BM28 VSS
N10 F2 AP33 AB34 BM27 VSS
N9 E38 AP12 AB33 BM26 VSS
N8 E35 AP11 AB6 BM23 VSS
VSS VSS VSS VSS VSS BC33
N7 E34 AP10 AA30 BM21 VSS
N4 D33 AN30 A30 BM9 VSS
VSS VSS VSS VSS VSS BB30
N1 D26 AN6 A24 BL29 VSS
M14 D24 AN5 A22 BK29 VSS
M13 VSS VSS D22 AM38 VSS VSS A20 BK15 VSS
M12 VSS VSS D20 AM37 VSS VSS A18 BK14 VSS
M6 VSS VSS D18 AM12 VSS VSS A16 BJ32 VSS
L34 VSS VSS D16 AM5 VSS VSS A14 BJ31 VSS
L33 VSS VSS D14 AM4 VSS VSS A12 BJ25 VSS
B L30 VSS VSS D12 AM3 VSS VSS A10 BJ22 VSS B
L29 VSS VSS D10 AM2 VSS VSS A9 BH14 VSS
K38 D9 AM1 A6 BH12 NCTFVSS
VSS VSS VSS VSS VSS BT36
K11 D6 AL34 BH9 NCTFVSS
VSS VSS VSS VSS BT35
K10 D3 AL33 BH8 NCTFVSS
VSS VSS VSS VSS BT4
K9 C37 AL14 B37 BH5 NCTFVSS
VSS VSS VSS NCTFVSS VSS BT3
K8 C31 AL12 B3 BH4 NCTFVSS
VSS VSS VSS NCTFVSS VSS BR38
K7 C29 AL10 A34 BH1 NCTFVSS
K5 VSS VSS C27 AL9 VSS NCTFVSS A4 BG38 VSS
K4 VSS VSS AL8 VSS NCTFVSS A3 BG13 VSS
K3 VSS D38 AL7 VSS NCTFVSS BG12 VSS
K2 VSS NCTFVSS AL4 VSS BF33 VSS
VSS 6 OF 14 VSS BF12 VSS
13 OF 14 BE29 VSS
SKL-H_BGA1440 BE6 VSS
SKL-H_BGA1440 BD9 VSS
BC34 VSS
BC12 VSS
BB12 VSS
VSS 12 OF 14
SKL-H_BGA1440
A A
Title
KBL-H (8/8)
A
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
<8> DDR_A_DQS#[0..7]
<8> DDR_A_DQS[0..7]
<8> DDR_A_D[0..15]
<8> DDR_A_D[16..31]
<8> DDR_A_D[32..47] +1.2V_MEM +1.2V_MEM
<8> DDR_A_D[48..63]
JDIMM1
<8> DDR_A_MA[0..16]
1 2
DDR_A_D5 3 VSS1 VSS2 4 DDR_A_D4
5 DQ5 DQ4 6
9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS5 VSS6 12
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_A_D6
D Layout Note: DDR_A_D2 17 VSS8 DQ6 18 D
DQ7 VSS9
Place near JDIMM1 DDR_A_D3
19
21 VSS10 DQ2
20
22
DDR_A_D7
23 DQ3 VSS11 24 DDR_A_D12

DDR_A_D9 25 VSS12 DQ12 26
27 DQ13 VSS13 28 DDR_A_D13
DDR_A_D8 29 VSS14 DQ8 30
31 DQ9 VSS15 32 DDR_A_DQS#1
+1.2V_MEM 33 VSS16 DQS1_c 34 DDR_A_DQS1
35 DM1_n/DBI_n DQS1_t 36 +1.2V_MEM
39 DQ15 DQ14 40
DDR_A_D10 VSS19 VSS20 DDR_A_D11
330U_D3_2.5VY_R6M
41 42
DQ10 DQ11
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
43 44
DDR_A_D33 45 VSS21 VSS22 46 DDR_A_D32 RD11
1 DQ21 DQ20
1 1 1 1 1 1 1 1 @ 47 48 470_0402_1%
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD21
+ 49 50
51 DQ17 DQ16 52
2
2 2 2 2 2 2 2 2 2 DDR_A_DQS4 55 DQS2_c DM2_n/DBI2_n 56
57 DQS2_t VSS27 58 DDR_A_D38 1 2 DDR_DRAMRST#
DDR_A_D34 VSS28 DQ22 <15> DDR_DRAMRST#_R DDR4_DRAMRST#_PCH <20>
59 60 RD12 0_0402_5%
61 DQ23 VSS29 62 DDR_A_D39
DDR_A_D35 63 VSS30 DQ18 64
+2.5V_MEM 65 DQ19 VSS31 66 DDR_A_D44
DDR_A_D41 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_A_D45
DDR_A_D40 71 VSS34 DQ24 72
DQ25 VSS35
DDR_A_DQS#5
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
73 74
75 VSS36 DQS3_c 76 DDR_A_DQS5
1 1 1 1 1 1 1 1 1 1 1 1 DM3_n/DBI3_n DQS3_t
77 78
CD9
CD10
CD11
CD12
CD13
CD14
CD15
CD16
CD17
CD18
CD19
CD20
79 80
81 DQ30 DQ31 82
2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_D43 83 VSS39 VSS40 84 DDR_A_D46
85 DQ26 DQ27 86
87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
C DQS8_c DM8_n/DBI_n/NC C
97 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
103 CB2/NC VSS49 104
105 VSS50 CB7/NC 106
107 CB3/NC VSS51 108 DDR_DRAMRST#_R
DDR_A_CKE0 109 VSS52 RESET_n 110 DDR_A_CKE1 JDIMM1_EVENT# 1 2
Layout Note: <8> DDR_A_CKE0
111 CKE0 CKE1 112 DDR_A_CKE1 <8> 1
@ RD14 1K_0402_5%
H_THERMTRIP# <7,15,16,38>
VDD1 VDD2
Place near <8> DDR_A_BG1
DDR_A_BG1
DDR_A_BG0
113
115 BG1 ACT_n
114
116
DDR_A_ACT#
DDR_A_ALERT# DDR_A_ACT# <8>
@ CD29
0.1U_0402_10V6K
JDIMM1.258 <8> DDR_A_BG0
117 BG0
VDD3
ALERT_n
VDD4
118
DDR_A_ALERT# <8> 2
DDR_A_MA12 119 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
123 A9 A7 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
DDR_A_MA6 127 A8 A5 128 DDR_A_MA4
129 A6 A4 130
DDR_A_MA3 131 VDD7 VDD8 132 DDR_A_MA2
+0.6V_DDR_VTT +DDR_VREF_A_CA DDR_A_MA1 133 A3 A2 134 JDIMM1_EVENT#
135 A1 EVENT_n/NF 136
DDR_A_CLK0 137 VDD9 VDD10 138 DDR_A_CLK1
<8> DDR_A_CLK0 DDR_A_CLK#0 CK0_t CK1_t/NF DDR_A_CLK#1 DDR_A_CLK1 <8>
139 140
<8> DDR_A_CLK#0 CK0_c CK1_c/NF DDR_A_CLK#1 <8>
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
141 142
DDR_A_PARITY VDD11 VDD12 DDR_A_MA0 +1.2V_MEM
0.1U_0402_10V6K
1 1 1 143 144
<8> DDR_A_PARITY DDR_A_BA1 PARITY A0 DDR_A_MA10
CD22
CD23
CD24
2.2U_0402_6.3V6M
1 1 145 146
<8> DDR_A_BA1 BA1 A10/AP
@ CD26
147 148
VDD13 VDD14
1
DDR_A_CS#0 DDR_A_BA0
CD25
1K_0402_1%
149 150
2 2 2 <8> DDR_A_CS#0 DDR_A_MA14 CS0_n BA0 DDR_A_MA16 DDR_A_BA0 <8>
151 152
2 2 WE_n/A14 RAS_n/A16
RD15
153 154
DDR_A_ODT0 155 VDD15 VDD16 156 DDR_A_MA15
<8> DDR_A_ODT0 DDR_A_CS#1 ODT0 CAS_n/A15 DDR_A_MA13 +DDR_VREF_A_CA +DDR_VREF_CA
157 158
<8> DDR_A_CS#1
2
159 CS1_n A13 160 +DDR_VREF_A_CA
DDR_A_ODT1 VDD17 VDD18 @ T50
161 162
<8> DDR_A_ODT1 ODT1 C0/CS2_n/NC PAD~D +DDR_VREF_A_CA
163 164 1 2
165 VDD19 VREFCA 166 DIMM1_SA2 RD17 2_0402_1%
T51 @ PAD~D C1, CS3_n,NC SA2
0.022U_0402_16V7K
167 168
DQ37 DQ36
1
1K_0402_1%
171 172 1
CD31
173 174
DQ33 DQ32
RD16
175 176
DDR_A_DQS2 179 DQS4_c DM4_n/DBI4_n 180 2
B B
2
DQS4_t VSS59 DDR_A_D23
24.9_0402_1%
181 182
VSS60 DQ39
1
DDR_A_D22 183 184
DQ38 VSS61 DDR_A_D18
RD18
185 186
DDR_A_D19 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D30
DDR_A_D25 191 VSS64 DQ45 192
DIMM Select
2
+3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN 193 DQ44 VSS65 194 DDR_A_D24
DDR_A_D26 195 VSS66 DQ41 196
197 DQ40 VSS67 198 DDR_A_DQS#3
VSS68 DQS5_c
1
199 200 DDR_A_DQS3

@ RD4 @ RD6 @ RD8 RD10 201 DM5_n/DBI5_n DQS5_t 202
0_0402_5% 0_0402_5% 0_0402_5% 0_0603_5% DDR_A_D28 203 VSS69 VSS70 204 DDR_A_D31
205 DQ46 DQ47 206
2
+3.3V_RUN_DIMM1 209 DQ42 DQ43 210

DIMM1_SA0 DDR_A_D49 211 VSS73 VSS74 212 DDR_A_D48
DIMM1_SA1 DQ52 DQ53
2.2U_0402_6.3V6M
0.1U_0201_10V6K
1 1 213 214
DIMM1_SA2 DDR_A_D50 215 VSS75 VSS76 216 DDR_A_D54
SA0 SA1 SA2 DQ49 DQ48 +3.3V_RUN
CD27
CD28
217 218
VSS77 VSS78
1
DDR_A_DQS#6 219 220

* DIMM1 0 0 0 RD5 RD7 RD9 2 2 DDR_A_DQS6 221 DQS6_c DM6_n/DBI6_n 222
0_0402_5% 0_0402_5% 0_0402_5% 223 DQS6_t VSS79 224 DDR_A_D53
DIMM2 1 0 0
1
DDR_A_D55 VSS80 DQ54
330K_0402_5%
225 226
DQ55 VSS81 DDR_A_D52
RD19
227 228
DIMM3 0 1 0
2
DDR_A_D51 229 VSS82 DQ50 230

231 DQ51 VSS83 232 DDR_A_D62
DIMM4 1 1 0 DDR_A_D60 233 VSS84 DQ60 234 +1.2V_MEM
2
235 DQ61 VSS85 236 DDR_A_D57
DDR_A_D59 237 VSS86 DQ57 238 UD1
239 DQ56 VSS87 240 DDR_A_DQS#7 1 5 1 2
241 VSS88 DQS7_c 242 DDR_A_DQS7 NC VCC @ CD32 0.1U_0402_25V6
243 DM7_n/DBI7_n DQS7_t 244 2
DDR_A_D61 VSS89 VSS90 DDR_A_D56 <7> DDR_VTT_CTRL A 0.6V_DDR_VTT_ON
245 246 4
DQ62 DQ63 Y 0.6V_DDR_VTT_ON <50>
247 248 3
Byte[0] DQ[7:0] DQS/DQS#[0] DDR_A_D58 249
251
253
VSS91
DQ58
VSS93
VSS92
DQ59
VSS94
250
252
254
DDR_A_D63 GND
74AUP1G07SE-7_SOT353
Byte[1] DQ[15:8] DQS/DQS#[1]

<7,15,20,41> DDR_XDP_W AN_SMBCLK
+2.5V_MEM
+3.3V_RUN_DIMM1 255
257
259
SCL
VDDSPD
VPP1
SDA
SA0
VTT
256
258
260
DIMM1_SA0
DIMM1_SA1
DDR_XDP_W AN_SMBDAT
+0.6V_DDR_VTT
<7,15,20,41>
A Byte[2] DQ[23:16] DQS/DQS#[2] 261 VPP2

GND1
SA1
GND2
262
A
* Byte[3] DQ[31:24] DQS/DQS#[3]

LCN_DAN05-Q0406-0103
Byte[4] DQ[39:32] DQS/DQS#[4] CONN@
* Byte[5] DQ[47:40] DQS/DQS#[5]

Byte[6] DQ[55:48] DQS/DQS#[6] DELL CONFIDENTIAL/PROPRIETARY
Byte[7] DQ[63:56] DQS/DQS#[7] Issued Date 2016/01/01 Deciphered Date 2017/01/01 Title
DDR4-SODIMM SLOT1
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
<8> DDR_B_DQS#[0..7]
<8> DDR_B_DQS[0..7]
<8> DDR_B_D[0..15] +1.2V_MEM +1.2V_MEM
<8> DDR_B_D[16..31]
JDIMM2
<8> DDR_B_D[32..47]
<8> DDR_B_D[48..63]
1 2
<8> DDR_B_MA[0..16] DDR_B_D0 VSS1 VSS2 DDR_B_D1
3 4
5 DQ5 DQ4 6
DDR_B_D4 7 VSS3 VSS4 8 DDR_B_D5
9 DQ1 DQ0 10
DDR_B_DQS#0 11 VSS5 VSS6 12
DDR_B_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_B_D2
Layout Note: DDR_B_D3 17 VSS8 DQ6 18
DQ7 VSS9
Place near JDIMM2 DDR_B_D7
19
21 VSS10 DQ2
20
22
DDR_B_D6
D 23 DQ3 VSS11 24 DDR_B_D8 D

DDR_B_D12 25 VSS12 DQ12 26
27 DQ13 VSS13 28 DDR_B_D13
DDR_B_D9 29 VSS14 DQ8 30
31 DQ9 VSS15 32 DDR_B_DQS#1
33 VSS16 DQS1_c 34 DDR_B_DQS1
+1.2V_MEM 35 DM1_n/DBI_n DQS1_t 36
39 DQ15 DQ14 40
DQ10 DQ11
330U_D3_2.5VY_R6M
43 44
DDR_B_D38 VSS21 VSS22 DDR_B_D36
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
45 46
47 DQ21 DQ20 48
1 VSS23 VSS24
@ DDR_B_D32 49 50 DDR_B_D34
1 1 1 1 1 1 1 1 DQ17 DQ16
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
CD49
+ 51 52
DDR_B_DQS4 55 DQS2_c DM2_n/DBI2_n 56
2 2 2 2 2 2 2 2 2 57 DQS2_t VSS27 58 DDR_B_D33
DDR_B_D35 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_B_D39
DDR_B_D37 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_B_D45
+2.5V_MEM DDR_B_D40 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_B_D41
DDR_B_D44 71 VSS34 DQ24 72
DQ25 VSS35
73 74 DDR_B_DQS#5
VSS36 DQS3_c DDR_B_DQS5
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
75 76
77 DM3_n/DBI3_n DQS3_t 78
1 1 1 1 1 1 1 1 1 1 1 1 VSS37 VSS38
DDR_B_D46 79 80 DDR_B_D43
DQ30 DQ31
CD41
CD42
CD43
CD44
CD45
CD46
CD47
CD48
CD50
CD51
CD52
CD53
81 82
2 2 2 2 2 2 2 2 2 2 2 2 85 DQ26 DQ27 86
87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
C CB2/NC VSS49 C
103 104
105 VSS50 CB7/NC 106
107 CB3/NC VSS51 108 DDR_DRAMRST#_R JDIMM2_EVENT# 1 2
DDR_B_CKE0 VSS52 RESET_n DDR_B_CKE1 DDR_DRAMRST#_R <14> H_THERMTRIP# <7,14,16,38>
109 110 @ RD27 1K_0402_5%
<8> DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 <8>
111 112
Layout Note: <8> DDR_B_BG1
DDR_B_BG1 113 VDD1 VDD2 114 DDR_B_ACT#
DDR_B_ACT# <8> 1
BG1 ACT_n
Place near <8> DDR_B_BG0
DDR_B_BG0 115
117 BG0 ALERT_n
116
118
DDR_B_ALERT#
DDR_B_ALERT# <8>
@ CD61
JDIMM2.258 DDR_B_MA12 119 VDD3
A12
VDD4
A11
120 DDR_B_MA11 0.1U_0402_10V6K
DDR_B_MA9 121 122 DDR_B_MA7 2
123 A9 A7 124
DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5
DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
129 A6 A4 130
DDR_B_MA3 131 VDD7 VDD8 132 DDR_B_MA2
+0.6V_DDR_VTT DDR_B_MA1 133 A3 A2 134 JDIMM2_EVENT#
+DDR_VREF_B_CA 135 A1 EVENT_n/NF 136
DDR_B_CLK0 137 VDD9 VDD10 138 DDR_B_CLK1
<8> DDR_B_CLK0 DDR_B_CLK#0 CK0_t CK1_t/NF DDR_B_CLK#1 DDR_B_CLK1 <8>
139 140
<8> DDR_B_CLK#0 CK0_c CK1_c/NF DDR_B_CLK#1 <8>
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
141 142
DDR_B_PARITY 143 VDD11 VDD12 144 DDR_B_MA0
1 1 1 <8> DDR_B_PARITY PARITY A0
DDR_B_BA1 DDR_B_MA10 +1.2V_MEM
CD54
CD55
CD56
0.1U_0402_10V6K
2.2U_0402_6.3V6M
145 146
<8> DDR_B_BA1 BA1 A10/AP
@ CD58
1 1 147 148
DDR_B_CS#0 VDD13 VDD14 DDR_B_BA0
CD57
<8> DDR_B_CS#0 149 150 DDR_B_BA0 <8>
1
2 2 2 DDR_B_MA14 CS0_n BA0 DDR_B_MA16
1K_0402_1%
151 152
153 WE_n/A14 RAS_n/A16 154
2 2 DDR_B_ODT0 VDD15 VDD16 DDR_B_MA15
RD28
155 156
<8> DDR_B_ODT0 DDR_B_CS#1 ODT0 CAS_n/A15 DDR_B_MA13 +DDR_VREF_B_CA +DDR_VREF_B_DQ
157 158
<8> DDR_B_CS#1 CS1_n A13 +DDR_VREF_B_CA
159 160
@ T52
2
DDR_B_ODT1 161 VDD17 VDD18 162
<8> DDR_B_ODT1 ODT1 C0/CS2_n/NC PAD~D +DDR_VREF_B_CA
163 164 1 2
165 VDD19 VREFCA 166 DIMM2_SA2 RD30 2_0402_1%
T53 @ PAD~D C1, CS3_n,NC SA2
0.022U_0402_16V7K
167 168
VSS53 VSS54
1
DDR_B_D22 DDR_B_D19
1K_0402_1%
169 170
171 DQ37 DQ36 172
VSS55 VSS56 1
DDR_B_D23 DDR_B_D18
RD29
CD62
173 174
175 DQ33 DQ32 176
2
DDR_B_DQS2 179 DQS4_c DM4_n/DBI4_n 180 2
181 DQS4_t VSS59 182 DDR_B_D21
DDR_B_D17 VSS60 DQ39
24.9_0402_1%
183 184
DQ38 VSS61
1
B 185 186 DDR_B_D20 B
DDR_B_D16 VSS62 DQ35
RD31
187 188
189 DQ34 VSS63 190 DDR_B_D28
DDR_B_D24 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_B_D29
2
DDR_B_D25 195 VSS66 DQ41 196
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN 197
199
201
DQ40
VSS68
DM5_n/DBI5_n
VSS67
DQS5_c
DQS5_t
198
200
202
DDR_B_DQS#3
DDR_B_DQS3
VSS69 VSS70
1
DDR_B_D26 203 204 DDR_B_D31

@ RD20 RD22 @ RD24 RD26 205 DQ46 DQ47 206
0_0402_5% 0_0402_5% 0_0402_5% 0_0603_5% DDR_B_D27 207 VSS71 VSS72 208 DDR_B_D30
209 DQ42 DQ43 210
2
+3.3V_RUN_DIMM2 213 DQ52 DQ53 214

DIMM2_SA0 DDR_B_D54 215 VSS75 VSS76 216 DDR_B_D48
DIMM2_SA1 DQ49 DQ48
2.2U_0402_6.3V6M
0.1U_0201_10V6K
1 1 217 218
DIMM2_SA2 DDR_B_DQS#6 219 VSS77 VSS78 220
SA0 SA1 SA2 DDR_B_DQS6 DQS6_c DM6_n/DBI6_n
CD59
CD60
221 222
DQS6_t VSS79
1
223 224 DDR_B_D55

DIMM1 0 0 0 RD21 @ RD23 RD25 2 2 DDR_B_D53 225 VSS80 DQ54 226
0_0402_5% 0_0402_5% 0_0402_5% 227 DQ55 VSS81 228 DDR_B_D50
DIMM2 1 0 0 DDR_B_D49 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_B_D61
* DIMM3 0 1 0
2
DDR_B_D62 233 VSS84 DQ60 234

235 DQ61 VSS85 236 DDR_B_D57
DIMM4 1 1 0 DDR_B_D59 237 VSS86 DQ57 238
239 DQ56 VSS87 240 DDR_B_DQS#7
241 VSS88 DQS7_c 242 DDR_B_DQS7
243 DM7_n/DBI7_n DQS7_t 244
247 DQ62 DQ63 248
251 DQ58 DQ59 252
Byte[0] DQ[7:0] DQS/DQS#[0] <7,14,20,41> DDR_XDP_W AN_SMBCLK +3.3V_RUN_DIMM2

253
255
257
VSS93
SCL
VDDSPD
VSS94
SDA
SA0
254
256
258
DIMM2_SA0 DDR_XDP_W AN_SMBDAT <7,14,20,41>

+2.5V_MEM
259
261
VPP1
VPP2
GND1
VTT
SA1
GND2
260
262
DIMM2_SA1 +0.6V_DDR_VTT
A
A
* Byte[3] DQ[31:24] DQS/DQS#[3] LCN_DAN05-Q0406-0103

CONN@

* Byte[5] DQ[47:40] DQS/DQS#[5]
Byte[6] DQ[55:48] DQS/DQS#[6] DELL CONFIDENTIAL/PROPRIETARY
Byte[7] DQ[63:56] DQS/DQS#[7] Security Classification Compal Secret Data
Title
DDR4-SODIMM SLOT2
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
D D
SPT-H_PCH
UH1C
Rev_1.3
PCH_CL_CLK1 AV2 G31 PCIE_PRX_DTX_N9
<35> PCH_CL_CLK1 PCH_CL_DATA1 CL_CLK PCIE9_RXN/SATA0A_RXN PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 <40>
AV3 H31
<35> PCH_CL_DATA1 PCH_CL_RST1# CL_DATA CLINK PCIE9_RXP/SATA0A_RXP PCIE_PTX_DRX_N9 PCIE_PRX_DTX_P9 <40>
AW2 C31
<35> PCH_CL_RST1# CL_RST# PCIE9_TXN/SATA0A_TXN PCIE_PTX_DRX_P9 PCIE_PTX_DRX_N9 <40>
B31
R44 PCIE9_TXP/SATA0A_TXP PCIE_PTX_DRX_P9 <40>
R43 GPP_G8/FAN_PWM_0
GPP_G9/FAN_PWM_1 PCIE_PRX_DTX_N10
M.2 Socket 3 (Key M)
U39 G29
GPP_G10/FAN_PWM_2 PCIE10_RXN/SATA1A_RXN PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 <40>
N42 E29
GPP_G11/FAN_PWM_3 PCIE10_RXP/SATA1A_RXP PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 <40>
+3.3V_RUN C32
CAM_MIC_CBL_DET# U43 FAN PCIE10_TXN/SATA1A_TXN B32 PCIE_PTX_DRX_P10 PCIE_PTX_DRX_N10 <40>
<32> CAM_MIC_CBL_DET# GPP_G0/FAN_TACH_0 PCIE10_TXP/SATA1A_TXP PCIE_PTX_DRX_P10 <40>
U42
U41 GPP_G1/FAN_TACH_1 F41 SATA_PRX_DTX_N2
CAM_MIC_CBL_DET# GPP_G2/FAN_TACH_2 PCIE15_RXN/SATA2_RXN SATA_PRX_DTX_P2 SATA_PRX_DTX_N2 <41>
1 2 M44 E41
CONTACTLESS_DET# GPP_G3/FAN_TACH_3 PCIE15_RXP/SATA2_RXP SATA_PTX_DRX_N2 SATA_PRX_DTX_P2 <41>
RH319 10K_0402_5% U36 B39 SATA HDD
M2280_PCIE_SATA# <39> CONTACTLESS_DET# HOST_SD_W P# GPP_G4/FAN_TACH_4 PCIE15_TXN/SATA2_TXN SATA_PTX_DRX_P2 SATA_PTX_DRX_N2 <41>
1 2 P44 A39
<34> HOST_SD_W P# AUD_PW R_EN GPP_G5/FAN_TACH_5 PCIE15_TXP/SATA2_TXP SATA_PTX_DRX_P2 <41>
RH318 10K_0402_5% T45
HOST_SD_W P# <36> AUD_PW R_EN GPP_G6/FAN_TACH_6
1 2 T44 D43
PCIe/SATA
RH214 100K_0402_5% GPP_G7/FAN_TACH_7 PCIE16_RXN/SATA3_RXN E42
1 2 HDD_DET# PCIE_PTX_DRX_P11 B33 PCIE16_RXP/SATA3_RXP A41
RH324 10K_0402_5% <40> PCIE_PTX_DRX_P11 PCIE_PTX_DRX_N11 C33 PCIE11_TXP PCIE16_TXN/SATA3_TXN A40
1 2 BIOS_REC <40> PCIE_PTX_DRX_N11 PCIE_PRX_DTX_P11 K31 PCIE11_TXN PCIE16_TXP/SATA3_TXP
M.2 Socket 3 (Key M) <40> PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11 PCIE11_RXP PCIE_PRX_DTX_N17
RH76 10K_0402_5% L31 H42
<40> PCIE_PRX_DTX_N11 PCIE11_RXN PCIE17_RXN/SATA4_RXN PCIE_PRX_DTX_P17 PCIE_PRX_DTX_N17 <35>
H40
m3042_PCIE#_SATA BIOS_REC PCIE17_RXP/SATA4_RXP PCIE_PTX_DRX_N17 PCIE_PRX_DTX_P17 <35>
1 2 AB33 E45 M.2 3042 HCA or QCA LTE SSD Cache
RH344 10K_0402_5% AB35 GPP_F10/SCLOCK PCIE17_TXN/SATA4_TXN F45 PCIE_PTX_DRX_P17 PCIE_PTX_DRX_N17 <35>
AA44 GPP_F11/SLOAD PCIE17_TXP/SATA4_TXP PCIE_PTX_DRX_P17 <35>
1 2 CONTACTLESS_DET# AA45 GPP_F13/SDATAOUT0 K37
RH90 10K_0402_5% GPP_F12/SDATAOUT1 PCIE18_RXN/SATA5_RXN G37
C AUD_PW R_EN PCIE18_RXP/SATA5_RXP C
1 2 B38 G45 SPSGP0 1 2280_PCIE_SATA# 0=SATA 1=PCIE
RH345 10K_0402_5% C38 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN G44
1 2 SATALED# D39 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP
E37 PCIE14_RXN/SATA1B_RXN AD44
RH380 10K_0402_5%
PCIE14_RXP/SATA1B_RXP GPP_E8/SATALED#
SATALED#
M2280_PCIE_SATA# SATALED# <35,40,45> SPSGP1 0 SATAGP1 1=SATA 0=PCIE
AG36
GPP_E0/SATAXPCIE0/SATAGP0 M2280_PCIE_SATA# <40>
1 2 SATAGP3 C36 AG35 SATAGP1
B36 PCIE13_TXN/SATA0B_TXN GPP_E1/SATAXPCIE1/SATAGP1 AG39 HDD_DET#
RH323 10K_0402_5%
PCIE13_TXP/SATA0B_TXP GPP_E2/SATAXPCIE2/SATAGP2 HDD_DET# <41> SPSGP2 1 HDD_DET# 0=SATA 1=PCIE
1 2 SATAGP1 G35 AD35 SATAGP3
RH377 10K_0402_5% E35 PCIE13_RXN/SATA0B_RXN GPP_F0/SATAXPCIE3/SATAGP3 AD31 m3042_PCIE#_SATA
PCIE13_RXP/SATA0B_RXP GPP_F1/SATAXPCIE4/SATAGP4 m3042_PCIE#_SATA <37>
1 2 SATAGP5 AD38 SATAGP5 SPSGP3 0 SATAGP3 1=SATA 0=PCIE
PCIE_PTX_DRX_P12 GPP_F2/SATAXPCIE5/SATAGP5 Reserve
@ RH325 10K_0402_5% A35 AC43 SATAGP6
<40> PCIE_PTX_DRX_P12 PCIE_PTX_DRX_N12 PCIE12_TXP GPP_F3/SATAXPCIE6/SATAGP6 Reserve
1 2 SATAGP6 B35 AB44 SATAGP7
<40> PCIE_PTX_DRX_N12 PCIE_PRX_DTX_P12 PCIE12_TXN GPP_F4/SATAXPCIE7/SATAGP7 Reserve
@ RH326 10K_0402_5% M.2 Socket 3 (Key M) H33 SPSGP4 1 3042_PCIE#_SATA 1=SATA 0=PCIE
<40> PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 PCIE12_RXP BIA_PW M_PCH
1 2 SATAGP7 <40> PCIE_PRX_DTX_N12 G33 W36
@ RH322 10K_0402_5% J45 PCIE12_RXN GPP_F21/EDP_BKLTCTL W35 PANEL_BKEN_PCH BIA_PW M_PCH <32>
K44 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN W42 ENVDD_PCH PANEL_BKEN_PCH <32>
N38 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN ENVDD_PCH <32,37>
N39 PCIE20_RXP/SATA7_RXP AJ3 PCH_THERMTRIP# 1 2
HOST H_THERMTRIP# <7,14,15,38>
H44 PCIE20_RXN/SATA7_RXN THERMTRIP# AL3 PCH_PECI RH75 1 2 620_0402_5% H_PECI
PCIE19_TXP/SATA6_TXP PECI H_PM_SYNC_R H_PECI <7,37>
H43 AJ4 RH73 1 2 43_0402_1% H_PM_SYNC
L39 PCIE19_TXN/SATA6_TXN PM_SYNC AK2 PLTRST_CPU# RH156 30_0402_5% H_PM_SYNC <7>
L37 PCIE19_RXP/SATA6_RXP PLTRST_PROC# AH2 H_PM_DOW N PLTRST_CPU# <7>
PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOW N <7>
3 OF 12
SKL-H-PCH_BGA837
PCH_PECI
1
@ RH74
10K_0402_5%
2
B B
A A
Title
KABYLAKE PCH-H (1/9)
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
1 2
@ RH66 0_0402_5%
+3.3V_RUN
@ CH10
1 2
5
D 0.1U_0402_25V6 D
1
P
<7> XDP_DBRESET# B SYS_RESET#
4
2 1 ME_RESET# 2 Y SYS_RESET# <20,21>
A
G
@ RH70 8.2K_0402_5% @ UC3
CIS LINK OK 74AHC1G09GW _TSSOP5
3
SPT-H_PCH
UH1B
Rev_1.3
DMI_CTX_PRX_N0 L27 AF5 USB20_N1
<6>
<6>
DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CTX_PRX_P0 N27 DMI_RXN0
DMI_RXP0
USB2N_1
USB2P_1
AG7 USB20_P1 USB20_N1
USB20_P1
<42>
<42>
-----> Ext USB Port 1 Charge(RIGHT)
DMI_CRX_PTX_N0 C27 AD5 USB20_N2
<6>
<6>
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CRX_PTX_P0 B27 DMI_TXN0
DMI_TXP0
USB2N_2
USB2P_2
AD7 USB20_P2 USB20_N2
USB20_P2
<43>
<43>
-----> Ext USB Port 2(LEFT)
DMI_CTX_PRX_N1 E24 AG8 USB20_N3
<6>
<6>
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CTX_PRX_P1 G24 DMI_RXN1
DMI_RXP1
USB2N_3
USB2P_3
AG10 USB20_P3 USB20_N3
USB20_P3
<43>
<43>
-----> Ext USB Port 3(REAR)
DMI_CRX_PTX_N1 B28 AE1 USB20_N4
<6>
<6>
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CRX_PTX_P1 A28 DMI_TXN1
DMI_TXP1
DMI
USB2N_4
USB2P_4
AE2 USB20_P4 USB20_N4
USB20_P4
<29>
<29>
-----> Type-C
DMI_CTX_PRX_N2 G27 AC2
<6> DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 DMI_RXN2 USB2N_5
E26 AC3
<6> DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI_RXP2 USB2P_5 USB20_N6
B29 AF2
C
<6>
<6>
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CRX_PTX_P2 C29 DMI_TXN2
DMI_TXP2
USB2N_6
USB2P_6
AF3 USB20_P6 USB20_N6
USB20_P6
<35>
<35>
-----> M.2 3030 (BT) C
DMI_CTX_PRX_N3 L29 AB3
<6> DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 DMI_RXN3 USB2N_7
K29 USB 2.0 AB2
<6> DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI_RXP3 USB2P_7 USB20_N8
B30 AL8
<6>
<6>
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3
DMI_CRX_PTX_P3 A30 DMI_TXN3
DMI_TXP3
USB2N_8
USB2P_8
AL7 USB20_P8 USB20_N8 <35>
USB20_P8 <35>
-----> M.2 3042 (WWAN)
AA1 USB20_N9
1 2 PCIECOMP# B18
PCIE_RCOMPN
USB2N_9
USB2P_9
AA2 USB20_P9
USB20_N10
USB20_N9 <32>
USB20_P9 <32>
-----> Touch Screen
RH192 100_0402_1% PCIECOMP C17 AJ8
PCIE_RCOMPP USB2N_10
USB2P_10
AJ7 USB20_P10 USB20_N10 <39>
USB20_P10 <39>
-----> USH
W2 USB20_N11
<35> PCIE_PRX_DTX_N1
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
H15
PCIE1_RXN/USB3_7_RXN
USB2N_11
USB2P_11
W3 USB20_P11 USB20_N11 <32>
USB20_P11 <32>
-----> Camera
G15 AD3
<35> PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE1_RXP/USB3_7_RXP USB2N_12
A16 AD2
WIGIG--->
PCIe/USB 3
<35> PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1 B16 PCIE1_TXN/USB3_7_TXN USB2P_12 V2
<35> PCIE_PTX_DRX_P1 PCIE_PTX_DRX_N2 B19 PCIE1_TXP/USB3_7_TXP USB2N_13 V1
<35> PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2 C19 PCIE2_TXN/USB3_8_TXN USB2P_13 AJ11
<35> PCIE_PTX_DRX_P2 PCIE_PRX_DTX_N2 E17 PCIE2_TXP/USB3_8_TXP USB2N_14 AJ13
WLAN ---> <35> PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 G17 PCIE2_RXN/USB3_8_RXN USB2P_14
<35> PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N3 PCIE2_RXP/USB3_8_RXP +3.3V_ALW _PCH
L17
<34> PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE3_RXN/USB3_9_RXN
K17
<34> PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE3_RXP/USB3_9_RXP USB_OC0#
B20 AD43 RPH6
Card Reader ---> <34> PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3 C20 PCIE3_TXN/USB3_9_TXN GPP_E9/USB2_OC0# AD42 USB_OC1# USB_OC0#
USB_OC1#
<42>
<43>
USB_OC1# 1 8
<34> PCIE_PTX_DRX_P3 PCIE_PRX_DTX_N4 E20 PCIE3_TXP/USB3_9_TXP GPP_E10/USB2_OC1# AD39 USB_OC2# USB_OC2# 2 7
<33> PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE4_RXN/USB3_10_RXN GPP_E11/USB2_OC2# USB_OC3# USB_OC2# <43> USB_OC3#
G19 AC44 3 6
<33> PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE4_RXP/USB3_10_RXP GPP_E12/USB2_OC3# Reserve USB_OC0#
B21 Y43 4 5
LAN ---> <33> PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 A21 PCIE4_TXN/USB3_10_TXN GPP_F15/USB2_OC4# Y41
<33> PCIE_PTX_DRX_P4 K19 PCIE4_TXP/USB3_10_TXP GPP_F16/USB2_OC5# W44 10K_0804_8P4R_5%
L19 PCIE5_RXN GPP_F17/USB2_OC6# W43
D22 PCIE5_RXP GPP_F18/USB2_OC7#
C22 PCIE5_TXN
G22 PCIE5_TXP AG3 USB2_COMP RH193 1 2 113_0402_1%
E22 PCIE6_RXN USB2_COMP AD10 USB2_VBUSSENSE RH364 1 2 1K_0402_5%
B22 PCIE6_RXP USB2_VBUSSENSE AB13
A23 PCIE6_TXN RSVD_AB13 AG2 USB2_ID RH365 1 2 0_0402_5%
L22 PCIE6_TXP USB2_ID
K22 PCIE7_RXN
PCIE7_RXP USB2_ID <29>
C23
B23 PCIE7_TXN BD14 3.3V_CAM_EN#
PCIE7_TXP GPD7/RSVD 3.3V_CAM_EN# <32>
K24
L24 PCIE8_RXN
C24 PCIE8_RXP
B24 PCIE8_TXN
PCIE8_TXP 2 OF 12
B B
SKL-H-PCH_BGA837
A A
Title
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
D D
SPT-H_PCH
UH1G
Rev_1.3
AR17 L1 PCH_XDP_CLK_DN_R RH154 1 2 0_0402_5% PCH_XDP_CLK_DN
GPP_A16/CLKOUT_48 CLKOUT_ITPXDP_N L2 PCH_XDP_CLK_DP_R RH155 1 2 0_0402_5% PCH_XDP_CLK_DP PCH_XDP_CLK_DN <7>
CPU_24MHZ_R_D RH169 1 2 0_0402_5% PCH_CPU_NSSC_CLK_D G1 CLKOUT_ITPXDP_P J1 PCH_CPU_PCIBCLK_D# RH168 1 2 0_0402_5% PCH_CPU_PCIBCLK_R_D# PCH_XDP_CLK_DP <7>
<7> CPU_24MHZ_R_D CPU_24MHZ_R_D# PCH_CPU_NSSC_CLK_D# CLKOUT_CPUNSSC_P CLKOUT_CPUPCIBCLK_N PCH_CPU_PCIBCLK_D PCH_CPU_PCIBCLK_R_D PCH_CPU_PCIBCLK_R_D# <7>
RH170 1 2 0_0402_5% F1 J2 RH167 1 2 0_0402_5%
<7> CPU_24MHZ_R_D# CLKOUT_CPUNSSC_N CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_R_D <7>
PCH_CPU_BCLK_R_D RH161 1 2 0_0402_5% PCH_CPU_BCLK_D G2
<7> PCH_CPU_BCLK_R_D PCH_CPU_BCLK_R_D# PCH_CPU_BCLK_D# CLKOUT_CPUBCLK_P CLK_PCIE_N0
RH166 1 2 0_0402_5% H2 N7
<7> PCH_CPU_BCLK_R_D# CLKOUT_CPUBCLK_N CLKOUT_PCIE_N0 CLK_PCIE_P0 CLK_PCIE_N0 <35>
N8 WWAN
XTAL24_OUT_R1 A5 CLKOUT_PCIE_P0 CLK_PCIE_P0 <35>
+1.0V_CLK5 XTAL24_IN_R A6 XTAL24_OUT L7 CLK_PCIE_N1
XTAL24_IN CLKOUT_PCIE_N1 CLK_PCIE_N1 <35>
L5 CLK_PCIE_P1
XCLK_RBIAS CLKOUT_PCIE_P1 CLK_PCIE_P1 <35> WLAN
1 2 E1
RH171 2.7K_0402_1% XCLK_BIASREF D3 CLK_PCIE_N2
C CLKOUT_PCIE_N2 CLK_PCIE_N2 <35> C
PCH_RTCX1 BC9 F2 CLK_PCIE_P2
PCH_RTCX2 RTCX1 CLKOUT_PCIE_P2 CLK_PCIE_P2 <35> WIGIG
BD10
RH123 2 1 10K_0402_5% RTCX2 E5 CLK_PCIE_N3
+3.3V_RUN CLKREQ_PCIE#0_R CLKOUT_PCIE_N3 CLK_PCIE_P3 CLK_PCIE_N3 <40>
WWAN RF@RH10 2 1 0_0402_5% BC24 G4 M.2 Socket 3 (Key M)
<35> CLKREQ_PCIE#0 CLKREQ_PCIE#1_R GPP_B5/SRCCLKREQ0# CLKOUT_PCIE_P3 CLK_PCIE_P3 <40>
+3.3V_RUN RH124 2 1 10K_0402_5% AW24
2 1 CLKREQ_PCIE#2_R AT24 GPP_B6/SRCCLKREQ1# D5 CLK_PCIE_N4
WLAN <35> CLKREQ_PCIE#1
RF@RH11 0_0402_5%
CLKREQ_PCIE#3_R GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_N4 CLK_PCIE_P4 CLK_PCIE_N4 <33>
+3.3V_RUN RH125 2 1 10K_0402_5% BD25 E6 LAN
2 1 CLKREQ_PCIE#4_R BB24 GPP_B8/SRCCLKREQ3# CLKOUT_PCIE_P4 CLK_PCIE_P4 <33>
WIGIG <35> CLKREQ_PCIE#2
RF@RH12 0_0402_5%
CLKREQ_PCIE#5_R GPP_B9/SRCCLKREQ4# CLK_PCIE_N5
RH126 2 1 10K_0402_5% BE25 D8
+3.3V_RUN GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_N5 CLK_PCIE_N5 <34>
M.2 Socket 3 RF@RH13 2 1 0_0402_5% CLKREQ_PCIE#6_R AT33 D7 CLK_PCIE_P5 MMI
<40> CLKREQ_PCIE#3 CLKREQ_PCIE#7_R GPP_H0/SRCCLKREQ6# CLKOUT_PCIE_P5 CLK_PCIE_P5 <34>
+3.3V_RUN RH127 2 1 10K_0402_5% AR31
2 1 BD32 GPP_H1/SRCCLKREQ7# R8
LAN <33> CLKREQ_PCIE#4
RF@RH14 0_0402_5%
GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_N6
RH131 2 1 10K_0402_5% BC32 R7
+3.3V_RUN GPP_H3/SRCCLKREQ9# CLKOUT_PCIE_P6
MMI RF@RH15 2 1 0_0402_5% BB31
<34> CLKREQ_PCIE#5 GPP_H4/SRCCLKREQ10#
+3.3V_RUN RH132 2 1 10K_0402_5% BC33 U5
BA33 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_N7 U7
RH133 2 1 10K_0402_5% AW33 GPP_H6/SRCCLKREQ12# CLKOUT_PCIE_P7
+3.3V_RUN GPP_H7/SRCCLKREQ13#
BB33 W10
BD33 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_N8 W11
GPP_H9/SRCCLKREQ15# CLKOUT_PCIE_P8
R13 N3
R11 CLKOUT_PCIE_N15 CLKOUT_PCIE_N9 N2
CLKOUT_PCIE_P15 CLKOUT_PCIE_P9
P1 P3
R2 CLKOUT_PCIE_N14 CLKOUT_PCIE_N10 P2
W7 R3
Y5 CLKOUT_PCIE_N13 CLKOUT_PCIE_N11 R4
U2
U3 CLKOUT_PCIE_N12
CLKOUT_PCIE_P12 7 OF 12
SKL-H-PCH_BGA837
B B
CH4 CH13
1 2 PCH_RTCX1_R 1 2 PCH_RTCX1 XTAL24_IN_R 1 2
RH43 0_0402_5%
15P_0402_50V8J 15P_0402_50V8J
1
3
4
YH1 RH44 RH153

32.768KHZ_12.5PF_9H03200042 10M_0402_5% 1M_0402_1% YH2
24MHZ_12PF_X3G024000DC1H
2
1
2
CH5
1 2 PCH_RTCX2 CH14
XTAL24_OUT_R1 1 2 XTAL24_OUT_R 1 2
15P_0402_50V8J RH152 0_0402_5%
15P_0402_50V8J
A A
Title
B
LA-E141P 0.2
Date: Thursday, June 30, 2016 Sheet 18 of 61

5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH
+3.3V_ALW_PCH
1 2 SIO_EXT_SMI#
5
RH310 10K_0402_5% UH7
PCH_PLTRST# 1
P
D B D
4 PCH_PLTRST#_AND
2 Y RH187 2 1 0_0402_5% PCH_PLTRST#_AND <34,35,39,40>
A PLTRST_TPM# <39>
1
TC7SH08FU_SSOP5 @ RH65 PCH_PLTRST# 1 2
3
+3.3V_RUN 100K_0402_5% @ RH60 0_0402_5%
2
1 2 TOUCH_SCREEN_PD# TOUCH_SCREEN_PD# don't move to RPC,
@ RH348 10K_0402_5%
1 2 TOUCHPAD_INTR#
RH402 10K_0402_5%
SPT-H_PCH
UH1A
Rev_1.3
PAD~D @ T178 PME# BD17 BB27 PCH_PLTRST# 2 1
GPP_A11/PME# GPP_B13/PLTRST# RH62 2 1 0_0402_5% PLTRST_LAN# <33>
PCH_PLTRST#_EC <38>
PAD~D @ T59 AG15 RH244 0_0402_5%
PAD~D @ T60 AG14 RSVD P43
PAD~D @ T61 AF17 RSVD GPP_G16/GSXCLK R39
PAD~D @ T58 AE17 RSVD GPP_G12/GSXDOUT R36
RSVD GPP_G13/GSXSLOAD R42
PAD~D @ T63 AR19 GPP_G14/GSXDIN R41
PAD~D @ T62 AN17 TP2 GPP_G15/GSXSRESET#
TP1
PCH_SPI_D0 BB29 AF41 SIO_EXT_SMI#
<7> PCH_SPI_D0 PCH_SPI_D1 SPI0_MOSI GPP_E3/CPU_GP0 TOUCH_SCREEN_PD# SIO_EXT_SMI# <37>
BE30 AE44
PCH_SPI_CS#0 SPI0_MISO GPP_E7/CPU_GP1 TOUCHPAD_INTR# TOUCH_SCREEN_PD# <32>
BD31 BC23
PCH_SPI_CLK BC31 SPI0_CS0# GPP_B3/CPU_GP2 BD24 TOUCHPAD_INTR# <37,44>
PCH_SPI_CS#1 SPI0_CLK GPP_B4/CPU_GP3 TOUCH_SCREEN_DET# <32>
AW31
SPI0_CS1# BC36
PCH_SPI_D2_XDP 1 2 PCH_SPI_D2 BC29 GPP_H18/SML4ALERT# BE34 +RTC_CELL
<7> PCH_SPI_D2_XDP PCH_SPI_D3 SPI0_IO2 GPP_H17/SML4DATA
RH180 0_0402_5% BD30 BD39
C AT31 SPI0_IO3 GPP_H16/SML4CLK BB36 C
<39> PCH_SPI_CS#2 SPI0_CS2# GPP_H15/SML3ALERT#
1
AN36 BA35
AL39 GPP_D1 GPP_H14/SML3DATA BC35 RH198
AN41 GPP_D0 GPP_H13/SML3CLK BD35 1M_0402_5%
AN38 GPP_D3 GPP_H12/SML2ALERT# AW35
AH43 GPP_D2 GPP_H11/SML2DATA BD34
GPP_D22 GPP_H10/SML2CLK
2
AG44 BE11 PCH_INTRUDER_HDR#
+3.3V_SPI GPP_D21 INTRUDER#
1 OF 12
1 2 PCH_SPI_D2_R1 SKL-H-PCH_BGA837
@ RH30 1K_0402_5%
1 2 PCH_SPI_D3_R1
@ RH335 1K_0402_5%
1 2 PCH_SPI_D3_R1
@ RH334 1K_0402_5% RPC1
PCH_SPI_D1_R1 1 8 PCH_SPI_D1_0_R
<39> PCH_SPI_D1_R1
<39> PCH_SPI_D0_R1 PCH_SPI_CLK_R1 PCH_SPI_CLK_0_R
3 6
<39> PCH_SPI_CLK_R1 PCH_SPI_D3_R1 4 5 PCH_SPI_D3_0_R
9/5 MOW
Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the 33_0804_8P4R_5%
required 1 kOhm pull-up resistor. In this case, customers must ensure that the SPI
flash device on the platform has HOLD functionality disabled by default.
@RPC2
Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms PCH_SPI_D0_R1 3 6 PCH_SPI_D0_1_R
with ES and SKL S/H platforms with pre-ES1/ES1 samples. PCH_SPI_CLK_R1 2 7 PCH_SPI_CLK_1_R
+3.3V_SPI
33_0804_8P4R_5%
CH9
1 2
B 128Mb Flash ROM 0.1U_0201_10V6K B

UC5
PCH_SPI_CS#0_R1 RH37 1 2 0_0402_5% PCH_SPI_CS#0_R2 1 8
PCH_SPI_D1_0_R 2 /CS VCC 7 PCH_SPI_D3_0_R
PCH_SPI_D2_R1 RH351 1 2 33_0402_5% PCH_SPI_D2_0_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_0_R
4 /WP(IO2) CLK 5 PCH_SPI_D0_0_R
GND DI(IO0)
ESPI LPC W25Q128FVSIQ_SO8 E-T_6705K-Y20N-00L

+3.3V_SPI 22
RH351 33 ohm 15 ohm 21 GND2
@ CH270 2 1 PCH_SPI_CS#1_R1 20 GND1
1 2 0_0402_5% @ RH177 PCH_SPI_CS#1 19 20
RPC1 33 ohm 15 ohm
64Mb Flash ROM 2 1 PCH_SPI_D0_R1 18 19
0.1U_0201_10V6K 0_0402_5% RH178 PCH_SPI_D0 17 18
@ UC6 2 1 PCH_SPI_D1_R1 16 17
RH178,RH179,RH181, 0 ohm 25 ohm PCH_SPI_CS#1_R1 @ RH352 1 2 0_0402_5% PCH_SPI_CS#1_R2 1 8 0_0402_5% RH179 PCH_SPI_D1 15 16
PCH_SPI_D1_1_R 2 /CS VCC 7 PCH_SPI_D3_1_R 2 1 PCH_SPI_CLK_R1 14 15
RH182,RH183,RH184 PCH_SPI_D2_R1 @ RH353 1 2 33_0402_5% PCH_SPI_D2_1_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_1_R 0_0402_5% RH181 PCH_SPI_CLK 13 14
Need check 4 /WP(IO2) CLK 5 PCH_SPI_D0_1_R 2 1 PCH_SPI_CS#0_R1 12 13
GND DI(IO0) 0_0402_5% RH182 PCH_SPI_CS#0 11 12
W25Q64FVSSIQ_SO8 2 1 PCH_SPI_D2_R1 10 11
0_0402_5% RH183 PCH_SPI_D2 9 10
2 1 PCH_SPI_D3_R1 8 9
0_0402_5% RH184 PCH_SPI_D3 7 8
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R
+3.3V_SPI
6 7
+3.3V_ALW_PCH
5 6
4 5
33_0402_5%
33_0402_5%
3 4
1
1
@EMI@
@EMI@
2 3
RH28
RH29
1 2
1
2 1 JSPI1
2
RH185 0_0402_5% CONN@

33P_0402_50V8J
33P_0402_50V8J
@EMI@
@EMI@
A
CIS link OK A
1
1
CH321
CH322
2
Title
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH +3.3V_1.8V_GPPA
ESPI_RESET# 1 2
1 2 MEM_SMBCLK @ RH95 10K_0402_5%
RH56 1K_0402_5% ESPI_ALERT# 1 2
1 2 MEM_SMBDATA UH1F SPT-H_PCH RH340 8.2K_0402_1%
RH57 1K_0402_5% USB3_PTX_DRX_N1 C11 Rev_1.3
<42> USB3_PTX_DRX_N1 USB3_PTX_DRX_P1 B11 USB3_1_TXN AT22 ESPI_IO0_R RC366 1 2 15_0402_5%
LPC/eSPI
SML0_SMBCLK <42> USB3_PTX_DRX_P1 USB3_PRX_DTX_N1 USB3_1_TXP GPP_A1/LAD0/ESPI_IO0 ESPI_IO1_R ESPI_IO0 <37,38> SYS_RESET#
1 2 Ext USB Port 1 Charge(RIGHT) B7 AV22 RC367 1 2 15_0402_5%
<42> USB3_PRX_DTX_N1 USB3_PRX_DTX_P1 USB3_1_RXN GPP_A2/LAD1/ESPI_IO1 ESPI_IO2_R ESPI_IO1 <37,38>
@ESD@ CC302
RH67 499_0402_1% A7 AT19 RC368 1 2 15_0402_5%
SML0_SMBDATA <42> USB3_PRX_DTX_P1 USB3_1_RXP GPP_A3/LAD2/ESPI_IO2 ESPI_IO3_R ESPI_IO2 <37,38>
0.1U_0402_25V6
1 2 BD16 RC369 1 2 15_0402_5%
USB3_PTX_DRX_N2 GPP_A4/LAD3/ESPI_IO3 ESPI_IO3 <37,38>
RH77 499_0402_1% B12
<35> USB3_PTX_DRX_N2 USB3_2_TXN
1
1 2 SML1_SMBCLK USB3_PTX_DRX_P2 A12 BE16
<35> USB3_PTX_DRX_P2 USB3_PRX_DTX_N2 C8 USB3_2_TXP GPP_A5/LFRAME#/ESPI_CS0# BA17 ESPI_ALERT# ESPI_CS# <37,38>
RH80 1K_0402_5%
SML1_SMBDATA
M.2 3042 (LTE) <35> USB3_PRX_DTX_N2 USB3_PRX_DTX_P2 USB3_2_RXN GPP_A6/SERIRQ/ESPI_CS1# ESPI_ALERT# <37>
1 2 B8 AW17
<35> USB3_PRX_DTX_P2 USB3_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0#
2
RH81 1K_0402_5% AT17 SIO_RCIN#
GPP_A0/RCIN#/ESPI_ALERT1# ESPI_RESET# SIO_RCIN# <37>
D
B15 BC18 D
C15 USB3_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <37>
K15 USB3_6_TXP
USB3_6_RXN
USB
K13 BC17 ESPI_CLK 1 2
USB3_6_RXP GPP_A9/CLKOUT_LPC0/ESPI_CLK PCI_CLK_LPC1 EMI@ RH97 1 ESPI_CLK_5105 <37,38>
+3.3V_PGPPBCH AV19 2 15_0402_5% ESD Request:place near PCH side
USB3_PTX_DRX_N5 B14 GPP_A10/CLKOUT_LPC1 @ RH99 22_0402_5%
<28> USB3_PTX_DRX_N5 USB3_PTX_DRX_P5 C14 USB3_5_TXN M45 CHECK,LPC_CLK FOR DEBUG CARD?
<28> USB3_PTX_DRX_P5 USB3_PRX_DTX_N5 G13 USB3_5_TXP GPP_G19/SMI# N43
PCH_SMB_ALERT#
Type C <28> USB3_PRX_DTX_N5 USB3_PRX_DTX_P5 USB3_5_RXN GPP_G18/NMI#
1 2 H13
<28> USB3_PRX_DTX_P5 USB3_5_RXP
RH61 4.7K_0402_5%
TLS CONFIDENTIALITY USB3_PTX_DRX_P3 D13 AE45
RF Request
HIGH ENABLE <43> USB3_PTX_DRX_P3 USB3_PTX_DRX_N3 C13 USB3_3_TXP GPP_E6/DEVSLP2 AG43 HDD_DEVSLP <41> ESPI_CLK_5105 1 2
LOW(DEFAULT) DISABLE <43> USB3_PTX_DRX_N3 USB3_PRX_DTX_P3 A9 USB3_2_TXN GPP_E5/DEVSLP1 AG42
Ext USB Port 2(LEFT) <43> USB3_PRX_DTX_P3 USB3_PRX_DTX_N3 USB3_3_RXP GPP_E4/DEVSLP0 M2280_DEVSLP <40>
@RF@ CC316 33P_0402_50V8J
B10 AB39
<43> USB3_PRX_DTX_N3 USB3_3_RXN GPP_F9/DEVSLP7 AB36
SATA
+3.3V_ALW_PCH USB3_PTX_DRX_P4 B13 GPP_F8/DEVSLP6 AB43
<43> USB3_PTX_DRX_P4 USB3_PTX_DRX_N4 A14 USB3_4_TXP GPP_F7/DEVSLP5 AB42
<43> USB3_PTX_DRX_N4 USB3_PRX_DTX_P4 G11 USB3_4_TXN GPP_F6/DEVSLP4 AB41 m3042_DEVSLP <35> SML0_SMBCLK 1 2
GPP_C5
Ext USB Port 3(REAR) <43> USB3_PRX_DTX_P4 USB3_PRX_DTX_N4 USB3_4_RXP GPP_F5/DEVSLP3
1 2 E11 @RF@ CC318 33P_0402_50V8J
<43> USB3_PRX_DTX_N4 USB3_4_RXN
ESPI@ RH78 4.7K_0402_5% 6 OF 12
EC interface SKL-H-PCH_BGA837 SML1_SMBCLK 1 2
HIGH ESPI @RF@ CC319 33P_0402_50V8J
LOW(DEFAULT) LPC
MEM_SMBCLK 1 2
@RF@ CC320 33P_0402_50V8J
+3.3V_ALW_PCH
Place close PCH side
1 2 SPKR
@ RH86 4.7K_0402_5%
TOP SWAP STRAP SPT-H_PCH +3.3V_LAN
UH1D
HIGH ENABLE RF@ 1 2 Rev_1.3
LOW(DEFAULT) DISABLE CH268 47P_0402_50V8J LAN_WAKE# 2 1
1 2 HDA_BIT_CLK BA9 BB17 @RL70 10K_0402_5%
<36> HDA_BIT_CLK_R EMI@ RH46 1 2 33_0402_5% HDA_RST# BD8 HDA_BCLK GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AW22 CLKRUN#
<36> HDA_RST#_R HDA_SDIN0 HDA_RST# GPP_A8/CLKRUN# CLKRUN# <37> +3.3V_ALW_PCH
RH50 33_0402_5% BE7
C +3.3V_ALW_PCH <36> HDA_SDIN0 BC8 HDA_SDI0 AR15 PM_LANPHY_ENABLE C
HDA_SDI1 GPD11/LANPHYPC PM_LANPHY_ENABLE <33>
ME_FWP 1 2
RH328 1 2 1K_0402_5% HDA_SDOUT BB7 AV13 SIO_SLP_WLAN#
<36> HDA_SDOUT_R HDA_SDO GPD9/SLP_WLAN# SIO_SLP_WLAN# <37,46>
RH45 1 2 33_0402_5% HDA_SYNC BD9 VRALERT# 1 2
1 2 KB_DET# <36> HDA_SYNC_R RH48 33_0402_5% HDA_SYNC BC14 DDR4_DRAMRST#_PCH @ RH203 10K_0402_5%
RC74 10K_0402_5% BD1 DRAM_RESET# BD23 VRALERT# DDR4_DRAMRST#_PCH <14> SIO_SLP_LAN# 1 2
BE2 RSVD_BD1 GPP_B2/VRALERT# AL27 @ RH204 10K_0402_5%
RSVD_BE2 GPP_B1 AR27 ME_SUS_PWR_ACK 1 2
AUD_AZACPU_SDO 1 2 AUD_AZACPU_SDO_R AM1 AUDIO GPP_B0 N44 @ RH327 10K_0402_5%
<9> AUD_AZACPU_SDO AUD_AZACPU_SDI_R DISPA_SDO GPP_G17/ADR_COMPLETE
RH39 30_0402_5% AN2 AN24
<9> AUD_AZACPU_SDI_R AUD_AZACPU_SCLK AUD_AZACPU_SCLK_R DISPA_SDI GPP_B11 SYS_PWROK
1 2 AM2 AY1
<9> AUD_AZACPU_SCLK DISPA_BCLK SYS_PWROK SYS_PWROK <7,37> +3.3V_DSW
RH38 30_0402_5%
AL42 BC13 PCH_PCIE_WAKE#
GPP_D8/I2S0_SCLK WAKE# SIO_SLP_A# PCH_PCIE_WAKE# <37,38> PCH_PCIE_WAKE#
AN42 BC15 1 2
AM43 GPP_D7/I2S0_RXD GPD6/SLP_A# AV15 SIO_SLP_LAN# SIO_SLP_A# <20,21,37> RH92 1K_0402_5%
AJ33 GPP_D6/I2S0_TXD SLP_LAN# BC26 SIO_SLP_S0# SIO_SLP_LAN# <37,46> LAN_WAKE# 1 2
TBT_PWR_EN AH44 GPP_D5/I2S0_SFRM GPP_B12/SLP_S0# AW15 SIO_SLP_S3# SIO_SLP_S0# <11,21,39,52> RH93 10K_0402_5%
T269@ PAD~D GPP_D20/DMIC_DATA0 GPD4/SLP_S3# SIO_SLP_S3# <21,37,38>
IR_CAM_DET# AJ35 BD15 SIO_SLP_S4# PCH_BATLOW# 1 2
<32> IR_CAM_DET# GPP_D19/DMIC_CLK0 GPD5/SLP_S4# SIO_SLP_S5# SIO_SLP_S4# <11,21,37,50,53>
AJ38 BA13 RH94 8.2K_0402_5%
KB_DET# AJ42 GPP_D18/DMIC_DATA1 GPD10/SLP_S5# SIO_SLP_S5# <21,37> AC_PRESENT 1 2
<44> KB_DET# GPP_D17/DMIC_CLK1
+RTC_CELL AN15 SUSCLK RH243 10K_0402_5%
GPD8/SUSCLK PCH_BATLOW# SUSCLK <35,40>
BD13
GPD0/BATLOW# BB19 SUSACK#
+3.3V_RUN +3.3V_ALW_PCH PCH_RTCRST# GPP_A15/SUSACK# ME_SUS_PWR_ACK SUSACK# <37> +3.3V_RUN
1 2 BC10 BD19
RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK ME_SUS_PWR_ACK <37>
RH2001 220K_0402_5% SRTCRST# BB10
SRTCRST#
150K_0402_5%
RH201 20K_0402_5%
2
PCH_PWROK LAN_WAKE#
@ RH347
AW11 BD11
<54> PCH_PWROK PCH_RSMRST#_AND PCH_PWROK GPD2/LAN_WAKE# AC_PRESENT LAN_WAKE# <33,37> SIO_RCIN#
1 2 RH329 BA11 BB15 1 2
<7,44> PCH_RSMRST#_AND RSMRST# GPD1/ACPRESENT AC_PRESENT <37>
RC327 0_0402_5% 150K_0402_5% BB13 LPC@ RH213 10K_0402_5%
PCH_DPWROK SLP_SUS# SIO_PWRBTN# SIO_SLP_SUS# <11,20,37,46,51,53>
AV11 AT13 SIO_PWRBTN# <7,37> CLKRUN# 1 2
<38> PCH_DPWROK PCH_SMB_ALERT# DSW_PWROK GPD3/PWRBTN# SYS_RESET#
BB41 AW1 SYS_RESET# <17,21> LPC@ RH202 8.2K_0402_5%
GPP_C2/SMBALERT# SYS_RESET#
1
GPP_B23 3 1 GPP_B23_Q MEM_SMBCLK AW44 BD26 SYS_PWROK 1 2

S
SPKR
SMBUS
GPP_C0/SMBCLK GPP_B14/SPKR SPKR <36>
@ QC3 MEM_SMBDATA BB43 AM3 H_PWRGD RH199 100K_0402_5%
GPP_C5 GPP_C1/SMBDATA PROCPWRGD H_PWRGD <7>
L2N7002WT1G_SC-70-3 BA40
SML0_SMBCLK GPP_C5/SML0ALERT# ITP_PMODE_CPU PAD~D @ T192
AY44 AT2
G
ITP_PMODE_CPU <7>
2
B 1 2 <33> SML0_SMBCLK SML0_SMBDATA BB39 GPP_C3/SML0CLK ITP_PMODE AR3 PCH_JTAGX IR_CAM_DET# 1 2 B

<20,21,37> SIO_SLP_A# <33> SML0_SMBDATA GPP_B23 AT27 GPP_C4/SML0DATA JTAGX AR2 PCH_JTAG_TMS PCH_JTAGX <7>
RH367 0_0402_5% JTAG PCH_JTAG_TMS <7> RH373 100K_0402_5%
SML1_SMBCLK AW42 GPP_B23/SML1ALERT#/PCHHOT# JTAG_TMS AP1 PCH_JTAG_TDO PCH_JTAG_TCK 1 2
<37> SML1_SMBCLK SML1_SMBDATA GPP_C6/SML1CLK JTAG_TDO PCH_JTAG_TDI PCH_JTAG_TDO <7>
1 2 AW45 AP2 @ RH313 51_0402_5%
0,37,46,51,53> SIO_SLP_SUS# <37> SML1_SMBDATA GPP_C7/SML1DATA JTAG_TDI PCH_JTAG_TCK PCH_JTAG_TDI <7> PCH_PWROK
@ RH368 0_0402_5% AN3 1 2
JTAG_TCK PCH_JTAG_TCK <7>
@ RH424 10K_0402_5%
4 OF 12 @ T182 SUSCLK 1 2
PAD~D
SKL-H-PCH_BGA837 @ T183 @ RH83 1K_0402_5%
PAD~D
EXI BOOT STALL BYPASS PAD~D @ T186
PAD~D @ T187
HIGH ENABLED PAD~D @ T188
LOW(DEFAULT) DIABLED
WEAK INTERNAL PD +1.0V_VCCSTG
PCH_JTAG_TMS 1 2
1 2 SRTCRST# RH312 51_0402_5%
Service Mode Switch: CH41 1U_0402_6.3VAK PCH_JTAG_TDI 1 2
Add a switch to ME_FWP signal to unlock the ME region and 1 2 PCH_RTCRST# RH314 51_0402_5%
allow the entire region of the SPI flash to be updated using FPT. CH40 1U_0402_6.3VAK PCH_JTAGX 1 2 PCH_JTAG_TDO 1 2
<21,37> PCH_RTCRST# @ESD@ CC305 0.1U_0402_25V6 RH315 51_0402_5%
PCH_JTAG_TDI 1 2
+3.3V_ALW_PCH +3.3V_RUN @ESD@ CC304 0.1U_0402_25V6
ME_FW_EC 1 2 ME_FWP 1 2 PCH_JTAG_TDO 1 2 +3.3V_RUN
@ RH100 0_0402_5% 1 2 @ESD@ CC303 0.1U_0402_25V6
RH215 PT,ST pop RH101 and SW1; MP pop RH100
1
@ CMOS1 SHORT PADS~D ESD request,Place near PCH side. DDR_XDP_WAN_SMBDAT 1 2

POP NO Support Deep sleep RH101 RH374 2.2K_0402_5%
2
1K_0402_5% DDR_XDP_WAN_SMBCLK 1 2
DE-POP Support Deep sleep RH333 2.2K_0402_5%
MEM_SMBCLK 6 1
DDR_XDP_WAN_SMBCLK <7,14,15,41>
2
PCH_DPWROK 1 2 PCH_RSMRST#_AND SW1

@ RH215 0_0402_5% 1 QH4A
<37> ME_FW_EC A
2 DMN65D8LDW-7_SOT363-6
B
1
ME_FWP
0.01U_0402_16V7K
100K_0402_5%
1 3
C
1
10K_0402_5%
@
A 4 A
G1 MEM_SMBDATA
CH266
RH308
RC75
5 3 4
G2 DDR_XDP_WAN_SMBDAT <7,14,15,41>
2 SS3-CMFTQR9_3P
2
QH4B
ME_FWP PCH has internal 20K PD.
2
DMN65D8LDW-7_SOT363-6
(suspend power rail)
FLASH DESCRIPTOR SECURITY OVERRIDE DELL CONFIDENTIAL/PROPRIETARY
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
Title
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
1 2 FFS_INT2
RH378 10K_0402_5%
1 2 GPP_C8
SPT-H_PCH
@ RH207 100K_0402_5% Reserved UH1K
1 2 3.3V_TS_EN Rev_1.3
RH375 100K_0402_5% BBS_BIT6 AT29 AL44 MEM_INTERLEAVED
1 2 LPSS_UART2_TXD 3.3V_TS_EN AR29 GPP_B22/GSPI1_MOSI GPP_D9 AL36 DGPU_HOLD_RST#
<32> 3.3V_TS_EN SIO_EXT_SCI# GPP_B21/GSPI1_MISO GPP_D10 AR_DET#
@ RH360 49.9K_0402_1% AV29 AL35
LPSS_UART2_RXD <37> SIO_EXT_SCI# HDD_FALL_INT GPP_B20/GSPI1_CLK GPP_D11
1 2 <41> HDD_FALL_INT BC27 AJ39 DGPU_PWR_EN
@ RH361 49.9K_0402_1% GPP_B19/GSPI1_CS# GPP_D12
1 2 HDD_FALL_INT NRB_BIT BD28 AJ43
TPM_PIRQ# GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS# ISH_UART0_CTS# <35> +3.3V_RUN
RH355 10K_0402_1% BD27 AL43
SIO_EXT_SCI#
<39> TPM_PIRQ# ONE_DIMM# GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS# ISH_UART0_RTS# <35>
1 2 AW27 AK44
D
MEDIACARD_IRQ# AR24 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL AK45 ISH_UART0_TXD <35> WLAN D
RH339 10K_0402_5%
1 2 NRB_BIT <34> MEDIACARD_IRQ# GPP_B15/GSPI0_CS# GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA ISH_UART0_RXD <35>
@ RH331 4.7K_0402_5% AV44 LCD_CBL_DET# RC370 1 2 10K_0402_5%
PCH STRAPS IF SAMPLED HIGH[ NO REBOOT ] <38> SBIOS_TX GPP_C8 BA41 GPP_C9/UART0_TXD
AU44 GPP_C8/UART0_RXD
AV43 GPP_C11/UART0_CTS# PCH_DP2_CTRL_DATA RH221 1 2 2.2K_0402_5%
+3.3V_ALW_PCH GPP_C10/UART0_RTS# BC38 PCH_DP1_CTRL_CLK RH222 1 2 2.2K_0402_5%
HDD_EN AU41 GPP_H20/ISH_I2C0_SCL BB38 PCH_DP1_CTRL_DATA RH223 1 2 2.2K_0402_5%
<41> HDD_EN LCD_CBL_DET# GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA PCH_DP3_CTRL_CLK
AT44 RH224 1 2 2.2K_0402_5%
<32> LCD_CBL_DET# RTD3_CIO_PWR_EN GPP_C14/UART1_RTS#/ISH_UART1_RTS# PCH_DP3_CTRL_DATA
T259@ PAD~D
AT43 BD38 RH225 1 2 2.2K_0402_5%
1 2 SIO_EXT_WAKE# SIO_EXT_WAKE# AU43 GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL BE39
<37> SIO_EXT_WAKE# GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
RH309 10K_0402_5%
8/20 AN43
1 2 LPSS_UART2_TXD AN44 GPP_C23/UART2_CTS#
RH330 49.9K_0402_1% LPSS_UART2_TXD AR39 GPP_C22/UART2_RTS# BC22 LID_CL#_PCH
LPSS_UART2_RXD GPP_C21/UART2_TXD GPP_A23/ISH_GP5 TPM_TYPE PAD~D @ T268
AR45 BD18
1 2 LPSS_UART2_RXD GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BE21
RH376 49.9K_0402_1% I2C1_SCK_TP AR41 GPP_A21/ISH_GP3 BD22
<44> I2C1_SCK_TP I2C1_SDA_TP GPP_C19/I2C1_SCL GPP_A20/ISH_GP2
AR44 BD21
<44> I2C1_SDA_TP GPP_C18/I2C1_SDA GPP_A19/ISH_GP1
1 2 EDP_HPD AR38 BB22 CLKDET#
GPP_C17/I2C0_SCL GPP_A18/ISH_GP0 PAD~D @ T258
RH1 100K_0402_5% AT42 BC19
TBT_FORCE_PWR AM44 GPP_C16/I2C0_SDA GPP_A17/ISH_GP7
T260@ PAD~D GPP_D4/ISH_I2C2/I2C3_SDA
FFS_INT2 AJ44
<41> FFS_INT2 GPP_D23/ISH_I2C2_SCL/I2C3_SCL
11 OF 12
SKL-H-PCH_BGA837
TPM_TYPE 1 2
Reserved @ RH379 100_0402_1%
C C
+3.3V_ALW_PCH
1
@ RH311
8.2K_0402_5%
2
BBS_BIT6
BOOT BIOS Destination(Bit 6)

HIGH LPC UH1E SPT-H_PCH
LOW(DEFAULT) SPI Rev_1.3
+5V_ALW
PCH_DP1_HPD AW4 BB3 CONN@

<26> PCH_DP1_HPD PCH_DP2_HPD GPP_I0/DDPB_HPD0 GPP_I7/DDPC_CTRLCLK PCH_DP2_CTRL_DATA
AY2 BD6 JUART1
<28,29> PCH_DP2_HPD PCH_DP3_HPD GPP_I1/DDPC_HPD1 GPP_I8/DDPC_CTRLDATA PCH_DP1_CTRL_CLK
AV4 BA5 1
<25> PCH_DP3_HPD GPP_I2/DDPD_HPD2 GPP_I5/DDPB_CTRLCLK PCH_DP1_CTRL_DATA PCH_DP1_CTRL_CLK <26> LPSS_UART2_TXD 1
BA4 BC4 2
GPP_I3/DDPE_HPD3 GPP_I6/DDPB_CTRLDATA PCH_DP3_CTRL_CLK PCH_DP1_CTRL_DATA <26> LPSS_UART2_RXD 2
BE5 3
GPP_I9/DDPD_CTRLCLK PCH_DP3_CTRL_DATA PCH_DP3_CTRL_CLK <25> 3
BE6 4
GPP_I10/DDPD_CTRLDATA PCH_DP3_CTRL_DATA <25> 4
Y44 5
EDP_HPD BD7 GPP_F14 V44 6 GND
<32> EDP_HPD GPP_I4/EDP_HPD GPP_F23 GND
W39
GPP_F22 L43 CVILU_CI1804M1VRA-NH
GPP_G23 L44
GPP_G22 U35
GPP_G21 R35
GPP_G20 BD36
B GPP_H23 B
5 OF 12
SKL-H-PCH_BGA837
+3.3V_ALW_PCH +3.3V_ALW_PCH Check ME about wire to board PN

JAPS1
+3.3V_RUN 1
+3.3V_ALW_PCH 1
2
<20,37,38> SIO_SLP_S3# 2
3
10K_0402_5%
+3.3V_ALW 3
2
@ RH267
4
<20,37> SIO_SLP_S5# 4
2
2
5
@ RH371 <11,20,37,50,53> SIO_SLP_S4# 5
RH400 6
<20,37> SIO_SLP_A# 6
10K_0402_5% 10K_0402_5% 7
+3.3V_ALW 7
8
8
1
9
<20,37> PCH_RTCRST#
1
1
ONE_DIMM# 10 9
11 10
<38,45> POWER_SW#_MB 11
1
MEM_INTERLEAVED AR_DET#
10K_0402_5%
12
13 12
<17,20> SYS_RESET# 13
RH268
14
15 14
<11,20,39,52> SIO_SLP_S0# 15
16
16
2
17
18 17
RH372 @ RH401 18
10K_0402_5%
19
10K_0402_5% GND
20
GND
2
DIMM Detect DIMM TYPE AR_DET# CONN@

Intel Management Engine Test Suite ACES_50506-01841-P01
HIGH 1 DIMM HIGH Interleave HIGH NON AR
A A
LOW 2 DIMM
LOW Non-Interleave LOW AR
Title
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_ALW +3.3V_PUSBDSW
+1.0V_PRIM +1.0V_ALW_PCH
1 2
RH276 0_0603_5%
1 2
RH254 0_1206_5%
SPT-H_PCH
+1.0V_PRIM UH1H
+RTC_CELL +3.3V_PRTC Rev_1.3 +2.8V_FHV
+1.0V_ALW_PCH +1.0V_DSW NO CAP AA23
AA26 VCCPRIM_1P0 +3.3V_DSW
1 2 0.0002A AA28 VCCPRIM_1P0 AL22 +3.3V_1.8V_GPPA
VCCPRIM_1P0 VCCPRIM_1P0
CORE
D
1 2 0.0454A RH297 0_0402_5% AC23 D
@ RH255 0_0402_5% +1.0V_CLK5 AC26 VCCPRIM_1P0 BA24 NO CAP +3.3V_PGPPBCH
AC28 VCCPRIM_1P0 VCCDSW_3P3
VCCPRIM_1P0
VCCGPIO
+1.0V_CLK1 +1.0V_CLK2 AE23 BA31 +3.3V_PGPPEF
AE26 VCCPRIM_1P0 VCCPGPPA BC42 +3.3V_PGPPG
1 2 0.0348A +1.0V_DSW Y23 VCCPRIM_1P0 VCCPGPPBCH BD40 +3.3V_PHVC
RH256 0_0402_5% +1.0V_CLK4 Y25 VCCPRIM_1P0 VCCPGPPBCH AJ41
+1.0V_CLK1 BA29 VCCPRIM_1P0 VCCPGPPEF AL41
+1.0V_CLK3 +1.0V_CLK3 DCPDSW_1P0 VCCPGPPEF AD41
NO CAP N17 VCCPGPPG AN5
1 2 0.0237A NO CAP R19 VCCCLK1 VCCPRIM_3P3 +1.0V_DTS
RH257 0_0402_5% NO CAP U20 VCCCLK3 +3.3V_RUN_ATS
+3.3V_ALW_PCH +3.3V_ALW_PCHRES NO CAP V17 VCCCLK4 AD15 +3.3V_PRTCPRIM
+1.0V_CLK4 R17 VCCCLK2 VCCPRIM_1P0 AD13 +3.3V_PRTC
VCCCLK2 VCCATS BA20
1 2 0.0327A 1 2 K2 VCCRTCPRIM_3P3 BA22
VCCCLK5 VCCRTC
0.1U_0201_10V6K
RH258 0_0402_5% RH279 0_0603_5% K3 BA26 +DCPRTC
+1.0V_MPHY VCCCLK5 DCPRTC
1
CH68
+1.0V_CLK2 U21 AJ20 +1.0V_PRIM
U23 VCCMPHY_1P0 VCCPRIM_1P0 AJ21
MPHY
+3.3V_ALW_PCHRES +3.3V_1.8V_GPPA
1 2 0.205A U25 VCCMPHY_1P0 VCCPRIM_1P0 AJ23
RH259 0_0402_5% +1.0V_AMPHYPLL U26 VCCMPHY_1P0 VCCPRIM_1P0 AJ25 +3.3V_1.8V_SPI 2
1 2 0.0879A V26 VCCMPHY_1P0 VCCPRIM_1P0
+1.0V_F24 LPC@ RH291 0_0402_5% eSPI Power A43 VCCMPHY_1P0 BE41 NO CAP
+1.8V_ALW_PCHRES B43 VCCAMPHYPLL_1P0 VCCSPI BE43
1 2 0.0046A C44 VCCAMPHYPLL_1P0 VCCSPI BE42
VCCMIPIPLL_1P0 VCCSPI +3.3V_1.8V_GPPD
RH260 0_0402_5% +1.0V_APLLEBB C45
1 2 +1.0V_DUSB VCCMIPIPLL_1P0 BC44
VCCPGPPD NO CAP
+1.0V_DUSB ESPI@ RH294 0_0402_5% NO CAP V28 BA45
+1.0V_AUSB VCCAPLLEBB_1P0 VCCPGPPD
USB
AC17 BC45
1 2 0.533A AJ5 VCCPRIM_1P0 VCCPGPPD BB45
VCCUSB2PLL_1P0 VCCPGPPD +3.3V_1.8V_FUSE
RH286 0_0402_5% +3.3V_ALW_PCHRES +3.3V_1.8V_AZIO AL5
1 2 +1.0V_AAZPLL_R AN19 VCCUSB2PLL_1P0 BD3
+1.0V_AAZPLL VCCHDAPLL_1P0 VCCPRIM_3P3
+2.8V_FHV BLM15GA750SN1D_2P 1 2 +3.3V_1.8V_AZIO_R BA15 BE3
+3.3V_1.8V_AZIO VCCHDA VCCPRIM_3P3
1 2 0.075A LC2 BLM15GA750SN1D_2P BE4
1 2 0.0908A RH292 0_0402_5% W15 VCCPRIM_3P3
LC1 +3.3V_PUSBDSW VCCDSW_3P3
C C
RH287 0_0402_5% +1.8V_ALW_PCHRES 8 OF 12
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1 SKL-H-PCH_BGA837
+1.0V_DTS RF Request
CC330
CC311
CC329
CC310
1 2
1 2 0.0061A @ RH295 0_0402_5%
RH288 0_0402_5% 2@ 2 2@ 2 +3.3V_1.8V_AZIO_R +1.0V_APLLEBB
+1.0V_MPHY
PJP3 +3.3V_ALW_PCHRES +3.3V_1.8V_GPPD
2 1 2.10A
2 1 1 2 0.0395A 1 1
2.2P_0402_50V8C
2.2P_0402_50V8C
JUMP_43X79 RH293 0_0402_5%
+1.8V_ALW_PCHRES
RF@ CC327
RF@ CC328
1 2 2 2
@ RH296 0_0402_5%
+1.0V_APLLEBB
1 2 0.095A
RH290 0_0402_5%
SPT-H_PCH
UH1J
Rev_1.3
AR22
RSVD PAD~D @ T66
+3.3V_ALW_PCH BD2 W13
VSS RSVD PAD~D @ T67
+3.3V_PRTCPRIM BD45 U13
BD44
1 2 0.0002A BE44 VSS P31
RH298 0_0402_5% D45 N31
+3.3V_PHVC A42
B45 VSS P27
1 2 0.2875A B44 R27 @
VSS RSVD PAD~D T72
RH299 0_0402_5% A4 N29 @ T74
VSS RSVD PAD~D
B +3.3V_1.8V_FUSE A3 P29 @ T73
B
VSS RSVD PAD~D
B2 AN29 @ T76
VSS RSVD PAD~D
1 2 0.0811A A2 R24 @
VSS RSVD PAD~D T75
RH300 0_0402_5% B1 P24 @
VSS RSVD PAD~D T77
+3.3V_DSW BB1
BC1 VSS AT3 PCH_XDP_PREQ#
VSS PREQ# PCH_XDP_PRDY# PCH_XDP_PREQ# <7>
1 2 0.0811A A44 AT4
VSS PRDY# CPU_XDP_TRST# PCH_XDP_PRDY# <7>
@ RH306 0_0402_5% AY5
CPU_TRST# PCH_2_CPU_TRIGGER_R CPU_XDP_TRST# <7>
+3.3V_ALW_PCHRES +3.3V_1.8V_SPI C1 AL2
+3.3V_ALW D1 RSVD PCH_TRIGOUT AK1 CPU_2_PCH_TRIGGER
RSVD PCH_TRIGIN CPU_2_PCH_TRIGGER <10>
1 2
1 2 0.403A RH246 0_0603_5%
RH301 0_0603_5% 10 OF 12
SKL-H-PCH_BGA837
+3.3V_RUN +3.3V_RUN_ATS
1 2 0.0066A
RH302 0_0402_5% +1.8V_ALW_PCHRES PCH_2_CPU_TRIGGER_R 1 2 PCH_2_CPU_TRIGGER
PCH_2_CPU_TRIGGER <10>
RH42 30_0402_5%
1 2
+3.3V_ALW_PCH @ RH250 0_0603_5%
+3.3V_PGPPEF +1.8V_PRIM
1 2 0.14107A 1 2
RH303 0_0402_5% RH247 0_0603_5%
+3.3V_PGPPBCH
1 2 0.27262A
RH304 0_0402_5%
+3.3V_PGPPG
1 2 0.1318A
A RH305 0_0402_5% A
Title
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+1.0V_ALW_PCH +1.0V_AMPHYPLL +3.3V_PUSBDSW +1.0V_MPHY +3.3V_PRTCPRIM
1 2 0.0248A
RH289 0_0603_5%
22U_0805_6.3VAM
22U_0805_6.3VAM
1U_0402_6.3VAK
1U_0402_6.3VAK
1U_0402_6.3VAK
22U_0603_6.3V6M
1U_0402_6.3VAK
0.1U_0402_25V6
1 1 1 1 1 1 1 1
@ CH323
@ CH324
@ CH31
CH267
CH34
CH47
CH37
CH67
2 2 2 2 2 2 2 2
D D
+1.0V_DUSB
+3.3V_PGPPEF +1.0V_DSW
+1.0V_ALW_PCH +VCCAUSB_VCCAAZPLL_1P0 +1.0V_AUSB
0.1U_0201_10V6K
1U_0402_6.3VAK
1
@ CH62
1U_0402_6.3VAK
1 2 1 2 1 1
CH38
RH238 0_0603_5% RH239 0_0603_5%
22U_0805_6.3VAM
22U_0805_6.3VAM
CH35
2
1 1 2 2
@ CH44
@ CH45
+1.0V_AAZPLL
2 2
1 2
RH240 0_0603_5%
+3.3V_RUN_ATS
+3.3V_PGPPBCH
+1.0V_F24 +1.0V_CLK5
C C
1U_0402_6.3VAK
1
0.1U_0402_25V6
1 2 1
@ CH63
CH36
RH241 0_0603_5%
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1U_0402_6.3VAK
1 1 1 2
@ CH29
@ CH46
@ CH32
2 2 2
+3.3V_PGPPG +3.3V_PHVC
+3.3V_PRTC
0.1U_0201_10V6K
@ CH64
0.1U_0402_25V6
1 1
@ CH66
1U_0402_6.3VAK
0.1U_0402_25V6
1 1
@ CH33
@ CH65
2 2
2 2
B B
A A
Title
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
D D
UH1I SPT-H_PCH
Rev_1.3 UH1L SPT-H_PCH
Rev_1.3
AC18 AR5
AN4 VSS VSS AR7 C42 AB11
AN10 VSS VSS U15 D10 VSS VSS AB7
BE14 VSS VSS AL4 D12 VSS VSS AB14
BE18 VSS VSS AE29 D15 VSS VSS AB31
BE32 VSS VSS AF18 D19 VSS VSS AB4
BE37 VSS VSS AF20 D21 VSS VSS AB5
BE40 VSS VSS AF21 D24 VSS VSS AC1
BE9 VSS VSS AF23 D25 VSS VSS AC20
C10 VSS VSS AF25 D27 VSS VSS AC21
J7 VSS VSS AG11 D33 VSS VSS AB8
K10 VSS VSS AG13 D35 VSS VSS AD11
K27 VSS VSS AG31 D36 VSS VSS AD14
K33 VSS VSS AG32 E13 VSS VSS AB15
K36 VSS VSS AG33 E15 VSS VSS AD32
K43 VSS VSS AH1 F44 VSS VSS AD4
L12 VSS VSS AH17 F8 VSS VSS AD8
L13 VSS VSS AH18 G42 VSS VSS AE18
C L15 VSS VSS AH20 G9 VSS VSS AE20 C
L4 VSS VSS AH21 H17 VSS VSS AE21
M35 VSS VSS AH26 H24 VSS VSS AL10
M42 VSS VSS AH28 H27 VSS VSS AL11
N10 VSS VSS AH29 H29 VSS VSS AL13
N15 VSS VSS AH45 H3 VSS VSS AL17
N19 VSS VSS AJ10 H35 VSS VSS AL19
N22 VSS VSS AJ14 J10 VSS VSS AL24
N41 VSS VSS AJ28 T42 VSS VSS AM15
N5 VSS VSS AJ29 U10 VSS VSS AM17
P17 VSS VSS AJ31 U11 VSS VSS AM19
P45 VSS VSS AK4 U18 VSS VSS AM27
R10 VSS VSS AK42 U28 VSS VSS AM29
R14 VSS VSS AU7 U29 VSS VSS AM45
R22 VSS VSS AV17 U31 VSS VSS AN11
T1 VSS VSS AV6 U8 VSS VSS AN7
T2 VSS VSS AW13 V18 VSS VSS AN8
T4 VSS VSS AW19 V20 VSS VSS AP11
Y18 VSS VSS AW29 V21 VSS VSS AP4
Y20 VSS VSS AW37 V23 VSS VSS AR33
Y21 VSS VSS AW9 V25 VSS VSS AR34
Y26 VSS VSS AY38 V29 VSS VSS AR42
Y28 VSS VSS AY45 V3 VSS VSS AR9
B Y29 VSS VSS B25 V45 VSS VSS AT10 B
A18 VSS VSS B3 W14 VSS VSS AT15
A37 VSS VSS B6 W33 VSS VSS AU1
AA17 VSS VSS BA1 W38 VSS VSS AU35
AA18 VSS VSS BB11 W4 VSS VSS AU36
AA20 VSS VSS BB16 W8 VSS VSS AU39
AA21 VSS VSS BB21 Y17 VSS VSS AU45
AA25 VSS VSS BB25 VSS VSS C4
AA29 VSS VSS BB30 VSS
AA4 VSS VSS BB34
AA42 VSS VSS BC2
AB10 VSS VSS BD43
VSS VSS 12 OF 12
9 OF 12 SKL-H-PCH_BGA837
SKL-H-PCH_BGA837
A A
Title
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
D D
+3.3V_RUN
1 2 SW1_PS8338_CFG0
RV125 4.7K_0402_5% CV62 CV61 close to pin30 &57 +3.3V_RUN
1 2 SW1_PS8338_SW CV66,CV69,CV70 close to pin5,21,51
@ RV126 4.7K_0402_5%
Priority : WIGI -> VGA
0.01UF_0402_25V7K
0.01UF_0402_25V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 2 SW1_PS8338_P0
RV127 4.7K_0402_5% 1 1 1
1
2 SW1_DP1_AUXN
CV62
CV63
CV64
1 UV8
CV60
CV61
RV128 100K_0402_5%
1 2 SW1_DP2_AUXN 5
VDD33
2
RV129 100K_0402_5% 2 2 2 21 50
30 VDD33 OUT1_D0p 49 SW1_DP1_P0 <35>
51 VDD33 OUT1_D0n SW1_DP1_N0 <35>
57 VDD33 47
VDD33 OUT1_D1p 46 SW1_DP1_P1 <35>
OUT1_D1n SW1_DP1_N1 <35>
CV65 1 2 0.1U_0201_10V6K CPU_DP3_P0_C 6 45
1 2 SW1_DP1_CADET <9> CPU_DP3_P0
CV66 1 2 0.1U_0201_10V6K CPU_DP3_N0_C 7 IN_D0p OUT1_D2p 44 SW1_DP1_P2 <35> WIGI
<9> CPU_DP3_N0 IN_D0n OUT1_D2n SW1_DP1_N2 <35>
RV130 1M_0402_5%
1 2 SW1_DP2_CADET CV67 1 2 0.1U_0201_10V6K CPU_DP3_P1_C 9 42
<9> CPU_DP3_P1 CPU_DP3_N1_C IN_D1p OUT1_D3p SW1_DP1_P3 <35>
RV131 1M_0402_5% CV68 1 2 0.1U_0201_10V6K 10 41
1 2 SW1_DP1_AUXP <9> CPU_DP3_N1 IN_D1n OUT1_D3n SW1_DP1_N3 <35>
RV132 100K_0402_5% CV69 1 2 0.1U_0201_10V6K CPU_DP3_P2_C 12
<9> CPU_DP3_P2 IN_D2p
1 2 SW1_DP2_AUXP CV70 1 2 0.1U_0201_10V6K CPU_DP3_N2_C 13 40
<9> CPU_DP3_N2 IN_D2n OUT2_D0p SW1_DP2_P0 <27>
RV133 100K_0402_5% 39
CV71 1 2 0.1U_0201_10V6K CPU_DP3_P3_C 15 OUT2_D0n SW1_DP2_N0 <27>
<9> CPU_DP3_P3 CPU_DP3_N3_C IN_D3p
CV72 1 2 0.1U_0201_10V6K 16 37
<9> CPU_DP3_N3 IN_D3n OUT2_D1p SW1_DP2_P1 <27>
36
OUT2_D1n SW1_DP2_N1 <27>
35 VGA
+3.3V_RUN 4 OUT2_D2p 34
C 3 IN_CA_DET OUT2_D2n C
<21> PCH_DP3_HPD 2 IN_HPD 32
SW1_PS8338_P1 1 I2C_CTL_EN OUT2_D3p 31
SW1_PS8338_P0 60 Pl1/SCL_CTL OUT2_D3n
Pl0/SDA_CTL
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
1
for support TMDS signal need contact SCL/SDA to P22,23 26

OUT1_AUXp_SCL SW1_DP1_AUXP <35>
22 27
RV55
RV57
RV59
RV61
RV63
RV65
<21> PCH_DP3_CTRL_CLK IN_DDC_SCL OUT1_AUXn_SDA SW1_DP1_AUXN <35>

23
<21> PCH_DP3_CTRL_DATA CPU_DP3_AUXP_C IN_DDC_SDA
CV73 1 2 0.1U_0201_10V6K 24 28
<9> CPU_DP3_AUXP CPU_DP3_AUXN_C IN_AUXp OUT2_AUXp_SCL SW1_DP2_AUXP <27>
@ @ @ @ @ CV74 1 2 0.1U_0201_10V6K 25 29
<9> CPU_DP3_AUXN SW1_DP2_AUXN <27>
2
SW1_PS8338_P1 IN_AUXn OUT2_AUXn_SDA

SW1_PS8338_CFG0 59 43 SW1_DP1_CADET
SW1_PS8338_PC10 58 CFG0 OUT1_CA_DET 48
SW1_PS8338_PC10 CFG1 OUT1_HPD SW1_DP1_HPD <35>
56
SW1_PS8338_PC11 SW1_PS8338_PC11 55 PC10 33 SW1_DP2_CADET
SW1_PS8338_PC20 54 PC11 OUT2_CA_DET 38
SW1_PS8338_PC20 SW1_PS8338_PC21 53 PC20 OUT2_HPD SW1_DP2_HPD <27>
PC21 18 SW1_PS8338_SW
SW1_PS8338_PC21 11 SW 8 SW1_PS8338_PEQ
19 GND PEQ 14
SW1_PS8338_PEQ 52 GND PD 17
61 GND CEXT 20
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
PAD(GND) REXT
1
1
4.99K_0402_1%
2.2U_0402_6.3V6M
PS8338BQFN60GTR-A0_QFN60_5X9
RV56
RV58
RV60
RV62
RV64
RV66
1
RV50
CV75
@ @ @ @ @
2
2
2
B B
Port switching control or prioritP configuration. Internal pull down ~150KΩ, 3.3V I/O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H):
SW = L: Port1 has higher prioritP when both ports are plugged (default)
SW = H: Port2 has higher prioritP when both ports are plugged
vender sugguest MUX use LLEQ PEQ=M and PI0=H !!
Programmable input equalization levels, Internal pull down at ~150Kohm,3.3V I/O

PEQ =
L: default,LEQ, compensate channel loss up to 11.5dB @HBR2
H: HEQ, compensate channel loss up to 14.5dB @HBR2
M:LLEQ, compensate channel loss up to 8.5dB @HBR2
PI0:Automatic EQ disable, Internal pull down ~150K ohm, 3.3V I/O

PI0 = L: Automatic EQ enable(default)
H: Automatic EQ disable
A A
Title
DP SW2 PS8338
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
For Breckenridge 14
+5V_RUN
0.1U_0201_10V6K
1
1
CV39
+VHDMI_VCC
2
IN
D D
AP2330W-7_SC59-3
UV2
0.1U_0201_10V6K
10U_0603_10V6M
@
1
1
CV40
CV41
EMI@ RV24 1 2 5.6_0402_5%
GND
OUT
HDMI_L_TX_P2
@EMI@ LV3
2
2
1 2 HDMI_TX_P2 1 4 EMI@ 2
<9> CPU_DP1_P0 1 4
3
CV31 0.1U_0402_25V6 RV26
<9> CPU_DP1_N0
1 2 HDMI_TX_N2 2
2 3
3
200_0402_5%
HDMI connector
CV32 0.1U_0402_25V6
1
HCM1012GH900BP_4P HDMI_L_TX_N2
1 2
EMI@ RV25 5.6_0402_5% JHDMI1 CONN@
HDMI_HPD 19
EMI@ RV27 1 2 5.6_0402_5% 18 HP_DET
HDMI_L_TX_P1 17 +5V
@EMI@ LV6 +3.3V_RUN HDMI_CTRL_DATA 16 DDC/CEC_GND
SDA
2
1 2 HDMI_TX_P1 1 4 EMI@ HDMI_CTRL_CLK 15
<9> CPU_DP1_P1 1 4 14 SCL
CV33 0.1U_0402_25V6 RV29
2 1 HDMI_CEC 13 Reserved
200_0402_5% CEC
1 2 HDMI_TX_N1 2 3 10K_0402_5% @ RV19 HDMI_L_CLKN 12 20
<9> CPU_DP1_N1 2 3 CK- GND
CV34 0.1U_0402_25V6 11 21
1
HCM1012GH900BP_4P HDMI_L_TX_N1 HDMI_L_CLKP 10 CK_shield GND 22
1 2 HDMI_L_TX_N0 9 CK+ GND 23
EMI@ RV28 5.6_0402_5% 8 D0- GND
HDMI_L_TX_P0 7 D0_shield
EMI@ RV30 1 2 5.6_0402_5% HDMI_L_TX_N1 6 D0+
HDMI_L_TX_P0 5 D1-
@EMI@ LV9 HDMI_L_TX_P1 4 D1_shield
D1+
2
1 2 HDMI_TX_P0 1 4 EMI@ HDMI_L_TX_N2 3
<9> CPU_DP1_P2 1 4 D2-
CV35 0.1U_0402_25V6 RV32 2
HDMI_L_TX_P2 1 D2_shield
200_0402_5% D2+
C 1 2 HDMI_TX_N0 2 3 C
<9> CPU_DP1_N2 2 3
CV36 0.1U_0402_25V6 CONCR_099BKAC19YBLCNF
1
HCM1012GH900BP_4P HDMI_L_TX_N0
1 2
EMI@ RV31 5.6_0402_5%
LINK 099BKAC19YBLCNF DONE
EMI@ RV33 1 2 5.6_0402_5%
HDMI_L_CLKP
@EMI@ LV12 HDMI_TX_P2 RV10 1 2 470_0402_1% HDMI_OB
2
2 1 HDMI_CLKP 1 4 EMI@ HDMI_TX_N2 RV11 1 2 470_0402_1%
<9> CPU_DP1_P3 0.1U_0402_25V6 1 4 HDMI_TX_P1
CV37 RV35 RV12 1 2 470_0402_1%
200_0402_5% HDMI_TX_N1 RV13 1 2 470_0402_1%
2 1 HDMI_CLKN 2 3 HDMI_TX_P0 RV14 1 2 470_0402_1%
<9> CPU_DP1_N3 2 3 HDMI_TX_N0
CV38 0.1U_0402_25V6 RV15 1 2 470_0402_1%
1
HCM1012GH900BP_4P HDMI_L_CLKN HDMI_CLKP RV16 1 2 470_0402_1%
HDMI_CLKN RV17 1 2 470_0402_1%
1 2
EMI@ RV34 5.6_0402_5%
1
D
+3.3V_RUN RV18 1 2 10K_0402_5% 2 QV4

G L2N7002WT1G_SC-70-3
S
3
+3.3V_RUN
1M_0402_5%
2
RV20
2
G
B B
1
3 1 HDMI_HPD 1 2
<21> PCH_DP1_HPD RV21 20K_0402_5%
S
QV5
L2N7002WT1G_SC-70-3
+3.3V_RUN
QV3A +VHDMI_VCC
2
1 6 HDMI_CTRL_CLK 1 2
<21> PCH_DP1_CTRL_CLK
RV22 2.2K_0402_5%
5
4 3 HDMI_CTRL_DATA 1 2
<21> PCH_DP1_CTRL_DATA
RV23 2.2K_0402_5%
QV3B
A A
Title
HDMI CONN
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
For TBT SW2_DP2

For non-TBT SW1_DP2
For Realtek Solution
+3.3V_RUN +3.3V_RUN Place near UV6.4 Place near UV6.25 Place near UV6.26
+3.3V_RUN
+VCCK_12
60ohm/1A UV6 60ohm/1A
+3.3V_RUN +3.3V_VGA +VDD_DAC_33
0.1U_0402_25V6
0.1U_0402_25V6
2.2U_0402_16V6K
1 2 1 20 2 1 1 1 1
+VCCK_12 AVC33 VDD_DAC_33
0.1U_0402_25V6
CV103
CV104
CV105
0.1U_0402_25V6
LV14 BLM15PX600SN1D_2P 4 BLM15PX600SN1D_2P LV30 1
AVCC_12 +VCCK_12
CV106
D 14 25 D
VCC_33 VCCK_12 1
CV100
2 1 ISPSCL 0.1U_0402_10V7K 1 2 CV111 SW1_DP2_AUXP_C 2 26 2 2 2
<25> SW1_DP2_AUXP SW1_DP2_AUXN_C AUX_P PVCC_33 +3.3V_RUN 2
@ RV106 4.7K_0402_5% 0.1U_0402_10V7K 1 2 CV112 3 +CRT_VCC
2 1 ISPSDA <25> SW1_DP2_AUXN AUX_N 2
@ RV107 4.7K_0402_5% 0.1U_0402_10V7K 1 2 CV107 SW1_DP2_P0_C 5 17
<25> SW1_DP2_P0 SW1_DP2_N0_C LANE0_P HVSYNC_PWR VSYNC_CRT
0.1U_0402_10V7K 1 2 CV108 6 18
<25> SW1_DP2_N0 SW1_DP2_P1_C LANE0_N VSYNC HSYNC_CRT
0.1U_0402_25V6
4.7U_0402_6.3V6M
0.1U_0402_10V7K 1 2 CV109 7 19
2 1 SW1_DP2_HPD <25> SW1_DP2_P1 SW1_DP2_N1_C LANE1_P HSYNC
0.1U_0402_10V7K 1 2 CV110 8 1 1
<25> SW1_DP2_N1 LANE1_N
CV101
CV102
RV102 100K_0402_5%
+3.3V_RUN
RV123
RV124
1
1
2 4.7K_0402_5%
2 4.7K_0402_5%
10
9 POL1/SPI_CEB
POL2
RTD2166 BLUE_P
21
22
BLUE_CRT
GREEN_CRT 2 2
11 GREEN_P
12 GPI1/SPI_CLK 23 RED_CRT
13 GPI2/SPI_SI RED_P
GPI3/SPI_SO
CLK_DDC2_CRT 15
DAT_DDC2_CRT 16 VGA_SCL
VGA_SDA 27
ISPSCL 30 LDO_RSTB 28
ISPSDA 29 SMB_SCL EXT_CLK_IN 31
SMB_SDA EXT1.2V_CTRL
SW1_DP2_HPD 32 24
<25> SW1_DP2_HPD HPD GND 33
EPAD_GND
RTD2166-CG_QFN32_4X4
Operation Mode Table

POL1(P10)
C 0 1 C
0 X X
POL2
(P9) 1 ROM EEPROM
+5V_RUN
3
PJDLC05C_SOT23-3
PJDLC05C_SOT23-3
@ESD@ DV5
@ESD@ DV6
1
UV4
IN
AP2330W-7_SC59-3
GND
OUT
RED_CRT 1 2
EMI@ LV16 BLM15BB470SN1D_2P
3
B GREEN_CRT 1 2 +CRT_VCC B
BLUE_CRT 1 2
40mils
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
3.3P_0402_50V8C
3.3P_0402_50V8C
3.3P_0402_50V8C
1
1
1
75_0402_1%
75_0402_1%
75_0402_1%
1 1 1
1 1 1 CV134
RV116
RV117
RV118
CV129
CV130
CV131
1U_0402_6.3V6K
2 JCRT1
2 2 2
CV126
CV127
CV128
6
2
2
2 @ 2 @ 2 @ @ T200PAD~D JCRT-11 11
RED 1
7
12
+CRT_VCC GREEN 2
8
HSYNC_CONN 13
BLUE 3
9
2
2.2K_0402_5%
2.2K_0402_5%
VSYNC_CONN 14
@
1K_0402_5%
1K_0402_5%
RV119 M_ID2# 4 G 16
RV120
RV121
RV122
10 G 17
15
5
1
1
DAT_DDC2_CRT
0.1U_0402_16V4Z
1 CCM_C070546HR015M29CZR
CLK_DDC2_CRT
CV135
CONN@
HSYNC_CRT 1 2
EMI@ LV19 BLM15AG121SN1D_L0402_2P 2
VSYNC_CRT 1 2
EMI@ LV20 BLM15AG121SN1D_L0402_2P
22P_0402_50V8J
22P_0402_50V8J
A A
1 1
CV132
CV133
2 2
@
Title
DP to VGA & VGA Conn
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +3.3V_CPS
1 2
LT11 BLM15PX600SN1D_2P
+3.3V_RUN
10U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
TUSB546: Pop RT246,Depop CT122
1 1 1 1 PS8740:Depop RT246,Pop CT122
CT118
CT119
CT120
CT121
CT117
2 1
2
1K_0402_5%
@ RT145
D
2.2U_0402_6.3V6M @ CT122 D
2
2 2 2 2
UT9
1 2 +3.3V_CPS_R1 1 35 MUX1_USB_EQ1
RT246 0_0402_5% 6 VCC EQ1 38 MUX1_USB_EQ0
VCC EQ0
1
20
28 VCC 17 MUX1_I2C_EN MUX1_I2C_EN
VCC I2C_EN
2 MUX1_DPEQ1
20K_0402_5%
1K_0402_5%
DPEQ1
1
CPU_DP2_P0_C MUX1_DPEQ0
@ RT301
1 2 9 14
<9> CPU_DP2_P0 CPU_DP2_N0_C DP0p DPEQ0/A1
CT103 1 2 0.1U_0402_25V6 10
RT300
<9> CPU_DP2_N0 DP0n 3 MUX1_SSEQ1
CT104 0.1U_0402_25V6
1 2 CPU_DP2_P1_C 12 SSEQ1 11 MUX1_SSEQ0
<9> CPU_DP2_P1 CPU_DP2_N1_C DP1p SSEQ0/A0
CT105 1 2 0.1U_0402_25V6 13
<9> CPU_DP2_N1 DP1n
2
CT106 0.1U_0402_25V6
1 2 CPU_DP2_P2_C 15 21 MUX1_FLIP_SEL
<9> CPU_DP2_P2 CPU_DP2_N2_C DP2p FLIP/SCL MUX1_FLIP_SEL <29>
CT107 1 2 0.1U_0402_25V6 16
<9> CPU_DP2_N2 DP2n 22 MUX1_USB_SEL
CT108 0.1U_0402_25V6
CPU_DP2_P3_C CTL0/SDA MUX1_USB_SEL <29>
1 2 18
<9> CPU_DP2_P3 CPU_DP2_N3_C DP3p MUX1_DP_SEL
CT109 1 2 0.1U_0402_25V6 19 23 I2C Programming or Pin Strap Programming Select,Internally
<9> CPU_DP2_N3 DP3n CTL1/HPDIN MUX1_DP_SEL <29> 30k pull-up and 60k pull-down
CT110 0.1U_0402_25V6
I2C_EN =
31 34 0: Tie 1k to GND,Pin Strap(I2C disable)
<31> TBTA_RX1N RX1n TX1n TBTA_TX1N <31> R:Tie 20k to GND,TI Test Mode(I2C enabled)
30 33
<31> TBTA_RX1P RX1p TX1p TBTA_TX1P <31> F: Float,TI Test Mode(I2C enabled)
1:Tie 1k to VCC,I2C enabled
39 37
<31> TBTA_RX2N RX2n TX2p TBTA_TX2P <31>
40 36
<31> TBTA_RX2P RX2p TX2n TBTA_TX2N <31>
+3.3V_RUN 1 2 USB3_PTX_C_DRX_P5 8 5 USB3_PRX_C_DTX_P5 2 1

<20> USB3_PTX_DRX_P5 SSTXp SSRXp USB3_PRX_DTX_P5 <20>
CT113 1 2 0.1U_0402_25V6 USB3_PTX_C_DRX_N5 7 4 USB3_PRX_C_DTX_N5 CT111 2 1 0.1U_0402_25V6
<20> USB3_PTX_DRX_N5 SSTXn SSRXn USB3_PRX_DTX_N5 <20>
CT114 0.1U_0402_25V6 CT112 0.1U_0402_25V6
2 1 AUX1_SNOOP_EN# AUX1_SNOOP_EN# 29 27 TUSB546A_SBU1_R 1 2

SNK_CAD/DCI_DAT SBU1 TUSB546A_SBU2_R TBTA_SBU1 <29,31>
RT308 4.7K_0402_5% 1 2 32 26 @ RT132 1 2 0_0402_5%
<21,29> PCH_DP2_HPD HPDIN/DCI_CLK SBU2 TBTA_SBU2 <29,31>
RT380 0_0402_5% @ RT133 0_0402_5%
C 24 CPU_DP2_AUXP_C 2 1 C
for pin control , connect to PD GPIO
AUXp CPU_DP2_AUXN_C CPU_DP2_AUXP <9,29>
@@
Check I2C or Pin control 41 25 CT115 2 1 0.1U_0402_25V6
PAD AUXn CPU_DP2_AUXN <9,29>
CT116 0.1U_0402_25V6
TUSB546_QFN40_4X6
+3.3V_RUN
+3.3V_RUN CPU_DP2_AUXN_C 1 2
+3.3V_RUN +3.3V_RUN 100K_0402_5% RT131
2
CPU_DP2_AUXP_C
1K_0402_5%
@ RT143
1 2
2
2
1K_0402_5%
@ RT137
1K_0402_5%
@ RT247
100K_0402_5% RT130
1
1
MUX1_USB_EQ0
MUX1_SSEQ0 MUX1_DPEQ1
20K_0402_5%
1
1
1K_0402_5%
@ RT304
20K_0402_5%
20K_0402_5%
1
1
1K_0402_5%
@ RT302
1K_0402_5%
@ RT303
RT144
RT138
RT248
2
2
Ser the USB receiver equalizer gain for upstream facing Select the DisplayPort receiver equalizer gain ,Internally Ser the USB receiver equalizer gain for downstream facing
B SSTXP/N,Internally 30k pull-up and 60k pull-down 30k pull-up and 60k pull-down RX1 and RX2 when USB utilized,Internally 30k pull-up and B
SSEQ = DPEQ = 60k pull-down
0: Tie 1k to GND 0: Tie 1k to GND USB_EQ =
R:Tie 20k to GND R:Tie 20k to GND 0: Tie 1k to GND
F: Float F: Float R:Tie 20k to GND
1:Tie 1k to VCC 1:Tie 1k to VCC F: Float
1:Tie 1k to VCC
+3.3V_RUN +3.3V_RUN +3.3V_RUN

2
2
1K_0402_5%
1K_0402_5%
1K_0402_5%
@ RT135
@ RT139
@ RT141
1
MUX1_SSEQ1 MUX1_DPEQ0 MUX1_USB_EQ1

20K_0402_5%
20K_0402_5%
20K_0402_5%
1
1
1K_0402_5%
@ RT305
1K_0402_5%
@ RT306
1K_0402_5%
@ RT307
RT136
RT142
RT140
2
A A
Title
DP/USB3 Repeater SW2 TUSB546
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
For Non-AR config

+3.3V_VDD_PIC
+3.3V_TBTA_FLASH +3.3V_TBTA_FLASH
2
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
.1U_0402_16V7K
1
1
RT50
CT70
RT51
RT52
RT53
1
1 6 UPD1_SMBCLK_Q
<37> UPD1_SMBCLK
@ QT1A
2
DMN66D0LDW -7_SOT363-6
2
2
RT58 1 2 0_0402_5%
UT6
5
8 1 TBTA_ROM_CS#_PD_R
TBTA_ROM_HOLD#_PD 7 VCC CS# 2 TBTA_ROM_DO_PD_R
TBTA_ROM_CLK_PD_R 6 HOLD#(IO3) DO(IO1) 3 TBTA_ROM_W P#_PD 4 3 UPD1_SMBDAT_Q
TBTA_ROM_DI_PD_R CLK WP#(IO2) <37> UPD1_SMBDAT
5 4
DI(IO0) GND @ QT1B
D W 25Q80DVSSIG_SO8 DMN66D0LDW -7_SOT363-6 D
RT59 1 2 0_0402_5%
TBTA_ROM_CLK_PD_R 0_0402_5% 2 1 RT54 TBTA_ROM_CLK_PD

TBTA_ROM_DI_PD_R 0_0402_5% 2 1 RT55 TBTA_ROM_DI_PD
TBTA_ROM_DO_PD_R 0_0402_5% 2 1 RT56 TBTA_ROM_DO_PD RT60 1 2 0_0402_5% UPD1_SMBUS_ALERT#
TBTA_ROM_CS#_PD_R TBTA_ROM_CS#_PD <37> UPD1_ALERT#
0_0402_5% 2 1 RT57
+3.3V_TBTA_FLASH
JDB1
1
1 2 TBTA_ROM_CLK_PD_R
2 3 TBTA_ROM_DI_PD_R +5V_ALW
3 4 TBTA_ROM_DO_PD_R
7 4 5 TBTA_ROM_CS#_PD_R PJP8 TI is 1x47uf+1x0.1uf
8 GND 5 6 1 2
GND 6
JXT_FP241AH-006GAAM PAD-OPEN 1x3m +TBTA_Vbus_1
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
CONN@ 1 1 1 1
CT75
CT76
CT77
CT78
2 2 2 2
+TBTA_LDO_BMC
+VCC1V8D_TBTA_LDO RT64 @ 1 2 0_0402_5%
+VCC1V8A_TBTA_LDO
RT65 @ 1 2 0_0402_5%
+3.3V_VDD_PIC +3.3V_VDD_PIC_PDA
HV_GATE1_A
HV_GATE2_A
2.2U_0402_16V6K
2.2U_0402_16V6K
2.2U_0402_16V6K
PJP7
1 1 1
TI is 3x1uf 1 2
+5V_ALW _PDA
CT71
CT72
CT73
PAD-OPEN1x1m
1U_0402_16V6K
2 2 2 1
1 2
CT74
RT63 0_0402_5%
C C
H10
C11
D11
A11
B11
B10
A10
2
H1
B1
K1
A2
E1
A6
A7
A8
B7
B9
A9
UT5
+3.3V_TBTA_FLASH
DIV = R2/(R1+R2) F1
VIN_3V3
VDDIO
LDO_1V8A
PP_CABLE
PP_5V0
PP_5V0
PP_5V0
PP_5V0
SENSEP
HV_GATE1
HV_GATE2
LDO_1V8D
LDO_BMC
GND
GND
GND
GND
SENSEN
Factory Device Description I2C_ADDR
DIV_min DIV_max Configuration RT378
RT379
2
2
1 10K_0402_5%
1 10K_0402_5%
D1
D2 I2C_SDA1 +TBTA_Vbus_1
+3.3V_TBTA_FLASH C1 I2C_SCL1
UFP only +3.3V_TBTA_FLASH I2C_IRQ1_N TI has 1x1uf
5V @0.9A Sink capability with "Ask for Max/" for +3.3V_ALW
0.00 0.08 0 anything from 0.9 -3.0A @ RT66 2 1 3.3K_0402_5% UPD1_SMBDAT_Q A5 +3.3V_PDA_VOUT +3.3V_TBTA_FLASH
TBT Alternate Modes not supported 1 3.3K_0402_5% UPD1_SMBCLK_Q I2C_SDA2
1U_0603_25V6K
@ RT67 2 B5 H11
DisplayPort Alternate Modes not supported I2C_SCL2 VBUS
2
1
@ RT68 2 1 10K_0402_5% UPD1_SMBUS_ALERT# B6 J10
TI VID supported RT76 I2C_IRQ2_N VBUS
CT82
J11
10U_0603_6.3V6M
1U_0402_16V6K
10K_0402_1% VBUS 1 1
MUX1_FLIP_SEL 2 1 MUX1_FLIP_SEL_R B2 K11
CT83
RT69 0_0402_5%
<28> MUX1_FLIP_SEL
2
2 1 EN_PD_HV_1_R C2 GPIO0 VBUS
CT84
UFP only RT70 0_0402_5%
5V @0.9A Sink capability with "Ask for Max/" for <59> EN_PD_HV_1 PD1_GPIO2 GPIO1
RT71 2 1 1M_0402_5% D10
1
0.10 0.18 1 anything from 0.9 -3.0A PD1_GPIO8 RT72 2 1 0_0402_5% AC1_DISC#_R G11 GPIO2 2 2
TBT Alternate Modes not supported <57,59> AC1_DISC# PCH_DP2_HPD_R GPIO3
RT73 2 1 0_0402_5% C10
DisplayPort Alternate Modes -Sink, C and D pin configuration <21,28> PCH_DP2_HPD
1
@ RT74 2 1 0_0402_5% OTG_ID E10 GPIO4 H2

TI VID supported <17> USB2_ID PD1_GPIO6 GPIO5 VOUT_3V3
RT377 @ RT75 2 1 0_0402_5% G10
@ RT339 2 1 0_0402_5% PD1_GPIO7 D7 GPIO6
43K_0402_1%
UFP only PD1_GPIO8 H6 GPIO7
0.20 0.28 2 5V @3.0A Source capability GPIO8 G1
2
TBT Alternate Modes not supported TBTA_ROM_CLK_PD A3 LDO_3V3

DisplayPort Alternate Modes not supported TBTA_ROM_DI_PD B4 SPI_CLK
TI VID supported TBTA_ROM_DO_PD A4 SPI_MOSI
TBTA_ROM_CS#_PD B3 SPI_MISO K6
SPI_SS_N C_USB_TP TBTA_TOP_P <31>
UFP only L6 TBTA_TOP_N <31>
0.30 0.38 3 5V @3.0A Source capability L5 C_USB_TN
TBT Alternate Modes not supported UART_MOSI <17> USB20_P4 USB_RP_P
2 1 K5
DisplayPort Alternate Modes -Sink, C and D pin configuration UART_MOSI <17> USB20_N4 USB_RP_N
RT81 100K_0402_5%
TI VID supported 2 1 UART_MISO RT83 2 1 0_0402_5% E2 K7
UART_MISO UART_TX C_USB_BP TBTA_BOT_P <31>
@ RT82 1M_0402_5% F2 L7 TBTA_BOT_N <31>
DRP UART_RX C_USB_BN
5V @0.9-3.0A Sink capability @ RT84 2 1 0_0402_5% F4
5V @3.0A Source capability @ T219 PAD~D SWD_DATA
0.40 0.48 TI SPEC: 100K PD @ RT85 2 1 0_0402_5% G4 TI has 2x220pf
TBT Alternate Modes not supported @ T220 PAD~D SWD_CLK TBTA_CC1 <31>
4 INTEL SCH :1M PD L9
DisplayPort Alternate Modes not supported C_CC1 L10
TI VID supported C_CC2 WHEN CONNECT BUSPOWERZ TO GND,
220P_0402_50V8J
220P_0402_50V8J
Accepts data and power role swaps, but does not TBTA_MRESET TBTA_CC2 <31>
initiate. RT86 2 1 1M_0402_5% E11 CONNECT ALSO RPD_Gn to C_CCn 1 1
MRESET
B B
K9 1 2 0_0402_5%
CT85
CT86
RT104
DRP @ RT87 1 2 0_0402_5% TBTA_LSTX_R L4 RPD_G1 K10 RT105 1 2 0_0402_5%
5V @0.9-3.0A Sink capability @ RT88 1 2 0_0402_5% TBTA_LSRX_R K4 TBT_LSTX/R2P RPD_G2 +3.3V_TBTA_FLASH 2 2
5V @3.0A Source capability TBT_LSRX/P2R
0.50 0.58 5 TBT Alternate Modes not supported
DisplayPort Alternate Modes - Source, C, D, and E MUX1_DP_SEL/MUX1_USB_SEL control by: RT89 1 2 0_0402_5% TBTA_DEBUG3 L3 E4 TBTA_DBG_CTL1 RT106 1 2 10K_0402_5%
pin configurations. GPIO: Pop RT69,RT90;Depop RT375,RT376 <28> MUX1_DP_SEL MUX1_USB_SEL TBTA_DEBUG4 DIG_AUD_P/DEBUG3 DEBUG_CTL1 TBTA_DBG_CTL2
RT90 1 2 0_0402_5% K3 D5 RT107 1 2 10K_0402_5%
TI VID supported I2C:Depop RT69,RT90;pop RT375,RT376 <28> MUX1_USB_SEL DIG_AUD_N/DEBUG4 DEBUG_CTL2
Accepts power role swaps but will not initiate.
Accepts data role swap to UFP and can initiate.
MUX1_FLIP_SEL @ RT375 1 2 0_0402_5% UPD1_SMBCLK_Q RT92 1 2 0_0402_5% TBTA_DEBUG1 L2
DRP MUX1_USB_SEL @ RT376 1 2 0_0402_5% UPD1_SMBDAT_Q RT93 1 2 0_0402_5% TBTA_DEBUG2 K2 DEBUG1
5V @0.9-3.0A Sink capability DEBUG2
5V @3.0A Source capability K8 TBTA_SBU1_R 1 2
TBT Alternate Modes not supported TBTA_AUXP_C C_SBU1 TBTA_SBU1 <28,31>
0.60 0.68 6 CT80 1 2 0.1U_0201_10V6K J1 RT108 0_0402_5%
DisplayPort Alternate Modes - Source, C, D, and E <9,28> CPU_DP2_AUXP TBTA_AUXN_C AUX_P TBTA_SBU2_R
pin configurations. Route in pass through manner so AUX can be snooped bP 546 <9,28> CPU_DP2_AUXN
CT81 1 2 0.1U_0201_10V6K J2
AUX_N C_SBU2
L8 1 2
TBTA_SBU2 <28,31>
TI VID supported RT109 0_0402_5%
Accepts power role swaps but will not initiate.
Accepts data role swap to DFP and can initiate. F10
BUSPOWER_N F11 TBTA_RESET_N_EC_R @ RT110 2 1 0_0402_5%
0.70 1.00 7 Infinite boot retry from Flash to Host I/F cycles. +3.3V_TBTA_FLASH RESET_N
HRESET
TBTA_ROSC G2
+3.3V_TBTA_FLASH R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
15K_0402_0.1%
SS
2
@
0_0402_5%
RT100
TPS65982_BGA96
A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
RT98
2 1 TBTA_AUXN_C
RT95 100K_0402_5%
2
1
2 1 TBTA_AUXP_C
RT96 100K_0402_5% +VCC1V8D_TBTA_LDO 1 2
@ RT97 0_0402_5%
100K_0402_5%
1
0_0402_5%
1
1
RT101
RT103
0_0402_5%
CT87
RT99
0.22U_0402_16V7K
2 @
2
2
A A
Need Link TPS65982D
Title
[Type C]PD Controller TI
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+5V_ALW
DT1 +5V_PD_VDD +3.3V_VDD_PIC

2 1
+5V_TBT_VBUS UT7
1N4148WS-7-F_SOD323-2 1 5
DT2 VCC VOUT
2 1 2
@ GND
0.1U_0201_10V6K
1U_0402_10V6K
1N4148WS-7-F_SOD323-2 1 1 3 4
EN ADJ/NC
2.2U_0603_25V6K
0.1U_0402_25V6K
D 1 D
1
CT88
CT89
@
CT91
CT92
1 2 AP2112K-3.3TRG1_SOT23-5
2 2 RT111 100K_0402_5%
2
2
1
CT90
1U_0402_10V6K
2
+TBTA_Vbus_1
UT8
place near UT7
1
VCC
1U_0603_50V6K
DT3 1
1 2+5V_TBTA_VBUS_D 3
VOUT
CT94
2
1N4148WS-7-F_SOD323-2 GND
AP2204R-5.0TRG1_SOT89-3 2
1U_0402_10V6K
1
CT93
C C
B B
A A
Title
[Type C]PD Power
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
For NON AR Config
D D
+TBTA_VBUS +TBTA_VBUS +TBTA_VBUS

RF Request
JUSBC1
A1 B12 +TBTA_VBUS
GND_A1 GND_B12
1 2 TBTA_TX1P_C A2 B11 TBTA_RX1P
<28> TBTA_TX1P TBTA_TX1N_C TX1+ RX1+ TBTA_RX1N TBTA_RX1P <28>
CT95 1 2 0.22U_0201_6.3V6K A3 B10
<28> TBTA_TX1N TBTA_RX1N <28>
2
CT96 0.22U_0201_6.3V6K TX1- RX1-
2 1 A4 B9 1 2 ESD@ DT4
CT99 0.47U_0201_25V VBUS_A4 VBUS_B9 CT100 0.47U_0201_25V L30ESD24VC3-2_SOT23-3
TBTA_CC1 A5 B8 TBTA_SBU2
<29> TBTA_CC1 CC1 SBU2 TBTA_SBU2 <28,29>
12P_0402_50V8J
RF@ CT189
82P_0402_50V8J
RF@ CT190
1 1
EMI@ RT120 1 2 0_0402_5% TBTA_TOP_P_R A6 B7 TBTA_BOT_N_R EMI@ RT122 1 2 0_0402_5%
<29> TBTA_TOP_P TBTA_TOP_N_R D+_A6 D-_B7 TBTA_BOT_P_R TBTA_BOT_N <29>
EMI@ RT121 1 2 0_0402_5% A7 B6 EMI@ RT123 1 2 0_0402_5%
<29> TBTA_TOP_N TBTA_BOT_P <29>
Bottom
D-_A7 D+_B6
TOP
TBTA_SBU1 A8 B5 TBTA_CC2 2 2
<28,29> TBTA_SBU1 TBTA_CC2 <29>
1
SBU1 CC2
2 1 A9 B4 1 2
C VBUS_A9 VBUS_B4 C
0.47U_0201_25V CT101 CT102 0.47U_0201_25V
TBTA_RX2N A10 B3 TBTA_TX2N_C 2 1
<28> TBTA_RX2N TBTA_RX2P RX2- TX2- TBTA_TX2P_C 0.22U_0201_6.3V6K 2 TBTA_TX2N <28>
A11 B2 1 CT98
<28> TBTA_RX2P RX2+ TX2+ TBTA_TX2P <28>
0.22U_0201_6.3V6K CT97
A12 B1
GND_A12 GND_B1
1 4
2 GND1 GND4 5
3 GND2 GND5 6
GND3 GND6
JAE_DX07BD24JJ2
CONN@
ESD@ DT5 ESD@ DT13
TBTA_TX1P_C 1 2 TBTA_RX1P 1 2
ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2
ESD@ DT6 ESD@ DT14
TBTA_TX1N_C 1 2 TBTA_RX1N 1 2
ESD@ DT7 ESD@ DT15
TBTA_CC1 1 2 TBTA_SBU2 1 2
B B
ESD@ DT8 ESD@ DT16
TBTA_SBU1 1 2 TBTA_CC2 1 2
ESD@ DT9 ESD@ DT17
TBTA_RX2N 1 2 TBTA_TX2P_C 1 2
ESD@ DT10 ESD@ DT18
TBTA_RX2P 1 2 TBTA_TX2N_C 1 2
ESD@ DT11 ESD@ DT19
TBTA_TOP_P_R 1 2 TBTA_BOT_P_R 1 2
ESD@ DT12 ESD@ DT20
TBTA_TOP_N_R 1 2 TBTA_BOT_N_R 1 2
A A
Title
USB 3.0 CONN TYPE C
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
TOUCH_PANEL_INTR#:
Close lid >> TP_EN = 0 >> Disable touch events
+5V_TSP Open lid >> TP_EN = 1 >> Enable touch events EXC24CQ900U_4P
For Breckenridge 14
JEDP1
1 4 3
1 USB20_N9_R USB20_N9 <17>
2
2 3 USB20_P9_R
3 4 1 2
4 USB20_P9 <17>
5
5 TOUCH_SCREEN_PD# <19> LV27
6 EMI@
6
AZC199-02SPR7G_SOT23-3
7
DMIC0 <36>
3
7
@ESD@
8
8 9
3
9 DMIC_CLK0 <36>
10 +3.3V_RUN
10 11
D 11 USB20_N11_R +3.3V_CAM D
1
100P_0402_50V8J
@EMI@ CA5
100P_0402_50V8J
@EMI@ CA6
12
12
USB20_P11_R RF Request
DV4
13
1
13
1
14 +5V_TSP
14 CAM_MIC_CBL_DET# <16>
15
15 Pin15: LOOP_BACK
16
2
16 17
17 +BL_PWR_SRC
18
18 19 +3.3V_RUN
19 ESD depop location
20
20 21 EMI@ LV1 1 2 BIA_PWM
10K_0402_5%
21
2
DISP_ON
12P_0402_50V8J
RF@ CV18
82P_0402_50V8J
RF@ CV19
22 BLM15PX221SN1D_2P ESD Request
RV8
22 1 1
23
23 24
24 25
25 26 +LCDVDD 2 2
EDP_HPD <21>
1
26 27 TOUCH_SCREEN_DET#
27 28 EDP_HPD 1 2
28 29 @ RV7 100K_0402_5%
29 30
LCD_TST <37> If touch panel, GPIO Low-> Touch Mic. EQ ;
30 31 Reserve for EA others the GPIO is High -> Non-Touch Mic.
31 +LCDVDD
32 TOUCH_SCREEN_DET# EQ
1TOUCH_SCREEN_DET#
32 EDP_AUXN_C <19>
33 CV1 2 0.1U_0402_25V6
33 EDP_AUXP_C EDP_AUXN <9>
34 CV2 2 1 0.1U_0402_25V6
34 EDP_TXP0_C EDP_AUXP <9>
35 CV3 2 1 0.1U_0402_25V6
35 EDP_TXN0_C EDP_TXP0 <9>
41 36 CV4 2 1 0.1U_0402_25V6
G1 36 EDP_TXP1_C EDP_TXN0 <9>
42 37 CV5 2 1 0.1U_0402_25V6
G2 37 EDP_TXN1_C EDP_TXP1 <9>
43 38 CV6 2 1 0.1U_0402_25V6
G3 38 EDP_TXN1 <9>
44 39
45 G4 39 40
G5 40 LCD_CBL_DET# <21>
ACES_50398-04041-001
CONN@
CONN@ JIR1 +PWR_SRC

+BL_PWR_SRC +LCDVDD +3.3V_CAM +5V_TSP +3.3V_RUN 1
1 IR_CAM_DET# <20>
2
2
0.1U_0603_50V7K
0.1U_0201_10V6K
100P_0201_25V7K
0.1U_0201_10V6K
100P_0201_25V7K
100P_0402_50V8J
RF@ CZ3
3 1
RF@ CZ1
RF@ CA7
3 4
1 1 1 1 4
1
@ CZ2
@
5
5
CV11
CV12
6 +PWR_SRC
6 7 2
2
C 2 2 2 2 GND C
8
GND
ACES_50208-0060N-P01
Close to JEDP1.17~19 Close to JEDP1.30~31 Close to JEDP1.11 Close to JEDP1.1 Close to JEDP1.10
RF Request
DV1 DV2
3 BIA_PWM_PCH 3
BIA_PWM_PCH <16> PANEL_BKEN_PCH <16>
BIA_PWM 1 DISP_ON 1
2 BIA_PWM_EC 2
BIA_PWM_EC <37> PANEL_BKEN_EC <37>
1
4.7K_0402_5%
4.7K_0402_5%
For Touchscreen
1
BAT54CW _SOT323-3 BAT54CW _SOT323-3

RV1
RV2
+5V_RUN +5V_TSP +5V_RUN

2
QV8
2
47K_0402_5%
LP2301ALT1G_SOT23-3
2
1 3
RV6
S
RF Request
G
1
2
+LCDVDD +3.3V_CAM +BL_PW R_SRC
L2N7002WT1G_SC-70-3
1
D
QV7
2
<21> 3.3V_TS_EN
G
12P_0402_50V8J
RF@ CV20
82P_0402_50V8J
RF@ CV21
12P_0402_50V8J
RF@ CV22
82P_0402_50V8J
RF@ CV23
12P_0402_50V8J
RF@ CV24
82P_0402_50V8J
RF@ CV25
1 1 1 1 1 1 S
3
2 2 2 2 2 2
B B
LCDVDD POWER +LCDVDD +EDP_VDD

+3.3V_ALW
@ CV16 PJP12 UV24
WebCAM Backlight POWER +BL_PWR_SRC

2 1 1 2 1
VOUT 5
10U_0603_10V6M VIN
+PWR_SRC QV1 PAD-OPEN1x1m 2
GND
0.01UF_0402_25V7K
4
+3.3V_CAM +3.3V_RUN EN
@
6
D
CV17
4 5 3
S
QZ1 2 /OC
LP2301ALT1G_SOT23-3 1 G524B1T11U_SOT23-5
2
1000P_0402_50V7K
0.1U_0603_50V7K
DV3
G
270K_0402_5%
2
1 3 AO6405_TSOP6
D
3
CV13
2
2
RV4
<37> LCD_VCC_TEST_EN EN_LCDPWR

CV15
1
G
2
3
<16,37> ENVDD_PCH
1
2
100K_0402_5%
RV3
<17> 3.3V_CAM_EN# BL_PWR_SRC_ON BAT54CW _SOT323-3
QV2
1
L2N7002W T1G_SC-70-3
0.01U_0402_50V7K
1
1 2 1 3
D
S
CV14
RV5 47K_0402_5%
EXC24CQ900U_4P
4 3 USB20_P11_R 2
G
<17> USB20_P11
2
A A
1 2 USB20_N11_R
<17> USB20_N11 <37> EN_INVPWR
LZ1 EMI@
Title
eDP CONN & Touch screen
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
Layout Notice : Place bead as

+3.3V_LAN UL1 close UL4 as possible
2 1 TP_LAN_JTAG_TMS CLKREQ_PCIE#4 48 13 LAN_MDIP0 RL71 1 2 2.2_0603_5% LAN_MDIP0_L
<18> CLKREQ_PCIE#4 CLK_REQ_N MDI_PLUS0 LAN_MDIN0 LAN_MDIN0_L
@ RL1 10K_0402_5% 36 14 RL72 1 2 2.2_0603_5%
TP_LAN_JTAG_TCK <19> PLTRST_LAN# PE_RST_N MDI_MINUS0
2 1
@ RL2 10K_0402_5% 44 17 LAN_MDIP1 RL73 1 2 2.2_0603_5% LAN_MDIP1_L
CLKREQ_PCIE#4 <18> CLK_PCIE_P4 PE_CLKP MDI_PLUS1 LAN_MDIN1 LAN_MDIN1_L
2 1 45 18 RL74 1 2 2.2_0603_5%
<18> CLK_PCIE_N4 PE_CLKN MDI_MINUS1
PCIE
@ RL4 4.7K_0402_5% 1 2 PCIE_PRX_C_DTX_P4
MDI
<17> PCIE_PRX_DTX_P4 LAN_MDIP2 LAN_MDIP2_L
CL1 0.1U_0402_25V6 38 20 RL75 1 2 2.2_0603_5%
1 2 PCIE_PRX_C_DTX_N4 39 PETp MDI_PLUS2 21 LAN_MDIN2 RL76 1 2 2.2_0603_5% LAN_MDIN2_L
<17> PCIE_PRX_DTX_N4 PETn MDI_MINUS2
CL2 0.1U_0402_25V6
D +3.3V_LAN 1 2 PCIE_PTX_C_DRX_P4 41 23 LAN_MDIP3 RL77 1 2 2.2_0603_5% LAN_MDIP3_L D
<17> PCIE_PTX_DRX_P4 PERp MDI_PLUS3 LAN_MDIN3 LAN_MDIN3_L
CL5 0.1U_0402_25V6 42 24 RL78 1 2 2.2_0603_5%
1 2 PCIE_PTX_C_DRX_N4 PERn MDI_MINUS3
<17> PCIE_PTX_DRX_N4
CL6 0.1U_0402_25V6
2
28 6 VCT_LAN_R1 1 2
10K_0402_5%
<20> SML0_SMBCLK SMB_CLK SVR_EN_N
SMBUS
31 0_0402_5% RL3
<20> SML0_SMBDATA SMB_DATA +RSVD_VCC3P3_1
1 4.7K_0402_5% 1 2 RL6
RL5 @
RSVD_VCC3P3_1 +3.3V_LAN
2 5
1
1 2 <20,37> LAN_WAKE# LAN_DISABLE#_R 3 LANWAKE_N VDD3P3_IN
<20> PM_LANPHY_ENABLE LAN_DISABLE_N +3.3V_LAN_OUT
RL7 0_0402_5% SMBus Device Address 0xC8 4 1 2 +3.3V_LAN
VDD3P3_4 0_0603_5% RL8
10K_0402_5%
15 1
VDD3P3_15
1
LOM_ACTLED_YEL#
@ RL9
0.1U_0201_10V6K
22U_0805_6.3V6M
LOM_SPD100LED_ORG#
26
LED0 VDD3P3_19
19
RF Request
CL7
CL28
27 29 Place CL28 close to UL1.5
LOM_SPD10LED_GRN# LED1 VDD3P3_29 +0.9V_LAN +3.3V_LAN_OUT
LED
25
2
LED2 2
47
2
VDD0P9_47 46
@ T88 PAD~D TP_LAN_JTAG_TDI 32 VDD0P9_46 37
@ T89 PAD~D TP_LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_37
+0.9V_LAN TP_LAN_JTAG_TMS JTAG_TDO
JTAG
33 43
TP_LAN_JTAG_TCK JTAG_TMS VDD0P9_43
@RF@ CL29
@RF@ CL30
35
JTAG_TCK
12P_0402_50V8J
82P_0402_50V8J
11 1 1
VDD0P9_11
XTALO_R 1 2 XTALO 9 40
XTAL_OUT VDD0P9_40
22U_0603_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
RL34 0_0402_5% XTALI 10 22

XTAL_IN VDD0P9_22
1
16 2 2
1 1 1 1 VDD0P9_16
1
+0.9V_LAN
CL9
CL10
CL11
CL8
8
LAN_TEST_EN VDD0P9_8
CL12
RL11 30
1M_0402_5% TEST_EN
2
2 2 2 2 YL1 RES_BIAS 12 7 +REGCTL_PNP10 1 2 +3.3V_LAN
2
3 1 RBIAS CTRL0P9 4.7UH_BRC2012T4R7MD_20% LL1
OUT IN
0.1U_0201_10V6K
10U_0603_10V6M
49 Idc_min=500mA
VSS_EPAD
1
27P_0402_50V8J
1K_0402_5%
3.01K_0402_1%
4 2 DCR=100mohm 1 @
GND GND
1
27P_0402_50V8J
CL3
CL4
W GI219LM-QREF- A0_QFN48_6X6~D
1
CL14
RL12
RL13
Note: 25MHZ_18PF_7V25000034
CL13
+1.0V_LAN will work at 0.95V to 1.15V
2
2
470P_0402_50V7K
change to SA000081G1L, S IC WGI219LM QREF A0 QFN 48P PHY
2
0.1U_0201_10V6K
1
CL18
CL19
C C
Place CL3, CL4 and LL1 close to UL1
RJ45 LOM circuit
2
2
+3.3V_LAN:20mils
JLOM1 CONN@
LAN_ACTLED_YEL# 1 2 LAN_ACTLED_YEL_R# 10
RL14 150_0402_5% Yellow LED-
9
Yellow LED+
RJ45_MDIN3 8
8
RJ45_MDIP3 7
7
RJ45_MDIN1 6
6
RJ45_MDIN2 5
5
RJ45_MDIP2 4
4
RJ45_MDIP1 3
3
RJ45_MDIN0 2
2 15
RJ45_MDIP0 1 GND_2
1 14
LED_10_GRN# 1 2 LED_10_GRN_R# 11 GND_1
RL19 150_0402_5% Green LED-
LED_100_ORG# 1 2 LED_100_ORG_R# 13
RL20 150_0402_5% Orange LED-
When LAN & WLAN are exist at the same time, WLAN will disable 12
TL1 Green-Orange LED+
1 24 Z2805
TCT1 MCT1 SANTA_130456-831
+3.3V_LAN LAN_MDIN3_L 2 23 RJ45_MDIN3
TD1+ MX1+
@ CL15 LAN_MDIP3_L 3 22 RJ45_MDIP3
1 2 TD1- MX1-
4 21 Z2807
0.1U_0201_10V6K TCT2 MCT2
B B
5
LAN_MDIN1_L 5 20 RJ45_MDIN1
LOM_SPD100LED_ORG# 1 TD2 MX2+
P
B 4 LAN_MDIP1_L 6 19 RJ45_MDIP1
LOM_SPD10LED_GRN# 2 O LOM_CABLE_DETECT# <37> TD2- MX2-
A
G
UL2 7 18 Z2806
TC7SH08FU_SSOP5~D TCT3 MCT3
3
LAN_MDIN2_L 8 17 RJ45_MDIN2
TD3+ MX3+
LAN_MDIP2_L 9 16 RJ45_MDIP2
TD3- MX3-
10 15 Z2808
QL1A TCT4 MCT4
DMN65D8LDW -7_SOT363-6 LAN_MDIN0_L 11 14 RJ45_MDIN0
LOM_ACTLED_YEL# 1 6 LAN_ACTLED_YEL# TD4+ MX4+
LAN_MDIP0_L RJ45_MDIP0
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
12 13
TD4- MX4-
1
+3.3V_LAN
2
CL16
CL17
CL20
CL21
350UH_IH-160
SYS_LED_MASK#
SYS_LED_MASK# <37,45>
2
2
1
RL29
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
1M_0402_5%
QL1B
2
LOM_SPD100LED_ORG#
4 3 LED_100_ORG#
+3.3V_LAN
5
1
SYS_LED_MASK#
RL30
1M_0402_5%
RL15 2
RL16 2
RL17 2
RL18 2
QL2A
2
LOM_SPD10LED_GRN# 1 6 LED_10_GRN#
GND 1 2 +GND_CHASSIS
EMI@ CL22 10P_1808_3KV8J
CHASSIS use 40mil trace if necessary
2
SYS_LED_MASK#
For WLAN can't recognize during enable
A Unobtrusive mode(BITS152312) A
QL2B
4 3
5

Title
LAN Clarkvillie & RJ45
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
For PCIE Interface
D D
+3.3V_RUN +3.3V_MMI_IN
PJP14
1 2
+3.3V_MMI_AUX +3.3V_MMI_IN
PAD-OPEN1x2m
+3.3V_MMI_IN +3.3V_MMI_AUX
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0402_6.3V6M
1 2
support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/off 3V3AUX)
1 1 1 1
CR4
0_0603_5% R274 @
CR3
CR1
CR2
2 2 2 2
+3.3V_MMI_AUX
2 1 MEDIACARD_IRQ# 7/18 Vender suggest.

RR19 10K_0402_5%
27
11
UR1
3V3aux
3V3_IN
1 12
<19,35,39,40> PCH_PLTRST#_AND PERST# CARD_3V3 +DV33_18 +3.3V_RUN_CARD
2 18 1 2
<18> CLKREQ_PCIE#5 CLK_REQ# DV33_18 CR22 1U_0402_6.3V6K
5
<18> CLK_PCIE_P5 REFCLKP SD/MMCDAT1/RCLK-_R
RF Request <18> CLK_PCIE_N5
6
REFCLKN SP1
15
16
SD/MMCDAT1/RCLK-
SD/MMCDAT0/RCLK+
RR9
RR10
1
1
2
2
0_0402_5%
0_0402_5% SD/MMCDAT0/RCLK+_R
+3.3V_MMI_AUX +3.3V_MMI_IN CR11 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P3 3 RTS5242 SP2 17 SD/MMCCLK EMI@ RR5 1 2 0_0402_5% SD/MMCCLK_R
<17> PCIE_PTX_DRX_P3 PCIE_PTX_C_DRX_N3 HSIP SP3 SD/MMCCMD_R
@EMI@ CR21
CR12 1 2 0.1U_0402_25V6 4 19 SD/MMCCMD RR6 1 2 0_0402_5%
<17> PCIE_PTX_DRX_N3 PCIE_PRX_C_DTX_P3 HSIN SP4 SD/MMCDAT3_R
5P_0402_50V8C
CR13 1 2 0.1U_0402_25V6 7 20 SD/MMCDAT3 RR7 1 2 0_0402_5%
<17> PCIE_PRX_DTX_P3 CR14 1 2 0.1U_0402_25V6 PCIE_PRX_C_DTX_N3 8 HSOP SP5 21 SD/MMCDAT2 RR8 1 2 0_0402_5% SD/MMCDAT2_R
<17> PCIE_PRX_DTX_N3 HSON SP6
1
29 SDWP
SP7
32
2
<21> MEDIACARD_IRQ# WAKE#
@RF@ CR27
@RF@ CR28
@RF@ CR25
@RF@ CR26
31
MS_INS#
12P_0402_50V8J
82P_0402_50V8J
12P_0402_50V8J
82P_0402_50V8J
1 1 1 1 SD/MMCCD# 30
C +1.2V_LDO SD_CD# C
7/18 Vender suggest
CR13 close to UR2.10 22 SD_UHS2_D1P EMI depop location
SD_LN1_P 23 SD_UHS2_D1N
2 2 2 2
CR9 CR10 close to UR2.14 SD_LN1_M
10
14 AV12 26 SD_UHS2_D0P
DV12S SD_LN0_P 25 SD_UHS2_D0N
SD_LN0_M
4.7U_0603_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
13
+1.8V_RUN_CARD SD_VDD2
1 1 24 +SDREG2 CR15 1 2
E-PAD
SDREG2
1
+RREF 9 28
CR5
1U_0402_6.3V6K
CR6
CR7
RREF GPIO SD_GPIO 2 1 +3.3V_MMI_AUX
10K_0402_5% RR3
2
2 2 RTS5242-GR_QFN32_4X4
33
1
6.2K_0402_1%
RR4
2
B B
QR1
L2N7002W T1G_SC-70-3
HOST_SD_WP# SDWP_Q SDWP STATUS
SDWP 1 3 SDWP_Q JSD1 CONN@
S
4
+3.3V_RUN_CARD VDD/VDD1
High High Write Protect(SD LOCK) 14
+1.8V_RUN_CARD SD/MMCCMD_R VDD2
2
G
2
High SD/MMCCLK_R 5 CMD
Low Low Write Enable CLK
<16> HOST_SD_WP#
SD/MMCCD# 18
SDWP_Q 19 CARD DETECT
High High Write Protect(SD& FW LOCK) WRITE PROTEC
Low SD/MMCDAT0/RCLK+_R 7
SD/MMCDAT1/RCLK-_R 8 DAT0/RCLK+
Low High Write Protect(FW LOCK) SD/MMCDAT2_R 9 DAT1/RCLK-
+3.3V_RUN_CARD +1.8V_RUN_CARD SD/MMCDAT3_R 1 DAT2
SD_UHS2_D0P 11 CD/DAT3
SD_UHS2_D0N 12 D0+
SD_UHS2_D1P 16 DO-
SD_UHS2_D1N 15 D1+ 20
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
D1- GND1 21
2 2 GND2
2
3 22
CR17
CR19
CR20
6 VSS1 GND3 23
CR18
10 VSS2 GND4 24
1
1 1 13 VSS3 GND5 25
17 VSS4 GND6 26
VSS5 GND7
T-SOL_156-2000302608_NR
CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14

LINK SP070011U00 DONE
A A
Title
Card Reader
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_WWAN
NGFF slot B Key B for Brekenridge 12/14/15 UMA

2 1 W W AN_PW R_EN
RZ43 47K_0402_5% +3.3V_WWAN
100P_0402_50V8J
For TBT SW2_DP1
RF@ CZ198
JNGFF2 CONN@
1 2
<37> SLOT2_CONFIG_3 1 2
1
3 4
5 3 4 6 W W AN_PW R_EN
For non-TBT SW1_DP1

USB20_P8_L 7 5 6 8 WWAN_RADIO_DIS#_R
NGFF slot A Key A
2
USB20_N8_L 9 7 8 10 SLOT2_SATA_LED# 1 2
9 10 SATALED# <16,40,45>
11 @ RN101 0_0402_5%
11
D +3.3V_WLAN D
12
13 12 14 JNGFF1 CONN@
<37> SLOT2_CONFIG_0 13 14
15 16 1 2
<37> WWAN_WAKE# 15 16 HW _GPS_DISABLE#_R USB20_P6_L 1 2
2 1 17 18 3 4
@RF@ RZ326 0_0402_5% 19 17 18 20 USB20_N6_L 5 3 4 6
USB3_PRX_L_DTX_N2 21 19 20 22 UIM_RESET 7 5 6
USB3_PRX_L_DTX_P2 23 21 22 24 UIM_CLK 7
25 23 24 26 UIM_DATA
USB3_PTX_L_DRX_N2 27 25 26 28
USB3_PTX_L_DRX_P2 27 28 +SIM_PWR
29 30 8
29 30 m3042_DEVSLP <20> 8
31 32 9 10
33 31 32 34 CV145 1 2 0.1U_0402_25V6 SW 1_DP1_N3_C 11 9 10 12 SW 1_DP1_AUXN_C 2 1
<16> PCIE_PRX_DTX_P17 33 34 <25> SW1_DP1_N3 11 12 SW1_DP1_AUXN <25>
35 36 CV146 1 2 0.1U_0402_25V6 SW 1_DP1_P3_C 13 14 SW 1_DP1_AUXP_C
0.1U_0402_25V6 2 1CV150
<16> PCIE_PRX_DTX_N17 35 36 <25> SW1_DP1_P3 13 14 SW1_DP1_AUXP <25>
37 38 15 16 0.1U_0402_25V6 CV149
CZ10 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_N17 39 37 38 40 CV148 1 2 0.1U_0402_25V6 SW 1_DP1_N2_C 17 15 16 18 SW 1_DP1_N1_C 2 1
<16> PCIE_PTX_DRX_N17
CZ11 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P17 41 39 40 42 PCH_PLTRST#_AND 9/24: Reserve for embedded location ,refer Intel PDG 0.9 <25> SW1_DP1_N2
CV147 1 2 0.1U_0402_25V6 SW 1_DP1_P2_C 19 17 18 20 SW 1_DP1_P1_C0.1U_0402_25V6 2 1CV152
SW1_DP1_N1 <25>
<16> PCIE_PTX_DRX_P17 41 42 <25> SW1_DP1_P2 19 20 SW1_DP1_P1 <25>
43 44 21 22 0.1U_0402_25V6 CV153
43 44 PCIE_W AKE# CLKREQ_PCIE#0 <18> 21 22 SW 1_DP1_N0_C
45 46 23 24 2 1
<18> CLK_PCIE_N0 45 46 <25> SW1_DP1_HPD 23 24 SW 1_DP1_P0_C0.1U_0402_25V6 SW1_DP1_N0 <25>
47 48 @ RZ131 2 1 0_0402_5% 25 26 2 1CV156
<18> CLK_PCIE_P0 47 48 PORT80_DET# <37> PCIE_PTX_C_DRX_P2 25 26 SW1_DP1_P0 <25>
49 50 @ RZ132 2 1 0_0402_5% CZ12 1 2 0.1U_0402_25V6 27 28 0.1U_0402_25V6 CV157
49 50 WWAN_COEX3 HOST_DEBUG_TX <37,38> <17> PCIE_PTX_DRX_P2 PCIE_PTX_C_DRX_N2 27 28
51 52 @RF@ RZ128 1 2 0_0201_5% W LAN_COEX3 CZ13 1 2 0.1U_0402_25V6 29 30
51 52 WWAN_COEX2 <17> PCIE_PTX_DRX_N2 29 30 PCH_CL_RST1# <16>
53 54 @RF@ RZ129 1 2 0_0201_5% W LAN_COEX2 31 32
53 54 WWAN_COEX1 31 32 PCH_CL_DATA1 <16>
55 56 @RF@ RZ130 1 2 0_0201_5% W LAN_COEX1 33 34
57 55 56 58 SIM_DET WLAN <17> PCIE_PRX_DTX_P2 35 33 34 36 W LAN_COEX3 PCH_CL_CLK1 <16>
59 57 58 60 <17> PCIE_PRX_DTX_N2 37 35 36 38 W LAN_COEX2
PAD~D @ T225 59 60 37 38 W LAN_COEX1
61 62 39 40
<37> SLOT2_CONFIG_1 61 62 <18> CLK_PCIE_P1 39 40 W IGIG_32KHZ
63 64 41 42 2 1
63 64 <18> CLK_PCIE_N1 41 42 PCH_PLTRST#_AND SUSCLK <20,40>
65 66 43 44 0_0402_5% RZ56
65 66 43 44 BT_RADIO_DIS#_R PCH_PLTRST#_AND <19,34,39,40>
67 45 46
<37> SLOT2_CONFIG_2 67 <18> CLKREQ_PCIE#1 PCIE_W AKE# 45 46 WLAN_WIGIG60GHZ_DIS#_R
47 48
<38,40> PCIE_WAKE# 49 47 48 50 ISH_UART0_RXD_R 2 1
PCIE_PTX_C_DRX_P1 49 50 ISH_UART0_TXD_R @ RZ78 2 ISH_UART0_RXD <21>
69 68 CZ14 1 2 0.1U_0402_25V6 51 52 1 0_0402_5%
GND GND <17> PCIE_PTX_DRX_P1 PCIE_PTX_C_DRX_N1 51 52 ISH_UART0_CTS#_R @ RZ79 2 ISH_UART0_TXD <21>
CZ15 1 2 0.1U_0402_25V6 53 54 1 0_0402_5%
<17> PCIE_PTX_DRX_N1 53 54 ISH_UART0_RTS#_R @ RZ80 2 ISH_UART0_CTS# <21>
55 56 1 0_0402_5%
55 56 PCH_PLTRST#_AND @ RZ81 ISH_UART0_RTS# <21>
57 58 0_0402_5%
BELLW _80149-4221 <17> PCIE_PRX_DTX_P1 59 57 58 60
WIGI <17> PCIE_PRX_DTX_N1 61 59 60 62 PCIE_W AKE# CLKREQ_PCIE#2 <18>
63 61 62 64
<18> CLK_PCIE_P2 63 64
65 66 9/24: Reserve for embedded location ,refer Intel PDG 0.9
<18> CLK_PCIE_N2 65 66
67
67
C
+3.3V_WWAN
RF Request C
69 68
GND GND
+3.3V_WWAN
BELLW _80148-4221
47P_0402_50V8J
100P_0402_50V8J
2200P_0402_50V7K
RF@
.047U_0402_16V7K
.047U_0402_16V7K
33P_0402_50V8J
22U_0603_6.3V6M
33P_0402_50V8J
RF@ CZ24
100U_B2_6.3VM_R35M
RF@ CZ26
1
RF@ CZ25
1
+
1
WWAN_RADIO_DIS#_R
CZ23
1 2
<37> WWAN_RADIO_DIS#
CZ17
CZ18
CZ19
CZ20
CZ21
2 DZ5
2
RB751S40T1G_SOD523-2
1 2 HW_GPS_DISABLE#_R
<37> HW_GPS_DISABLE#
DZ6
+3.3V_WLAN
1 2
@RF@ RI27 0_0402_5%
LI16 RF@
1 2 USB3_PRX_L_DTX_P2
<20> USB3_PRX_DTX_P2
0.01UF_0402_25V7K
0.1U_0201_10V6K
10U_0603_10V6M
0.01UF_0402_25V7K
0.1U_0201_10V6K
4.7U_0603_6.3V6K
4 3 USB3_PRX_L_DTX_N2
<20> USB3_PRX_DTX_N2 1 1 1
1
1 2 WLAN_WIGIG60GHZ_DIS#_R
<37> WLAN_WIGIG60GHZ_DIS#
CZ28
CZ30
CZ27
CZ29
CZ31
CZ32
HCM1012GH900BP_4P
1 2 DZ1
2
@RF@ RI28 0_0402_5% RB751S40T1G_SOD523-2 2 2 2
1 2
@RF@ RI29 0_0402_5%
LI17 RF@
2 1 USB3_PTX_C_DRX_P2 1 2 USB3_PTX_L_DRX_P2
<20> USB3_PTX_DRX_P2
CI30 0.1U_0402_25V6
Place near JNGFF1.72/JNGFF1.74 Place near JNGFF1.2/JNGFF1.4
B 2 1 USB3_PTX_C_DRX_N2 4 3 USB3_PTX_L_DRX_N2 1 2 BT_RADIO_DIS#_R B
<20> USB3_PTX_DRX_N2 <37> BT_RADIO_DIS#
CI29 0.1U_0402_25V6
HCM1012GH900BP_4P RF Request DZ2
1 2
@RF@ RI30 0_0402_5%
1 2
RF Request
+3.3V_WLAN
SIM Card Push-Push
@RF@ RI47 0_0402_5%
+SIM_PWR
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J
RF@ CZ33
RF@ CZ34
RF@ CZ35
RF@ CZ36
JSIM1 CONN@
4.7U_0402_6.3V6M
1 5 LI8 RF@
VCC GND
1
UIM_RESET USB20_P8_L
2
RST VPP
6
<17> USB20_P8
1 2 RF Request
1
UIM_CLK 3 7 UIM_DATA
CLK I/O
CZ37
4 8 1 2
2
RFU1 RFU2 4 3 USB20_N8_L @RF@ RI49 0_0402_5%
<17> USB20_N8
2
9 SIM_DET
DTSW MCM1012B900F06BP_4P
10
11 GND 14
12 GND GND 15
13 GND GND 16 1 2
GND GND @RF@ RI48 0_0402_5% LI9 RF@
4 3 USB20_P6_L
<17> USB20_P6
T-SOL_5-991503004000-6
1 2 USB20_N6_L
<17> USB20_N6
MCM1012B900F06BP_4P
Power Rating TBD
Primary Power Aux Power
+SIM_PWR
1 2 PWR Voltage
STATE # CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type m3042_PCIE#_SATA @RF@ RI50 0_0402_5%
Rail Tolerance
Peak Normal Normal
UIM_CLK
@RF@ RZ335
0 GND GND GND GND SSD-SATA High

1
15K_0402_5%
+3.3V
47P_0402_50V8J
@RF@ CZ38
A
1 GND HIGH GND GND SSD-PCIE(2 lane) Low A
1
+SIM_PWR
UIM_DATA UIM_RESET
8 HIGH GND GND GND WWAN Low
2
33P_0402_50V8J
33P_0402_50V8J
14 HIGH GND HIGH HIGH HCA-PCIE(1 lane) Low

@RF@ RZ334
@RF@ CZ39
@RF@ CZ40
1
51_0402_5%
0.1U_0402_25V6
RF@ CZ41
1
1
15 HIGH HIGH HIGH HIGH NA Low

2
2
2
Issued Date 2017/01/01 Title

2016/01/01 Deciphered Date
NGFF Card
RF Request AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
SPKR_R
100P_0402_50V8J
10K_0402_5%
1
1
BEEP_R
@ CA72
@ RA51
+5V_RUN_AUDIO
100P_0402_50V8J
10K_0402_5%
place close to pin41 place close to pin46 LA13
1
+5V_RUN_PVDD_L
@ CA62
@ RA45
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.) 1 2
HCB2012VF-601T20_2P
Internal Speakers Header
2
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
1 1 1 1 600 Ohm/2A 1 1
2
CA45
CA47
CA60
CA46
CA48
CA59
40 mils trace keep 20 mil spacing CONN@
2
JSPK1
INT_SPK_L+ EMI@ LA6 1 2 BLM15PX330SN1D_2P INT_SPKR_L+ 1 2 2 2 2 2 2
INT_SPK_L- EMI@ LA7 1 2 BLM15PX330SN1D_2P INT_SPKR_L- 2 1
INT_SPK_R+ EMI@ LA8 1 2 BLM15PX330SN1D_2P INT_SPKR_R+ 3 2
INT_SPK_R- EMI@ LA9 1 2 BLM15PX330SN1D_2P INT_SPKR_R- 4 3
5 4 +3.3V_RUN_AUDIO
D G1 D
L03ESDL5V0CC3-2_SOT23-3
6
3
G2 +5V_RUN_AUDIO
+3.3V_RUN_AUDIO_IO
@ESD@
@ESD@
ACES_50278-00401-001 2 1 LA5
LA12 BLM15PX600SN1D_2P +VDDA_AVDD1 place close to pin26 1 2
@EMI@ CA22
@EMI@ CA23
@EMI@ CA19
@EMI@ CA24
0.1U_0201_10V6K
10U_0603_10V6M
BLM15PX600SN1D_2P
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
10U_0603_10V6M
0.1U_0201_10V6K
1 RF Request
1
1
CA55
CA56
2 1 1
1
+5V_RUN_AUDIO
DA6
DA7
CA8
LA14 BLM15PX600SN1D_2P
CA9
2
2
2
0.1U_0201_10V6K
10U_0603_10V6M
1
2
2
1
1
CA10
CA61
place close to pin9
+1.8V_RUN
2
2 +3.3V_RUN_AUDIO_DVDD
+1.8V_RUN_AUDIO
12P_0402_50V8J
RF@ CA63
68P_0402_50V8J
RF@ CA64
place close to pin40 1 2 1 1
Close to UA1 RA3 0_0603_5%
10U_0603_10V6M
0.1U_0201_10V6K
place close to pin1 1
1
2 2
CA58
CA57
2
2
41
46
26
40
36
1
9
UA1
Close to UA1 pin6
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
CPVDD
HDA_BIT_CLK_R DMIC_CLK0 11
I2C_SDA AUD_HP_OUT_L
@EMI@ RA17
12 31 +LINE1-VREFO-L RA57 1 2 4.7K_0402_5%

I2C_SCL LINE1-VREFO-L AUD_HP_OUT_R
10P_0402_50V8J
@EMI@CA54
30 +LINE1-VREFO-R RA58 1 2 4.7K_0402_5% AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width

1
LINE1-VREFO-R
33_0402_5%
10 29 +MIC2-VREFO
<20> HDA_SYNC_R HDA_BIT_CLK_R SYNC MIC2-VREFO
<20> HDA_BIT_CLK_R HDA_SDOUT_R
6
5 BIT-CLK VREF
28
35 CA35
1 2
2.2U_0402_6.3V6M
RF Request
<20> HDA_SDOUT_R Place RA9 close to codec
2
1 2 HDA_SDIN0_R 8 SDATA-OUT CBN 37 2 1 +1.8V_RUN_AUDIO +1.8V_RUN

<20> HDA_SDIN0 RA9 33_0402_5% SDATA-IN CBP CA29 1U_0603_10V6K
Place CA29 close to Codec
2
100K_0402_5%1 2 RA52 4 20 @ RA53 1 2 0_0402_5%

+5V_ALW
EAPD/DC DET 5VSTB
10P_0402_50V8J
@EMI@ CA33
2 RA54 1 2 0_0402_5%
<32> DMIC0 DMIC_CLK0 1 DMIC_CLK_CODEC GPIO0/DMIC-DATA12 +RTC_CELL
place close to UA1 pin3 2 3 34 1 2 1 2 RING2
<32> DMIC_CLK0 GPIO1/DMIC-CLK CPVEE
1
EMI@ RA14 22_0402_5% 47 CA49 1U_0603_10V6K RA5 2.2K_0402_5%

PDB
RF@ CA69
+3.3V_RUN_AUDIO 10K_0402_5% 2 1 RA18 PD# 48 +MIC2-VREFO 1 2 SLEEVE
SPDIFO/GPIO2/DMIC-DATA-34/DMIC-CLK-In/MIC-GPI
33P_0402_50V8J
2 1 SLEEVE/RING2 please keep 40 mils trace width RA6 2.2K_0402_5%
2
C C
12P_0402_50V8J
RF@ CA65
68P_0402_50V8J
RF@ CA66
100K_0402_5% 2 1 RA44 27 1 1 1
1U_0603_10V6K 2 1 CA31 10U_0603_10V6M 2 1 CA51 39 LDO1-CAP 17 RING2 AUD_PC_BEEP 2 1 SPKR_R 1 2
LDO2-CAP MIC2-L/RING2 BEEP_R SPKR <20>
10U_0603_10V6M 2 1 CA52 7 18 SLEEVE CA27 2 1 0.1U_0402_25V6 RA12 1 2 1K_0402_5%
LDO3-CAP MIC2-R/SLEEVE BEEP <37>
10U_0603_10V6M CA53 19 1 2 CA28 0.1U_0402_25V6 RA13 1K_0402_5%
MIC-CAP 24 10U_0603_10V6M CA25 2 2 2
INT_SPK_L+ 42 LINE2-L 23
INT_SPK_L- 43 SPK-L+ LINE2-R 22 LINE1_L 1 2 HP_OUT_L
INT_SPK_R- 44 SPK-L- LINE1-L 21 LINE1_R 10U_0603_10V6M 1 2 CA43 HP_OUT_R AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
INT_SPK_R+ 45 SPK-R- LINE1-R 16 AUD_PC_BEEP
10U_0603_10V6M CA44
SPK-R+ PCBEEP 32 HP_OUT_L 1 2 AUD_HP_OUT_L
AUD_SENSE_A 13 HP-OUT-L 33 HP_OUT_R 16.2_0402_1% 1 2 RA7 AUD_HP_OUT_R
+3.3V_RUN_AUDIO 100K_0402_5% 1 2 RA61 AUD_SENSE_B 14 HP/LINE1 JD1 HP-OUT-R 16.2_0402_1% RA8
+3.3V_RUN_AUDIO MIC2/LINE2 JD2
15 25
SPDIFO/FRONT JD3/GPIO3 AVSS1 38
Place closely to Pin 13. AVSS2 49
100K_0402_1% 200K_0402_1%
THERMAL PAD
1
RA59
ALC3246-CG_MQFN48_6X6 RF Request
+3.3V_RUN_AUDIO
2
AUD_SENSE_A
0.1U_0402_25V6
1
@
CA41
RA60
2
2
12P_0402_50V8J
RF@ CA67
68P_0402_50V8J
RF@ CA68
Add for solve 1 1
AUD_HP_NB_SENSE
pop noise and
detect issue
2 2
CLASS-D POWER DOWN CONTROL CIRCUIT

Add this Filter to avoid other HP-Out-Right Nokia-MIC
components/chips be influenced
HP-Out-Left iPhone-MIC
B B
1 2
RA48 0_0402_5%
place at AGND and DGND plane
680P_0402_50V7K
@ESD@ CA13
1 2 @ DA8 1 2 1
<37> AUD_NB_MUTE#
RA35 0_0402_5%
RB751S40T1G_SOD523-2 PD#
Global Headset
1 2
1
PJP19
2 <20> HDA_RST#_R
1 2 2 Universal Jack
RA36 0_0402_5% @ RA50 0_0402_5%
HDA_Link is 3.3V,no need level shift circuit
PAD-OPEN1x1m JHP1 CONN@
1 2 7
RA37 0_0402_5% RE313@one control line if DVDD is 3.3V RING2 ESD@ LA10 1 2 BLM15PX330SN1D_2P RING2_R 4 GND
DE2@two control lines1 AUD_HP_OUT_L EMI@ RA55 1 2 0_0402_5% AUD_HP_OUT_L1 1 #4 G/M
#1 L Normal
Open
5
Only BR15U UMA use LA2,LA3,because 6L #5
AUD_HP_NB_SENSE 6
#6 AGND
AUD_HP_OUT_R EMI@ RA56 1 2 0_0402_5% AUD_HP_OUT_R1 2
SLEEVE ESD@ LA11 1 2 BLM15PX330SN1D_2P SLEEVE_R 3 #2 R
PJP17 #3 M/G
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN
330P_0402_50V8J
330P_0402_50V8J
680P_0402_50V7K
1 2 SINGA_2SJ3095-136111F
680P_0402_50V7K
+5V_RUN +5V_RUN_AUDIO
ESD@
EMI@
EMI@
ESD@
ESD@ ESD@ ESD@
3
+5V_RUN_AUDIO PAD-OPEN1x2m DA1 DA2 DA3
2.5A
AZ5123-02S.R7G_SOT23-3
AZ5123-02S.R7G_SOT23-3
680P_0402_50V7K
@ESD@ CA12
2 1 1 1 1
Reserve for support D3 cold
1
CA1
CA2
CA3
CA4
PJP18
@ PJP15 1 2
+3.3V_RUN +3.3V_RUN_AUDIO 1 2 2 2 2
PAD-OPEN1x1m
+5V_RUN PAD-OPEN1x1m
500mA
@ UZ5
2
1
1 14 +5V_RUN_AUDIO_UZ5 1 2
2 VIN1 VOUT1 13 @ CZ125 0.1U_0201_10V6K
A VIN1 VOUT1 A
3 12 1 2
<16> AUD_PWR_EN ON1 CT1 220P_0402_50V7K
@ CZ126
4 11
+5V_ALW VBIAS GND
5 10 1 2
ON2 CT2 @ CZ127 1000P_0402_50V7K
6 9 @ PJP16
+3.3V_RUN VIN2 VOUT2 +3.3V_RUN_AUDIO_UZ5
7 8 1 2
VIN2 VOUT2 +3.3V_RUN_AUDIO
15
GPAD PAD-OPEN1x1m DELL CONFIDENTIAL/PROPRIETARY
EM5209VF_SON14_2X3 1 2
@ CZ128 0.1U_0201_10V6K Security Classification Compal Secret Data
Codec ALC3246
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
For BR UMA
GPIO223 GPIO224 GPIO227 GPIO016 GPIO056 GPIO055
2 1 +RTC_CELL_VBAT eSPI NA NA *PRIM_PW RGD NA NA PCH_RSMRST#
+RTC_CELL
RE32 0_0402_5% LPC SHD_IO0 SHD_IO1 SHD_IO2 SHD_IO3 SHD_CLK SHD_CS#
0.1U_0201_10V6K
1 * For Version B IC
UPD1_SMBDAT
CE11
1 2
+3.3V_ALW_UE1 GPIO204 GPIO011 GPIO100 GPIO021 GPIO067 RE302 2.2K_0402_5%
eSPI NA NA NA SIO_RCIN# NA UPD1_SMBCLK 1 2
2
0.1U_0201_10V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
PJP22 LPC RSMRST# SIO_EXT_SMI# SIO_EXT_SCI# LPCPD# CLKRUN# RE303 2.2K_0402_5%
1 2 UPD1_ALERT# 1 2
+3.3V_ALW 1 1
1
CE13
CE14
CE23
RE91 100K_0402_5%
UPD2_ALERT#
10U_0603_6.3V6M
PAD-OPEN1x1m 1 2
1
RE92 100K_0402_5%
2
2 2
CE16
2
UE1 PBAT_CHARGER_SMBDAT 1 2
F2 TYPEC_ID RE37 2.2K_0402_5%
GPIO033/RC_ID0 PANEL_ID TYPEC_ID <38> PBAT_CHARGER_SMBCLK
A2 J10 PANEL_ID <38>
1 2
+3.3V_ALW_UE1 VBAT GPIO034/RC_ID1/SPI0_CLK J13 BOARD_ID RE43 2.2K_0402_5%
D GPIO036/RC_ID2/SPI0_MISO UPD2_SMBDAT BOARD_ID <38> D
B7 E7 RPE12
2 1 VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# D7 UPD2_SMBCLK EXPANDER_GPU_SMDAT 1 8
+3.3V_ALW_UE1 GPIO004/SMB00_CLK/SPI0_MOSI EXPANDER_GPU_SMCLK
0.1U_0201_10V6K
0.1U_0201_10V6K
100_0402_1% RE314 K2 2 7
VREF_ADC UPD2_SMBCLK
22U_0603_6.3V6M
0.1U_0201_10V6K
1 1 1 1 G3 RUNPW ROK 3 6
+3.3V_EC_PLL GPIO057/VCC_PWRGD HW _GPS_DISABLE# UPD2_SMBDAT
CE19
CE20
@ CE17
F1 H5 4 5
VTR_PLL GPIO060/KBRST/48MHZ_OUT HW_GPS_DISABLE# <35>
CE18
G11
GPIO104/UART0_TX HOST_DEBUG_TX <35,38>
H1 G12 2.2K_0804_8P4R_5%
2 2 2 2 VTR_REG GPIO105/UART0_RX ME_FW_EC <20>
B13
GPIO127/A20M/UART0_CTS# UPD1_ALERT# ME_SUS_PWR_ACK <20>
G8 F10 RPE9
M9 VTR1 GPIO225/UART0_RTS# UPD1_ALERT# <29> SLOT2_CONFIG_2 1 8
+VSS_PLL +3.3V_ALW_UE1 VTR2 PCIE_W AKE#_R SLOT2_CONFIG_1
close to pin G8/M9 +1.8V_3.3V_ALW_VTR3 N5 N13 2 7
VTR3 GPIO025/TIN0/nEM_INT/UART_CLK N12 PCIE_WAKE#_R <38> SLOT2_CONFIG_0 3 6
GPIO026/TIN1 SIO_SLP_S4# <11,20,21,50,53> SLOT2_CONFIG_3
F8 M11 4 5
+3.3V_ALW_UE1 <38> PCH_DPWROK_EC RUN_ON_EC GPIO020 GPIO027/TIN2 SIO_SLP_A# <20,21>
RF Request <38> RUN_ON_EC
E8
GPIO045 GPIO030/TIN3
H9
SIO_SLP_LAN# <20,46>
0.1U_0201_10V6K
1 M12 100K_0804_8P4R_5%
+3.3V_ALW <21> SIO_EXT_WAKE# BT_RADIO_DIS# GPIO120
C2 L9
<35> BT_RADIO_DIS# GPIO166 GPIO017/GPTP-IN5 BEEP <36>
CE15
F9 M10 RPE11
<48,57> PBAT_PRES# GPIO175 GPIO151/ICT4 SLOT2_CONFIG_1 <35> USB_PW R_SHR_VBUS_EN
1 2 N4 N9 1 8
2 <11,20,46,51,53> SIO_SLP_SUS# PCH_ALW _ON GPIO230 GPIO152/GPTP-OUT3 SLOT2_CONFIG_0 <35> USB_PW R_SHR_LFT_EN#
RE349 43K_0402_1% M8 2 7
<46> PCH_ALW_ON GPIO231 USB_PW R_EN1#
K8 C11 3 6
<20> AC_PRESENT GPIO233 GPIO156/LED0 BREATH_LED# <45> USB_PW R_EN2#
D10 4 5
GPIO157/LED1 BAT1_LED# <45>
E11 D11
<20> SML1_SMBDATA GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 BAT2_LED# <45>
Close to pin H1 D8 E1 100K_0804_8P4R_5%
<20> SML1_SMBCLK W W AN_W AKE# GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <32> AC_DIS
12P_0402_50V8J
RF@ CE59
68P_0402_50V8J
RF@ CE60
1 1 M13 1 2
<35> WWAN_WAKE# K12 GPIO110/PS2_CLK2 E5 @ RE83 100K_0402_5%
<20> SUSACK# W LAN_W IGIG60GHZ_DIS# L13 GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 USH_SMBDAT <39> HW _GPS_DISABLE#
B3 1 2
<35> WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 EXPANDER_GPU_SMDAT USH_SMBCLK <39>
K11 M7 RE12 100K_0402_5%
2 2 <7,20> SIO_PWRBTN# VCCST_PW RGD_EC K10 GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 EXPANDER_GPU_SMCLK EXPANDER_GPU_SMDAT <38> W LAN_W IGIG60GHZ_DIS#
1 2 M4 1 2
<7,38> VCCST_PWRGD RE308 @ 0_0402_5% N11 GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 M3 PBAT_CHARGER_SMBDAT EXPANDER_GPU_SMCLK <38> RE8 100K_0402_5%
<38> LID_CL#_NB GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK PBAT_CHARGER_SMBDAT <48,57> W W AN_W AKE#
E10 N2 1 2
<44> CLK_TP_SIO_I2C_DAT GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 PBAT_CHARGER_SMBCLK <48,57>
C12 N10 SLOT2_CONFIG_2 <35> RE38 10K_0402_5%
<44> DAT_TP_SIO_I2C_CLK GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA SYS_LED_MASK# SYS_LED_MASK#
A12 1 2
JTAG_TDI GPIO140/SMB06_CLK/ICT5 RTCRST_ON_GPIO141 SYS_LED_MASK# <33,45>
E9 B6 RE21 10K_0402_5%
<38> JTAG_TDI JTAG_TDO F6 GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# F7 THERMATRIP1# 1 2
<38> JTAG_TDO JTAG_CLK C8 GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# B4 UPD1_SMBDAT RE301 10K_0402_5%
<38> JTAG_CLK JTAG_TMS GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR# UPD1_SMBCLK UPD1_SMBDAT <29> PORT80_DET#
C5 C3 1 2
<38> JTAG_TMS JTAG_RST# GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# UPD1_SMBCLK <29>
G13 RE512 100K_0402_5%
JTAG_RST# J4 I_BATT_R RE64 1 2 300_0402_5% PCIE_W AKE#_R 1 2
GPIO200/ADC00 I_SYS_R I_BATT <57>
PJP20 E3 J5 RE312 1 2 300_0402_5% RE35 10K_0402_5%
<38> FAN1_TACH LCD_TST GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 I_SYS <54,57>
1 2 D1 J6 GPIO126 1 2
+1.8V_PRIM +1.8V_3.3V_ALW_VTR3 <32> LCD_TST W W AN_RADIO_DIS# M2 GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 G2 RE318 1 2 0_0402_5% RE5 10K_0402_5%
1 <35> WWAN_RADIO_DIS# GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 TOUCHPAD_INTR# <19,44>
PAD-OPEN1x1m L10 H2 PCH_RSMRST#_GPIO204
C <38> FAN1_PWM GPIO053/PWM0/GPWM0 GPIO204/ADC04 USB_PW R_SHR_VBUS_EN C
CE22 L11 J2
<48> PS_ID SHD_CS# GPIO054/PWM1/GPWM1 GPIO205/ADC05 USB_PW R_SHR_LFT_EN# USB_PWR_SHR_VBUS_EN <42> +RTC_CELL
0.1U_0201_10V6K M5 J3
2 SHD_CLK J8 GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 K3 USB_PW R_EN1# USB_PWR_SHR_LFT_EN# <42>
GPIO056/PWM3/SHD_CLK GPIO207/ADC07 USB_PWR_EN1# <43>
1 CE21 <32> BIA_PWM_EC N1 D3
TBT_RESET_N_EC_R L8 GPIO001/PWM4 GPIO210/ADC08 LOM_CABLE_DETECT# AUX_EN_WOWL <46> VCI_IN1#
@ PJP21 0.1U_0201_10V6K D2 1 2
GPIO002/PWM5 GPIO211/ADC09 LOM_CABLE_DETECT# <33>
+3.3V_ALW
1 2 N6 E2 RE507 100K_0402_5%
<48,57,59> ACAV_IN_NB GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 USB_PW R_EN2# BC_INT#_ECE1117 <44> VCI_IN2#
Close to pin N5 J9 G5 1 2
2 <32> PANEL_BKEN_EC VGA_ID GPIO015/PWM7 GPIO213/ADC11 UPD2_ALERT# USB_PWR_EN2# <43>
PAD-OPEN1x1m H11 F5 RE508 100K_0402_5%
+3.3V_ALW D9 GPIO035/PWM8/CTOUT1 GPIO214/ADC12 K4 PORT80_DET# SHD_CLK RE374 1 2 24.9_0402_1% SHD_CLK_R1
<20,46> SIO_SLP_WLAN# AC_DIS GPIO133/PWM9 GPIO215/ADC13 PORT80_DET# <35> +3.3V_ALW
<57> AC_DIS
H12 L1
WWAN_RADIO_DIS# GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 PCH_PCIE_WAKE# <20,38>
2 1 G10 L3
<39> BCM5882_ALERT# GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# <20,33> SHD_IO2_R1
RE10 100K_0402_5% MSCLK H10 1 2
BT_RADIO_DIS# <38> MSCLK GPIO170/TFDP_CLK/UART1_TX
2 1 MSDATA G9 H8 LPC@ RE376 1K_0402_5%
<38> MSDATA GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ SHD_IO0 CV2_ON <37,39> SHD_IO0_R1 LPC@ RE367 1 SHD_IO0_R2 SHD_IO3_R1
RE11 100K_0402_5% J7 LPC@ RE366 1 2 24.9_0402_1% 2 45.3_0402_1% 1 2
2 1 BC_DAT_ECE1117 A4 GPIO223/SHD_IO0 L6 SHD_IO1 LPC@ RE368 1 2 24.9_0402_1% SHD_IO1_R1 LPC@ RE369 1 2 45.3_0402_1% SHD_IO1_R2 LPC@ RE377 1K_0402_5%
RE365 100K_0402_5% <36> AUD_NB_MUTE# EN_INVPW R B2 GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 L7 SHD_IO2 LPC@ RE370 1 2 24.9_0402_1% SHD_IO2_R1 LPC@ RE371 1 2 45.3_0402_1% SHD_IO2_R2 SHD_CS# 1 2
<32> EN_INVPWR PRIM_PW RGD_GPIO024 GPIO023/GPTP-IN1 GPIO227/SHD_IO2 SHD_IO3 SHD_IO3_R1 LPC@ RE373 1 SHD_IO3_R2
C1 M6 LPC@ RE372 1 2 24.9_0402_1% 2 45.3_0402_1% LPC@ RE98 4.7K_0402_5%
RPE10 IMVP_VR_ON_EC N7 GPIO024/nRESETI GPIO016/GPTP-IN7/SHD_IO3/ICT3 Place near UE1 Place near UE9
8 1 CV2_ON <38> IMVP_VR_ON_EC K9 GPIO031/GPTP-OUT1 D6
IMVP_VR_ON_EC CV2_ON <37,39> <20,21,38> SIO_SLP_S3# GPIO032/GPTP-OUT0 BGPO0 EC_FPM_EN <39>
7 2 N8 C7 RE59 close to UE2 at least 250mils
PCH_ALW _ON <20,21> SIO_SLP_S5# GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN ACAV_IN <57>
6 3 A5
RUN_ON_EC VCI_OUT ALWON <49> +PECI_VREF +3.3V_ALW
5 4 F13 D5 2 1
AC_DISC# GPIO121/PVT_IO0 GPIO163/VCI_IN0# VCI_IN1# POWER_SW_IN# <38> +1.0V_VCCST
E13 B5 RE59 0_0402_5% LPC@ UE9
<48,59> AC_DISC# GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# VCI_IN2# SHD_CS#
0.1U_0201_10V6K
100K_0804_8P4R_5% C13 D4 8 1
<39> USH_DET# GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# POA_W AKE# SHD_IO3_R2 VCC CS# SHD_IO1_R2
GPIO126 E12 E4 7 2
GPIO126/PVT_IO3 GPIO000/VCI_IN3# POA_WAKE# <39> HOLD#(IO3) DO(IO1)
1
TBT_RESET_N_EC_R SHD_CLK_R1 SHD_IO2_R2
CE25
1 2 6 3
@ RE95 100K_0402_5% RTCRST_ON_GPIO122 F11 SHD_IO0_R2 5 CLK WP#(IO2) 4
F12 GPIO122/BCM0_DAT/PVT_IO1 C6 DI(IO0) GND
2
BC_DAT_ECE1117 D12 GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 3.3V_WWAN_EN <46> W 25Q80DVSSIG_SO8
<44> BC_DAT_ECE1117 GPIO046/BCM1_DAT 32KHZ_OUT
D13 F3 @ CE54 1 2 10P_0402_50V8J
<44> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT
F4
<35> SLOT2_CONFIG_3 GPIO041/SYS_SHDN# +PECI_VREF
RE57 2 1 1K_0402_5% B1 J11
+3.3V_ALW2 SIO_EXT_SMI#_EC SYSPWR_PRES GPIO044/VREF_VTT PECI_EC_R
K7 K13 RE60 1 2 43_0402_5%
H_PECI <7,16>
1
SIO_RCIN#_EC N3 GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT J12 m3042_PCIE#_SATA I_BATT_R CE3 1 2 2200P_0402_50V7K

GPIO021/LPCPD# GPIO043/SB-TSI_CLK REM_DIODE1_N m3042_PCIE#_SATA <16>
100K_0402_5%
K6 A8 CE24 1 2 2200P_0402_50V7K
<20> ESPI_RESET# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A REM_DIODE1_P REM_DIODE1_N I_SYS_R
RE58
H7 A7 CE4 1 2 2200P_0402_50V7K
<20> ESPI_ALERT# GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A REM_DIODE2_N REM_DIODE1_P REM_DIODE1_N <38>
K1 A10 CE26 1 2 2200P_0402_50V7K
<38> PCH_PLTRST#_5105 GPIO064/LRESET# DN2_DP2A REM_DIODE2_P REM_DIODE2_N REM_DIODE1_P <38>
G7 A9
REM_DIODE2_N <38>
2
<20,38> ESPI_CLK_5105 H6 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A B9 REM_DIODE2_P

<20,38> ESPI_CS# GPIO066/LFRAME#/ESPI_CS# DN3_DP3A REM_DIODE2_P <38>
K5 B8
<20,38> ESPI_IO0 GPIO070/LAD0/ESPI_IO0 DP3_DN3A REM_DIODE4_N
B L4 A11 CE27 1 2 2200P_0402_50V7K B
<20,38> ESPI_IO1 GPIO071/LAD1/ESPI_IO1 DN4_DP4A REM_DIODE4_P REM_DIODE4_N
+3.3V_ALW G6 B10
<20,38> ESPI_IO2 GPIO072/LAD2/ESPI_IO2 DP4_DN4A +VR_CAP REM_DIODE4_P REM_DIODE4_N <38>
L5 C10
100K_0402_5%
<20,38> ESPI_IO3 CLKRUN#_EC GPIO073/LAD3/ESPI_IO3 VIN VSET_5105 REM_DIODE4_P <38>

L2 C9 VSET_5105 <38>
GPIO067/CLKRUN# VSET
2
SIO_EXT_SCI#_EC M1 B11 PCH_RSMRST# 1 2

I_ADP <57>
RE63
SYS_PW ROK G4 GPIO100/nEC_SCI VCP H3 THERMATRIP2# RE342 10K_0402_5%
VSS_ANALOG
<7,20> SYS_PWROK GPIO106/PWROK GPIO103/THERMTRIP2# THERMATRIP2# <38> SYS_PW ROK
L12 B12 THERMATRIP1# 1 2
<16,32> ENVDD_PCH GPIO107/nSMI THERMTRIP1# H_PROCHOT#_R1
H13 1 2 100_0402_5%
VSS_ADC
RE288 RE56 10K_0402_5%
VSS_PLL
VR_CAP
MEC_XTAL1 A1 GPIO160/PWM11/PROCHOT# H_PROCHOT# <7,54,57> I_SYS_R 1 2
1
MEC_XTAL2_R A3 XTAL1
VSS1
VSS2
VSS3
@ RE313 10K_0402_5%
XTAL2 LCD_TST 1 2
JTAG_RST# RE20 100K_0402_5%
MEC5105_W FBGA169_11X11 EN_INVPWR 1 2
A6
A13
E6
H4
1+VR_CAP J1
C4
G1
RE94 RE55 100K_0402_5%
1U_0402_6.3V6K
1
1 2 PORT80_DET# 1 2
PCH_RTCRST# <20,21>
1U_0402_6.3V6K
75_0402_5% @ RE513 100K_0402_5%

1
1
D
@SHORT PADS~D
100_0402_1%
+VSS_PLL
1
RTCRST_ON_GPIO141 RTCRST_ON
@ JTAG1
@ RE65
1 2 2 QE12
CE30
@ RE514 0_0402_5% G L2N7002W T1G_SC-70-3
1
RTCRST_ON_GPIO122 1 2 S +RTC_CELL
2
3
RE515 0_0402_5% RE93
2
CE31
2
2
100K_0201_5%
POA_W AKE# 1 2
2
2
For MEC5105 Rev.A:Pop RE361,Depop RE360,RE362 RE324 100K_0402_5%
For MEC5105 Rev.B:Depop RE361,Pop RE360,RE362
+3.3V_RUN
SHD_IO2 RE360 1 2 0_0402_5% 1.8V_PRIM_PWRGD <53>
2
+3.3V_ALW +3.3V_ALW
10K_0402_5% DMN65D8LDW-7_SOT363-6
PRIM_PW RGD_GPIO024 @ RE361 1 2 49.9K_0402_1%

For EMI request
RE67
RE362 1 2 100K_0402_5% ESPI_CLK_5105 VGA_ID 1 2

+3.3V_ALW
RE84 100K_0402_5%
100K_0402_5%
1
2
GPIO055 use for SHD_CS# (LPC) or PCH_RSMRST#(eSPI) RUNPWROK VGA_ID 1 2
33_0402_5%
1
GPIO227 use for SHD_IO2 (LPC) or PRIM_PWRGD(eSPI) @ RE85 100K_0402_5%
@EMI@
RE68
MEC_XTAL2_R
RE350
PCH_RSMRST#_GPIO204 LPC@ RE363 1 2 0_0402_5%
PCH_RSMRST# <44>
3
1
QE2B
2
1
SHD_CS# ESPI@ RE364 1 2 0_0402_5%
33P_0402_50V8J
RE290 RUN_ON# 5
32 KHz Clock
@EMI@
A 0_0402_5% A
1
VGA_ID0
4
CE57
2
YE1 Discrete 0
2
QE2A
MEC_XTAL1 1 2 MEC_XTAL2 8/28 schematic review

2
UMA 1
<11,38,46,52> RUN_ON
10P_0402_50V8J
10P_0402_50V8J
32.768KHZ_9PF_X1A000141000200
1
1
1
CE28
CE29
2
<20> CLKRUN#
LPC@ RE337 1 2 0_0402_5% CLKRUN#_EC Security Classification Compal Secret Data
Title
<19> SIO_EXT_SMI#
LPC@ RE338 1
LPC@ RE339 1
2 0_0402_5%
2 0_0402_5%
SIO_EXT_SMI#_EC
SIO_RCIN#_EC EC MEC5105
<20> SIO_RCIN# SIO_EXT_SCI#_EC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LPC@ RE341 1 2 0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
<21> SIO_EXT_SCI#
Custom
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+1.8V_3.3V_ALW_VTR3
+3.3V_ALW For BR UMA
2
UE6
RE340
1 5 10K_0402_5%
NC VCC
2
<19> PCH_PLTRST#_EC
1
A 4
3 Y PCH_PLTRST#_5105 <37>
GND
74AUP1G07GW_TSSOP5
+RTC_CELL
PCIE_WAKE# <35,40>
1
100K_0402_5%
RE31
@ CE10
1 2 2 1 1 2
<37> PCIE_WAKE#_R PCH_PCIE_WAKE# <20,37>
RE275 0_0402_5% 0_0402_5% @ RE274
1U_0402_6.3V6K
2
1 2 Stuff RE275 and no stuff RE274 keep E5 design
<37> POWER_SW_IN# POWER_SW#_MB <21,45>
PAGE ESPI LPC RE33 10K_0402_5% Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
1U_0402_6.3V6K
D D
CE12
2 1
2
0_0402_5% @ RE304
CONN@
JESPI
+3.3V_RUN
8 RC25_10K RC8_15ohm +3.3V_ALW
@ CE53
RC13/RC27_8.2K
1 +3.3V_ALW 1 2
1 +3.3V_ALW
100K_0402_5%
2 UE4
2
1
RE25
3 ESPI_IO0 <20,37> 0.1U_0402_25V6K
3
5
4 ESPI_IO1 <20,37> 1 5
4 5 IMVP_VR_ON_EC 1 NC VCC
ESPI_IO2 <20,37> <37> IMVP_VR_ON_EC
P
5 6 B 4 IMVP_VR_ON 2
6 7 ESPI_IO3 <20,37> SIO_SLP_S3# 2 O A 4
RE26 <20,21,37,38> SIO_SLP_S3#
ESPI_CS# <20,37>
2
7 A Y VCCST_PWRGD <7,37>
G
8 LPC@ RE375 1 20_0402_5% PCH_PLTRST#_EC LID_CL#_NB 2 1 UE3 3
8 <37> LID_CL#_NB LID_CL# <45> GND
18 RC212_0ohm RC211_0ohm
.047U_0402_16V7K
11 9 TC7SH08FU_SSOP5~D
3
12 GND 9 10 10_0402_5% 74AUP1G07GW_TSSOP5
GND 10 ESPI_CLK_5105 <20,37>
CE8
JXT_FP241AH-010GAAM
0603 0603 RF Request
2
IMVP_VR_ON <54>
+3.3V_ALW 1 2
0_0402_5% @ RE280
68P_0402_50V8J
1
RUN_ON_EC 2 1
RF@ CE61
<37> RUN_ON_EC RUN_ON <11,37,46,52>
RE337,RE338 0_0402_5% @ RE292

2
+3.3V_ALW
RE339,RE340, @ CE52
1 2
31 RE341
0.1U_0402_25V6K
5
1
P
B 4
O
LPC 80Port Debug LPC ESPI 2
A
0_ohm
G
UE5
TC7SH08FU_SSOP5~D
3
1 +3.3V_RUN +3.3V_RUN
2 +3.3V_RUN +3.3V_RUN
+3.3V_ALW +3.3V_ALW
RE2 / RE3
+3.3V_ALW
3 LPC_LAD0 ESPI_IO0
32
1
4 LPC_LAD1 ESPI_IO1
0_ohm
C RE343 RE79 RE300 C
240K_0402_5% 240K_0402_5% 130K_0402_5%
5 LPC_LAD2 ESPI_IO2
2
<37> TYPEC_ID <37> BOARD_ID <37> PANEL_ID
1
6 LPC_LAD3 ESPI_IO3 CE62 CE40 CE47
4700P_0402_25V7K 4700P_0402_25V7K 4700P_0402_25V7K
2
7 LPC_FRAME# ESPI_CS#
8 PCH_PLTRST# NA RE343 CE62 REV RE79 CE40 REV

Single Port ACE w/o AR
9 GND GND * 240K 4700p * 240K 4700p X00 RE300 CE47 PANEL SIZE
130K 4700p Single Port ACE w/AR 130K 4700p
10 LPC_CLOCK ESPI_CLK Dual Port ACE w/o AR 240K 4700p 12"
62K 4700p 62K 4700p
Dual Port ACE w/AR * 130K 4700p 14"
33K 4700p 33K 4700p
Dual Port ACE (w/AR +w/o AR) 33K 4700p BR15 H
8.2K 4700p 8.2K 4700p
4.3K 4700p BR15 P
4.3K 4700p 4.3K 4700p
2K 4700p 2K 4700p
1K 4700p 1K 4700p
PD_ACE_DET# rise time is measured from 5%~68%. BOARD_ID rise time is measured from 5%~68%. PANEL_ID rise time is measured from 5%~68%.
VSET_5105
VSET_5105 <37>
0.1U_0402_25V6
1
1.58K_0402_1%
1
CE38
RE77
2
+3.3V_ALW
2
1
8
7
6
5
10K_8P4R_5%
49.9_0402_1%
RE71
RPE7
Rest=1.58K , Tp=96 degree???
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
@ RE75
CONN@
1
2
3
4
+3.3V_ALW
RE72
RE73
RE74
B JDEG1 B
1 +EC_DEBUG_VCC
UE7 1 2 JTAG_TDI Link 50271-0040N-001 DONE
JTAG_TDI <37>
2
5 1 2 3 JTAG_TMS JFAN1
VDD RESET PCH_DPWROK <20> 3 JTAG_CLK JTAG_TMS <37>
1 4 1
3 4 4 5 JTAG_TDO JTAG_CLK <37> 1 2 FAN1_PWM
CE6 RE86
MR CT 5 6 JTAG_TDO <37> 2 3 FAN1_TACH FAN1_PWM <37>
MSCLK 10K_0402_5%
6 3 FAN1_TACH <37>
2
0.1U_0402_25V6K 2 7 MSDATA 1 2 +3.3V_RUN 4

2 GND 7 4 +5V_RUN
1
RE348 8 HOST_DEBUG_TX
8 DEBUG_TX
10U_0603_6.3V6M
10K_0402_5% CE5 11 9 5
RT9826-30GB GND 9 GND1
1
3300P_0402_50V7-K 12 10 6
2
GND 10 GND2
1
FAN1_PWM
@ DE1
1 2 1 2
<21> SBIOS_TX
1
CE32
JXT_FP241AH-010GAAM @ RE306 RE48 10K_0402_5% ACES_50271-0040N-001
RE34 1 20_0402_5% 0_0402_5% 1 2 FAN1_TACH CONN@
<37> PCH_DPWROK_EC CT: 3300 pF ~ 10ms delay
2
RE51 10K_0402_5%
HOST_DEBUG_TX <35,37>
2
MSDATA <37>
Reset Threshold Level 3.0V 1

RE30
0_0402_5%
2 MSCLK <37>
Thermal diode mapping

5105 Channel Location
Control Byte Place under CPU
Place CE35 close to the QE3 as possible
DP1/DN1 CPU (QE3)
0 1 0 0 A2 A1 A0 R/W REM_DIODE1_P <37>
100P_0402_50V8J
R/W = 0 = Wire DP2/DN2 WiGig (QE5)
1
C
R/W = 1 = Read +3.3V_ALW
@ CE35
2
DN2a/DP2a DDR (QE7) B
1
E QE3
3
SMBus address 0x40 1 LMBT3904WT1G SC70-3
1
NA
0.1U_0402_25V6K
1U_0402_6.3V6K
DP3/DN3 REM_DIODE1_N <37>

CE1
CE2
DP2/DN2 for WiGig on QE5, place QE5 close

2
2
DP4/DN4 CPU VR (QE6) to WiGig and CE37 close to QE5
+3.3V_ALW
DP4/DN4 for Skin on

UE2
CHECK QE6, place QE6 close to DN2a/DP2a for DDR on QE7, place QE7 close
1
1
10K_0402_5%
100K_0402_5%
10K_0402_5%
18 RE69
VSTBY33 Vcore VR choke. to DDR and CE46 close to QE7
@ RE15
@ RE17
0.1U_0402_25V6
@ 1 2
+1.0VS_VCCIO +3.3V_ALW THERMATRIP2# <37>
RE13
19
<37> EXPANDER_GPU_SMCLK 20 SCL REM_DIODE4_P <37> REM_DIODE2_P <37>
<20,21,37,38> 8.2K_0402_5%
LMBT3904WT1G SC70-3
<37> EXPANDER_GPU_SMDAT SDL SIO_SLP_S3#
1
LMBT3904WT1G SC70-3
CE36
100P_0402_50V8J
16 @ QE11
VBUS2_ECOK <48,59>
2
GP7
2
1
100P_0402_50V8J
100P_0402_50V8J
@ CE37
QE7
1 15
E
C
G
A2 GP6 DCIN2_EN <48>
1
@ CE46
2 14 C C B
2 2
SATA_LED_EN <45>
2
A1 GP5
2
QE4
@CE39
A 3 13 1 3 1 2 2 2 B A
VBUS1_ECOK <59>
2
A0 GP4 12 RE70 2.2K_0402_5% B B C E QE5
D
DCIN1_EN <59>
3
1 2 4 GP3 11 +1.0V_VCCST E E QE6 LMBT3904WT1G SC70-3
+3.3V_ALW
3
WRST# GP2
1
1
100K_0402_5%
10K_0402_5%
100K_0402_5%
RE6 10K_0402_5% 10 L2N7002WT1G_SC-70-3 LMBT3904WT1G SC70-3

EXPANDER_ALERT# 7 GP1 9
T267 @ PAD~D INT GP0 USH_PWR_STATE# <39> REM_DIODE2_N <37>
RE14
RE16
RE18
RE90 1 2 0_0402_5%
<7,14,15,16> H_THERMTRIP#
5 REM_DIODE4_N <37>
6 NC
2
8 NC 17
NC VSS 21
EPAD
IT8010FN-AX_QFN20_4X4
Title
Issued Date 2017/01/01
MEC5105 SUPPORT
Custom
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
For NUVOTON TPM RF Request RF Request

+3.3V_ALW +3.3V_M_TPM
place CZ50, CZ75 as close as UZ12.8

+UZ12_TPM
12P_0402_50V8J
RF@ CZ57
68P_0402_50V8J
RF@ CZ58
12P_0402_50V8J
RF@ CZ59
68P_0402_50V8J
RF@ CZ60
1 2 1 1 1 1
D +3.3V_RUN D
RZ89 0_0402_5%
4.7U_0402_6.3V6M
0.1U_0201_10V6K
1 1 2 2 2 2
CZ75
CZ50
2 2
+3.3V_ALW_PCH +3.3V_M_TPM
PJP391
1 2
PAD-OPEN1x1m
+3.3V_ALW
+3.3V_M_TPM
+3.3V_ALW
1 2 USH_SMBCLK
1 2 TPM_PIRQ# @ RZ8 2.2K_0402_5%
USH_SMBDAT
0.1U_0201_10V6K
10U_0603_10V6M
RZ69 10K_0402_5% 1 2
1 1 place CZ51,CZ52 as close as UZ12.1 @ RZ9 2.2K_0402_5%
+3.3V_RUN
USH_PWR_STATE#
CZ51
CZ52
1 2
RZ10 100K_0402_5%
1
2 2
@ RZ362
10K_0402_5%
UZ12
1 +3.3V_M_TPM USH CONN
2
1 2 29 VSB
C <11,20,21,52> SIO_SLP_S0# 30 GPIO0/SDA/XOR_OUT 8 +UZ12_TPM C
@ RZ112 0_0402_5% CONN@
1 2 TPM_LPM# 3 GPIO1/SCL VDD 14 JUSH1
RZ363 0_0402_5% 6 GPIO2/GPX VHIO 22 RZ85 1 2 0_0402_5% +PWR_SRC_R 1
GPIO3/BADD VHIO +PWR_SRC 1
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_10V6M
2
RZ58 1 2 33_0402_5% PCH_SPI_D1_2_R 24 2 3 2
<19> PCH_SPI_D1_R1 LAD0/MISO NC 1 1 1 <37> CV2_ON 3
RZ59 1 2 33_0402_5% PCH_SPI_D0_2_R 21 7 4
<19> PCH_SPI_D0_R1 LAD1/MOSI NC <37> POA_WAKE# 4
CZ53
CZ54
CZ55
18 10 5
<21> TPM_PIRQ# 15 LAD2/SPI_IRQ# NC 11 <37> EC_FPM_EN 6 5
LAD3 NC 25 2 2 2 7 6
EMI@ RZ60 1 2 33_0402_5% PCH_SPI_CLK_2_R 19 NC 26 8 7
<19> PCH_SPI_CLK_R1 PCH_SPI_CS#2_R 20 LCKL/SCLK NC <17> USB20_N10 8
RZ61 1 2 0_0402_5% 31 9
<19> PCH_SPI_CS#2 17 LFRAME#/SCS# NC <17> USB20_P10 10 9
<19> PLTRST_TPM# 27 LRESET#/SPI_RST#/SRESET# 9 11 10
TPM_GPIO4 13 SERIRQ GND 16 <37> USH_SMBCLK 12 11
T283@ PAD~D CLKRUN#/GPIO4/SINT# GND <37> USH_SMBDAT 12
28 23 CZ53,CZ55 as close as UZ12.14 13
LPCPD# GND <37> BCM5882_ALERT# 13
1
10K_0402_5%
32 CZ54 as close as UZ12.22 14

GND 14
RZ62
4 33 15
5 PP PGND 12 16 15
TEST Reserved +3.3V_ALW 16
17
NPCT650JB2YX_QFN32_5X5 18 17
+5V_ALW
2
19 18
+3.3V_RUN 19
20
+5V_RUN USH_RST#_R 20
@ RZ114 1 2 0_0402_5% 21
<19,34,35,40> PCH_PLTRST#_AND 22 21
<38> USH_PWR_STATE# 23 22
<16> CONTACTLESS_DET# 24 23
25 24
RZ87 1 2 0_0402_5% USH_DET#_R 26 25
<37> USH_DET# 26
@ DZ7 27
2 1 28 GND1
PCH_SPI_CLK_2_R GND2
B RB751S40T1G_SOD523-2 CVILU_CF5026FD0RK-05-NH B
33_0402_5%
2
@EMI@
RZ63
1
0.1U_0402_25V6
PCH_PLTRST#_AND Close to JUSH1

1
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW

@EMI@
+3.3V_M_TPM
CZ56
.047U_0402_16V7K
ESD@ CZ61
2
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1
@
2
3
CZ64
CZ66
CZ67
CZ68
PCH_SPI_CS#2_R 1 2 2
G LP2301ALT1G_SOT23-3
@ RZ113 100_0402_5% @ QZ9 For ESD solution 2 2 2 2
D
1
TPM_LPM#
1
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW

@ RZ111 RF Request
RZ113 RZ111 POP 10K_0402_5% RF Request
1K MMBT3906
68P_0402_50V8J
RF@ CZ69
68P_0402_50V8J
RF@ CZ71
68P_0402_50V8J
RF@ CZ72
68P_0402_50V8J
RF@ CZ73
1K
2
USH_SMBCLK 1 2 1 1 1 1
100 10K LP2301A @RF@CZ62 68P_0402_50V8J
USH_SMBDAT 1 2
A @RF@CZ63 68P_0402_50V8J 2 2 2 2 A
Title
USH & TPM

5 4 3 2 1
5 4 3 2 1
For Breckenridge 15
RF Request
+3.3V_HDD_M2
+3.3V_HDD_M2
D D
68P_0402_50V8J
@RF@ CN60
0.1U_0201_10V6K
0.1U_0201_10V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1 @ 1
1
CN61
CN62
CN63
CN64
2
2
2 2
Place near HDD CONN

2280 SSD
+3.3V_HDD_M2 NGFF slot C Key M

1 2 M2280_DEVSLP
@ RN37 10K_0402_5% if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD +3.3V_HDD_M2 2.8A
JNGFF3 CONN@ PJP31
1 2 1 2 +3.3V_RUN
3 GND 3.3VAUX 4
5 GND 3.3VAUX 6 PAD-OPEN1x3m
<16> PCIE_PRX_DTX_N12 PERn3 N/C
7 8
<16> PCIE_PRX_DTX_P12 PERp3 N/C NVME_LED#
9 10 1 2
PCIE_PTX_C_DRX_N12 GND DAS/DSS# SATALED# <16,35,45>
CN65 2 1 0.22U_0402_10V6K 11 12 @ RN100 0_0402_5%
C <16> PCIE_PTX_DRX_N12 CN66 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_P12 13 PETn3 3.3VAUX 14 C
<16> PCIE_PTX_DRX_P12 15 PETp3 3.3VAUX 16
17 GND 3.3VAUX 18
<16> PCIE_PRX_DTX_N11 PERn2 3.3VAUX
19 20
<16> PCIE_PRX_DTX_P11 PERp2 N/C
21 22
CN67 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N11 23 GND N/C 24
<16> PCIE_PTX_DRX_N11 PETn2 N/C
CN68 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_P11 25 26
<16> PCIE_PTX_DRX_P11 PETp2 N/C
27 28
29 GND N/C 30
<16> PCIE_PRX_DTX_N10 PERn1 N/C
31 32
<16> PCIE_PRX_DTX_P10 PERp1 N/C
33 34
<16> PCIE_PTX_DRX_N10 PETn1 N/C
CN70 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_P10 37 38
<16> PCIE_PTX_DRX_P10 PETp1 DEVSLP M2280_DEVSLP <20>
39 40
41 GND N/C 42
<16> PCIE_PRX_DTX_P9 43 PERn0/SATA B+ N/C 44
<16> PCIE_PRX_DTX_N9 45 PERp0/SATA B- N/C 46
<16> PCIE_PTX_DRX_N9 PCIE_PTX_C_DRX_P9 PETn0/SATA A- N/C
CN72 2 1 0.22U_0402_10V6K 49 50
<16> PCIE_PTX_DRX_P9 PETp0/SATA A+ PERST# PCH_PLTRST#_AND <19,34,35,39>
51 52
GND CLKREQ# PCIE_WAKE# CLKREQ_PCIE#3 <18>
53 54
<18> CLK_PCIE_N3
55 REFCLKn PEWake# 56 PCIE_WAKE# <35,38>
<18> CLK_PCIE_P3 REFCLKp N/C
57 58
GND N/C
67 68 SUSCLK_R 1 2
N/C SUSCLK SUSCLK <20,35>
69 70 RN99 0_0402_5%
<16> M2280_PCIE_SATA# 71 PEDET 3.3VAUX 72
73 GND 3.3VAUX 74
75 GND 3.3VAUX
GND
77 76
B MTG77 MTG76 B
LCN_DAN05-67356-0103
A A
Title
M2 2280 Socket
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_HDD
pin 3 pin 6 pin pin pin +3.3V_HDD

13 16 18
@
1
1
NC
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
Pericom TDet_B# NC TDet_A# TDeT_EN
@ RN10
@ RN12
@ RN14
@ RN16
@ RN18
@ RN20
RN6
RN8
TI GND DEW2 GND DEW1 GND
0.01UF_0402_25V7K
0.1U_0201_10V6K
2
1 1
Parade GND REXT B_EQ2 DEW A_EQ2 +5V_HDD
D SATA Repeater HDD_A_PRE
D
CN16
CN17
1
2 2 HDD_B_PRE
100K_0402_5%
@ RN1
UN7
DEW2 6 10 HDD_A_EQ +3.3V_RUN
DEW1 16 NC VDD 20
NC VDD HDD_B_EQ
2
1
HDD_B_EQ2
100K_0402_5%
3 13
HDD_A_EQ 17 TDet_B# TDet_A# 19 HDD_B_EQ DEW2 FFS_INT2_Q
HDD_A_PRE A_EQ B_EQ HDD_B_PRE
RN2
9 8
A_EM B_EM
3
7 18 HDD_A_EQ2 DEW1
EN TDeT_EN
2
2 0.01UF_0402_25V7K SATA_PTX_C_RD_DRX_P2 1 15 SATA_PTX_RD_DRX_P2 HDD_B_EQ2
QN1B
CN12 1
<16> SATA_PTX_DRX_P2 AI+ AO+
CN13 1 2 0.01UF_0402_25V7K SATA_PTX_C_RD_DRX_N2 2 14 SATA_PTX_RD_DRX_N2 5
<16> SATA_PTX_DRX_N2 AI- AO- HDD_A_EQ2
2 0.01UF_0402_25V7K SATA_PRX_C_RD_DTX_N2 4
<16> SATA_PRX_DTX_N2 CN14 1 12 SATA_PRX_RD_DTX_N2
4
BO- BI-
6
<16> SATA_PRX_DTX_P2 CN15 1 2 0.01UF_0402_25V7K SATA_PRX_C_RD_DTX_P2 5 11 SATA_PRX_RD_DTX_P2
BO+ BI+
1
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
7.87K_0402_1%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
@ RN17
QN1A
@
21
GND FFS_INT2
RN7
RN9
RN11
RN13
RN15
RN19
RN21
2
PI3EQX6741STZDEX_TQFN20_4X4
1
HDD_A_EQ HDD_B_EQ HDD_A_EQ2 HDD_B_EQ2 DEW1 DEW2 HDD_A_PRE HDD_B_PRE
PIN17 PIN19 PIN18 PIN13 PIN16 PIN6 PIN9 PIN8
Pericom PI3EQX6741ST PD PD PD PD NC NC PD PD
(RN13) (RN16) (RN83) (RN23) (RN9) (RN11)
+3.3V_RUN
TI SN75LVCP601 PD NC PD PD NC NC PH PH
(RN13) (RN83) (RN23) (IPU) (IPU) (RN8) (RN10)
10U_0603_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
C
Parade PS8527C PD PD PD PD NC PD NC NC C
1
(RN16) (RN83) (RN23) (RN19) (1/2 VDD) (1/2 VDD)
(RN13) (1/2 VDD) Free Fall Sensor
CN1
CN2
CN3
2
2
LGA1
A_EQ B_EQ A_EM B_EM LNG2DM
10 5 INT1/IN2:Push-Pull,active high
9 VDD_IO RES
VDD
0 3dB 3dB 0 0dB 0dB 3 INT 1
12
11 FFS_INT2 HDD_FALL_INT <21>
SDO/SA0 INT 2 FFS_INT2 <21>
Main Pericom NC 6dB 6dB NC <7,14,15,20> DDR_XDP_WAN_SMBDAT
4
1 SDA/SDI/SDO 6
<7,14,15,20> DDR_XDP_WAN_SMBCLK SCL/SPC GND
1 9dB 9dB 1 1.5dB 1.5dB 2 GND
7
8
CS GND
0 7dB 7dB 0 0dB 0dB LNG2DMTR_LGA12_2X2
2nd TI NC 0dB 0dB NC -4dB -4dB

1 14dB 14dB 1 -2dB -2dB
+3.3V_HDD
EQ2 EQ1 A_EQ B_EQ A_EM B_EM
1 2 HDD_DEVSLP
@ RN3 10K_0402_5%
(M = VDD/2)
0 M 2.4dB 2.4dB CONN@

JSATA1
0 0 7.4dB 7.4dB 1 0.01UF_0402_25V7K SATA_PTX_C_DRX_P2
1
1
3rd Parade
SATA_PTX_RD_DRX_P2 CN4 2 2
B
0 1 14.4dB 14.4dB 0 0dB 0dB
SATA_PTX_RD_DRX_N2 CN5 2 1 0.01UF_0402_25V7K SATA_PTX_C_DRX_N2 3
4
2
3
B
4
M M 12.2dB 12.2dB M -3.5dB -3.5dB
SATA_PRX_RD_DTX_N2 CN6
SATA_PRX_RD_DTX_P2 CN7
2
2
1 0.01UF_0402_25V7K SATA_PRX_C_DTX_N2
1 0.01UF_0402_25V7K SATA_PRX_C_DTX_P2
5
6 5
6
M 0 9.4dB 9.4dB 1 -1.5dB -1.5dB PJP34
7
8 7
8
M 1 13.3dB 13.3dB +3.3V_RUN
1 2 +3.3V_HDD 9
10 9
10
1 M 6.2dB 6.2dB * red color is PAD-OPEN1x2m
<20> HDD_DEVSLP
11
12 11
11.2dB 11.2dB current setting 12
1 0 <16> HDD_DET#
13
14 13
14
1 1 5dB 5dB +5V_HDD +3.3V_HDD
+5V_HDD
15
16 15
17 16
18 17
FFS_INT2_Q 18
1000P_0402_50V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
19
+5V_RUN +5V_HDD 20 19
20
1
+3.3V_RUN
CN8
CN9
@ CN10
CN11
@ PJP33 21
2 1 22 G1
23 G2
+5V_HDD source G3
2
24
PAD-OPEN1x1m G4
1
@ RN4 PJP32
10K_0402_5% 1 2 1.5A+5V_HDD ACES_59003-02006-002
+5V_ALW UZ23
PAD-OPEN1x1m
2
1 7
HDD_EN 2 VIN VOUT 8 +5V_HDD_UZ23 1 2
VIN VOUT CZ129 0.1U_0201_10V6K
3 6 1 2
Place near HDD CONN
<21> HDD_EN ON CT CZ130 470P_0402_50V7K
1
RN5 4
VBIAS 5
10K_0402_5% GND
A 9 A
GND
2
AOZ1336_DFN8_2X2
Title
HDD CONN
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
For PWR SW + Charger combine IC
+5V_USB_CHG_PWR
DI4 ESD@
USB3_PRX_DTX_N1 1 1 10 9 USB3_PRX_DTX_N1 JUSB1
<20> USB3_PRX_DTX_N1 1
D VBUS D
USB3_PRX_DTX_P1 USB3_PRX_DTX_P1 USB20_N1_R
150U_B2_6.3VM_R35M
2 2 9 8 2
<20> USB3_PRX_DTX_P1 USB20_P1_R D-
100U_1206_6.3V6M
0.1U_0201_10V6K
3
USB3_PTX_C_DRX_N1 4 4 USB3_PTX_C_DRX_N1 D+
<20> USB3_PTX_DRX_N1
2 1 7 7 1 @ 1 1 4
USB3_PRX_DTX_N1 GND
CI17
CI13 0.1U_0402_25V6 5
USB3_PTX_C_DRX_P1 + USB3_PRX_DTX_P1 SSRX-
CI32
CI14
2 1 USB3_PTX_C_DRX_P1 5 5 6 6 6 10
<20> USB3_PTX_DRX_P1 SSRX+ GND
2
CI16 0.1U_0402_25V6 7 11
2 2 USB3_PTX_C_DRX_N1 GND GND
ESD@ DI5
3 3 8 12
2
2 USB3_PTX_C_DRX_P1 9 SSTX- GND 13
8 SSTX+ GND
1
C-K_26230A-8K1A-02
L05ESDL5V0NA-4_SLP2510P8-10-9 CONN@
1
RF Request
+5V_USB_CHG_PWR
LI7 EMI@
SW_USB20_N1 4 3 USB20_N1_R
SW_USB20_P1 1 2 USB20_P1_R
12P_0402_50V8J
RF@ CI43
68P_0402_50V8J
RF@ CI44
1 1
EXC24CQ900U_4P
+5V_ALW
C +5V_USB_CHG_PWR 2 2 C
UI3
1 12
VIN VOUT
2
<17> USB20_N1 DM_OUT
3
<17> USB20_P1 DP_OUT SW_USB20_P1
10
13 DP_IN 11 SW_USB20_N1
<17> USB_OC0# FAULT# DM_IN
ILIM_SEL 4
ILIM_SEL
5 15
<37> USB_PWR_SHR_VBUS_EN EN ILIM_L 16 RI14 2 1
ILIM_HI 22.1K_0402_1%
6
<37> USB_PWR_SHR_LFT_EN# 7 CTL1 9
8 CTL2 NC 14
CTL3 GND 17
Thermal Pad
SLGC55544CVTR_TQFN16_3X3
+5V_ALW
RI13 2 1 ILIM_SEL
10K_0402_5%
+5V_ALW
47U_0603_6.3V6M
47U_0603_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
B B
1 1 1 1
@ CI34
@ CI33
@ CI31
CI19
2 2 2 2
Place near UI3.1
A A
Title
USB SW
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
For Breckenridge 14&15/Steamboat 14

DI1 ESD@
USB3_PRX_DTX_N3 USB3_PRX_DTX_N3 +USB_EX2_PWR
<20> USB3_PRX_DTX_N3
1 1 10 9 RF Request
USB3_PRX_DTX_P3 2 2 9 8 USB3_PRX_DTX_P3 +USB_EX2_PWR JUSB2
<20> USB3_PRX_DTX_P3 USB3_PTX_C_DRX_P3 9
USB3_PTX_C_DRX_N3 4 4 USB3_PTX_C_DRX_N3 SSTX+
<20> USB3_PTX_DRX_N3
2 1 7 7 1
VBUS
CI5 0.1U_0402_25V6 USB3_PTX_C_DRX_N3 8
USB3_PTX_C_DRX_P3 USB3_PTX_C_DRX_P3 USB20_P2_R SSTX-
0.1U_0201_10V6K
2 1 5 5 6 6 3
<20> USB3_PTX_DRX_P3 D+
100U_1206_6.3V6M
CI4 0.1U_0402_25V6 1 7
GND
1
USB20_N2_R
CI3
3 3 2 10
USB3_PRX_DTX_P3 D- GND
CI1
6 11
SSRX+ GND
2
12P_0402_50V8J
RF@ CI45
68P_0402_50V8J
RF@ CI46
8 1 1 4 12
GND GND
2
2 USB3_PRX_DTX_N3
ESD@ DI2
5 13
2
D SSRX- GND D
L05ESDL5V0NA-4_SLP2510P8-10-9
LOTES_AUSB0014-P003A
2 2
1
CONN@
1
LI3 EMI@
USB20_P2 4 3 USB20_P2_R
<17> USB20_P2
USB20_N2 1 2 USB20_N2_R
<17> USB20_N2
EXC24CQ900U_4P
DFB request:
main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P) +USB_EX2_PWR
Pitch change from 0.5mm to 0.55mm
+5V_ALW
UI1
1
5 OUT
IN 2
GND
10U_0603_10V6M
0.1U_0201_10V6K
4
<37> USB_PWR_EN1# EN 3
1 OCB USB_OC1# <17>
@ CI6
CI7
SY6288D20AAC_SOT23-5
2
2
C C
RF Request
+USB_EX3_PWR
+USB_EX3_PWR
JUSB3 CONN@
DI6 ESD@ 1
USB3_PRX_DTX_N4 1 1 USB3_PRX_DTX_N4 USB20_N3_R VBUS
10 9 2
<20> USB3_PRX_DTX_N4 USB20_P3_R 3 D-
USB3_PRX_DTX_P4 USB3_PRX_DTX_P4 D+
100U_1206_6.3V6M
0.1U_0201_10V6K
2 2 9 8 4
<20> USB3_PRX_DTX_P4 USB3_PRX_DTX_N4 GND
12P_0402_50V8J
RF@ CI47
68P_0402_50V8J
RF@ CI48
1 1 1 5
StdA-SSRX-
1
USB3_PTX_C_DRX_N4 USB3_PTX_C_DRX_N4 USB3_PRX_DTX_P4
CI10
2 1 4 4 7 7 6 10
<20> USB3_PTX_DRX_N4 StdA-SSRX+ GND
CI8
CI27 0.1U_0402_25V6 7 11
USB3_PTX_C_DRX_P4 USB3_PTX_C_DRX_P4 USB3_PTX_C_DRX_N4 GND-DRAIN GND
2 1 5 5 6 6 8 12
<20> USB3_PTX_DRX_P4 StdA-SSTX- GND
2
CI28 0.1U_0402_25V6 2 2 2 USB3_PTX_C_DRX_P4 9 13
StdA-SSTX+ GND
ESD@ DI3
3 3
2
C-K_26210B-8K1A-02
8
1
L05ESDL5V0NA-4_SLP2510P8-10-9
1
B B
+USB_EX3_PWR
LI4 EMI@
USB20_P3 1 2 USB20_P3_R +5V_ALW
<17> USB20_P3
UI2
1
USB20_N3 4 3 USB20_N3_R 5 OUT
<17> USB20_N3 IN 2
GND
10U_0603_10V6M
0.1U_0201_10V6K
EXC24CQ900U_4P 4
<37> USB_PWR_EN2# EN
@ CI11
1 3
OCB USB_OC2# <17>
CI12
SY6288D20AAC_SOT23-5
2
2
A A
Title
JUSB2&JUSB3
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
RF Request
Touch Pad +3.3V_TP +3.3V_TP
KB_DET#
RF@ CZ84
1 2
68P_0402_50V8J
+3.3V_RUN +3.3V_TP BC_INT#_ECE1117 1 2

D 1 @RF@ CZ85 68P_0402_50V8J D
4.7K_0402_5%
4.7K_0402_5%
1
1
PJP35 RF@CZ83 BC_DAT_ECE1117 1 2
RZ18
RZ19
1 2 68P_0402_50V8J @RF@ CZ86 68P_0402_50V8J
2
PS2 PAD-OPEN1x1m BC_CLK_ECE1117 1
@RF@ CZ87
2
68P_0402_50V8J
2
2 1 DAT_TP_SIO_R DAT_TP_SIO_R 1 2
<37> DAT_TP_SIO_I2C_CLK
@ RZ22 0_0402_5% @RF@ CZ88 68P_0402_50V8J
2 1 CLK_TP_SIO_R
<37> CLK_TP_SIO_I2C_DAT CLK_TP_SIO_R 1 2
@ RZ23 0_0402_5%
@RF@ CZ89 68P_0402_50V8J
330P_0402_50V8J
330P_0402_50V8J
1
1
I2C1_SDA_TP_R
CZ80
CZ81
2 1
RZ346 0_0402_5%
2
2 1 I2C1_SCK_TP_R
RZ347 0_0402_5% CONN@
JKBTP1
I2C From EC
Keyboard 22
21 GND
GND
KB_DET# 20
<20> KB_DET# 19 20
18 19
17 18
16 17
+3.3V_TP +3.3V_TP +5V_RUN 16
+3.3V_ALW 15
BC_INT#_ECE1117 14 15 +3.3V_TP +3.3V_ALW +5V_RUN
<37> BC_INT#_ECE1117 BC_DAT_ECE1117 13 14
<37> BC_DAT_ECE1117 13
10K_0402_5%
10K_0402_5%
12
12
1
C BC_CLK_ECE1117 C
4.7K_0402_5%
4.7K_0402_5%
@ @ 11
<37> BC_CLK_ECE1117 11
RZ116
RZ117
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
10 1 1 1
10
RZ20
RZ21
@
9
+3.3V_TP DAT_TP_SIO_R 9
CZ90
CZ91
CZ92
8
CLK_TP_SIO_R 7 8
2
6 7 2 2 2
2 6
2
5
1 2 I2C1_SDA_TP_R <19,37> TOUCHPAD_INTR# 4 5
<21> I2C1_SDA_TP I2C1_SDA_TP_R 3 4
RZ26 0_0402_5%
1 2 I2C1_SCK_TP_R I2C1_SCK_TP_R 2 3
<21> I2C1_SCK_TP 2
RZ29 0_0402_5% 1
1 Place close to JKBTP1
I2C From CPU CVILU_CF5020FD0RK-05-NH
Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues
B B
RSMRST circuit
+3.3V_ALW
@ CZ82
1 2
0.1U_0201_10V6K
5
1
P
<37> PCH_RSMRST# B 4 PCH_RSMRST#_AND <7,20>

2 O
<49> ALW_PWRGD_3V_5V A
G
UZ6
3
TC7SH08FU_SSOP5~D
A A
Title
Keyboard
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
HDD LED MUX Battery LED

means EC can switch battery white led and HDD LED by hot key “Fn+H”
<38> SATA_LED_EN
BATT_WHITE#
1 2 BATT_WHITE#
<37,45> BAT2_LED#
5
D RZ361 150_0402_5% D
4 3 BAT2_LED#_R
<16,35,40> SATALED#
@ QZ2B
3
DMN65D8LDW -7_SOT363-6 1 2 BATT_YELLOW#
<37> BAT1_LED#
R1=47k/R2=10k RZ28 330_0402_5%
R2
2
R1
@ QZ3
+3.3V_ALW DDTA144VCA-7-F_SOT23-3
1
2
1 6 BAT2_LED#_R
<37,45> BAT2_LED#
1 2
@ QZ2A @ RZ25 150_0402_5%
LED P/N change to SC50000FL00 from SC50000BA00
Breath LED
+5V_ALW
C C
QZ7B LED3
DMN65D8LDW -7_SOT363-6 LTW -C193DC-C_W HITE
4 3 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_SNIFF# 1 2
<37> BREATH_LED#
RZ32 330_0402_5%
Place LED3 close to SW3
5
+3.3V_ALW
MASK_BASE_LEDS#
@ CZ93
1 2
0.1U_0201_10V6K
5
1
P
<33,37> SYS_LED_MASK# B MASK_BASE_LEDS#

4
2 O
<38,45> LID_CL# A
G
UZ10
TC7SH08FU_SSOP5~D
3
POWER & INSTANT ON SWITCH

LED board CONN
SW 3
2 1
<21,38> POWER_SW#_MB CONN@
+5V_ALW JLED1
1
4 3 BATT_YELLOW # 2 1
BATT_W HITE# 3 2
SKRBAAE010_4P 4 3
B B
5 4
<38,45> LID_CL# 5
+3.3V_ALW 6
6 7
GND1 8
GND2
CVILU_CF5006FD0R0-05-NH
LED Circuit Control Table

Fiducial Mark
@ FD1
1 SYS_LED_MASK# LID_CL#
FIDUCIAL MARK~D
@ FD2 Mask All LEDs (Unobtrusive mode) 0 X

1
Mask Base MB LEDs (Lid Closed) 1 0
FIDUCIAL MARK~D
Do not Mask LEDs (Lid Opened) 1 1
@ FD3
1
FIDUCIAL MARK~D CPU NGFF Standoff For JAE JSIM1 boss hole
@ FD4 @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H42 @ H43 @ H23 @ H24 @ H25 @ H18 @ H16 @ H17 @ H26 @ H9 @ H20 @ H28 @ H15
1 H_3P8 H_3P8 H_3P8 H_3P8 H_1P0N H_1P0N H_3P2 H_3P2 H_0P7N H_0P9N H_2P5 H_2P5 H_2P2 H_2P5 H_2P3 H_4P0 H_2P3 H_2P3 H_4P0 H_2P5 H_4P0
FIDUCIAL MARK~D
1
A A
eDP Standoff Frame Standoff PCH

@ H34 @ H35 @ H38 @ H46 @ H45 @ H14 @ H22 @ H29 @ H10 @ H12 @ H32 @ CLIP1
H_3P2 H_3P2 H_3P8 H_1P0N H_1P0N H_4P0 H_4P0 H_2P5 H_3P0 H_2P5 H_2P6X3P6 CLIP_SH1506X616
1
Title
PAD, LED
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_WWAN/+3.3V_LAN source +1.8V_RUN source

PJP41
1 2
+3.3V_ALW +3.3V_WWAN
UZ2 PAD-OPEN1x3m 2.5A PJP42 0.025A

1 14 +3.3V_WWAN_UZ2 1 2 1 2
VIN1 VOUT1 +1.8V_PRIM +1.8V_RUN
2 13 CZ119 0.1U_0201_10V6K UZ8
VIN1 VOUT1 PAD-OPEN1x1m
3.3V_WWAN_EN 3 12 1 2 1 7
D <37> 3.3V_WWAN_EN ON1 CT1 VIN VOUT +1.8V_RUN_UZ8
D
CZ109 470P_0402_50V7K 2 8 1 2
4 11 +3.3V_WWAN_UZ2 VIN VOUT CZ120 0.1U_0201_10V6K
+5V_ALW VBIAS GND RUN_ON_1.8V
1 2 3 6 1 2
5 10 1 2 <11,37,38,46,52> RUN_ON ON CT
RZ345 0_0402_5% CZ121 470P_0402_50V7K
<20,37> SIO_SLP_LAN# ON2 CT2 CZ110 470P_0402_50V7K 1
6 9 +5V_ALW
4
7 VIN2 VOUT2 8 +3.3V_LAN_UZ2 1 2 RF@ CZ124 VBIAS 5
VIN2 VOUT2 CZ111 0.1U_0201_10V6K 2200P_0402_50V7K GND 9
GND
1
1 2 3.3V_WWAN_EN 15 2
RZ40 100K_0402_5% GPAD PJP37 @ CZ197
EM5209VF_SON14_2X3 1 2 +3.3V_LAN 470P_0402_50V7K AOZ1336_DFN8_2X2
2
PAD-OPEN1x1m
1A RF Request
Reserve R/C for Audio power sequence, +5V->+3.3V->+1.8V
+3.3V_ALW_PCH/+3.3V_RUN source
PJP38 1.102A
1 2 +3.3V_ALW_PCH
PAD-OPEN1x1m
+3.3V_ALW
C C
UZ3
1 14 +3.3V_ALW_PCH_UZ3 1 2
2 VIN1 VOUT1 13 CZ112 0.1U_0201_10V6K
VIN1 VOUT1
@ RZ65 1 2 0_0402_5% 3 12 1 2
<37> PCH_ALW_ON ON1 CT1
RZ64 1 2 0_0402_5% CZ113 470P_0402_50V7K
<11,20,37,51,53> SIO_SLP_SUS#
+5V_ALW 4 11
VBIAS GND
RUN_ON 5 10 1 2
ON2 CT2 CZ114 1000P_0402_50V7K
6 9
7 VIN2 VOUT2 8 +3.3V_RUN_UZ3 1 2
VIN2 VOUT2 CZ115 0.1U_0201_10V6K
15
GPAD
EM5209VF_SON14_2X3 PJP39
1 2 +3.3V_RUN
PAD-OPEN1x3m
4.677A
+5V_RUN/+3.3V_WLAN source
B B
PJP40 3.076A
1 2 +5V_RUN
+5V_ALW
UZ4 PAD-OPEN1x2m
1 14 +5V_RUN_UZ4 1 2
2 VIN1 VOUT1 13 CZ116 0.1U_0201_10V6K
VIN1 VOUT1
3 12 1 2
<11,37,38,46,52> RUN_ON ON1 CT1 CZ117 470P_0402_50V7K
1 2 4 11
<20,37> SIO_SLP_WLAN# VBIAS GND
@ RZ71 0_0402_5%
1 2 5 10 1 2
<37> AUX_EN_WOWL ON2 CT2
RZ70 0_0402_5% CZ118 470P_0402_50V7K
6 9 +3.3V_WLAN_UZ4 1 2
+3.3V_ALW VIN2 VOUT2
7 8 CZ122 0.1U_0201_10V6K
VIN2 VOUT2 PJP36
15 1 2
GPAD +3.3V_WLAN
EM5209VF_SON14_2X3 PAD-OPEN1x2m
2A
1 2 AUX_EN_WOWL
RZ38 100K_0402_5%
A A
Title
Power control
B
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM
VCCPRIM_1P0 PCH SIO_PWRBTN# 8
Timing Diagram for S5 to S0 mode VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCAPLL_1P0
PWRBTN#
RSMRST#
PCH_RSMRST#
7
VCCCLK1~6 SIO_SLP_SUS#
TPS22961 VCCMPHYGT_1P0
VCCSRAM_1P0
SLP_SUS# 5
+PWR_SRC 6 +1.0V_MPHYGT VCCAMPHYPLL_1P0 SLP_S5#
SIO_SLP_S5#
9
6 VCCAPLLEBB
SIO_SLP_S4#
+1.0V_PRIM SYX198
EXT_PWR_GATE#
EXT_PWR_GATE#
SLP_S4# 10
SIO_SLP_S3#
+3.3V_ALW +3.3V_ALW_DSW SLP_S3#
3 VCCDSW_3P3
SLP_A#
SIO_SLP_A#
CPU
+3.3V_SPI 5 +3.3V_ALW_PCH SIO_SLP_LAN#
11
D VCCST_PWRGD
+VCC_CORE VCCHDA SLP_LAN#
D
VCCSPI
12 VCCST_PWRGD VCC VCCPRIM_3P3
VCCPGPPA~E
SLP_WLAN#/GPD9
SIO_SLP_WLAN#
+1.0VS_VCCIO VCCRTCPRIM RESET_OUT#
H_CPUPWRGD
VCCIO
5 +1.8V_PRIM SYS_PWROK
16
15 PROCPWRGD +VCC_GT VCCPGPPG
VCCATS PCH_PWROK
PCH_PWROK
PCH_PLTRST#
VCCGT
+RTC_CELL 14
+1.35V_MEM
17 PLTRST#
VDDQ
VCCRTC
VCCST_PWRGD
VCCST_PWRGD
12
0.675V_DDR_VTT_ON
VDDQC
VCCPLL_OC +1.0V_PRIM 5 +1.0V_PRIM_CORE
VCCPRIM_CORE
12 DDR_VTT_CNTL +1.0V_VCCST 10 SIO_SLP_S4# PROCPWRGD
H_CPUPWRGD
15
VCCST TPS22961
VCCSTG
VCCPLL
17 PCH_PLTRST#
PLTRST#
+VCC_SA
VCCSA
PCH_DPWROK
4 DSW_PWROK
+3.3V_ALW
ENVDD_PCH
+LCDVDD AP2821K EDP_VDDEN
+PWR_SRC
5 +1.0V_PRIM_CORE
TLV62130
SIO_SLP_SUS# +3.3V_ALW
SIO_SLP_LAN#
+3.3V_ALW 11 +3.3V_LAN EM5209VF SLP_LAN#
5 +1.8V_PRIM
TLV62130
+5V_RUN
C 3.3V_TS_EN C
+5V_TSP LP2301ALT1G GPP_B21
+3.3V_RUN
3.3V_CAM_EN#
+3.3V_CAM LP2301ALT1G GPD7
Power Button
SIO 5048 1BAT 2AC

11 SIO_SLP_WLAN#
11 ADAPTER
+PWR_SRC
+5V_ALW +5V_ALW2
RUN_ON
EC 5085 ALWON SYX198
+5V_ALW
EM5209VF
+5V_RUN +5V_HDD 1BAT
+PWR_SRC
+3.3V_ALW +3.3V_RTC_LDO
BATTERY SYX198
+3.3V_ALW2 2AC
EM5209VF +3.3V_RUN +3.3V_HDD +3.3V_ALW
+3.3V_RUN
11
5
B
+PWR_SRC
APL5930 +1.5V_RUN 7 PCH_RSMRST#
SIO_SLP_SUS#
+3.3V_ALW
B
+3.3V_ALW @SIO_SLP_WLAN# TLV62130 +1.0VS_VCCIO 4 PCH_DPWROK

EM5209VF
@PCH_ALW_ON +3.3V_ALW_PCH 5
RESET_OUT#
11 +3.3V_WLAN EM5209VF AUX_EN_WOWL 16 +3.3V_ALW
11 Pop option
A_ON
EM5209VF +3.3V_M +3.3V_SPI
5 SIO_SLP_SUS#
10 SIO_SLP_S4#
10 +3.3V_ALW
9 SIO_SLP_S5# SUS_ON
EM5209VF +3.3V_SUS
SIO_SLP_LAN#
11 SIO_SLP_S3# +PWR_SRC
SIO_SLP_A# EN_INVPWR
AO6405 +BL_PWR_SRC 18
+PWR_SRC
12
+VCC_SA IMVP_VR_ON 10 +PWR_SRC
13 +VCC_CORE ISL95857 SUS_ON
+VCC_GT +1.35V_MEM VDDQ
RT8207MZ DDR
+0.675V_DDR_VTT VTT
PCH_PWROK
12
0.675V_DDR_VTT_ON
A
BC BUS 14 A
Title
Power Sequence
Custom
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
2200P_0402_50V7K
1
PR2
1
1K_0402_5%
EMC@ PC2
+3.3V_RTC_LDO
+Z4012 2
2
@ JRTC1
1 3
+COINCELL 2 1 G 4
2 G
D D
ACES_50271-0020N-001
2
+RTC_CELL
1
PD1 EMC@ PD2 EMC@
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMC@ PL1 PD3
1
FBMJ4516HS720NT_2P
+3.3V_ALW BAS40CW SOT-323 1
3
1 2 PC3
Primary Battery Connector 1U_0603_25V6K
EMC@ PL2
1
FBMJ4516HS720NT_2P 2
PBATT+_C
@ PBATT1
1 2 +PBATT
PR1
1
1 2 100K_0402_5%
2
2 3 PRP1
3 4 PBAT_SMBCLK_C 8 1
2200P_0402_50V7K
4 5 PBAT_SMBDAT_C 7 2
5 PBAT_PRES#_C PBAT_CHARGER_SMBDAT <37,57>
6 6 3
6 PBAT_CHARGER_SMBCLK <37,57> PBAT_PRES# <37,57>
1
7 5 4
EMC@ PC1
7 8
8 9 100_0804_8P4R_5%
2
9 10
10 11
GND 12
GND
DEREN_40-42251-01001RHF +3.3V_ALW
@ PR3
2
GND 1 2
0_0402_5%
PR4
2.2K_0402_5%
C EMC@ PL3 PR5 C
1
BLM15AG102SN1D_2P 33_0402_5%
NB_PSID 2 1 1 3 1 2 PS_ID
S
PS_ID <37>
PQ2
2
FDV301N-G_SOT23-3 +5V_ALW
G
2
PR6
100K_0402_1%
3
PD4 EMC@
1
PESD5V0U2BT_SOT23-3 C
2 PQ3 PR7
B MMST3904-7-F_SOT323~D 10K_0402_1%
E
1
3
2
2
PR8
15K_0402_1%
1
PD5
PDS5100H-13_POWERDI5-3~D
+3.3V_VDD_DCIN +DC_IN
2
DC_IN+ Source 1 PU2
3 2
+DC_IN VIN
1U_0603_50V6K
3 1
VOUT
S1 S2 +SDC_IN
PC11
1
GND
PQ9 +DC_IN_SS PQ4 2
AP2204RA-3.3TRG1_SOT89-3
1
AON7409_DFN8-5 AON7409_DFN8-5
EMC@ PL4 1 1 +SDC_IN PC10
FBMJ4516HS720NT_2P 2 2 2.2U_0402_10V6M
AO3409_SOT23
2
1
1 2 3 5 5 3
0.022U_0603_50V7K
PR10
PC4
300K_0402_5%
1
PR11
PQ5
499K_0402_1%
4
4
1
3
B S B
PC7 can't over 1000P
499K_0402_1%
0.022U_0603_50V7K
2
2
G
2
2
2 PR12
PC6
1000P_0603_50V7K
1
1
@ PJPDC1 D +3.3V_VDD_DCIN
100K_0402_5%
4.7K_0805_5%
10U_0805_25V6K
0.1U_0603_25V7K
1
1
7 PR15
PR13
GND
1
6
EMC@ PC5
PC7
PC8
100K_0402_5%
2
GND 5 -DCIN_JACK
PR14
5 4
2
2
4
1
PR16
+DCIN_JACK
@
3
@EMC@
49.9K_0402_1%
2
3 2 PR17
2 1
1 100K_0402_5%
6
1
CVILU_CI0805M1HRC-NH
2
2
PQ1A
PR18 2 2 1
DMN65D8LW-7_SOT323-3
PC9
+3.3V_VDD_DCIN D
1
2 1 49.9K_0402_1% PR20 PR19

2
1
2 1 2 0_0402_5%
PQ7
0.1U_0402_10V7K G
S 0_0402_5%
3
PR21 PU1 VBUS2_ECOK <38,59>

5
0_0402_5% TC7SH08FU_SSOP5~D
D
1
3
<37,57,59> ACAV_IN_NB 1 2 1 PR23
P
B 4 2 1 2
PQ6
1 2 2 O G
PQ1B
A
G
0_0402_5% S PR24 5 2 1
AC_DISC# <37,59>
3
PR22 100K_0402_5%
3
0_0402_5% PR25
4
0_0402_5%
PQ8
PR26 DMN65D8LW-7_SOT323-3
0_0402_5%
1 2 3 1
S
<38> DCIN2_EN
G
2 2
1
A A
0_0402_5%
100K_0402_5%
1
PR28
PR29
PR27
2
100K_0402_5%
1
+3.3V_VDD_DCIN
+3.3V_ALW
+DCIN
C
LA-E141P 0.2

5 4 3 2 1
A B C D E
PR119
0_0402_5%
PGOOD_3V 1 2
ALW_PWRGD_3V_5V <44>
PGOOD_5V 1 2
1 1
PR120
0_0402_5%
PR102
499K_0402_1%
+PWR_SRC ENLDO_3V5V 1 2
PR100
+PWR_SRC
PJP100 PC102
1
3V_VIN BST_3V1
499K_0402_1%
1 2 2 1 2
PR103
PAD-OPEN 1x2m~D 0.1U_0603_25V7K
0_0603_5%
100P_0402_50V8J
100P_0402_50V8J
@
1
PU100
2
10U_0805_25V6K
10U_0805_25V6K
EMC@ PC100
EMC@ PC103
BS
IN
IN
IN
IN
1
1
LX_3V 6
PC105
PC104
20 PL100
LX LX 1.5UH_PCMC063T-1R5MN_9A_20%
2
2
7 19 LX_3V 1 2
GND
SY8288BRAC_QFN20_3X3 LX
+3.3V_ALWP
EMC@ PR106
8 18 PR104
GND GND
4.7_1206_5%
0_0402_5%
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
9 17 1 2
PG LDO +3.3V_ALW2
1
Update PH401 change
PC106
PC107
PC108
PC109
PC110
@ PC129
10 16 PR105
NC NC 1 2 to Common Part
+3.3V_RTC_LDO 3VALWP
OUT
SH000016800 20141202
2
EN2
EN1
21 0_0402_5%
NC
FF
GND
TDC 6.8 A
1 3V_SN 2
PR107
Peak Current 9.7 A
11
12
13
14
15
680P_0603_50V7K
100K_0402_5% 3.3V LDO 150mA~300mA
EMC@ PC112
2 1 2 2
+3.3V_ALW OCP Current 11.6 A
1
ENLDO_3V5V
PC111
4.7U_0603_6.3V6K
Vout is 3.234V~3.366V
2
PGOOD_3V
@ PJP102
PC113 PR108 +3.3V_ALWP 1 2 +3.3V_ALW
1000P_0402_50V7K 1K_0402_5% 1 2
3V5V_EN 3V_FB 1 2 1 2 JUMP_43X118
+PWR_SRC @ PJP103
+5V_ALWP 1 2 +5V_ALW
PJP101 @ PR111 1 2
PC114
1 2 5V_VIN BST_5V 1 2 1 2 JUMP_43X118
PAD-OPEN 1x2m~D 0.1U_0603_25V7K

0_0603_5%
100P_0402_50V8J
100P_0402_50V8J
1
10U_0805_25V6K
10U_0805_25V6K
EMC@ PC115
EMC@ PC116
PU102
1
BS
IN
IN
IN
IN
PC117
PC118
LX_5V 6 20 PL101
2
LX LX 2.2UH +-20% 7.8A 7X7X3 MOLDING

7 19 LX_5V 1 2 +5V_ALWP
3 GND LX 3
8 SY8288CRAC_QFN20_3X3 18
GND GND
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PR112
680P_0603_50V7K 4.7_1206_5%
PC119
1
9 17 1 2
PC120
PC121
PC122
PC123
PC124
@ PC130
PG VCC
@EMC@
Update PH401 change
10 16
to Common Part
2
NC NC 4.7U_0603_6.3V6K
1 5V_SN
OUT
SH000016800 20141202
LDO
2
EN2
EN1
21
FF
GND
11
12
13
14
15
PC125
PR113
@EMC@
100K_0402_5%
+5V_ALW2
2
1 2
+3.3V_ALW
ENLDO_3V5V
5V LDO 150mA~300mA
3V5V_EN
PGOOD_5V
PC126
4.7U_0603_6.3V6K
PR114
2
1 2
<37> ALWON 5VALWP
0_0402_5%
TDC 5.4 A
3V5V_EN Peak Current 7.7 A
OCP Current 9.2 A
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR116
PC128
PC127 PR117
1000P_0402_50V7K 1K_0402_5%
5V_FB 1 2 1 2
2
2
4 4
EN1 and EN2 dont't floating
Title
+5V_ALW/3.3V_ALW

A B C D E
5 4 3 2 1
D D
+PWR_SRC
PJP202 @
@EMC@ PC202
@EMC@ PC203
1 2 +1.2V_DDR_B+
PU200
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
PAD-OPEN 1x2m~D EMC@ EMC@

1
10 19 PR202 PC204
PC200
PC201
+3.3V_ALW
IN OT 4.7_1206_5% 680P_0603_50V7K
13 18 1 2 1 2
2
BYP PG
1U_0402_6.3V6K
14 12
PR203
1 2 1
PC205
2
+1.2V_DDRP
VCC BS
1
PC206
C 0_0603_5% 0.1U_0603_16V7K PL201 C
1
2.2U_0402_6.3V6M
4 11 LX_DDR 1 2
VTTGND LX
PC207
1UH_PCMB063T-1R0MS_12A_20%
2
330P_0402_50V7K
2 9 16
PGND FB
1
102K_0402_1%
@EMC@
@EMC@
1
PC208
PR204
15 8 +1.2V_DDRP PC209
+3.3V_ALW SGND VDDQSNS
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2200P_0402_50V7K
22U_0603_6.3V6M
R1
100P_0402_50V8J
7 1 2
2
VLDOIN
1
PC210
PC211
PC212
PC213
PC223
PC214
PC216
PC217
2
2
ILMT_DDR 17 6
PR205 @ ILMT VTT +0.6VSP
2
The current limit is 0_0402_5% 1
S5 VTTSNS
5
set to 8A, 12A or 16A
1
100K_0402_1%
2 3
when this pin is pull
1
S3 VTTREF
22U_0603_6.3V6M
PR206
R2
1
low, floating or pull
1U_0402_10V6K
PC218
ILMT_DDR
PC219
high SY8210AQVC_QFN19_4X3
EN_1.2V
+1.2V_DDR OCP set 8A
2
2
EN_0.6V
PR207 @
0_0402_5%
1
PR208
0_0402_5%
2 1
B B
0.1U_0402_10V7K
<11,20,21,37,53> SIO_SLP_S4#
1M_0402_5%
1
1
@ PC221
PR209
+1.2V_DDRP +1.2V_MEM +0.6VSP +0.6V_DDR_VTT

2
@ PJP200 @ PJP201
2
JUMP_43X118 JUMP_43X39
1 2 1 2
PR210 1 2 1 2
0_0402_5%
<14> 0.6V_DDR_VTT_ON
2 1
0.1U_0402_10V7K
1M_0402_5%
1
@ PC222
+1.2V_DDR 0.6Volt +/- 5%

PR212
TDC 5.6A TDC 0.007A

2
Mode S3 S5 VOUT VTT Peak Current 8.0A Peak Current 0.01A

Normal H H on on
2
Stadby L H on off OCP Current 9.5A OCP Current 2A (fix)

Shutdown L L off off
Note: S3 - sleep ; S5 - power off
A A
Title
+1.2V_MEN/+0.6V_DDR_VTT
Custom
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
D D
PR312
1 2
SIO_SLP_SUS# <11,20,37,46,53>
0_0402_5%
EN_+1VALW P
1
1M_0402_1%
PR302 PJP302
+1VALWP 1 2 +1.0V_PRIM
2
1 2
JUMP_43X118
@
@EMC@ PL302
FBMA-L11-201209-121LMA50T_0805 EMC@ PR303 EMC@ PC302
1 2 4.7_1206_5% 680P_0603_50V7K
2 SNB_+1VALW P 1
+PWR_SRC @ PJP301 PU301
1 2
1 2 +1VALW P_B+ 8 1 PC304 PR304

100P_0402_50V8J
100P_0402_50V8J
IN EN 0.1U_0603_25V7K 0_0603_5%
10U_0805_25V6K
10U_0805_25V6K
PAD-OPEN 1x2m~D 6 BST_+1VALW P 1 2BST_+1VALW P_C
1 2 PL301
BS
1
1
0.68UH_MMD-05CZ-R68M-X2L_8.5A_20%
PC305
PC306
C 9 10 SW _+1VALW P 1 2 +1VALWP C
EMC@ PC301
EMC@ PC303
GND LX
2
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
330P_0402_50V7K
1
1
4 FB_+1VALW P
FB
PC307
PC308
PC309
PC310
PC311
21.5K_0402_1%
1
ILMT_+1VALW P 3 7
+3.3V_ALW
2
ILMT BYP
PR306
4.7U_0603_6.3V6K
+3.3V_ALW 2 5
4.7U_0603_6.3V6K
PG LDO
1
PC312
1K_0402_5%
1
SYX198DQNC_QFN10_3X3
PC313
PR308
2
1
2
2
@ PR307
2
0_0402_5%
2
ILMT_+1VALW P
1
1
PR311
31.6K_0402_1%
@ PR310
0_0402_5%
2
+1.0V_PRIM
2
TDC 5.8 A
Peak Current 11.1 A
OCP Current 13.3 A
B TYP MAX B
Choke DCR 11.0mohm , 12.0mohm
The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high
A A
Title
+1VALWP
Custom
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
1
D D
PR425 PR405 @
1 2 0_0402_5%
<11,20,21,39> SIO_SLP_S0#
0_0402_5%
2
PJP401
1 2
PR402 +1VS_VCCIOP 1 2 +1.0VS_VCCIO
<11,37,38,46> RUN_ON 1 2 JUMP_43X118
0_0402_5% @
EN_1VS_VCCIO
0.1U_0402_25V6
1
1
PC415
PR403
1M_0402_1%
2
@
13
14
15
16
17
Vin=3~17V PU401
+1.0VS_VCCIO
EN
PGND
PGND
TP
LPM
PJP402 TDC 3.9A
+5V_ALW 1 2 VIN_1VS_VCCIO 12
PVIN VOS
1
+1VS_VCCIOP Peak Current 5.5 A
PAD-OPEN 1x2m~D PL401 OCP Current 6.6 A Fix by IC
10U_0603_10V6M
10U_0603_10V6M
1UH_PCMB042T-1R0MS_4.5A_20%
@ TYP MAX
1
11 2 LX_1VS_VCCIO 1 2
+1VS_VCCIOP
PC404
PC408
PVIN SW
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
2
S IC SY8057QDC QFN 16P PWM
1
10 3
PC410
PC411
PC412
PC401
AVIN SW
+3.3V_ALW
100P_0402_50V8J
2
100P_0402_50V8J
1
1
VID0_VCCIO 9 4
EMC@ PC407
1SNUB_1VS_VCCIO
EMC@ PC405
VID0 PG EMC@ PR404

2
AGND
4.7_0603_5%
VID1
FBS
SS
C C
2
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
5
1
EMC@ PC403 0 X X 0(LPM)
SS_1VS_VCCIO
PR417 @ PR418 +1VS_VCCIOP
10K_0402_1% 10K_0402_1% VID1_VCCIO 470P_0402_50V7K SY8057 1 0 0 0.85
100_0402_1%
2
1
2
VID0_VCCIO
PR414
1 0 1 0.875
VID1_VCCIO
1 1 0 0.95
470P_0402_50V7K
PR415
2
2
1
1 1 1 0.975
1
PR427 2 1
PC409
200K_0402_1% VCC_IO_SENSE <11>
2
@ PR419 PR420
PR416 0_0402_5%
10K_0402_1% 10K_0402_1%
1 @ 2 1
2
VSS_IO_SENSE <11>
0_0402_5%
Preset the different pull down resistor to choose

the required power rail
(VCCIO/PCH/EDRAM/EOPIO applications.)
RMODE>500k or floating Vcc_PRIM_CORE.
RMODE=200k Vcc_IO.
RMODE=0 Vcc_EDRAM.
B B
A A
Title
+1VS_VCCIO
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
PC502
22U_0603_6.3V6M
1 2 PJP502 @
1 2
PJP501
@ +1.8VALWP +1.8V_PRIM
1 2 VIN_1.8VALW
+3.3V_ALW PAD-OPEN1x1m
PAD-OPEN1x1m
Imax= 2A, Ipeak= 3A
FB=0.6V
D D
PR517 PU501
PL501
2 1 1UH_1277AS-H-1R0N-P2_3.3A_30%
+3.3V_ALW 4 3 LX_1.8VALW 1 2
100K_0402_5% IN LX +1.8VALWP
1
5 2
68P_0402_50V8J
<37> 1.8V_PRIM_PWRGD PG GND @EMC@ PR502
1SNUB_1.8VALW
22U_0603_6.3V6M
22U_0603_6.3V6M
1
6 1
PC503
FB EN
1
4.7_0603_5%
PC501
PC504
PR501
2
RT8097ALGE_SOT23-6
PR504
2
20K_0402_1%
EN_1.8VALW
<11,20,37,46,51> SIO_SLP_SUS# 1 2
Rup
2
@EMC@ PC506
0_0402_5%
1
680P_0402_50V7K
2
1
PR505 @ PC505
1M_0402_1% 0.1U_0402_16V7K
2
FB_1.8VALW
1
PR506
Rdown +1.8V_PRIM
10K_0402_1% TDC 0.896 A
Note: Peak Current 1.25 A
2
When design Vin=5V, please stuff snubber OCP Current 3.5A fix by IC
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
C C
B B
+2.5V_MEM
TDC 0.45 A
Peak Current 1.1 A
OCP Current 1.5 A
PU503
PJP505
AP7361C-FGE-7_U-DFN3030-8_3X3 PJP506
1 2 +2.5V_VIN 9
+3.3V_ALW GND 1 2.5VSP 1 2
OUT +2.5V_MEM
1
8
PAD-OPEN1x1m PC514 IN 2
NC PAD-OPEN1x1m
1
@ 4.7U_0603_6.3V6K 7 PR515
2
NC 3 21.5K_0402_1% PC515 @
6 ADJ/NC 0.01UF_0402_25V7K
2
NC
1
PR513 4
1 2 5 GND PC516
<11,20,21,37,50> SIO_SLP_S4# EN 22U_0603_6.3V6M
2
0_0402_5%
1
@
PR514 PC513
PR516
2
A 1M_0402_1% .1U_0402_16V7K 10.2K_0402_1% A

2
Title
+1.8VALWP/+1.5VSP/2.5V_MEN
C
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
<7,37,57> H_PROCHOT#
47P_0402_50V8J~D
1
PC602
+5V_ALW
2
+1.0V_VCCST CPU_B+
1
PR605
PR606
PR607
0.1U_0402_25V6
1
PC603
0_0402_5%
0_0402_5%
D D
1_0402_5%
45.3_0402_1%
75_0402_1%
100_0402_1%
PC604
PR604
PR602
PR603
2
@ 1U_0402_6.3V6K
2
1 2 1 2
<7> VR_SVID_CLK 49.9_0402_1% PR609
<7> VR_SVID_ALERT# 1 2
PR612 0_0402_5% PR611
1 2 <7> VR_SVID_DATA 1 2 1 2
10_0402_1% PR614
VR_SVID_ALERT#_B
100K_0402_1% 1 2 PC605
VR_SVID_DATA_B
0.22U_0603_16V7K
VR_SVID_CLK_B
PC606 PH602
470K_0402_5%_TSM0B474J4702RE
1 2
PR616
330P_0402_50V7K 10.5K_0402_1% +3.3V_RUN
1 2 1 2
PR617
20.5K_0402_1%
1
1
PR615 1 2
110K_0402_1%
16.9K_0402_1%
1
PC607 27.4K_0402_1% 1.91K_0402_1%
PR619
PR620
PR621
1 2
182K_0402_1%
PR622
PR618
2
68P_0402_50V8J <20> PCH_PWROK 1 2
2
0_0402_5%
PC608 PR623 PC609 PR624 PR626
2 1 2 1
1 2 1 2 <38> IMVP_VR_ON 1 2 1.1K_0402_1%
.001U_0402_50V7-M 1 2 ISUMN_SA <56>
2200P_0402_25V7K 4.87K_0402_1% 2K_0402_1% PR625
1
0_0402_5%
+VCC_GT 10K_0402_5%_ERTJ0ER103J
6800P_0402_25V7K
PC610 PR627 <37,57> I_SYS PR628 PC611 PR629
680P_0402_50V7K 1K_0402_1% PU601 PH603
48
47
46
45
44
43
42
41
40
39
38
37
C C
11K_0402_1%
1
1
.1U_0402_16V7K
1 2 1 2 ISL95855HRTZTS27_TQFN48_6X6~D 48.7K_0402_1% 2 1 2 1
PC612
100_0402_1%
1 2
1
1 2
PR707
PR631
VCC
VIN
VR_ENABLE
VR_READY
SCLK
SDA
VR_HOT#
ALERT#
PROG1
PROG2
PROG3
PROG4
2.61K_0402_1%
0.033U_0402_16V7K
PR630 2200P_0402_50V7K 1K_0402_1%
PC614
PC613
2
PR633
PR632
0_0402_5% PWM_SA <56>
2 2.94K_0402_1% @
2
<12> VCC_GT_SENSE 2 1 FCCM_SA <56>
1
1 36
100_0402_1%
2
2 PSYS PROG5 35
PR710
<12> VSS_GT_SENSE IMON_B PWM_C
3 34
NTC_B FCCM_C
1
4 33
100_0402_1%
1 5 COMP_B ISUMN_C 32
PR708
FB_B ISUMP_C ISUMP_SA <56>
2
PC615 6 31
RTN_B RTN_C VSS_SA_SENSE <11>
0.01UF_0402_25V7K 7 30 1 2 1 2
ISUMP_B FB_C VCC_SA_SENSE <11>
2
8 29
2
ISUMN_B COMP_C
1
9 28 PR634 PC616
100_0402_1%
10 ISEN1_B IMON_C 27 316_0402_1% 1500P_0402_50V7K PC617
PR709
<56> ISUMP_GT
2K_0402_1%
11 ISEN2_B PWM3_A 26 1 2 0.01UF_0402_25V7K
2
FCCM_B PWM2_A
1
12 25
PWM1_B PWM1_A
1
1
2.61K_0402_1%
PR635
PR636
PR638
2
1
330P_0402_50V7K
2.74K_0402_1%
PR637
11K_0402_1%
68P_0402_50V8J
PR639 PC620
ISUMN_A
ISUMP_A
PWM2_B
COMP_A
ISEN1_A
ISEN2_A
ISEN3_A
FCCM_A
1
1
.1U_0402_16V7K
0.033U_0402_16V7K
IMON_A
49
+VCC_SA
PC618
PC619
PR601
NTC_A
RTN_A
2
EP
1
1 2 1 2 PR640
FB_A
PC621
1 2
PC622
2
1
1K_0402_1% 2200P_0402_50V7K 4.53K_0402_1%
PC624
2
680P_0402_50V7K
PWM2_VCORE 115K_0402_1%
<55>
10K_0402_5%_ERTJ0ER103J
13
14
15
16
17
18
19
20
21
22
23
24
1
2
2
PH604 PR641 PC623
PWM1_VCORE <55>
2
2
1 2 2200P_0402_50V7K
<56> ISUMN_GT
FCCM_VCORE <55>
402_0402_1% PR653
1
PC625
.1U_0402_16V7K
1 2
+5V_ALW
2
PC627 0_0402_5%
B ISEN2_GT <56> B
1 2
1 2
0.022U_0402_25V7K
PC628 0.022U_0402_25V7K ISUMN_VCORE <55>
PC629 <55> ISEN2_VCORE
0.022U_0402_25V7K 1 2
ISEN1_GT <56>
1
1 2 PH601
.1U_0402_16V7K
0.047U_0402_25V7K
PR642 PC630 0.022U_0402_25V7K
PC631
11K_0402_1%
10K_0402_5%_ERTJ0ER103J
1
<55> ISEN1_VCORE
<56> FCCM_GT
1
1 2
PR643
PC601
3.6K_0402_1%
1
.1U_0402_16V7K
PC632
<56> PWM1_GT
2
412_0402_1%
2
<56> PWM2_GT PC633 PR644
PR645
1 2 1 2
2200P_0402_50V7K 1K_0402_1%
2
ISUMP_VCORE <55>
VSS_SENSE <12>
PR646
10.5K_0402_1% 1 2 2 1 VCC_SENSE <12>
1 2
1
330P_0402_50V7K
PR647 PC634 PC635

1
1K_0402_1% 2200P_0402_50V7K 0.01UF_0402_25V7K

PC636
2
2
27.4K_0402_1%
PR648
470K_0402_5%_TSM0B474J4702RE
2
2
1 2 1
PR649
PH605
2K_0402_1%
95.3K_0402_1%
PR650
1
PR651
2
2.15K_0402_1%
1
PR652
1
1 2
68P_0402_50V8J
PC638
2
1
680P 50V K X7R 0402
3.6K_0402_1%
PC637
A A
2
PC639
2200P_0402_25V7K
1
Title
VCORE_ISL95855
Custom
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
VCC_core
TDC 50A
Peak Current 60A
OCP current 81.6A
Choke DCR 0.9 +-7%m ohm
PR673
0_0402_5%
D 1 2 D
+PWR_SRC CPU_B+ +5V_ALW
1U_0402_10V6K
1
PR655
PC641
5.11K_0402_1%
2
2 1 +VCC_CORE
rating 9A
PR654
PL610
@EMC@ PU610
PL602 2 1 0.15UH_MMD06CZER15MG_37A_20%
<54> PWM1_VCORE
1 2 9
0_0402_5% PC642 8 PGND
FBMA-L11-453215800LMA90T_2P 1 2 7 PWM 4 SW1_VCC_CORE 4 1
BOOT VSW 3
0.22U_0603_16V7K
@EMC@ PR657
PGND
1
@ PJP601 1 2 6 2 3 2 CORE_V1N
1 2 PR656 5 BOOT_R VDD 1
33P_0603_50V8J 10_1206_5%
1 2 2.2_0603_5% VIN SKIP#
JUMP_43X118 PR659 PR660
CSD97396Q4M_VSON8_3P5X4P5 3.65K_0603_1% 100K_0402_1%
2
1
1 2 1 2
100U_D_20VM_R55M
PC680 VCC_CORE_SNUB1
2200P_0402_50V7K
10P_0402_50V8K
1 1
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
100U_D_20VM_R55M
2
@EMC@ PC651
PC652
1000P_0402_50V7K
0.1U_0402_25V6
10_0402_1%
10U_0805_25VAK
2
1
1
+ +
PC645
PC646
PR661
@EMC@ PC650
PC647
PC648
PC649
PC655
PC686
PR658 <54> ISEN1_VCORE
2
1 2
@EMC@
2
2
2 2
<54,55>
@ @ PR662
ISUMP_VCORE
1
0_0402_5% 100K_0402_1%
FCCM_VCORE <54,55> CORE_V2N 1 2
1
PR678 @
5.11K_0402_1%
2
Polymer cap for noise issue
<54,55>
ISUMN_VCORE
C PC683 C
PR674 1U_0402_10V6K
0_0402_5%
1 2 1 2
PR663 +5V_ALW
5.11K_0402_1%
2 1
PR665
2 1 PL611
<54> PWM2_VCORE PU611
0.15UH_MMD06CZER15MG_37A_20%
0_0402_5% 9
PC684 8 PGND
1 2 7 PWM 4 SW2_VCC_CORE 4 1
BOOT VSW 3
0.22U_0603_16V7K
@EMC@ PR667
PGND
1
1 2 6 2 3 2 CORE_V2N
PR666 5 BOOT_R VDD 1
10_1206_5%
2.2_0603_5% VIN SKIP#

PR669 PR670
CSD97396Q4M_VSON8_3P5X4P5 3.65K_0603_1% 100K_0402_1%
2
1 2 1 2
2200P_0402_50V7K
10U_0805_25VAK
10U_0805_25VAK
VCC_CORE_SNUB2
@EMC@ PC702
0.1U_0402_25V6
10U_0805_25VAK
10U_0805_25VAK
1
2
@EMC@ PC703
PC656
PC699
PC700
PC701
10_0402_1%
1
PR671
@EMC@ PC704
33P_0603_50V8J
PC654 <54> ISEN2_VCORE

10P_0402_50V8K
PR668
2
1000P_0402_50V7K
2
2
1
<54,55>
1 2 @ PR672
PC653
ISUMP_VCORE
1
100K_0402_1%
0_0402_5% CORE_V1N 1 2
2
<54,55> FCCM_VCORE
1
PR679
5.11K_0402_1%
<54,55>
2
ISUMN_VCORE
B B
A A
Title
Issued Date 2017/01/01
VCORE
Custom
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
PC776
PR675 1U_0402_10V6K
0_0402_5%
1 2 1 2
+5V_ALW
+PWR_SRC PR680
5.11K_0402_1%
rating 9A 2 1
@EMC@ PL606
D PR684 D
1 2
FBMA-L11-453215800LMA90T_2P
<54> PWM1_GT
2 1
PL612
+VCC_GT
PU612
0_0402_5% 0.15UH_MMD06CZER15MG_37A_20%
9
8 PGND
@ PJP602
PC777
1 2 7 PWM 4 SW1_VCC_GT 4 1
VCC_GT
2
2 1
1 0.22U_0603_16V7K
BOOT VSW
PGND
3
GT_V1N
TDC 25A
1 2 6 2 3 2
PR687
Peak Current 55A
4.7_1206_5%
VCCGT_B+ BOOT_R VDD
1
JUMP_43X118 PR686 5 1
VIN SKIP#
2.2_0603_5% OCP current 66A
@EMC@
PR689 PR690
CSD97396Q4M_VSON8_3P5X4P5 3.65K_0603_1% 100K_0402_1% Choke DCR 0.9 +-7%m ohm
1
1 2 1 2
2
PC706 VCC_GT_SNUB1
10P_0402_50V8K
2
2200P_0402_50V7K
1000P_0402_50V7K
10_0402_1%
680P_0603_50V7K
10U_0805_25VAK
10U_0805_25VAK
2
1
1
@EMC@ PC779
0.1U_0402_25V6
PR691
PC705
@EMC@ PC780
10U_0805_25VAK
10U_0805_25VAK
1
1
<54> ISEN1_GT
@EMC@ PC783
PC781
PC782
PC778
PC709
PR688
<54,56>
@ PR692
ISUMP_GT
1 2
2
1
100K_0402_1%
<54,56> FCCM_GT 0_0402_5% GT_V2N 1 2
1
PR681 @
5.11K_0402_1%
<54,56>
ISUMN_GT
2
C PC784 C
PR676 1U_0402_10V6K
0_0402_5%
1 2 1 2
PR693 +5V_ALW
5.11K_0402_1%
2 1
PR694
2 1 PL613
<54> PWM2_GT PU613
0.15UH_MMD06CZER15MG_37A_20%
0_0402_5% 9
PC785 8 PGND
1 2 7 PWM 4 SW2_VCC_GT 4 1
BOOT VSW 3
0.22U_0603_16V7K PGND
1 2 6 2 3 2 GT_V2N
PR696
4.7_1206_5%
BOOT_R VDD
1
PR695 5 1
2.2_0603_5% VIN SKIP#
PR698 PR699
@EMC@
CSD97396Q4M_VSON8_3P5X4P5 3.65K_0603_1% 100K_0402_1%
1
1 2 1 2
PR697
1 2
VCC_GT_SNUB2
2200P_0402_50V7K
PC708
10P_0402_50V8K
10U_0805_25VAK
10U_0805_25VAK
2
@EMC@ PC788
1 2
0.1U_0402_25V6
1000P_0402_50V7K
10_0402_1%
10U_0805_25VAK
10U_0805_25VAK
2
1
1
@EMC@ PC789
PR700
PC786
PC775
PC787
PC710
PC707
680P_0603_50V7K <54> ISEN2_GT

PC790
0_0402_5%
2
1
<54,56> FCCM_GT
2
<54,56>
ISUMP_GT
PR682 @ @ PR701
1
@EMC@
5.11K_0402_1% 100K_0402_1%
GT_V1N 1 2
2
VCC_SA
<54,56>
TDC 10A
ISUMN_GT
DH_VCC_SA Peak Current 11.1A
OCP current 13.32A
B Choke DCR 6.2+-5%m ohm B
+PWR_SRC
PJP603 @
2 1
2 1
JUMP_43X118
PU614 PR702 PQ614 +VCC_SA
2
ISL95808HRZ-TS2778_DFN8_2X2~D
@EMC@ PC792
1 2
2200P_0402_50V7K
AON6994 2N DFN5X6D
10U_0805_25VAK
10U_0805_25VAK
FCCM_SA <54> PL614

0.1U_0402_25V6
D1
G1
S1/D2
10U_0805_25VAK
10U_0805_25VAK
1
1
@EMC@ PC791
1 8 0_0402_5% 0.47UH_MMD05CZR47M_12A_20%
PC793
PC794
PC795
PC711
UGATE PHASE SW_VCC_SA 1 4

+5V_ALW
2 7
0_0402_5%
BOOT FCCM
1
PR703 2 3
PR677
G2
S2
S2
S2
1 2 3 6
PR704
<54> PWM_SA
4.7_1206_5%
PWM VCC
1
3
1
0_0402_5% 4 5
3.65K_0603_1%
GND LGATE
2
PR705
EMC@
TP
PR683
0_0402_5%
9
2
2
VCC_SA_SNUB
1
PC796
1
1
4.7U_0402_6.3V6M
680P_0603_50V7K
PC797
2
<54> ISUMP_SA
EMC@
<54> ISUMN_SA
DL_VCC_SA
A A
PR706 PC798
BST_VCC_SA 1 2 BST_VCC_SA_C 1 2
2.2_0603_5% 0.22U_0603_16V7K
Title
VGT_VSA
C
LA-E141P 0.2

5 4 3 2 1
A B C D
+PWR_SRC_AC
+SDC_IN +CHARGER_SRC
PR901
0.01_1206_1% @EMC@ PL901
1UH_MMD-05CZ-1R0M-M7L_7A_20%
1 4 2 1
2 3 +PWR_SRC
2200P_0402_50V7K
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
0.1U_0402_25V6
15U_B2_25VM_R100M
15U_B2_25VM_R100M
15U_B2_25VM_R100M
1 1 1
@EMC@ PC902
@EMC@ PC903
1
1
+ + +
PC911
PC904
PC905
PC906
PC909
PC910
PC951
PJP901@
1 2
2
1 PAD-OPEN 4x4m 2 2 2 1
@ @ @
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
1
1
PC913
PC914
PC915
PC916
PC917
PC918
PC919
PC920
2
2
1
1
PR909 PR910
1_0402_1% 1_0402_1%
2
CSIN_ISL88738
PC925
CSIP_ISL88738
1U_0402_25V6K
2200P_0402_50V7K
1 2
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
@EMC@ PC928
@EMC@ PC929
1
1
PC926
PC927
2
2
2
@ @
2
PC930
+SDC_IN
PR943
PD901 0.22U_0603_25V7K
2 1
2 1 2 1 ADP_ISL88738
+PBATT
SDMK0340L-7-F_SOD323-2~D PR914
0_0603_5%
1
0_0603_5%
PD903
PR944
2 1 442K_0402_1%
+VBUS_DC_SS
1
2 2
RB520SM-30T2R_EMD2-2
2
BOOT1_ISL88738
ACIN_ISL88738
CSIP_ISL88738
CSIN_ISL88738
UG1_ISL88738
LX1_ISL88738
LG1_ISL88738
PD904
1
2 1
+DC_IN_SS PR945 PR915
SDMK0340L-7-F_SOD323-2~D 100K_0402_5% 4.7_0402_5%
2
1 2 VDD_ISL88738
PR916
2
PU901
16
15
14
13
12
11
10
33
1_0805_5%~D
9
ISL88738HRTZ-T_TQFN32_4X4 PQ905 PQ904
PC931 1U_0603_25V6 CSD87351Q5D_SON8-7 CSD87351Q5D_SON8-7
BOOT1
UGATE1
PHASE1
LGATE1
CSIN
PAD
ADP
CSIP
ASGATE
1
PC932
+VCHGR PQ906
1
1 2 DCIN_ISL88738 1U_0402_6.3V6K
17 8 VDDP_ISL88738 2 1 UG1_ISL88738 2 2UG2_ISL88738 PR917 AON7409_DFN8-5
DCIN VDDP
2 1 VDD_ISL88738 18 7 LG2_ISL88738
PL902 0.005_1206_1% 1
2
+PBATT
2.2UH_PCMB103T-2R2MS_13A_20%
VDD LGATE2
2
7 7 1 4 3 5
PC933 PR918 PR960 10_0402_5% 2 ACIN_ISL88738 19 6 LX2_ISL88738 LX1_ISL887383 6 1 2 6 3 LX2_ISL88738
1U_0402_6.3V6K ACIN PHASE2 5 5 2 3
100K_0402_1%
PR919 10_0402_5% 2@ OTGEN/CMIN 20 5 UG2_ISL88738 LG1_ISL887384 SW1_ISL88738 SW2_ISL88738 4 LG2_ISL88738
4
OTGEN/CMIN UGATE2 PC934 PR921
1
ACAV_IN1 1 PR920 2 0_0402_5% 21 4 BOOT2_ISL88738 2 1 2 1
10U_0805_25V6K
10U_0805_25V6K
<37,48> PBAT_CHARGER_SMBDAT SDA BOOT2
1
4.7_1206_5%
4.7_1206_5%
1
1 PR922 2 0_0402_5% 22 3
@EMC@ PR923
@EMC@ PR924
PQ909 0.22U_0603_25V7K 2.2_0603_5%
4700P_0402_25V7K
<37,48> PBAT_CHARGER_SMBCLK
8
D SCL VSYS
1
1
PC935
PC936
DMN65D8LW-7_SOT323-3 PR925
OTGPG/CMOUT
2
2 1 PR926 2 PROCHOT#_ISL8873823 2 CSOP_ISL88738
PC937
154K_0402_1% <7,37,54> H_PROCHOT# 0_0402_5%
PROCHOT# CSOP
AMON/BMON
<37> AC_DIS G <59> PROCHOT#_ISL88738
1SNUB_CHG1 2
1SNUB_CHG2 2
2
1
1 PR928 2 ACOK_ISL88738
24 1 CSON_ISL88738
BATGONE
S
3
1
0_0402_5% ACOK CSON PR929 @
BGATE_ISL88738
BGATE
CMOP
PROG
PSYS
VBAT
0_0402_5%
1 2
680P_0603_50V7K
680P_0603_50V7K
PR927 +PWR_SRC
2
1M_0402_1% @ PR930 PC938

25
26
27
118K_0402_1% 28
29
30
31
BGATE_ISL88738 32
@EMC@ PC940
@EMC@ PC941
100K_0402_1% 10P_0402_50V8J
PR931 1 2 1 2 1 2
2 PR932 1
<37,48> PBAT_PRES# 100K_0402_1%
2
3
1 2 @ PC939 0.1U_0402_25V6 3
VBAT1_ISL88738
PR933
100K_0402_1%
1
1 2
0_0402_5%
+3.3V_ALW
PR949
PR951
0_0402_5%
1 2
<59> CMOUT
2
COMP_ISL88738
1 2
0_0402_5%
1
PR934
560P_0402_50V7K
@ PC942 0.1U_0402_25V6
1
1
0_0402_5%
7.5K_0402_1%
0.1U_0402_25V6
1
1 2
PC943
PR936
DSC@ PR948
1
PC947
2
PC945 PR937
2
1
0_0402_5%
0_0402_5%
@ 1U_0402_25V6K 1_0402_1%
0.047U_0402_25V7K
2
1
PC944
PR947
PR935
PR938
1
1 2
2
UMA@ PR948 LM393_P

2
9.31K_0402_1% @ PR950
1 2 0_0402_5%
I_SYS <37,54> 1 2
@ PC946 0.1U_0402_25V6
PD905
I_BATT
I_ADP
PR939 BAT54CW_SOT323-3 PC949

0_0402_5% 0.1U_0402_10V7K
1 2 3 1 2
<29,59> AC1_DISC#
PU903
I_BATT <37> 1 TC7SH08FU_SSOP5
+PBATT
5
I_ADP <37> PR946
1 2 2 1 0_0402_5%
P
<37,48,59> ACAV_IN_NB B <37> ACAV_IN
2 1 PR941 4 1 2
ACAV_IN1 Y
Close to EC ADP_I pin 0_0402_5% 1 2 2
A
G
PR940 PR942
2
4
100_0402_1% 0_0402_5% 4
3
@ PC950
0.1U_0402_25V6
1
Title
PWR_CHARGER_ISL9237 (Colay)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom
LA-E141P 0.2

A B C D
4
3
2
1
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC841 PC819 PC1192 PC1162 PC1132 PC1103 PC1074 PC1041

+VCC_CORE
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

A
A
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
Back Side.
2 1 2 1 2 1 2 1 2 1 2 1 2 1
2
1
+
Primary Side.
Back Side.

330U_D2_2.5V_R6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
Primary Side.
2
1
+
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
VCC_SA Place on CPU

330U_D2_2.5V_R6M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC824 PC1197 PC1167 PC1137 PC1108 PC1079 PC1046

VCC_CORE Place on CPU
2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC825 PC1198 PC1168 PC1138 PC1109 PC1080 PC1047

2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC826 PC1199 PC1169 PC1139 PC1110 PC1081 PC1048

22U_0603 * 2 pcs + 220u_D2*1 pcs

2 1 2 1 2 1 2 1 2 1 2 1 2 1
22U_0603 * 8 pcs+330u_D2*2 pcs
PC827 PC800 PC1170 PC1140 PC1111 PC1082 PC1049

2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC828 PC801 PC1171 PC1141 PC1112 PC1083 PC1050

2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC829 PC802 PC1172 PC1142 PC1113 PC1084 PC1051

2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC830 PC803 PC1173 PC1143 PC1114 PC1085 PC1052
B
B
22U_0603 * 2 pcs + 10U_0402*7 pcs + 1U_0201*3 pcs

2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC831 PC804 PC1174 PC1144 PC1115 PC1086 PC1053

22U_0603 * 8 pcs + 10U_0402*28 pcs + 1U_0201*35 pcs
2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC832 PC805 PC1175 PC1145 PC1116 PC1087 PC1054

2 1 2 1 2 1 2 1 2 1
PC833 PC806 PC1176 PC1146 PC1055

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
PC1056
+VCC_SA
22U_0603_6.3V6M
2 1 2 1 2 1
PC844 PC834 PC815

1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
PC845 PC835 PC816

1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
PC846 PC836 PC817

1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
+
PC850 PC837 PC818
220U_D2_2.5VY_R9M 10U_0402_6.3V6M 22U_0603_6.3V6M
2 1
PC838
10U_0402_6.3V6M
2 1
C
C
PC839
10U_0402_6.3V6M
2 1
PC840
10U_0402_6.3V6M
Issued Date
Security Classification
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

+VCC_GT

2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
2016/01/01
Back Side.
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

Primary Side.

2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

VCC_GT Place on CPU
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
Compal Secret Data
D
D
Deciphered Date
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

2 1 2 1 2 1 2 1 2 1 2 1 2 1
22U_0603 * 12 pcs +470u_D2*2 pcs
PC1185 PC1155 PC1125 PC1096 PC1065 PC1031 PC1009

2 1 2 1 2 1 2 1 2 1 2 1 2 1
2
1
+

2017/01/01
470U_X_2VM_R6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1 2 1 2 1 2 1
2
1
+

470U_X_2VM_R6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC1188 PC1158 PC1128 PC1099 PC1068 PC1034 PC1012

2 1 2 1 2 1 2 1 2 1 2 1 2 1
22U_0603 * 8 pcs +10U_0402*35 pcs +1U_0201*68 pcs
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Date:
Title
PC1189 PC1159 PC1129 PC1100 PC1069 PC1035 PC1013

Custom

2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC1190 PC1160 PC1130 PC1101 PC1070 PC1036 PC1014

2 1 2 1 2 1 2 1 2 1 2 1 2 1
LA-E141P
Document Number
PC1191 PC1161 PC1131 PC1102 PC1071 PC1037 PC1015

2 1 2 1 2 1
PC1072 PC1038 PC1016

10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
Wednesday, June 29, 2016
2 1 2 1 2 1
E
E
PC1073 PC1039 PC1017

10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
2 1 2 1
Sheet
PC1040 PC1018
10U_0402_6.3V6M 22U_0603_6.3V6M
2 1
PROCESSOR DECOUPLING
58
PC1019
22U_0603_6.3V6M
of
2 1
PC1020
22U_0603_6.3V6M
61
Rev
0.2
4
3
2
1
5 4 3 2 1
PD1202
PDS5100H-13_POWERDI5-3~D
2
DCIN_AC_Detector 1
3
@ PC1201
0.01U_0402_25V7K~D
1 2
PD1801
S4 S5
+3.3V_VDD_DCIN
+DC_IN +3.3V_VDD_DCIN 3 +3.3V_VDD_DCIN PQ1213 +VBUS_DC_SS PQ1202
AON7409_DFN8-5 AON7409_DFN8-5
1 LM393_P 1 1
+AC_IN 2 2
+SDC_IN
AO3409_SOT23
1
D +3.3V_VDD_PIC 2 3 5 5 3 D
2200P 50V K X7R 0603
1
PR1251
1500P_0402_50V7K
BAT54CW_SOT323-3 PR1202
PQ1203
AO3409_SOT23
300K_0402_5%
1
PR1203 300K_0402_5%
499K_0402_1%
4
3
1
S
1.8M_0402_1%
PQ1215
PC1202
499K_0402_1%
2
1
3
G S
1 2 2
PR1205
PC1203
2
2PR1207
G
PR1206 2
2
1K_0402_1% D
2
1
+3.3V_VDD_PIC
LM393_P
240K_0402_1%
1
1
1
+3.3V_VDD_PIC PR1252
102K_0402_1%
2
PR1209
PR1201
100K_0402_5%
PR1208
100K_0402_5%
PR1253
PU1201A
62
1
100K_0402_5%
2
2
8
LM393DGKR_VSSOP8 PR1213 PR1214
1
3
PQ1214A
49.9K_0402_1% 100K_0402_5%
P
2
+
3
(>17.6V) 1 ACAV_IN_NB EN_PD_HV_1# 2 PR1212
2 O ACAV_IN_NB <37,48,57,59>
49.9K_0402_1%
3 2
2
-
G
PQ1204B
1
5 2 1
1200P_0402_50V7K
100P_0402_50V8J~D
220P_0402_50V8J~D
2
1
PQ1214B
23.2K_0402_1%
84.5K_0402_1%
<29,59> EN_PD_HV_1 <38,59> VBUS1_ECOK

1
5 PR1218
PQ1201B
PC1205
PC1206
4
1
6
PR1216 VBUS1_ECOK 2 1 5 0_0402_5%
PR1219
PR1217
PC1207
0_0402_5% PR1220
2
0_0402_5%
PQ1201A
2
4
1
1 2 2
2
6
1
PR1222
100K_0402_5%
PQ1204A
2
2 2 1 AC_DISC# <37,48,59>
PR1223
+3.3V_VDD_PIC
1
PC1204 0_0402_5%
0.1U_0402_10V7K
2 1
@ PR1254
PR1210 0_0402_5%
1M_0402_5% 1 2
2 1
PR1211 PU1200
5
0_0402_5% TC7SH08FU_SSOP5~D
<29,59> EN_PD_HV_1 1 2 1
P
B 4
C O C
(From TI GPIO1) 1 2 2
A
G
PR1215
3
0_0402_5%
PQ1205
PR1221 DMN65D8LW-7_SOT323-3 +3.3V_ALW +3.3V_ALW +3.3V_ALW
0_0402_5%
1 2 3 1
D
<38> DCIN1_EN
2
PR1231
@ PR1235 @ PR1233 100K_0402_5%
G
1 2
1
100K_0402_5% 100K_0402_5%
100K_0402_5%
PR1242
2
0_0402_5%
0_0402_5%
100K_0402_5%
1
1 2
PR1225
PR1226
<38,48> VBUS2_ECOK AC_DISC# <37,48,59> CMOUT <57>
PR1224
<38,59> VBUS1_ECOK 1 2
2
PR1257 1 2
1
0_0402_5% PR1245
PQ1211B 0_0402_5%
1500P_0402_50V7K
+3.3V_ALW DMN66D0LDW-7_SOT363-6
3
+3.3V_ALW D D D D
2 5 2 5
PQ1211A
PC1217
2
+3.3V_VDD_PIC G G G G
PQ1210B
2
PJP1202 +3.3V_ALW
2
1 2 PR1234 S S @ S PQ1210A S
4
1 2 +3.3V_ALW DMN66D0LDW-7_SOT363-6
100K_0402_5%
JUMP_43X118 PR1259
1
@ PR1260
EMI Part @ 100K_0402_5%
0_0402_5%
S3
100K_0402_5%
+TBTA_Vbus_1 PQ1206
2
PL1201 EMC@ 1 2 D +3.3V_ALW
AON7409_DFN8-5 <29,59> EN_PD_HV_1
5A_Z120_25M_0805_2P 2
PR1230
PROCHOT#_ISL88738 <57>
1 2 1 G
PQ1208A
3
2
2 D
PQ1208B
D
1
+TBTA_Vbus_1
+TBTA_VBUS 1 2 5 3 <29,57> AC1_DISC# 1 2 5 S
PL1202 G PR1232 2
PQ1216
PR1244
5A_Z120_25M_0805_2P 0_0402_5% 100K_0402_5% G
100P_0402_50V8J
100P_0402_50V8J
6
S D S
100K_0402_5%
EMC@
4
3
1
@ PR1261 2 PQ1207A
1000P_0402_50V7K
1500P_0402_50V7K
0.1U_0402_25V6
1
0_0402_5% G DMN66D0LDW-7_SOT363-6
PC1215
EMC@ PC1208
PC1209
PR1227
PC1216
499K_0402_1%
2
B 1 2 B
3
D
PC1210
PR1228
S
2
1
<37,48,57,59> ACAV_IN_NB 1 2 5
2
1
@EMC@
@EMC@
EMC@
PR1241 G PQ1207B
2
0_0402_5% DMN66D0LDW-7_SOT363-6
1
4
PR1255
150K_0402_1% 1 2
PC1209 can't over 1000P
2
@ PR1258
0_0402_5%
+TBTA_Vbus_1 +3.3V_VDD_PIC
1
S11 OVP
PD1205
SDMK0340L-7-F_SOD323-2 PR1229
1
1 2 +3.3V_VDD_PIC 49.9K_0402_1%
100K_0402_1%
PR1238
0_0402_5%
PR1237
1 2
2
2
PR1236
1
100K_0402_5%
150K_0402_1%
1
PR1240
LM393_P 100K_0402_1% PQ1209A
PR1239
2 DMN65D8LDW-7_SOT363-6
PU1201B
2
3
2
1
8
LM393DGKR_VSSOP8 PR1243
@
5 0_0402_5%
P
+ 7 1 2 5 PQ1209B
1200P_0402_50V7K
100P_0402_50V8J
6 O
0.01UF_0402_25V7K
-
G
1
100K_0402_1%
200K_0402_1%
100P_0402_50V8J
4
1
1
PC1211
PC1213
4
1
1
PR1246
PR1247
PC1212
PC1214
2
2
2
2
2
A A
OVP setting: 5.5V

PR1248 PT1 @
D
1
0_0402_5% PAD~D
2 1 2 LPS_PROTECT# (From EC)
PQ1212
G
1
S PR1250
3
PR1249 0_0402_5%

10K_0402_5% 1 2 EN_PD_HV_1 <29,59> Security Classification Compal Secret Data
ParkCity_TypeC_PD
2
Custom
LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
Version Change ListRequest

( P. I. R. List ) Issue Solution
Item Page# Title Date Owner Description Description Rev.
PWR_VCORE_ 2016 change solution version to fix PS4 funciton issue

1 65 ISL95855 05/23 POWER change solution from ISL95855 to ISL95855A
DVT
DVT
70
PWR_1Type-C 2016
PD Selector 06/14 POWER Modify PD schematic
2
PR1219 change from 22.6K to 23.2K(SD034232280)
PR1212, PR1213 change from 1M(SD034100480) to 634K(SD034634380)
DVT
2016
PWR_VCORE 06/14 Change location PU602 to PU610, PL603 to PL610,
3 66 _VCORE POWER location alignment PU603 to PU611, PL604 to PL611
DVT
Change location PU606 to PU612, PL607 to PL612,
PWR_VCORE 2016 PU605 to PU613, PL608 to PL613, PU607 to PU614,
4 67 _VGT,VSA 06/14 POWER location alignment PQ601 to PQ614, PL609 to PL614
DVT
5 PD903 change from SDMK0340L-7-F_SOD323-2~D
2016 Change footprint (SCS0340L010) to RB520SM-30T2R_EMD2-2
68 PWR_CHARGER 06/14 POWER
(SCS00006C00)
DVT
PWR_+DCIN PR12, PR11, PR1205, PR1207 and PR1228 change to 499K from 1M ohm
6 2016 PR16, PR18, PR1212, PR1213 and PR1229 change to 49.9K from 1M ohm
61,72 PWR_1Type-C 06/22 POWER Modify DC IN schematic PR1251 and PR1202 change to 300K from 100K ohm.
PD Selector DVT
PU1,PU903,PU1200
7 2016 change the main source part to SA007080180(S IC
06/22 POWER Trail run 2nd source SN74AHC1G08DCKR SC-70 5P AND) from SA007080120
(S IC TC7SH08FU SSOP 5P AND) DVT
D D
BOM change no need link the new footprint.
PQ1210,PQ1207,PQ1208,PQ1211,PQ1,PQ1201,PQ1204,PQ1209,PQ1214
2016 change the main source part to SB00000ZU00 (S TR
06/22 POWER Trail run 2nd source
8 DMN65D8LDW-7 2N SOT363-6) from SB00000DH00
(S TR DMN66D0LDW-7 2N SOT363-6) DVT
PQ5,PQ1215,PQ1203
2016 change the main source part to SB934090000
06/22 POWER
9 Trail run 2nd source (S TR AO3409 P-CHANNEL SOT-23) from SB00000IU10 DVT
(S TR SI2303CDS-T1-GE3 1P SOT23-3)
PL100
change the main source part to SH000016700
2016 (S COIL 1.5UH +-20% 9A 7X7X3 MOLDING) from DVT
06/22 POWER Trail run 2nd source
SH000008800 (S COIL 1.5UH +-20% 9A)
10 PL201
change the main source part to SH00000YE00
(S COIL 1UH +-20% 11A 7X7X3 MOLDING) from
SH00000PJ00 (S COIL 1UH +-20% 1R0MS 12A)
PL1301, PL1302(DSC only)
2nd source trial run the SH00000UF00
(S COIL 0.22UH +-20% ETQP4LR22AGM 24A)
PL1400(14H DSC only)
change the main source part to SH00000Z200
(S COIL 1UH +-20% 6.6A 5X5X3 MOLDING) from
SH00000PA00 (S COIL 1UH +-20% 1R0M-M7L 7A)
PC601 change from 33nF to 47nF

PC609 change from 680pFto 1000pF
PWR_VCORE_ 2016 PC624 change from 330pFto 680pF
11 65 ISL95855 06/22 POWER CPU transient
PC634 change from 680pF to 2200pF DVT
PR640 change from 110k to 115k
Pop PC403 、PC204 、PC797 、PC302 、PC112 4.7R(1206)

12 2016 Pop PC403 、PC204 、PC797 、PC302 、PC112 680pF(0603)
06/27 POWER Add RF request part Pop PC100 、PC405 、PC407 、PC115 、PC116 、PC301 、PC303 、PC103 100pF(0402) DVT
C C
B B
A A
Security Classification Com pal Secret Data Compal Electronics, Inc.
T itle
PWR P.I.R
Custom LA-E141P 0.2

5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request Issue Solution
Item Page# Title Date Owner Rev.
Description Description
D D
1 11 HW 2016/5/27 COMPAL S0ix(modern standy) support for VCCPLL_OC Pop RZ120 and Depop UZ34 0.2(X01)
Add net name VCCSTG_EN(UZ19.4) and connect to RZ120.1
2 37 HW 2016/5/27 COMPAL Reserve PORT80_DET# PD resistance Reserve RE513 100k (SD028100380) to GND 0.2(X01)
3 35 HW 2016/6/1 COMPAL Intel schematics reivew modify item CZ28,CZ29 change from 0.047uF to 0.01uF 0.2(X01)
CZ27 change from 0.1uF(@)_0201 to 10uF_0603
4 39 HW 2016/6/1 COMPAL TPM change to NUVOTON Change TPM from Atmel to NUVOTON. 0.2(X01)
Intel reviwe result Add RZ128 0 ohm connect WWAN_COEX3 and WLAN_COEX3
5 35 HW 2016/6/1 COMPAL (WWAN Coex feature support) Add RZ129 0 ohm connect WWAN_COEX2 and WLAN_COEX2 0.2(X01)
Add RZ130 0 ohm connect WWAN_COEX1 and WLAN_COEX1
6 35 HW 2016/6/7 COMPAL Debug card reserve Add RZ131, RZ132 for PORT80_DET# and HOST_DEBUG_TX 0.2(X01)
7 37 HW 2016/6/7 COMPAL For MEC5105K-D1-TN setting 1. Change UE1 to SA00009GL00 0.2(X01)

2. POP RE360,RE362
C 3. De-POP RE361 C
8 35,32 HW 2016/6/16 COMPAL For EMC request De-pop RZ131, RZ132. CL22 change to 10pf , POP CA7,CZ1 (100P),CH268 0.2(X01)
modify from 22p to 47p and POP,Change LV1 to SM01000NY00
9 41 HW 2016/6/16 COMPAL BITS284924-HDD is still working after press POP RN5 0.2(X01)
power button into S5 during POST.
10 39 ME 2016/6/17 COMPAL Connector change 1. JKBTP1 change to CVILU_CF5020FD0RK-05-NH 0.2(X01)
2. JUSH1 change to CVILU_CF5026FD0RK-05-NH
3. JIR1 change to ACES_50208-0060N-P01
11 36 HW 2016/6/20 COMPAL Vender suggest RA7,RA8 change to 16.2ohm 0.2(X01)
12 37 HW 2016/6/22 COMPAL The posibility of GPIO map update Add RE514,RE515 for RTCRST_ON 0.2(X01)
13 41 HW 2016/6/22 COMPAL BITS283552 - [BR_CSLP] FFS AP no function FFS VDD_IO change to +3.3V_RUN 0.2(X01)
when execute FF generator or shake SU
B B
A A
Title
EE P.I.R (1/6)

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Dell - Latitude - 5480 - CDP70 - LA-E141P R0.2 2016-07-01 PDF

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Dell - Latitude - 5480 - CDP70 - LA-E141P R0.2 2016-07-01 PDF

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5 4 3 2 1

REV : 0.2 (X01) C

XDP@ : XDP Component

DAB0001R000 PCB 1SC LA-E141P REV0 MB UMA 1

Layout Dell logo

Date: Friday, July 01, 2016 Sheet 1 of 61

Card reader Intel Jacksonville

SD4.0 Transformer USB2.0[8]

USB3.0-2 SSIC-1 JNGFF2-->M2 3042(LTE) 2 JUSB1-->Right

USB3.0-4 JUSB2-->Left 4 Type C

USB3.0-6 NA 6 JNGFF1--> M.2 3030(BT)

USB3.0-10 PCIE-4 LOM 10 JUSH1-->USH

+3.3V_ALW USH H BIO

Date: Wednesday, June 29, 2016 Sheet 3 of 61

SIO_SLP_SUS# CPU PWR

(UZ4) +3.3V_WWAN EM5209

Date: Wednesday, June 29, 2016 Sheet 4 of 61

Date: Wednesday, June 29, 2016 Sheet 5 of 61

Trace width=5 mils

Date: Wednesday, June 29, 2016 Sheet 6 of 61

CFG5 30 CFG13 @ RC136 51_0402_5%

XDP@ RC124 1 2 1K_0402_5% H_VCCST_PWRGD_XDP 40 PCH_XDP_CLK_DP

CFG0 XDP@ RC126 1 2 1K_0402_5% 46 1 2 ITP_PMODE_CPU <20>

CPU_VIDALERT# BH31 BT19 CFG15

<54> VR_SVID_CLK BH32

VCCST_PWRGD 1 2 VCCST_PWRGD_CPU H13 BT30

H_PM_SYNC BM34 BL32 CPU_XDP_TDI

@RF@ CC325 33P_0402_50V8J

Date: Wednesday, June 29, 2016 Sheet 7 of 61

UC1A SKYLAKE_HALO UC1B SKYLAKE_HALO

Trace width=12-15 mils

Date: Wednesday, June 29, 2016 Sheet 8 of 61

Date: Wednesday, June 29, 2016 Sheet 9 of 61

+VCC_EDRAM UC1J SKYLAKE_HALO

Date: Wednesday, June 29, 2016 Sheet 10 of 61

+1.0V_VCCSTG source +1.0V_VCCSTG

+5V_ALW 7 6 +1.0V_VCCSTG_C 1 2 PJP1

<20,21,39,52> SIO_SLP_S0# IN1 VCCSTG_EN

Date: Wednesday, June 29, 2016 Sheet 11 of 61

PLACE CAP BACKSIDE

2 2 AN33 VCC VCC

AN35 VCC VCC

AR32 VCC VCC

AR35 AH37 VCC VCC

AU29 VSS_SENSE VSS_SENSE <54>

AU36 VCCGT SKL-H_BGA1440

Date: Wednesday, June 29, 2016 Sheet 12 of 61

Date: Wednesday, June 29, 2016 Sheet 13 of 61

23 DQ3 VSS11 24 DDR_A_D12

199 200 DDR_A_DQS3

+3.3V_RUN_DIMM1 209 DQ42 DQ43 210

DDR_A_DQS#6 219 220

DDR_A_D51 229 VSS82 DQ50 230

Byte[1] DQ[15:8] DQS/DQS#[1]

A Byte[2] DQ[23:16] DQS/DQS#[2] 261 VPP2

* Byte[3] DQ[31:24] DQS/DQS#[3]

Byte[4] DQ[39:32] DQS/DQS#[4] CONN@

* Byte[5] DQ[47:40] DQS/DQS#[5]

Date: Wednesday, June 29, 2016 Sheet 14 of 61

D 23 DQ3 VSS11 24 DDR_B_D8 D

<8> DDR_B_CS#0 149 150 DDR_B_BA0 <8>

DDR_B_D26 203 204 DDR_B_D31

+3.3V_RUN_DIMM2 213 DQ52 DQ53 214