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Stm32h747ag 1851233 PDF
Stm32h747ag 1851233 PDF
Features FBGA
Dual core
• 32-bit Arm® Cortex®-M7 core with double- LQFP176 UFBGA169 WLCSP156
precision FPU and L1 cache: 16 Kbytes of data (24x24 mm) (7 × 7 mm) (4.96x4.64 mm)
LQFP208 TFBGA240+25
and 16 Kbytes of instruction cache; frequency (28x28 mm) (14x14 mm)
up to 480 MHz, MPU, 1027 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions Reset and power management
® ® • 3 separate power domains which can be
• 32-bit Arm 32-bit Cortex -M4 core with FPU,
Adaptive real-time accelerator (ART independently clock-gated or switched off:
Accelerator™) for internal Flash memory and – D1: high-performance capabilities
external memories, frequency up to 240 MHz, – D2: communication peripherals and timers
MPU, 300 DMIPS/1.25 DMIPS /MHz
– D3: reset/clock control/power management
(Dhrystone 2.1), and DSP instructions
• 1.62 to 3.6 V application supply and I/Os
Memories • POR, PDR, PVD and BOR
• Up to 2 Mbytes of Flash memory with read- • Dedicated USB power embedding a 3.3 V
while-write support internal regulator to supply the internal PHYs
• 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. • Embedded regulator (LDO) to supply the digital
64 Kbytes of ITCM RAM + 128 Kbytes of circuitry
DTCM RAM for time critical routines), • High power-efficiency SMPS step-down
864 Kbytes of user SRAM, and 4 Kbytes of converter regulator to directly supply VCORE
SRAM in Backup domain
and/or external circuitry
• Dual mode Quad-SPI memory interface
• Voltage scaling in Run and Stop mode (6
running up to 133 MHz
configurable ranges)
• Flexible external memory controller with up to
• Backup regulator (~0.9 V)
32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND Flash • Voltage reference for analog peripheral/VREF+
memory clocked up to 125 MHz in • 1.2 to 3.6 V VBAT supply
Synchronous mode
• Low-power modes: Sleep, Stop, Standby and
• CRC calculation unit VBAT supporting battery charging
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Dual Arm® Cortex® cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.2 Arm® Cortex®-M4 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.3 ART™ accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5.3 Voltage regulator (SMPS step-down converter and LDO) . . . . . . . . . . . 18
3.5.4 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 24
3.13 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 24
3.14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 24
3.15 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.16 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 25
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.3 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.4 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 105
6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . 106
6.3.6 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.12 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.13 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.14 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.15 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.3.16 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 144
6.3.17 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.18 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
List of tables
running from Flash memory, only Arm Cortex-M7 running, cache ON,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 38. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M7 running, cache OFF,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 39. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 40. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M4 running, ART accelerator ON,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 41. Typical and maximum current consumption in Run mode, code with data processing
running from Flash bank 2, only Arm Cortex-M4 running, ART accelerator ON,
SMPS regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 42. Typical and maximum current consumption in Stop, LDO regulator ON . . . . . . . . . . . . . 115
Table 43. Typical and maximum current consumption in Stop, SMPS regulator . . . . . . . . . . . . . . . 116
Table 44. Typical and maximum current consumption in Sleep mode, LDO regulator . . . . . . . . . . 117
Table 45. Typical and maximum current consumption in Sleep mode, SMPS regulator . . . . . . . . . 117
Table 46. Typical and maximum current consumption in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 47. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 118
Table 48. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 49. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 50. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 51. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 52. 4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 53. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 54. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 55. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 56. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 57. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 58. PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 59. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 60. MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 61. MIPI D-PHY AC characteristics LP mode and HS/LP
transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 62. DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 63. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 64. Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 141
Table 65. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 66. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 67. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 68. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 69. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 70. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 71. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 72. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 148
Table 73. Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 149
Table 74. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 75. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 76. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 77. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 155
Table 78. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 155
Table 79. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 157
List of figures
1 Introduction
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
2 Description
Refer to Table 1: STM32H747xI/G features and peripheral counts for the list of peripherals
available on each part number.
STM32H747xI/G devices operate in the –40 to +85 °C temperature range from a 1.62 to
3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power
supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to
VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power
voltage detector enabled.
Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages to
allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H747xI/G devices are offered in 5 packages ranging from 156 pins to 240 pins/balls.
The set of included peripherals changes with the device chosen.
These features make STM32H747xI/G microcontrollers suitable for a wide range of
applications:
• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances
• Mobile applications, Internet of Things
• Wearable devices: smart watches.
Figure 1 shows the device block diagram.
STM32H747AG
STM32H747BG
STM32H747XG
STM32H747IG
STM32H747AI
STM32H747BI
STM32H747XI
STM32H747ZI
STM32H747II
Peripherals
STM32H747AG
STM32H747BG
STM32H747XG
STM32H747IG
STM32H747AI
STM32H747BI
STM32H747XI
STM32H747ZI
STM32H747II
Peripherals
16-bit ADCs 3
Number of Direct channels 2 2 4 2 2 2 4
Number of Fast channels 9 9 9 7 9 9 9
Number of Slow channels 17 21 23 14 17 21 23
12-bit DAC Yes
Number of channels 2
Comparators 2
Operational amplifiers 2
DFSDM Yes
Maximum CPU frequency 480 MHz
STM32H747AG
STM32H747BG
STM32H747XG
STM32H747IG
STM32H747AI
STM32H747BI
STM32H747XI
STM32H747ZI
STM32H747II
Peripherals
AHB1 (200MHz)
PHY PHY
ETHER
I- D- D- ARM DMA1 DMA2 SDMMC2 OTG_HS OTG_FS
TCM TCM TCM MAC
64KB 64KB
Cortex
4KB
M4
8 Stream 8 Stream DMA DMA/ DMA/
I- D- S- FIFO
AHBP AXI/AHB12 (200MHz) FIFOs FIFOs FIFO FIFO
JTDO/SWD, JTDO Bus Bus Bus
JTRST, JTDI, Arm Up to 1 MB
JTCK/SWCLK JTAG/SW Cortex FLASH
AXIM 32-bit AHB BUS-MATRIX
M7 Up to 1 MB
TRACECK ETM FLASH
AHB1 (200MHz)
DMA
TRACED[3:0]
I-Cache D-Cache 512 KB AXI Mux1 SRAM1 SRAM2 SRAM3
16KB 16KB 128 KB 128 KB 32 KB
SRAM
AHB4 (200MHz)
AHB2 (200MHz)
AHBS
RNG ADC1
16 Streams 64-bit AXI BUS-MATRIX FMC Up to 20 analog inputs
MDMA FIFO common to ADC1 & 2
FMC_signals ADC2
LCD_R[7:0], LCD_G[7:0], CHROM-ART AHB/APB
FIFO Quad-SPI
LCD_B[7:0], LCD_HSYNC, (DMA2D)
AHB ART(200MHz)
LCD_VSYNC, LCD_DE,
CLK, CS,D[7:0] TIM2 4 channels, ETR as AF
LCD_CLK 32b
LCD-TFT FIFO
DSI_D0_P, DSI_D0_N D AXI/AHB34 (200MHz)
TIM6 16b TIM3
PHY
SAI3
3
SD, SCK, FS, MCLK as AF UART8 RX, TX as AF
Digital filter
DMA
1 compl. chan.(TIM17_CH1N),
AHB4
I/F
MOSI, MISO, SCK, NSS/
SPI/I2S1 IWDG2 FDCAN2 TX, RX
SDO, SDI, CK, WS, MCK, as AF
AHB4 (200MHz)
smcard CRS
RX, TX, SCK, CTS, RTS as AF
irDA USART6
smcard 4 KB BKP SPDIFRX1
64 KB SRAM IN[1:4] as AF
RX, TX, SCK, CTS, RTS as AF
irDA USART1 RAM
4 compl. chan. (TIM1_CH1[1:4]N), TIM1/PWM HDMI-CEC CEC as AF
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF 16b
4 compl. chan.(TIM8_CH1[1:4]N), HSEM DAC1&2 DAC1_OUT, DAC2_OUT as AF
4 chan. (TIM8_CH1[1:4], ETR, BKIN as TIM8/PWM 16b LPTIM1_IN1, LPTIM1_IN2,
AF CRC LPTIM1 16b LPTIM1_OUT as AF
WWDG2
OPAMPx_VINM
AHB4 (200MHz)
VDDREF_ADC VDD12
RCC Voltage regulator VDDUSB33 = 3.0 to 3.6V
PWRCTRL
PA..J[15:0] GPIO PORTA.. J Reset & 3.3 to 1.2V VDDDSI = 1.8 to 3.6V
control VSS
SMPS step-down VCAP
PK[7:0] GPIO PORTK AHB/APB VDDMMC33 = 1.8 to 3.6 V
converter VDDSMPS, VSSSMPS
@VSW VLXSMPS, VFBSMPS
SD, SCK, FS, MCLK,
PDM_DI/CK[4:1] as AF
SAI4 OSC32_IN
XTAL 32 kHz
COMPx_INP, COMPx_INM, OSC32_OUT
LS
COMP1&2
COMPx_OUT as AF RTC RTC_TS
@VDD
LPTIM5_OUT as AF LPTIM5 Backup registers RTC_TAMP[1:3]
VREF AWU RTC_OUT
APB4 100 MHz (max)
LS
MSv43739V12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
A VSS PI6 PI5 PI4 PB5 VDDLDO VCAP PK5 PG10 PG9 PD5 PD4 PC10 PA15 PI1 PI0 VSS
B VBAT VSS PI7 PE1 PB6 VSS PB4 PK4 PG11 PJ15 PD6 PD3 PC11 PA14 PI2 PH15 PH14
PC15- PC14-
C OSC32_ OSC32_ PE2 PE0 PB7 PB3 PK6 PK3 PG12 VSS PD7 PC12 VSS PI3 PA13 VSS VDDLDO
OUT IN
D PE5 PE4 PE3 PB9 PB8 PG15 PK7 PG14 PG13 PJ14 PJ12 PD2 PD0 PA10 PA9 PH13 VCAP
PDR
E PI9 PC13 PI8 PE6 VDD BOOT0 VDD PJ13 VDD PD1 PC8 PC9 PA8 PA12 PA11
_ON
VDD33
F PI10 PI11 VDD PC7 PC6 PG8 PG7
USB
VDD5
G PF2 PF1 PF0 VDD VSS VSS VSS VSS VSS VDD PG5 PG6 VSS
USB
H PI12 PI13 PI14 PF3 VDD VSS VSS VSS VSS VSS VDD PG4 PG3 PG2 PK2
PH1- PH0-
VSS
J OSC_ OSC_ VSS PF5 PF4 VSS VSS VSS VSS VSS VDD PK0 PK1 VSSDSI
DSI
OUT IN
K NRST PF6 PF7 PF8 VDD VSS VSS VSS VSS VSS VDD PJ11
L VDDA PC0 PF10 PF9 VDD VSS VSS VSS VSS VSS VDD PJ10
N VREF- PH2 PA2 PA1 PA0 PJ0 VDD VDD PE10 VDD VDD VDD PJ8 PJ7 PJ6 VSS
P VSSA PH3 PH4 PH5 PI15 PJ1 PF13 PF14 PE9 PE11 PB10 PB11 PH10 PH11 PD15 PD14
R PC2_C PC3_C PA6 VSS PA7 PB2 PF12 VSS PF15 PE12 PE15 PJ5 PH9 PH12 PD11 PD12 PD13
T PA0_C PA1_C PA5 PC4 PB1 PJ2 PF11 PG0 PE8 PE13 PH6 VSS PH8 PB12 PB15 PD10 PD9
U VSS PA3 PA4 PC5 PB0 PJ3 PJ4 PG1 PE7 PE14 VCAP VDDLDO PH7 PB13 PB14 PD8 VSS
STM32H7x7 STM32H7x3
VLX
PI9 PI9 DSI_D1N
VSSDSI DSI_D1P NC PI9 VSS PI9
NC NC
SMPS
VDD VSS
VSSDSI DSI_CKP DSI_CKN NC NC VSS NC NC
SMPS SMPS
VFB
PF2 VSSDSI
PF2 DSI_D0P DSI_D0N PF2 NC VSS
PF2 NC NC
SMPS
VDDCAP
PJ6 VSS PJ6 VSS NC
DSI
MSv48802V2
1. The balls highlighted in gray correspond to different signals on STM32H747xI/G and STM32H7x3 devices.
3 Functional overview
3.3 Memories
Non-cacheable Cacheable
access path access path
AHB switch
control
Detect of instruction
write to cacheable page fetch
cache
refill
Master interface
AXI AHB FMC
Slave interface
MSv39757V2
The bootloader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller System memory Boot mode application note (AN2606) for details.
3.6
VDDX(1)
VDD
VBOR0
0.3
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1
1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB and VDDDSI.
2. VDD and VDDSMPS must be wired together into order to follow the same voltage sequence.
The SMPS step-down converter can be used for the following purposes:
• Direct supply of the VCORE domain
– the SMPS step-down converter operating modes follow the device system
operating modes (Run, Stop, Standby).
– the SMPS step-down converter output voltage are set according to the selected
VOS and SVOS bits (voltage scaling)
• Delivery of an intermediate voltage level to supply the internal voltage regulator (LDO)
– SMPS step-down converter operating modes
When the SDEXTHP bit is equal to 0 in the PWR_CR3 register, the SMPS step-
down converter follows the device system operating modes (Run, Stop and
Standby).
When the SDEXTHP bit is equal to 1 in PWR_CR3, the SMPS step-down
converter is forced to High-performance mode and does not follow the device
system operating modes (Run, Stop and Standby).
– The SMPS step-down converter output equals 1.8 V or 2.5 V according to the
selected SD level
• Delivery of an external supply
– The SMPS step-down converter is forced to High-performance mode (provided
SDEXTHP bit is equal to 1 in PWR_CR3)
– The SMPS step-down converter output equals 1.8 V or 2.5 V according to the
selected SD level
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode. For instance
D1 or D2 domain enters DStop/DStandby mode when the CPU of the domain is in CStop
mode AND the other CPU has no peripheral allocated in that domain, or if it is in CStop
mode too. D3 domain can enter DStop/DStandby mode if both core subsystems do not have
active peripherals in D3 domain, and D3 is not forced in Run mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.
The clock system can be re-initialize by a master CPU (either the Cortex®-M4 or -M7) after
exiting Stop mode while the slave CPU is held in low-power mode. Once the master CPU
has re-initialized the system, the slave CPU can receive a wakeup interrupt and proceed
with the interrupt service routine.
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
Functional overview
22/242 AHBS
7
CPU ITCM
Cortex-M7 64 Kbyte CPU
Cortex-M4
I$ D$ DTCM Ethernet SDMMC2 USBHS1
16KB 16KB 128 Kbyte DMA1 DMA2 USBHS2
MAC
AXIM
AHBP
DMA1_PERIPH
DMA2_PERIPH
DMA1_MEM
DMA2_MEM
D-bus
S-bus
I-bus
ART SDMMC1 MDMA DMA2D LTDC
D1-to-D2 AHB
SRAM1 128
APB3 Kbyte
4 SRAM2 128
AHB3 Kbyte
SRAM3
32 Kbyte
Flash A
Up to 1 Mbyte 5
AHB1
DS12930 Rev 1
Flash B
Up to 1 Mbyte
AHB2
AXI SRAM
512 Kbyte
APB1
QSPI
APB2
FMC
1
64-bit AXI bus matrix
D1 domain
2
32-bit AHB bus matrix
D2 domain
D2-to-D1 AHB
D2-to-D3 AHB
BDMA
D1-to-D3 AHB
STM32H747xI/G
Legend 3 6
AHB4 APB4
TCM AHB
32-bit bus AXI APB SRAM4
64-bit bus Master interface 64 Kbyte
In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer.
The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
• short circuit detector to detect saturated analog input values (bottom and top range):
– up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
– monitoring continuously each input serial channel
• break signal generation on analog watchdog event or on short circuit detector event
• extremes detector:
– storage of minimum and maximum values of final conversion data
– refreshed by software
• DMA capability to read the final conversion data
• interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
• “regular” or “injected” conversions:
– “regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
– “injected” conversions for precise timing and with high conversion priority
Number of filters 4
Number of input
8
transceivers/channels
Internal ADC parallel input X
Number of external triggers 16
Regular channel information in
X
identification register
• 3D transmission support
• Configurable selection of system interfaces
– AMBA APB for control and optional support for Generic and DCS commands
– Video mode interface through LTDC
– Adapted Command mode interface through LTDC
– Independently programmable Virtual Channel ID in Video, Adapted Command or
APB Slave mode
• Video mode interfaces features
– LTDC interface color coding mappings into 24-bit interface:
16-bit RGB, configurations 1, 2, and 3
18-bit RGB, configurations 1 and 2
24-bit RGB
– Programmable polarity of all LTDC interface signals
– Extended resolutions beyond the DPI standard maximum resolution of 800x480
pixels; the maximum resolution is limited by the available DSI physical link
bandwidth:
Number of lanes: 2
Maximum speed per lane: 1 Gbps
• Adapted interface features
– Support for sending large amounts of data through the memory_write_start (WMS)
and memory_write_continue (WMC) DCS commands
– LTDC interface color coding mappings into 24-bit interface:
16-bit RGB, configurations 1, 2, and 3
18-bit RGB, configurations 1 and 2
24-bit RGB
• Video mode pattern generator
– Vertical and horizontal color bar generation without LTDC stimuli
– BER pattern without LTDC stimuli
/1 /2 /4
High-
(x2 x4 x8
resolution HRTIM1 16-bit Up Yes 10 Yes 480 480
x16 x32,
timer
with DLL)
Any
Up, integer
Advanced TIM1,
16-bit Down, between 1 Yes 4 Yes 120 240
-control TIM8
Up/down and
65536
Any
Up, integer
TIM2,
32-bit Down, between 1 Yes 4 No 120 240
TIM5
Up/down and
65536
Any
Up, integer
TIM3,
16-bit Down, between 1 Yes 4 No 120 240
TIM4
Up/down and
65536
Any
integer
TIM12 16-bit Up between 1 No 2 No 120 240
and
General 65536
purpose Any
integer
TIM13,
16-bit Up between 1 No 1 No 120 240
TIM14
and
65536
Any
integer
TIM15 16-bit Up between 1 Yes 2 1 120 240
and
65536
Any
integer
TIM16,
16-bit Up between 1 Yes 1 1 120 240
TIM17
and
65536
Any
integer
TIM6,
Basic 16-bit Up between 1 Yes 0 No 120 240
TIM7
and
65536
LPTIM1,
Low- LPTIM2, 1, 2, 4, 8,
power LPTIM3, 16-bit Up 16, 32, 64, No 0 No 120 240
timer LPTIM4, 128
LPTIM5
1. The maximum timer clock is up to 480 MHz depending on TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.
All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can
be done on:
• Start bit detection
• Any received data frame
• A specific programmed data frame
• Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
• Start bit detection
• Any received data frame
• A specific programmed data frame
• Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
A 4-Kbyte embedded trace FIFO (ETF) allows recording data and sending them to any com
port. In Trace mode, the trace is transferred by DMA to system RAM or to a high-speed
interface (such as SPI or USB). It can even be monitored by a software running on one of
the cores. Unlike hardware FIFO mode, this mode is invasive since it uses system
resources which are shared by the processors.
4 Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
5 Pin descriptions
A DNC(1) VDDLDO VCAP PB8 VDD PB4 PG15 VDD PD4 PD0 PA15 VDDLDO VSS
B VBAT PE4 VDD PE0 VSS PB5 PB3 VSS PD3 PC12 VDD VCAP PA12
PC14- PC15-
C PE5 VSS PB9 PB7 PB6 PD6 PC11 VSS PA13 PA10 PA11
OSC32_IN OSC32_OUT
VSS
D VDD VSS PE3 PE2 PE1 BOOT0 PD7 PC10 PA9 PA8 PC9 PC8
SMPS
VDD VLX VFB VDD50 VDD33
E PF0 PC13 PE6 PDR_ON PD2 PA14 PC7 VDD
SMPS SMPS SMPS USB USB
F PF3 PF2 PF4 PF5 PF1 PF11 PD5 PD1 PC6 PG4 VSS PG8 PG5
DSI_ DSI_
G VDD VSS PC0 PC1 PA6 PF12 PE10 PE11 PD8 PG3 PG2
D1P D1N
PH1- PH0- DSI_ DSI_
H OSC_OUT NRST PA5 PB1 PF13 PE7 PB10 PB13 PD14 VSSDSI
OSC_IN CKP CKN
DSI_ DSI_
J VSSA VREF+ VDDA PA3 PA7 PF15 PE8 PE12 PB12 PD11 PD15
D0P D0N
VCAP
K PC2_C PC3_C PA2 PA4 PB0 PF14 PE9 PE13 PB11 PD9 PD13 VDD
DSI
L PA0 PA1 VSS PC5 VSS PG0 VSS PE15 VSS VDDLDO PD10 PD12 VSS
M VSS VDD PC4 PB2 VDD PG1 VDD PE14 VCAP VDD PB14 PB15 VSS
MSv43741V5
A VSS PE2 VDDLDO VCAP PB5 PB3 VSS PD7 VDD PD3 PA14 VSS PA10
PDR_
B VBAT VDD VSS BOOT0 PB4 VDD PD6 VSS PA15 PA13 VDD VDDLDO
ON
PC14_
C OSC32_ PE6 PE3 PE1 PB7 PG15 PG9 PD5 PD1 PD0 PC10 VSS VCAP
IN
PC15_
D VSS OSC32_ PE4 PE0 PB8 PB9 PG10 PD4 PC12 PA8 PA9 PA11 PA12
OUT
VLX
E VDD PC13 PE5 PB6 PG14 PG11 PD2 PC11 PC7 PC9 VDD VSS
SMPS
G PF4 PF3 PF5 PF6 PF7 PF8 PG12 PG3 PG5 PG4 PG6 VSSDSI VSSDSI
VSSA_ VCAP
L VDDA PC4 PB2 PG0 PE10 PE8 VDD PB12 VDD VSS
VREF- PA1 DSI
VDD
M VREF+ VDD PA2 PA6 PF13 VSS PF15 PE14 VSS PB13 PB15 PD9
DSI
N VSS PA3 PA4 PB0 PF14 PE9 PE11 PB11 VCAP VDDLDO PB14 PD8 PD10
MSv43740V4
VDDLDO
PDR_ON
VDDLDO
BOOT0
VCAP
VCAP
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
PA15
PA14
VDD
VDD
VDD
VDD
VSS
VSS
PG9
VSS
VSS
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
158
159
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PE2 1 132 PA13
PE3 2 131 PA12
PE4 3 130 PA11
PE5 4 129 PA10
PE6 5 128 PA9
VSS 6 127 PA8
VDD 7 126 VDD
VBAT 8 125 PC9
PC13 9 124 PC8
PC14-OSC32_IN 10 123 PC7
PC15-OSC32_OUT 11 122 PC6
VSS 12 121 VDD33USB
VDD 13 120 VDD50USB
VSSSMPS 14 119 VSS
VLXSMPS 15 118 PG8
VDDSMPS 16 117 PG7
VFBSMPs 17 116 PG6
PF0 18 115 PG5
PF1 19 114 PG4
PF2 20 113 VDD
PF3
PF4
21
22
176-pins 112
111
VSS
PG3
PF5 23 110 PG2
VSS 24 109 VSSDSI
VDD 25 108 VDD12DSI
PF6 26 107 DSI_CKN
PF7 27 106 DSI_CKP
PF8 28 105 VSSDSI
PF9 29 104 DSI_D0N
PF10 30 103 DSI_D0P
PH0-OSC_IN 31 102 VDD12DSI
PH1-OSC_OUT 32 101 VCAPDSI
NRST 33 100 VSS
PC0 34 99 VDD
PC1 35 98 PD15
PC2_C 36 97 PD14
PC3_C 37 96 PD13
VSSA 38 95 PD12
VREF+ 39 94 PD11
VDDA 40 93 VSS
PA0 41 92 VDD
PA1 42 91 PD10
PA2 43 90 PD9
VDD 44 89 PD8
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
PF12
PF13
PF14
PF15
PG0
PG1
PE10
PE12
PE13
PE14
PE15
PB10
PB12
PB13
PB14
PB15
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PF11
PE11
PB11
PA3
PA4
PA5
PA6
PA7
VDDLDO
VCAP
MSv43745V4
VDDLDO
PDR_ON
BOOT0
VCAP
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PH15
PH14
PG11
PC11
PA15
PA14
VDD
VDD
VDD
VDD
VSS
VSS
VSS
PG9
VSS
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
PE2 1 156 PH13
PE3 2 155 VDD
PE4 3 154 VDDLDO
PE5 4 153 VSS
PE6 5 152 VCAP
VSS 6 151 PA13
VDD 7 150 PA12
VBAT 8 149 PA11
PI8 9 148 PA10
PC13 10 147 PA9
PC14-OSC32_IN 11 146 PA8
PC15-OSC32_OUT 12 145 PC9
PI9 13 144 PC8
PI10 14 143 PC7
PI11 15 142 PC6
VSS 16 141 VDD33USB
VDD 17 140 VDD50USB
VSSSMPS 18 139 VSS
VLXSMPS 19 138 PG8
VDDSMPS 20 137 PG7
VFBSMPS 21 136 PG6
PF0 22 135 PG5
PF1 23 134 PG4
PF2 24 133 VDD
PF3 25 208-pins 132 VSS
PF4 26 131 PG3
PF5 27 130 PG2
VSS 28 129 VSSDSI
VDD 29 128 DSI_D1N
PF6 30 127 DSI_D1P
PF7 31 126 VDD12DSI
PF8 32 125 DSI_CKN
PF9 33 124 DSI_CKP
PF10 34 123 VSSDSI
PH0-OSC_IN 35 122 DSI_D0N
PH1-OSC_OUT 36 121 DSI_D0P
NRST 37 120 VDD12DSI
PC0 38 119 VCAPDSI
PC1 39 118 VSS
PC2_C 40 117 VDD
PC3_C 41 116 PD15
VSSA 42 115 PD14
VREF+ 43 114 VDD
VDDA 44 113 VSS
PA0 45 112 PD13
PA1 46 111 PD12
PA2 47 110 PD11
PH2 48 109 VSS
VDD 49 108 VDD
VSS 50 107 PD10
PH3 51 106 PD9
100
101
102
103
104
PH4 52 PD8
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
PH5
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PI15
PF12
PF13
PF14
PF15
PG0
VSS
VDD
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VCAP
VSS
VDDLDO
PH6
PH7
PH8
PH9
VSS
PH10
PH12
VDD
PB12
PB13
PB14
PB15
PA3
PA4
PA5
PA6
PA7
PF11
PE11
PB11
PH11
MSv43749V4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
VDD VCAP
A VSS PI6 PI5 PI4 PB5 PK5 PG10 PG9 PD5 PD4 PC10 PA15 PI1 PI0 VSS
LDO
B VBAT VSS PI7 PE1 PB6 VSS PB4 PK4 PG11 PJ15 PD6 PD3 PC11 PA14 PI2 PH15 PH14
PC15- PC14-
VDD
C OSC32_ OSC32 PE2 PE0 PB7 PB3 PK6 PK3 PG12 VSS PD7 PC12 VSS PI3 PA13 VSS
LDO
OUT _IN
D PE5 PE4 PE3 PB9 PB8 PG15 PK7 PG14 PG13 PJ14 PJ12 PD2 PD0 PA10 PA9 PH13 VCAP
VLX PDR
E PI9 PC13 PI8 PE6 VDD BOOT0 VDD PJ13 VDD PD1 PC8 PC9 PA8 PA12 PA11
SMPS _ON
VFB VDD50
G PF2 PF1 PF0 VDD VSS VSS VSS VSS VSS VDD PG5 PG6 VSS
SMPS USB
H PI12 PI13 PI14 PF3 VDD VSS VSS VSS VSS VSS VDD PG4 PG3 PG2 PK2
PH1- PH0-
VSS
J OSC_ OSC VSS PF5 PF4 VSS VSS VSS VSS VSS VDD PK0 PK1 VSSDSI
DSI
OUT _IN
DSI_ DSI_
K NRST PF6 PF7 PF8 VDD VSS VSS VSS VSS VSS VDD PJ11 VSSDSI
D1P D1N
DSI_ DSI_
L VDDA PC0 PF10 PF9 VDD VSS VSS VSS VSS VSS VDD PJ10 VSSDSI
CKP CKN
DSI_ DSI_
M VREF+ PC1 PC2 PC3 VDD VDD PJ9 VSSDSI
D0P D0N
VCAP
N VREF- PH2 PA2 PA1 PA0 PJ0 VDD VDD PE10 VDD VDD VDD PJ8 PJ7 PJ6 VSS
DSI
VDD
P VSSA PH3 PH4 PH5 PI15 PJ1 PF13 PF14 PE9 PE11 PB10 PB11 PH10 PH11 PD15 PD14
DSI
R PC2_C PC3_C PA6 VSS PA7 PB2 PF12 VSS PF15 PE12 PE15 PJ5 PH9 PH12 PD11 PD12 PD13
T PA0_C PA1_C PA5 PC4 PB1 PJ2 PF11 PG0 PE8 PE13 PH6 VSS PH8 PB12 PB15 PD10 PD9
VDD
U VSS PA3 PA4 PC5 PB0 PJ3 PJ4 PG1 PE7 PE14 VCAP PH7 PB13 PB14 PD8 VSS
LDO
MSv43743V4
Unless otherwise specified in brackets below the pin name, the pin function during
Pin name
and after reset is the same as the actual pin name
S Supply pin
I Input only pin
Pin type
I/O Input / output pin
ANA Analog-only Input
FT 5 V tolerant I/O
TT 3.3 V tolerant I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
TRACECLK, SAI1_CK1,
SPI4_SCK,
SAI1_MCLK_A,
FT_ SAI4_MCLK_A,
D9 A2 1 1 C3 PE2 I/O - -
h QUADSPI_BK1_IO2,
SAI4_CK1,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
TRACED0,
TIM15_BKIN,
FT_
D10 C3 2 2 D3 PE3 I/O - SAI1_SD_B, -
h
SAI4_SD_B, FMC_A19,
EVENTOUT
TRACED1, SAI1_D2,
DFSDM1_DATIN3,
TIM15_CH1N,
FT_
B12 D3 3 3 D2 PE4 I/O - SPI4_NSS, SAI1_FS_A, -
h
SAI4_FS_A, SAI4_D2,
FMC_A20, DCMI_D4,
LCD_B0, EVENTOUT
TRACED2, SAI1_CK2,
DFSDM1_CKIN3,
TIM15_CH1,
SPI4_MISO,
FT_
C11 E4 4 4 D1 PE5 I/O - SAI1_SCK_A, -
h
SAI4_SCK_A,
SAI4_CK2, FMC_A21,
DCMI_D6, LCD_G0,
EVENTOUT
TRACED3,
TIM1_BKIN2, SAI1_D1,
TIM15_CH2,
SPI4_MOSI,
FT_ SAI1_SD_A,
E8 C2 5 5 E5 PE6 I/O - -
h SAI4_SD_A, SAI4_D1,
SAI2_MCLK_B,
TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
- A1 6 6 A1 VSS S - - - -
- A9 7 7 - VDD S - - - -
B13 B1 8 8 B1 VBAT S - - - -
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
D11 - - - B2 VSS S - - - -
RTC_TAMP2/
- - - 9 E4 PI8 I/O FT - EVENTOUT
WKUP3
RTC_TAMP1/
E9 E3 9 10 E3 PC13 I/O FT - EVENTOUT
RTC_TS/WKUP2
PC14-
C13 C1 10 11 C2 OSC32_IN I/O FT - EVENTOUT OSC32_IN
(OSC32_IN)(1)
PC15-
OSC32_OUT(
C12 D2 11 12 C1 I/O FT - EVENTOUT OSC32_OUT
OSC32_OUT)
(1)
UART4_RX,
FDCAN1_RX,
FT_
- - - 13 E2 PI9 I/O - FMC_D30, -
h
LCD_VSYNC,
EVENTOUT
FDCAN1_RXFD_MODE,
ETH_MII_RX_ER,
FT_
- - - 14 F3 PI10 I/O - FMC_D31, -
h
LCD_HSYNC,
EVENTOUT
LCD_G6,
- - - 15 F4 PI11 I/O FT - OTG_HS_ULPI_DIR, WKUP4
EVENTOUT
- B4 12 16 A17 VSS S - - - -
D13 E2 13 17 E6 VDD S - - - -
D12 F2 14 18 F2 VSSSMPS S - - - -
E12 E1 15 19 E1 VLXSMPS S - - - -
E13 F1 16 20 F1 VDDSMPS S - - - -
E11 F3 17 21 G2 VFBSMPS S - - - -
I2C2_SDA, FMC_A0,
E10 F4 18 22 G4 PF0 I/O FT_f - -
EVENTOUT
I2C2_SCL, FMC_A1,
F9 F5 19 23 G3 PF1 I/O FT_f - -
EVENTOUT
I2C2_SMBA, FMC_A2,
F12 F6 20 24 G1 PF2 I/O FT - -
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
LCD_HSYNC,
- - - - H1 PI12 I/O FT - -
EVENTOUT
LCD_VSYNC,
- - - - H2 PI13 I/O FT - -
EVENTOUT
FT_
- - - - H3 PI14 I/O - LCD_CLK, EVENTOUT -
h
FT_
F13 G2 21 25 H4 PF3 I/O - FMC_A3, EVENTOUT ADC3_INP5
ha
FT_ ADC3_INN5,
F11 G1 22 26 J5 PF4 I/O - FMC_A4, EVENTOUT
ha ADC3_INP9
FT_
F10 G3 23 27 J4 PF5 I/O - FMC_A5, EVENTOUT ADC3_INP4
ha
G12 - 24 28 C10 VSS S - - -
G13 H1 25 29 E9 VDD S - - -
TIM16_CH1, SPI5_NSS,
SAI1_SD_B,
FT_ UART7_RX, ADC3_INN4,
- G4 26 30 K2 PF6 I/O -
ha SAI4_SD_B, ADC3_INP8
QUADSPI_BK1_IO3,
EVENTOUT
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B,
FT_ UART7_TX,
- G5 27 31 K3 PF7 I/O - ADC3_INP3
ha SAI4_MCLK_B,
QUADSPI_BK1_IO2,
EVENTOUT
TIM16_CH1N,
SPI5_MISO,
SAI1_SCK_B,
FT_ UART7_RTS/UART7_ ADC3_INN3,
- G6 28 32 K4 PF8 I/O -
ha DE, SAI4_SCK_B, ADC3_INP7
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
TIM17_CH1N,
SPI5_MOSI,
SAI1_FS_B,
FT_ UART7_CTS,
- H3 29 33 L4 PF9 I/O - ADC3_INP2
ha SAI4_FS_B,
TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
TIM16_BKIN, SAI1_D3,
FT_ QUADSPI_CLK, ADC3_INN2,
- H4 30 34 L3 PF10 I/O -
ha SAI4_D3, DCMI_D11, ADC3_INP6
LCD_DE, EVENTOUT
PH0-
H12 J2 31 35 J2 I/O FT - EVENTOUT OSC_IN
OSC_IN(PH0)
PH1-
H13 J1 32 36 J1 OSC_OUT(P I/O FT - EVENTOUT OSC_OUT
H1)
H11 H5 33 37 K1 NRST I/O RST - - -
DFSDM1_CKIN0,
DFSDM1_DATIN4,
FT_ SAI2_FS_B,
G11 J4 34 38 L2 PC0 I/O - ADC123_INP10
a OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
TRACED0, SAI1_D1,
DFSDM1_DATIN0,
DFSDM1_CKIN4,
SPI2_MOSI/I2S2_SDO, ADC123_INN10,
FT_ SAI1_SD_A, ADC123_INP11,
G10 J3 35 39 M2 PC1 I/O -
ha SAI4_SD_A, RTC_TAMP3/
SDMMC2_CK, SAI4_D1, WKUP5
ETH_MDC,
MDIOS_MDC,
EVENTOUT
FT_ C1DSLEEP, ADC123_INN11,
- - - - M3(2) PC2 I/O -
a DFSDM1_CKIN1, ADC123_INP12
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
AN TT_ OTG_HS_ULPI_DIR, ADC3_INN1,
K13(3) K1(3) 36(3) 40(3) R1(1) PC2_C - ETH_MII_TXD2,
A a ADC3_INP0
FMC_SDNE0,
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
LPTIM1_IN2,
QUADSPI_BK2_IO0,
FT_ SAI2_SCK_B,
- - - 48 N2 PH2 I/O - ADC3_INP13
ha ETH_MII_CRS,
FMC_SDCKE0,
LCD_R0, EVENTOUT
- - 44 49 F5 VDD S - - - -
- N1 45 50 C16 VSS S - - - -
QUADSPI_BK2_IO1,
SAI2_MCLK_B,
FT_ ADC3_INN13,
- - - 51 P2 PH3 I/O - ETH_MII_COL,
ha ADC3_INP14
FMC_SDNE0, LCD_R1,
EVENTOUT
I2C2_SCL, LCD_G5,
FT_f ADC3_INN14,
- - - 52 P3 PH4 I/O - OTG_HS_ULPI_NXT,
a ADC3_INP15
LCD_G4, EVENTOUT
I2C2_SDA, SPI5_NSS,
FT_f ADC3_INN15,
- - - 53 P4 PH5 I/O - FMC_SDNWE,
a ADC3_INP16
EVENTOUT
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT,
TIM15_CH2,
FT_
J10 N2 46 54 U2 PA3 I/O - USART2_RX, LCD_B2, ADC12_INP15
ha
OTG_HS_ULPI_D0,
ETH_MII_COL,
LCD_B5, EVENTOUT
L11 - 47 55 - VSS S - - - -
M12 - 48 56 G5 VDD S - - - -
D1PWREN, TIM5_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
TT_ ADC12_INP18,
K10 N3 49 57 U3 PA4 I/O - SPI6_NSS,
a DAC1_OUT1
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
D2PWREN,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N, ADC12_INN18,
TT_
H10 J5 50 58 T3 PA5 I/O - SPI1_SCK/I2S1_CK, ADC12_INP19,
ha
SPI6_SCK, DAC1_OUT2
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
SPI6_MISO,
FT_ TIM13_CH1,
G9 M4 51 59 R3 PA6 I/O - ADC12_INP3
a TIM8_BKIN_COMP12,
MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK,
LCD_G2, EVENTOUT
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SDO,
ADC12_INN3,
TT_ SPI6_MOSI,
J9 K4 52 60 R5 PA7 I/O - ADC12_INP7,
a TIM14_CH1,
OPAMP1_VINM
ETH_MII_RX_DV/ETH_
RMII_CRS_DV,
FMC_SDNWE,
EVENTOUT
C2DSLEEP,
DFSDM1_CKIN2,
I2S1_MCK,
ADC12_INP4,
TT_ SPDIFRX1_IN3,
M11 L4 53 61 T4 PC4 I/O - OPAMP1_VOUT,
a ETH_MII_RXD0/ETH_R
COMP1_INM
MII_RXD0,
FMC_SDNE0,
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
C2SLEEP, SAI1_D3,
DFSDM1_DATIN2,
SPDIFRX1_IN4,
SAI4_D3, ADC12_INN4,
TT_
L10 K5 54 62 U4 PC5 I/O - ETH_MII_RXD1/ETH_R ADC12_INP8,
a
MII_RXD1, OPAMP1_VINM
FMC_SDCKE0,
COMP1_OUT,
EVENTOUT
- - - - G13 VDD S - - - -
- H2 - - R4 VSS S - - - -
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N, ADC12_INN5,
FT_ DFSDM1_CKOUT, ADC12_INP9,
K9 N4 55 63 U5 PB0 I/O -
a UART4_CTS, LCD_R3, OPAMP1_VINP,
OTG_HS_ULPI_D1, COMP1_INP
ETH_MII_RXD2,
LCD_G1, EVENTOUT
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N,
TT_ DFSDM1_DATIN1, ADC12_INP5,
H9 H6 56 64 T5 PB1 I/O -
u LCD_R6, COMP1_INM
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
LCD_G0, EVENTOUT
RTC_OUT, SAI1_D1,
DFSDM1_CKIN1,
SAI1_SD_A,
FT_
M10 L5 57 65 R6 PB2 I/O - SPI3_MOSI/I2S3_SDO, COMP1_INP
ha
SAI4_SD_A,
QUADSPI_CLK,
SAI4_D1, EVENTOUT
LCD_G2, LCD_R0,
- - - 66 P5 PI15 I/O FT - -
EVENTOUT
LCD_R7, LCD_R1,
- - - - N6 PJ0 I/O FT - -
EVENTOUT
- - - - P6 PJ1 I/O FT - LCD_R2, EVENTOUT -
DSI_TE, LCD_R3,
- - - - T6 PJ2 I/O FT - -
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
TIM1_CH1,
DFSDM1_CKOUT,
UART7_RTS/UART7_
TT_ OPAMP2_VINP,
K7 N6 69 78 P9 PE9 I/O - DE,
ha COMP2_INP
QUADSPI_BK2_IO2,
FMC_D6/FMC_DA6,
EVENTOUT
L7 M6 70 79 J17 VSS S - - - -
M7 - 71 80 J13 VDD S - - - -
TIM1_CH2N,
DFSDM1_DATIN4,
FT_ UART7_CTS,
G7 L7 72 81 N9 PE10 I/O - COMP2_INM
ha QUADSPI_BK2_IO3,
FMC_D7/FMC_DA7,
EVENTOUT
TIM1_CH2,
DFSDM1_CKIN4,
FT_
G6 N7 73 82 P10 PE11 I/O - SPI4_NSS, SAI2_SD_B, COMP2_INP
ha
FMC_D8/FMC_DA8,
LCD_G3, EVENTOUT
TIM1_CH3N,
DFSDM1_DATIN5,
SPI4_SCK,
FT_
J6 J8 74 83 R10 PE12 I/O - SAI2_SCK_B, -
h
FMC_D9/FMC_DA9,
COMP1_OUT, LCD_B4,
EVENTOUT
TIM1_CH3,
DFSDM1_CKIN5,
SPI4_MISO,
FT_
K6 H8 75 84 T10 PE13 I/O - SAI2_FS_B, -
h
FMC_D10/FMC_DA10,
COMP2_OUT, LCD_DE,
EVENTOUT
- H2 - - T12 VSS S - - - -
- - - - K13 VDD S - - -
TIM1_CH4, SPI4_MOSI,
FT_ SAI2_MCLK_B,
M6 M8 76 85 U10 PE14 I/O - -
h FMC_D11/FMC_DA11,
LCD_CLK, EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
TIM1_BKIN,
COMP_TIM1_BKIN,
FT_
L6 K8 77 86 R11 PE15 I/O - FMC_D12/FMC_DA12, -
h
TIM1_BKIN_COMP12,
LCD_R7, EVENTOUT
TIM2_CH3,
HRTIM_SCOUT,
LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7,
H6 K9 78 87 P11 PB10 I/O FT_f - -
USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
TIM2_CH4,
HRTIM_SCIN,
LPTIM2_ETR,
I2C2_SDA,
DFSDM1_CKIN7,
K5 N8 79 88 P12 PB11 I/O FT_f - -
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_
RMII_TX_EN, DSI_TE,
LCD_G5, EVENTOUT
M5 N9 80 89 U11 VCAP S - - - -
L5 - 81 90 - VSS S - - - -
L4 N10 82 91 U12 VDDLDO S - - - -
M4 - - - L13 VDD S - - - -
- - - - R12 PJ5 I/O FT - LCD_R6, EVENTOUT -
TIM12_CH1,
I2C2_SMBA, SPI5_SCK,
- - - 92 T11 PH6 I/O FT - ETH_MII_RXD2, -
FMC_SDNE1,
DCMI_D8, EVENTOUT
I2C3_SCL, SPI5_MISO,
FT_f ETH_MII_RXD3,
- - - 93 U13 PH7 I/O - -
a FMC_SDCKE1,
DCMI_D9, EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
TIM5_ETR, I2C3_SDA,
FT_f FMC_D16,
- - - 94 T13 PH8 I/O - -
ha DCMI_HSYNC,
LCD_R2, EVENTOUT
- E13 - - - VSS S - - - -
M4 L9 - - M13 VDD S - - - -
TIM12_CH2,
FT_ I2C3_SMBA, FMC_D17,
- - - 95 R13 PH9 I/O - -
h DCMI_D0, LCD_R3,
EVENTOUT
TIM5_CH1,
FT_ I2C4_SMBA, FMC_D18,
- - - 96 P13 PH10 I/O - -
h DCMI_D1, LCD_R4,
EVENTOUT
TIM5_CH2, I2C4_SCL,
FT_f
- - - 97 P14 PH11 I/O - FMC_D19, DCMI_D2, -
h
LCD_R5, EVENTOUT
TIM5_CH3, I2C4_SDA,
FT_f
- - - 98 R14 PH12 I/O - FMC_D20, DCMI_D3, -
h
LCD_R6, EVENTOUT
- D1 83 99 N16 VSS S - - - -
M4 - 84 100 - VDD S - - - -
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1,
USART3_CK,
FT_ FDCAN2_RX,
J5 L10 85 101 T14 PB12 I/O - -
u OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_R
MII_TXD0, OTG_HS_ID,
TIM1_BKIN_COMP12,
UART5_RX,
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
TIM1_CH1N,
LPTIM2_OUT,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
FT_ USART3_CTS/USART3
H5 M10 86 102 U14 PB13 I/O - OTG_HS_VBUS
u _NSS, FDCAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_R
MII_TXD1, UART5_TX,
EVENTOUT
TIM1_CH2N,
TIM12_CH1,
TIM8_CH2N,
USART1_TX,
SPI2_MISO/I2S2_SDI,
FT_ DFSDM1_DATIN2,
M3 N11 87 103 U15 PB14 I/O - -
u USART3_RTS/USART3
_DE, UART4_RTS/
UART4_DE,
SDMMC2_D0,
OTG_HS_DM,
EVENTOUT
RTC_REFIN,
TIM1_CH3N,
TIM12_CH2,
TIM8_CH3N,
USART1_RX,
FT_
M2 M11 88 104 T15 PB15 I/O - SPI2_MOSI/I2S2_SDO, -
u
DFSDM1_CKIN2,
UART4_CTS,
SDMMC2_D1,
OTG_HS_DP,
EVENTOUT
DFSDM1_CKIN3,
SAI3_SCK_B,
FT_ USART3_TX,
G5 N12 89 105 U16 PD8 I/O - -
h SPDIFRX1_IN2,
FMC_D13/FMC_DA13,
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
DFSDM1_DATIN3,
SAI3_SD_B,
FT_ USART3_RX,
K4 M12 90 106 T17 PD9 I/O - -
h FDCAN2_RXFD_MODE,
FMC_D14/FMC_DA14,
EVENTOUT
DFSDM1_CKOUT,
SAI3_FS_B,
FT_ USART3_CK,
L3 N13 91 107 T16 PD10 I/O -
h FDCAN2_TXFD_MODE,
FMC_D15/FMC_DA15,
LCD_B3, EVENTOUT
- L11 92 108 N12 VDD S - - - -
M1 L13 93 109 U17 VSS S - - - -
LPTIM2_IN2,
I2C4_SMBA,
USART3_CTS/USART3
FT_
J4 K10 94 110 R15 PD11 I/O - _NSS, -
h
QUADSPI_BK1_IO0,
SAI2_SD_A, FMC_A16,
EVENTOUT
LPTIM1_IN1,
TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
FT_f USART3_RTS/
L2 J10 95 111 R16 PD12 I/O - -
h USART3_DE,
QUADSPI_BK1_IO1,
SAI2_FS_A, FMC_A17,
EVENTOUT
LPTIM1_OUT,
TIM4_CH2, I2C4_SDA,
FT_f
K3 J9 96 112 R17 PD13 I/O - QUADSPI_BK1_IO3, -
h
SAI2_SCK_A,
FMC_A18, EVENTOUT
L1 - - 113 - VSS S - - - -
- - - 114 N11 VDD S - - - -
TIM4_CH3,
SAI3_MCLK_B,
FT_
H4 H9 97 115 P16 PD14 I/O - UART8_CTS, -
h
FMC_D0/FMC_DA0,
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
TIM4_CH4,
SAI3_MCLK_A,
FT_ UART8_RTS/
J3 H10 98 116 P15 PD15 I/O - -
h UART8_DE,
FMC_D1/FMC_DA1,
EVENTOUT
TIM8_CH2, LCD_R7,
- - - - N15 PJ6 I/O FT - -
EVENTOUT
TRGIN, TIM8_CH2N,
- - - - N14 PJ7 I/O FT - -
LCD_G0, EVENTOUT
K2 - - - N10 VDD S - - - -
- C12 - - R8 VSS S - - - -
TIM1_CH3N,
- - - - N13 PJ8 I/O FT - TIM8_CH1, UART8_TX, -
LCD_G1, EVENTOUT
TIM1_CH3,
TIM8_CH1N,
- - - - M14 PJ9 I/O FT - -
UART8_RX, LCD_G2,
EVENTOUT
TIM1_CH2N,
- - - - L14 PJ10 I/O FT - TIM8_CH2, SPI5_MOSI, -
LCD_G3, EVENTOUT
TIM1_CH2,
TIM8_CH2N,
- - - - K14 PJ11 I/O FT - -
SPI5_MISO, LCD_G4,
EVENTOUT
- - 99 117 N8 VDD S - - -
- M13 - - P17 VDDDSI S - - -
- - 100 118 U1 VSS S - - -
K1 L12 101 119 N17 VCAPDSI S - - -
- - 102 120 - VDD12DSI S - - -
J2 K12 103 121 M16 DSI_D0P I/O TT - - -
J1 K13 104 122 M17 DSI_D0N I/O TT - - -
H3 G12 105 123 K15 VSSDSI S - - -
H2 J12 106 124 L16 DSI_CKP I/O TT - - -
H1 J13 107 125 L17 DSI_CKN I/O TT - - -
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
HRTIM_CHE2,
SAI1_MCLK_A,
FT_
- F8 117 137 F16 PG7 I/O - USART6_CK, FMC_INT, -
h
DCMI_D13, LCD_CLK,
EVENTOUT
TIM8_ETR, SPI6_NSS,
USART6_RTS/USART6
FT_ _DE, SPDIFRX1_IN3,
F2 F9 118 138 F15 PG8 I/O - -
h ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
F3 - 119 139 G16 VSS S - - - -
E3 F12 120 140 G17 VDD50USB S - - - -
E1 F13 121 141 F17 VDD33USB S - - - -
E2 - - - M5 VDD S - - - -
HRTIM_CHA1,
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
I2S2_MCK,
USART6_TX,
FT_ SDMMC1_D0DIR,
F5 F11 122 142 F14 PC6 I/O - SWPMI_IO
h FMC_NWAIT,
SDMMC2_D6,
SDMMC1_D6,
DCMI_D0,
LCD_HSYNC,
EVENTOUT
TRGIO, HRTIM_CHA2,
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3,
I2S3_MCK,
USART6_RX,
FT_ SDMMC1_D123DIR,
E4 E10 123 143 F13 PC7 I/O - -
h FMC_NE1,
SDMMC2_D7,
SWPMI_TX,
SDMMC1_D7,
DCMI_D1, LCD_G6,
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
TRACED1,
HRTIM_CHB1,
TIM3_CH3, TIM8_CH3,
USART6_CK,
FT_ UART5_RTS/
D1 F10 124 144 E13 PC8 I/O - -
h UART5_DE,
FMC_NE2/FMC_NCE,
SWPMI_RX,
SDMMC1_D0,
DCMI_D2, EVENTOUT
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
QUADSPI_BK1_IO0,
FT_f
D2 E11 125 145 E14 PC9 I/O - LCD_G3, -
h
SWPMI_SUSPEND,
SDMMC1_D1,
DCMI_D3, LCD_B2,
EVENTOUT
- - 126 - L5 VDD S - - - -
MCO1, TIM1_CH1,
HRTIM_CHB2,
TIM8_BKIN2,
I2C3_SCL,
FT_f USART1_CK,
D3 D10 127 146 E15 PA8 I/O - -
ha OTG_FS_SOF,
UART7_RX,
TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6,
EVENTOUT
TIM1_CH2,
HRTIM_CHC1,
LPUART1_TX,
I2C3_SMBA,
FT_
D4 D11 128 147 D15 PA9 I/O - SPI2_SCK/I2S2_CK, OTG_FS_VBUS
u
USART1_TX,
FDCAN1_RXFD_MODE,
DCMI_D0, LCD_R5,
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
TIM1_CH3,
HRTIM_CHC2,
LPUART1_RX,
USART1_RX,
FT_
C2 A13 129 148 D14 PA10 I/O - FDCAN1_TXFD_MODE, -
u
OTG_FS_ID,
MDIOS_MDIO, LCD_B4,
DCMI_D1, LCD_B1,
EVENTOUT
TIM1_CH4,
HRTIM_CHD1,
LPUART1_CTS,
SPI2_NSS/I2S2_WS,
FT_
C1 D12 130 149 E17 PA11 I/O - UART4_RX, -
u
USART1_CTS/USART1
_NSS, FDCAN1_RX,
OTG_FS_DM, LCD_R4,
EVENTOUT
TIM1_ETR,
HRTIM_CHD2,
LPUART1_RTS/
LPUART1_DE,
SPI2_SCK/I2S2_CK,
FT_ UART4_TX,
B1 D13 131 150 E16 PA12 I/O - -
u USART1_RTS/
USART1_DE,
SAI2_FS_B,
FDCAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT
PA13(JTMS/ JTMS-SWDIO,
C3 B11 132 151 C15 I/O FT - -
SWDIO) EVENTOUT
B2 C13 133 152 D17 VCAP S - - - -
A1 - 134 153 - VSS S - - - -
A2 B13 135 154 C17 VDDLDO - - - -
B3 - 136 155 K5 VDD S - - - -
TIM8_CH1N,
UART4_TX,
FT_
- - - 156 D16 PH13 I/O - FDCAN1_TX, -
h
FMC_D21, LCD_G2,
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
TIM8_CH2N,
UART4_RX,
FT_
- - - 157 B17 PH14 I/O - FDCAN1_RX, -
h
FMC_D22, DCMI_D4,
LCD_G3, EVENTOUT
TIM8_CH3N,
FT_ FDCAN1_TXFD_MODE,
- - - 158 B16 PH15 I/O - -
h FMC_D23, DCMI_D11,
LCD_G4, EVENTOUT
TIM5_CH4,
SPI2_NSS/I2S2_WS,
FT_
- - - 159 A16 PI0 I/O - FDCAN1_RXFD_MODE, -
h
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
- - - 160 - VSS S - - -
- B12 - 161 VDD VDD S - - -
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
FT_
- - - 162 A15 PI1 I/O - TIM8_BKIN2_COMP12, -
h
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
TIM8_CH4,
FT_ SPI2_MISO/I2S2_SDI,
- - - 163 B15 PI2 I/O - -
h FMC_D26, DCMI_D9,
LCD_G7, EVENTOUT
TIM8_ETR,
FT_ SPI2_MOSI/I2S2_SDO,
- - - 164 C14 PI3 I/O - -
h FMC_D27, DCMI_D10,
EVENTOUT
C4 - 137 - - VSS S - - - -
B3 - - - VDD VDD S - - - -
PA14(JTCK/ JTCK-SWCLK,
E5 A11 138 165 B14 I/O FT - -
SWCLK) EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
JTDI,
TIM2_CH1/TIM2_ETR,
HRTIM_FLT1, CEC,
SPI1_NSS/I2S1_WS,
A3 B10 139 166 A14 PA15(JTDI) I/O FT - SPI3_NSS/I2S3_WS, -
SPI6_NSS,
UART4_RTS/UART4_D
E, UART7_TX, DSI_TE,
EVENTOUT
HRTIM_EEV1,
DFSDM1_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX,
FT_
D5 C11 140 167 A13 PC10 I/O - UART4_TX, -
ha
QUADSPI_BK1_IO1,
SDMMC1_D2,
DCMI_D8, LCD_R2,
EVENTOUT
HRTIM_FLT2,
DFSDM1_DATIN5,
SPI3_MISO/I2S3_SDI,
FT_ USART3_RX,
C5 E9 141 168 B13 PC11 I/O - -
h UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3,
DCMI_D4, EVENTOUT
TRACED3,
HRTIM_EEV2,
SPI3_MOSI/I2S3_SDO,
FT_
B4 D9 142 169 C12 PC12 I/O - USART3_CK, -
h
UART5_TX,
SDMMC1_CK,
DCMI_D9, EVENTOUT
- A7 - - - VSS S - - - -
- - - - VDD VDD S - - - -
DFSDM1_CKIN6,
SAI3_SCK_A,
FT_ UART4_RX,
A4 C10 143 170 D13 PD0 I/O - -
h FDCAN1_RX,
FMC_D2/FMC_DA2,
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
DFSDM1_DATIN6,
SAI3_SD_A,
FT_ UART4_TX,
F6 C9 144 171 E12 PD1 I/O - -
h FDCAN1_TX,
FMC_D3/FMC_DA3,
EVENTOUT
TRACED2, TIM3_ETR,
FT_ UART5_RX,
E6 E8 145 172 D12 PD2 I/O - -
h SDMMC1_CMD,
DCMI_D11, EVENTOUT
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
FT_ USART2_CTS/USART2
B5 A10 146 173 B12 PD3 I/O - -
h _NSS, FMC_CLK,
DCMI_D5, LCD_G7,
EVENTOUT
HRTIM_FLT3,
SAI3_FS_A,
FT_ USART2_RTS/USART2
A5 D8 147 174 A12 PD4 I/O - -
h _DE,
FDCAN1_RXFD_MODE,
FMC_NOE, EVENTOUT
HRTIM_EEV3,
FT_ USART2_TX,
F7 C8 148 175 A11 PD5 I/O - -
h FDCAN1_TXFD_MODE,
FMC_NWE, EVENTOUT
B6 - - - - VSS S - - - -
A6 B2 - - VDD VDD S - - - -
SAI1_D1,
DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A,
FT_ USART2_RX,
C6 B8 149 176 B11 PD6 I/O - -
h SAI4_SD_A,
FDCAN2_RXFD_MODE,
SAI4_D1, SDMMC2_CK,
FMC_NWAIT,
DCMI_D10, LCD_B2,
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1,
FT_
D6 A8 150 177 C11 PD7 I/O - USART2_CK, -
h
SPDIFRX1_IN0,
SDMMC2_CMD,
FMC_NE1, EVENTOUT
TRGOUT, LCD_G3,
- - - - D11 PJ12 I/O FT - -
LCD_B0, EVENTOUT
LCD_B4, LCD_B1,
- - - - E10 PJ13 I/O FT - -
EVENTOUT
- - - - D10 PJ14 I/O FT - LCD_B2, EVENTOUT -
- - - - B10 PJ15 I/O FT - LCD_B3, EVENTOUT -
B9 B9 151 178 - VSS S - - - -
- - 152 179 VDD VDD S - - - -
SPI1_MISO/I2S1_SDI,
USART6_RX,
SPDIFRX1_IN4,
FT_ QUADSPI_BK2_IO2,
- C7 153 180 A10 PG9 I/O - -
h SAI2_FS_B,
FMC_NE2/FMC_NCE,
DCMI_VSYNC,
EVENTOUT
HRTIM_FLT5,
SPI1_NSS/I2S1_WS,
FT_
- D7 154 181 A9 PG10 I/O - LCD_G3, SAI2_SD_B, -
h
FMC_NE3, DCMI_D2,
LCD_B2, EVENTOUT
LPTIM1_IN2,
HRTIM_EEV4,
SPI1_SCK/I2S1_CK,
FT_ SPDIFRX1_IN1,
- E7 155 182 B9 PG11 I/O - -
h SDMMC2_D2,
ETH_MII_TX_EN/ETH_
RMII_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
LPTIM1_IN1,
HRTIM_EEV5,
SPI6_MISO,
USART6_RTS/USART6
FT_
- G7 156 183 C9 PG12 I/O - _DE, SPDIFRX1_IN2, -
h
LCD_B4,
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_NE4,
LCD_B1, EVENTOUT
TRACED0,
LPTIM1_OUT,
HRTIM_EEV10,
SPI6_SCK,
FT_
- F7 157 184 D9 PG13 I/O - USART6_CTS/USART6 -
h
_NSS,
ETH_MII_TXD0/ETH_R
MII_TXD0, FMC_A24,
LCD_R0, EVENTOUT
TRACED1,
LPTIM1_ETR,
SPI6_MOSI,
FT_ USART6_TX,
- E6 158 185 D8 PG14 I/O - -
h QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_A25,
LCD_B0, EVENTOUT
- - 159 186 - VSS S - - - -
- - 160 187 VDD VDD S - - - -
- - - - C8 PK3 I/O FT - LCD_B4, EVENTOUT -
- - - - B8 PK4 I/O FT - LCD_B5, EVENTOUT -
- - - - A8 PK5 I/O FT - LCD_B6, EVENTOUT -
- - - - C7 PK6 I/O FT - LCD_B7, EVENTOUT -
- - - - D7 PK7 I/O FT - LCD_DE, EVENTOUT -
- B7 - - VDD VDD S - - -
USART6_CTS/USART6
FT_
A7 C6 161 188 D6 PG15 I/O - _NSS, FMC_SDNCAS, -
h
DCMI_D13, EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
JTDO/TRACESWO,
TIM2_CH2,
HRTIM_FLT4,
SPI1_SCK/I2S1_CK,
PB3(JTDO/TR SPI3_SCK/I2S3_CK,
B7 A6 162 189 C6 I/O FT - -
ACESWO) SPI6_SCK,
SDMMC2_D2,
CRS_SYNC,
UART7_RX,
EVENTOUT
NJTRST, TIM16_BKIN,
TIM3_CH1,
HRTIM_EEV6,
SPI1_MISO/I2S1_SDI,
A8 B6 163 190 B7 PB4(NJTRST) I/O FT - SPI3_MISO/I2S3_SDI, -
SPI2_NSS/I2S2_WS,
SPI6_MISO,
SDMMC2_D3,
UART7_TX, EVENTOUT
TIM17_BKIN,
TIM3_CH2,
HRTIM_EEV7,
I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
B8 A5 164 191 A5 PB5 I/O FT - -
SPI6_MOSI,
FDCAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10, UART5_RX,
EVENTOUT
A9 - - - VDD VDD S - - - -
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
TIM16_CH1N,
TIM4_CH1,
HRTIM_EEV8,
I2C1_SCL, CEC,
I2C4_SCL,
USART1_TX,
C7 E5 165 192 B5 PB6 I/O FT_f - LPUART1_TX, -
FDCAN2_TX,
QUADSPI_BK1_NCS,
DFSDM1_DATIN5,
FMC_SDNE1,
DCMI_D5, UART5_TX,
EVENTOUT
TIM17_CH1N,
TIM4_CH2,
HRTIM_EEV9,
I2C1_SDA, I2C4_SDA,
USART1_RX,
FT_f
C8 C5 166 193 C5 PB7 I/O - LPUART1_RX, PVD_IN
a
FDCAN2_TXFD_MODE,
DFSDM1_CKIN5,
FMC_NL,
DCMI_VSYNC,
EVENTOUT
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7,
I2C1_SCL, I2C4_SCL,
SDMMC1_CKIN,
UART4_RX,
FT_f
A10 D5 168 195 D5 PB8 I/O - FDCAN1_RX, -
h
SDMMC2_D4,
ETH_MII_TXD3,
SDMMC1_D4,
DCMI_D6, LCD_B6,
EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
I2C4_SDA,
SDMMC1_CDIR,
FT_f
C9 D6 169 196 D4 PB9 I/O - UART4_TX, -
h
FDCAN1_TX,
SDMMC2_D5,
I2C4_SMBA,
SDMMC1_D5,
DCMI_D7, LCD_B7,
EVENTOUT
LPTIM1_ETR,
TIM4_ETR,
HRTIM_SCIN,
LPTIM2_ETR,
FT_
B10 D4 170 197 C4 PE0 I/O - UART8_RX, -
h
FDCAN1_RXFD_MODE,
SAI2_MCLK_A,
FMC_NBL0, DCMI_D2,
EVENTOUT
LPTIM1_IN2,
HRTIM_SCOUT,
FT_ UART8_TX,
D8 C4 171 198 B4 PE1 I/O - -
h FDCAN1_TXFD_MODE,
FMC_NBL1, DCMI_D3,
EVENTOUT
A11 A4 172 199 A7 VCAP S - - - -
C10 - 173 200 B6 VSS S - - - -
E7 B3 174 201 E7 PDR_ON I FT - - -
A12 A3 175 202 A6 VDDLDO S - - - -
B11 - - - VDD VDD S - - - -
TIM8_BKIN,
SAI2_MCLK_A,
FT_
- - - 203 A4 PI4 I/O - TIM8_BKIN_COMP12, -
h
FMC_NBL2, DCMI_D5,
LCD_B4, EVENTOUT
I/O structure
TFBGA240+25
Pin type
Pin name
WLCSP156
UFBGA169
Notes
Additional
LQFP176
LQFP208
(function Alternate functions
functions
after reset)
TIM8_CH1,
SAI2_SCK_A,
FT_
- - - 204 A3 PI5 I/O - FMC_NBL3, -
h
DCMI_VSYNC,
LCD_B5, EVENTOUT
TIM8_CH2, SAI2_SD_A,
FT_
- - - 205 A2 PI6 I/O - FMC_D28, DCMI_D6, -
h
LCD_B6, EVENTOUT
TIM8_CH3, SAI2_FS_A,
FT_
- - - 206 B3 PI7 I/O - FMC_D29, DCMI_D7, -
h
LCD_B7, EVENTOUT
- - - 207 - VSS S - - - -
B11 - 176 208 VDD VDD S - - - -
M13 - - - - VSS S - - - -
A13 - - - - DNC - - - -
- - - - M15 VSSDSI S - - - -
1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is
valid for all resets except for power-on reset.
2. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG
register. Refer to the product reference manual for a detailed description of the switch configuration bits.
3. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on
Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product
reference manual for a detailed description of the switch configuration bits.
SAI4/FDCA I2C4/UART
I2C1/2/3/4/U SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port SART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ /SDMMC2/ UART5/
SYS 7/LPTIM1/ 4/5/HRTIM 2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ OTG1_HS/ LCD
HRTIM1 1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
DFSDM1/CE DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
C LCD
SPDIFRX1 ETH
USART2_
TIM2_CH1/ SDMMC2_ ETH_MII_ EVENT
PA0 - TIM5_CH1 TIM8_ETR TIM15_BKIN - - CTS/USAR UART4_TX SAI2_SD_B - - -
TIM2_ETR CMD CRS OUT
T2_NSS
USART2_ ETH_MII_
LPTIM3_ TIM15_ RTS/ QUADSPI_ SAI2_MCLK RX_CLK/ EVENT
PA1 - TIM2_CH2 TIM5_CH2 - - UART4_RX - - LCD_R2
OUT CH1N USART2_ BK1_IO3 _B ETH_RMII_ OUT
DE REF_CLK
ETH_MII_R
SPI1_MOSI TIM14_ X_DV/ETH_ FMC_ EVENT
PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - - - SPI6_MOSI - -
/I2S1_SDO CH1 RMII_CRS_ SDNWE OUT
DV
FDCAN1_
HRTIM_ LPUART1_ SPI2_SCK/ USART1_ ETH_TX_ EVENT
PA9 - TIM1_CH2 I2C3_SMBA - - RXFD_ - - DCMI_D0 LCD_R5
CHC1 TX I2S2_CK TX ER OUT
MODE
FDCAN1_
HRTIM_ LPUART1_ USART1_ OTG_FS_ MDIOS_ EVENT
PA10 - TIM1_CH3 - - - - TXFD_ LCD_B4 DCMI_D1 LCD_B1
CHC2 RX RX ID MDIO OUT
MODE
USART1_
Pin descriptions
HRTIM_ LPUART1_ SPI2_NSS/ CTS/ FDCAN1_ OTG_FS_ EVENT
PA11 - TIM1_CH4 - UART4_RX - - - - LCD_R4
CHD1 CTS I2S2_WS USART1_ RX DM OUT
NSS
LPUART1_ USART1_
HRTIM_ RTS/ SPI2_SCK/ RTS/ FDCAN1_ OTG_FS_ EVENT
PA12 - TIM1_ETR - UART4_TX SAI2_FS_B - - - LCD_R5
CHD2 LPUART1_ I2S2_CK USART1_ TX DP OUT
81/242
DE DE
Table 8. Port A alternate functions (continued)
82/242
Pin descriptions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/U SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port SART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ /SDMMC2/ UART5/
SYS 7/LPTIM1/ 4/5/HRTIM 2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ OTG1_HS/ LCD
HRTIM1 1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
DFSDM1/CE DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
C LCD
SPDIFRX1 ETH
JTMS/ EVENT
PA13 - - - - - - - - - - - - - -
SWDIO OUT
JTCK/ EVENT
Port A
PA14 - - - - - - - - - - - - - -
SWCLK OUT
UART4_
TIM2_CH1/ HRTIM_FL SPI1_NSS/ SPI3_NSS/ EVENT
PA15 JTDI - CEC SPI6_NSS RTS/UART - - UART7_TX - DSI_TE -
TIM2_ETR T1 I2S1_WS I2S3_WS OUT
4_DE
DS12930 Rev 1
STM32H747xI/G
Table 9. Port B alternate functions
STM32H747xI/G
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/U SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port SART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ /SDMMC2/ UART5/
SYS 7/LPTIM1/ 4/5/HRTIM 2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ OTG1_HS/ LCD
HRTIM1 1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
DFSDM1/ DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
CEC LCD/CRS
SPDIFRX1 ETH
JTDO/
HRTIM_ SPI1_SCK/ SPI3_SCK/I SDMMC2_ EVENT
PB3 TRACES TIM2_CH2 - - - SPI6_SCK CRS_SYNC UART7_RX - - -
FLT4 I2S1_CK 2S3_CK D2 OUT
WO
Port B
TIM16_CH1 HRTIM_EEV USART1_ LPUART1_ FDCAN2_ QUADSPI_ DFSDM1_D FMC_SDNE UART5_T EVENT
PB6 - TIM4_CH1 I2C1_SCL CEC I2C4_SCL DCMI_D5
N 8 TX TX TX BK1_NCS ATIN5 1 X OUT
FDCAN2_
TIM17_CH1 HRTIM_EEV USART1_ LPUART1_ DFSDM1_C DCMI_VSY EVENT
PB7 - TIM4_CH2 I2C1_SDA - I2C4_SDA TXFD_ - FMC_NL -
N 9 RX RX KIN5 NC OUT
MODE
Pin descriptions
83/242
Table 9. Port B alternate functions (continued)
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Pin descriptions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/U SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port SART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ /SDMMC2/ UART5/
SYS 7/LPTIM1/ 4/5/HRTIM 2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ OTG1_HS/ LCD
HRTIM1 1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
DFSDM1/ DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
CEC LCD/CRS
SPDIFRX1 ETH
ETH_MII_
HRTIM_ LPTIM2_ DFSDM1_ USART3_ OTG_HS_ TX_EN/ETH EVENT
PB11 - TIM2_CH4 I2C2_SDA - - - - DSI_TE LCD_G5
SCIN ETR CKIN7 RX ULPI_D4 _RMII_TX_ OUT
EN
ETH_MII_
SPI2_NSS/ DFSDM1_ USART3_ FDCAN2_ OTG_HS_U OTG_HS_ TIM1_BKIN UART5_ EVENT
PB12 - TIM1_BKIN - - I2C2_SMBA - TXD0/ETH_
Port B
USART3_
ETH_MII_
DS12930 Rev 1
USART3_
UART4_
SPI2_MISO DFSDM1_ RTS/ SDMMC2_ OTG_HS_ EVENT
PB14 - TIM1_CH2N - TIM8_CH2N USART1_TX RTS/ - - -
/I2S2_SDI DATIN2 USART3_ D0 DM OUT
UART4_DE
DE
STM32H747xI/G
Table 10. Port C alternate functions
STM32H747xI/G
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/U SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port SART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ /SDMMC2/ UART5/
SYS 7/LPTIM1/ 4/5/HRTIM 2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ OTG1_HS/ LCD
HRTIM1 1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
DFSDM1/ DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
CEC LCD
SPDIFRX1 ETH
ETH_MII_
C2 DFSDM1_ SPDIFRX1 FMC_SDNE EVENT
PC4 - - - I2S1_MCK - - - RXD0/ETH_ - -
DSLEEP CKIN2 _IN3 0 OUT
RMII_RXD0
DS12930 Rev 1
ETH_MII_ COMP1_
C2 DFSDM1_ SPDIFRX1 FMC_ EVENT
PC5 - SAI1_D3 - - - - - SAI4_D3 RXD1/ETH_ -
SLEEP DATIN2 _IN4 SDCKE0 OUT OUT
RMII_RXD1
UART5_
TRACED HRTIM_CH USART6_ FMC_NE2/ SDMMC1_ EVENT
PC8 TIM3_CH3 TIM8_CH3 - - - RTS/ - SWPMI_RX DCMI_D2 -
1 B1 CK FMC_NCE D0 OUT
UART5_DE
Pin descriptions
EVENT
PC13 - - - - - - - - - - - - - - -
OUT
EVENT
PC14 - - - - - - - - - - - - - - -
OUT
EVENT
PC15 - - - - - - - - - - - - - - -
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OUT
Table 11. Port D alternate functions
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Pin descriptions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/ SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port TIM1/2/16/ USART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
SAI1/TIM3/ TIM8/LPTI 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
17/LPTIM1 TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/3/6/ /SDMMC2/ UART5/
SYS 4/5/HRTIM M2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
/ LPTIM2/ 5/6/CEC UART4/ UART7/ OTG1_HS/ LCD
1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
HRTIM1 DFSDM1/ DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
CEC LCD
SPDIFRX1 ETH
FDCAN1_
HRTIM_ USART2_RTS/ EVENT
PD4 - - - - - SAI3_FS_A - RXFD_ - - FMC_NOE - -
FLT3 USART2_DE OUT
MODE
DS12930 Rev 1
FDCAN1_
HRTIM_EE USART2_ EVENT
PD5 - - - - - - TXFD_ - - FMC_NWE - -
V3 TX OUT
MODE
FDCAN2_
DFSDM1_ DFSDM1_ SPI3_MOSI USART2_ SAI4_SD_ SDMMC2_ FMC_ EVENT
PD6 - - SAI1_D1 SAI1_SD_A RXFD_ SAI4_D1 DCMI_D10 LCD_B2
CKIN4 DATIN1 /I2S3_SDO RX A CK NWAIT OUT
Port D
MODE
FDCAN2_
DFSDM1_ USART3_ FMC_D14/F EVENT
PD9 - - - - - SAI3_SD_B - RXFD_ - - - -
DATIN3 RX MC_DA14 OUT
MODE
FDCAN2_
DFSDM1_ USART3_ FMC_D15/ EVENT
PD10 - - - - - SAI3_FS_B - TXFD_ - - - LCD_B3
CKOUT CK FMC_DA15 OUT
MODE
STM32H747xI/G
LPTIM1_ QUADSPI_ SAI2_SCK_ EVENT
PD13 - TIM4_CH2 I2C4_SDA - - - FMC_A18 - -
OUT BK1_IO3 A OUT
Table 11. Port D alternate functions (continued)
STM32H747xI/G
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/ SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port TIM1/2/16/ USART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
SAI1/TIM3/ TIM8/LPTI 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
17/LPTIM1 TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/3/6/ /SDMMC2/ UART5/
SYS 4/5/HRTIM M2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
/ LPTIM2/ 5/6/CEC UART4/ UART7/ OTG1_HS/ LCD
1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
HRTIM1 DFSDM1/ DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
CEC LCD
SPDIFRX1 ETH
UART8_
SAI3_MCLK FMC_D1/ EVENT
PD15 - TIM4_CH4 - - - - RTS/UART - - - - -
_A FMC_DA1 OUT
8_DE
DS12930 Rev 1
Pin descriptions
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Table 12. Port E alternate functions
88/242
Pin descriptions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/U SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port SART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
TIM1/2/16/ SAI1/TIM3/ TIM8/LPTIM 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ /SDMMC2/ UART5/
SYS 17/LPTIM1 4/5/HRTIM 2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ OTG1_HS/ LCD
/HRTIM1 1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
DFSDM1/ DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
CEC LCD
SPDIFRX1 ETH
FDCAN1_
LPTIM1_ HRTIM_ LPTIM2_ SAI2_MCLK EVENT
PE0 - TIM4_ETR - - - UART8_RX RXFD_ - FMC_NBL0 DCMI_D2 -
ETR SCIN ETR _A OUT
MODE
FDCAN1_
LPTIM1_ HRTIM_SC EVENT
PE1 - - - - - - UART8_TX TXFD_ - - FMC_NBL1 DCMI_D3 -
IN2 OUT OUT
MODE
UART7_
DFSDM1_C QUADSPI_ FMC_D6/ EVENT
PE9 - TIM1_CH1 - - - - RTS/UART - - - - -
KOUT BK2_IO2 FMC_DA6 OUT
7_DE
STM32H747xI/G
PE13 - TIM1_CH3 - - SPI4_MISO - - - - SAI2_FS_B - LCD_DE
KIN5 FMC_DA10 OUT OUT
TIM1_BKIN
TIM1_ FMC_D12/ _COMP12/ EVENT
PE15 - - - - TIM1_BKIN - - - - - - LCD_R7
BKIN FMC_DA12 COMP_TIM OUT
1_BKIN
Table 13. Port F alternate functions
STM32H747xI/G
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/U SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port SART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
TIM1/2/16/ SAI1/TIM3/ TIM8/LPTIM 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ /SDMMC2/ UART5/
SYS 17/LPTIM1/ 4/5/HRTIM 2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ OTG1_HS/ LCD
HRTIM1 1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
DFSDM1/ DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
CEC LCD
SPDIFRX1 ETH
EVENT
PF0 - - - - I2C2_SDA - - - - - - - FMC_A0 - -
OUT
EVENT
PF1 - - - - I2C2_SCL - - - - - - - FMC_A1 - -
OUT
EVENT
PF2 - - - - I2C2_SMBA - - - - - - - FMC_A2 - -
OUT
EVENT
PF3 - - - - - - - - - - - - FMC_A3 - -
OUT
EVENT
PF4 - - - - - - - - - - - - FMC_A4 - -
OUT
EVENT
DS12930 Rev 1
PF5 - - - - - - - - - - - - FMC_A5 - -
OUT
UART7_
TIM16_ SAI1_SCK_ SAI4_SCK TIM13_CH QUADSPI_ EVENT
PF8 - - - - SPI5_MISO RTS/UART - - - -
CH1N B _B 1 BK1_IO0 OUT
7_DE
EVENT
PF12 - - - - - - - - - - - - FMC_A6 - -
OUT
DFSDM1_D EVENT
PF13 - - - I2C4_SMBA - - - - - - - FMC_A7 - -
ATIN6 OUT
Pin descriptions
DFSDM1_C EVENT
PF14 - - - I2C4_SCL - - - - - - - FMC_A8 - -
KIN6 OUT
EVENT
PF15 - - - - I2C4_SDA - - - - - - - FMC_A9 - -
OUT
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Table 14. Port G alternate functions
90/242
Pin descriptions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/U SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port SART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ /SDMMC2/ UART5/
SYS 7/LPTIM1/ 4/5/HRTIM 2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ OTG1_HS/ LCD
HRTIM1 1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
DFSDM1/ DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
CEC LCD
SPDIFRX1 ETH
EVENT
PG0 - - - - - - - - - - - - FMC_A10 - -
OUT
EVENT
PG1 - - - - - - - - - - - - FMC_A11 - -
OUT
TIM8_BKIN EVENT
PG2 - - - TIM8_BKIN - - - - - - - FMC_A12 - -
_COMP12 OUT
TIM8_BKIN EVENT
PG3 - - - TIM8_BKIN2 - - - - - - - FMC_A13 - -
2_COMP12 OUT
FMC_A15/ EVENT
DS12930 Rev 1
PG5 - TIM1_ETR - - - - - - - - - - - -
FMC_BA1 OUT
USART6_
SPDIFRX1 ETH_PPS_ FMC_SDCL EVENT
PG8 - - - TIM8_ETR - SPI6_NSS - RTS/USAR - - - LCD_G7
_IN3 OUT K OUT
T6_DE
ETH_MII_
LPTIM1_IN HRTIM_ SPI1_SCK/ SPDIFRX1 SDMMC2_ TX_EN/ EVENT
PG11 - - - - - - - DCMI_D3 LCD_B3
2 EEV4 I2S1_CK _IN1 D2 ETH_RMII_ OUT
TX_EN
USART6_
ETH_MII_T
LPTIM1_IN HRTIM_ RTS/ SPDIFRX1 EVENT
PG12 - - SPI6_MISO - LCD_B4 - XD1/ETH_R FMC_NE4 - LCD_B1
1 EEV5 USART6_ _IN2 OUT
MII_TXD1
STM32H747xI/G
DE
USART6_
ETH_MII_T
TRACE LPTIM1_ HRTIM_ CTS/ EVENT
PG13 - - SPI6_SCK - - - - XD0/ETH_R FMC_A24 - LCD_R0
D0 OUT EEV10 USART6_ OUT
MII_TXD0
NSS
Table 14. Port G alternate functions (continued)
STM32H747xI/G
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/U SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port SART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ /SDMMC2/ UART5/
SYS 7/LPTIM1/ 4/5/HRTIM 2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ OTG1_HS/ LCD
HRTIM1 1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
DFSDM1/ DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
CEC LCD
SPDIFRX1 ETH
ETH_MII_
TRACE LPTIM1_ USART6_ QUADSPI_ EVENT
PG14 - - - SPI6_MOSI - - - TXD1/ETH_ FMC_A25 - LCD_B0
D1 ETR TX BK2_IO3 OUT
RMII_TXD1
Port G
USART6_ DCMI_D13
CTS/ FMC_SDNC EVENT
PG15 - - - - - - - - - - - -
USART6_ AS OUT
NSS
DS12930 Rev 1
Pin descriptions
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Table 15. Port H alternate functions
92/242
Pin descriptions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/U SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port SART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ /SDMMC2/ UART5/
SYS 7/LPTIM1/ 4/5/HRTIM 2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ OTG1_HS/ LCD
HRTIM1 1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
DFSDM1/ DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
CEC LCD
SPDIFRX1 ETH
EVENT
PH0 - - - - - - - - - - - - - - -
OUT
EVENT
PH1 - - - - - - - - - - - - - - -
OUT
OTG_HS_ EVENT
PH4 - - - - I2C2_SCL - - - - LCD_G5 - - LCD_G4
ULPI_NXT OUT
FMC_ EVENT
DS12930 Rev 1
DCMI_ EVENT
PH8 - - TIM5_ETR - I2C3_SDA - - - - - - - FMC_D16 LCD_R2
HSYNC OUT
DCMI_D0 EVENT
PH9 - - - - I2C3_SMBA - - - - - - - FMC_D17 LCD_R3
OUT
DCMI_D1 EVENT
PH10 - - TIM5_CH1 - I2C4_SMBA - - - - - - - FMC_D18 LCD_R4
OUT
DCMI_D2 EVENT
PH11 - - TIM5_CH2 - I2C4_SCL - - - - - - - FMC_D19 LCD_R5
OUT
DCMI_D3 EVENT
PH12 - - TIM5_CH3 - I2C4_SDA - - - - - - - FMC_D20 LCD_R6
OUT
FDCAN1_ EVENT
PH13 - - - TIM8_CH1N - - - - UART4_TX - - FMC_D21 - LCD_G2
TX OUT
STM32H747xI/G
FDCAN1_ DCMI_D4 EVENT
PH14 - - - TIM8_CH2N - - - - UART4_RX - - FMC_D22 LCD_G3
RX OUT
STM32H747xI/G
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/U SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port SART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ /SDMMC2/ UART5/
SYS 7/LPTIM1/ 4/5/HRTIM 2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ OTG1_HS/ LCD
HRTIM1 1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
DFSDM1/ DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
CEC LCD
SPDIFRX1 ETH
FDCAN1_ DCMI_D13
SPI2_NSS/ EVENT
PI0 - - TIM5_CH4 - - - - - RXFD_ - - FMC_D24 LCD_G5
I2S2_WS OUT
MODE
DCMI_D6 EVENT
PI6 - - - TIM8_CH2 - - - - - - SAI2_SD_A - FMC_D28 LCD_B6
OUT
DCMI_D7 EVENT
PI7 - - - TIM8_CH3 - - - - - - SAI2_FS_A - FMC_D29 LCD_B7
OUT
Port I
EVENT
PI8 - - - - - - - - - - - - - - -
OUT
FDCAN1_
ETH_MII_ LCD_ EVENT
PI10 - - - - - - - - - RXFD_ - FMC_D31 -
RX_ER HSYNC OUT
MODE
OTG_HS_U EVENT
PI11 - - - - - - - - - LCD_G6 - - -
LPI_DIR OUT
EVENT
PI12 - - - - - - - - - - - - - - LCD_HSY
OUT
NC
Pin descriptions
EVENT
PI13 - - - - - - - - - - - - - - LCD_VSY
OUT
NC
EVENT
PI14 - - - - - - - - - - - - - - LCD_CLK
OUT
93/242
EVENT
PI15 - - - - - - - - - LCD_G2 - - - - LCD_R0
OUT
Table 17. Port J alternate functions
94/242
Pin descriptions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/U SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port SART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ /SDMMC2/ UART5/
SYS 7/LPTIM1/ 4/5/HRTIM 2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ OTG1_HS/ LCD
HRTIM1 1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
DFSDM1/ DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
CEC LCD
SPDIFRX1 ETH
EVENT
PJ0 - - - - - - - - - LCD_R7 - - - - LCD_R1
OUT
EVENT
PJ1 - - - - - - - - - - - - - - LCD_R2
OUT
DSI_TE EVENT
PJ2 - - - - - - - - - - - - - LCD_R3
OUT
EVENT
PJ3 - - - - - - - - - - - - - - LCD_R4
OUT
EVENT
PJ4 - - - - - - - - - - - - - - LCD_R5
OUT
EVENT
DS12930 Rev 1
PJ5 - - - - - - - - - - - - - - LCD_R6
OUT
EVENT
PJ6 - - - TIM8_CH2 - - - - - - - - - - LCD_R7
OUT
EVENT
PJ7 TRGIN - - TIM8_CH2N - - - - - - - - - - LCD_G0
OUT
Port J
EVENT
PJ8 - TIM1_CH3N - TIM8_CH1 - - - - UART8_TX - - - - - LCD_G1
OUT
EVENT
PJ9 - TIM1_CH3 - TIM8_CH1N - - - - UART8_RX - - - - - LCD_G2
OUT
EVENT
PJ10 - TIM1_CH2N - TIM8_CH2 - SPI5_MOSI - - - - - - - - LCD_G3
OUT
EVENT
PJ11 - TIM1_CH2 - TIM8_CH2N - SPI5_MISO - - - - - - - - LCD_G4
OUT
TRGOU EVENT
PJ12 - - - - - - - - LCD_G3 - - - - LCD_B0
T OUT
EVENT
PJ13 - - - - - - - - - LCD_B4 - - - - LCD_B1
OUT
EVENT
STM32H747xI/G
PJ14 - - - - - - - - - - - - - - LCD_B2
OUT
EVENT
PJ15 - - - - - - - - - - - - - - LCD_B3
OUT
Table 18. Port K alternate functions
STM32H747xI/G
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/FDCA I2C4/UART
I2C1/2/3/4/U SAI2/4/TIM
LPUART/ SPI6/SAI2/ N1/FDACN 7/SWPMI1/ TIM1/8/FMC
Port SART1/ SPI2/3/SAI1 SPI2/3/6/ 8/QUADSPI
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM 4/UART4/5/ 2/TIM13/14 TIM1/8/ /SDMMC1/ TIM1/DCMI/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ /SDMMC2/ UART5/
SYS 7/LPTIM1/ 4/5/HRTIM 2/3/4/5/ 8/LPUART/ /QUADSPI/ DFSDM1/ MDIOS/ LCD/DSI/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ OTG1_HS/ LCD
HRTIM1 1 HRTIM1/ SDMMC1/ FMC/SDM SDMMC2/ OTG1_FS/ COMP
DFSDM1/ DFSDM1 SDMMC1 OTG2_FS/
DFSDM1 SPDIFRX1 MC2/LCD/ MDIOS/ LCD
CEC LCD
SPDIFRX1 ETH
EVENT
PK0 - TIM1_CH1N - TIM8_CH3 - SPI5_SCK - - - - - - - - LCD_G5
OUT
EVENT
PK1 - TIM1_CH1 - TIM8_CH3N - SPI5_NSS - - - - - - - - LCD_G6
OUT
EVENT
PK3 - - - - - - - - - - - - - - LCD_B4
OUT
Port K
EVENT
PK4 - - - - - - - - - - - - - - LCD_B5
OUT
EVENT
DS12930 Rev 1
PK5 - - - - - - - - - - - - - - LCD_B6
OUT
EVENT
PK6 - - - - - - - - - - - - - - LCD_B7
OUT
EVENT
PK7 - - - - - - - - - - - - - - LCD_DE
OUT
Pin descriptions
95/242
Electrical characteristics STM32H747xI/G
6 Electrical characteristics
Figure 11. Pin loading conditions Figure 12. Pin input voltage
C = 50 pF VIN
MS19011V2 MS19010V2
VCAPDSI(1)
VDD33USB VDD50USB
VDD12DSI
100 nF
100 nF
2.2 μF
VDDDSI
VSSDSI
VDD33USB VDD50USB
VSS USB
IOs
VDDSMPS Step
VLXSMPS USB DSI DSI
Down VSS
regulator PHY regulator
VFBSMPS Coverter
VSSSMPS (SMPS)
VDDLDO
VCAP
Core domain (VCORE)
2 x 2.2 μF
VDDLDO Voltage
4..7μF
regulator
Power
Power
switch
switch
VSS
D3 domain
(System
Level shifter
logic, D1 domain
IO EXTI, D2 domain (CPU, peripherals,
IOs (peripherals, RAM)
logic Peripherals,
RAM) RAM) Flash
VDD
VSS
N(1) x 100 nF
VDD domain
+ 1 x 4.7 μF
HSI, CSI,
VDD
HSI48,
VBAT HSE, PLLs Backup domain
charging
VBAT VSW Backup VBKP
1.2 to 3.6V VBAT regulator
Power switch
Power switch
LSI, LSE,
RTC, Wakeup
Backup
logic, backup
BKUP IO RAM
registers,
IOs logic Reset
VREF
VDDA VSS
VDDA VSS
Analog domain
100 nF + 1 x 1 μF
100 nF + 1 x 1 μF
MSv62410V2
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
ΣIVDD (1)
Total current into sum of all VDD power lines (source) 620
ΣIVSS Total current out of sum of all VSS ground lines (sink)(1) 620
IVDD Maximum current into each VDD power pin (source)(1) 100
(1)
IVSS Maximum current out of each VSS ground pin (sink) 100
IIO Output current sunk by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins(2) 140 mA
ΣI(PIN)
Total output current sourced by sum of all I/Os and control pins(2) 140
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
−5/+0
IINJ(PIN) (3)(4) PA5
Injected current on PA4, PA5 −0/0
ΣIINJ(PIN) Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 19: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
VOS3 - - 200
VOS2 - - 300
fCPU1 Arm® Cortex®-M7 clock frequency
VOS1 - - 400
VOS0 - - 480(6)
VOS3 - - 200
VOS2 - - 150
fCPU2 Arm® Cortex®-M4 clock frequency
VOS1 - - 200
VOS0 - - 240(6)
VOS3 - - 100
VOS2 - - 150
fACLK AXI clock frequency MHz
VOS1 - - 200
VOS0 - - 240(6)
VOS3 - - 100
VOS2 - - 150
fHCLK AHB clock frequency
VOS1 - - 200
VOS0 - - 240(6)
VOS3 - - 50(8)
VOS2 - - 75
fPCLK APB clock frequency
VOS1 - - 100
VOS0 - - 120(6)
1. When RESET is released functionality is guaranteed down to VBOR0 min
2. Only for power-up sequence when the SMPS step-down converter is configured to supply the LDO and TJMax = 105 °C.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
4. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must
be disabled.
5. VOS0 is available only when the LDO regulator is ON.
6. TJmax = 105 °C.
7. At startup, the external VCORE voltage must remain higher or equal to 1.10 V before disabling the internal regulator (LDO).
8. Maximum APB clock frequency when at least one peripheral is enabled.
ESR
R Leak
MS19044V2
VVDD VDDSMPS
VDDSMPS VVDD VDDSMPS
VDDSMPS
DD DD
Cin L VLXSMPS
VLXSMPS Cin L VLXSMPS
VLXSMPS
SMPS
SMPS SMPS
SMPS
P
VFBSMPS Cfilt VFBSMPS Cfilt
VFBSMPS (ON)
(ON) VVDD_ VFBSMPS (ON)
(ON
N)
DD_
External
External
Cout1 2xCout
VSSSMPS
VSSSMPS VSSSMPS
VSSSMPS
VCAP
VCAP VCAP
VCAP
VDDLDO
VDDLDO VVCORE
CORE
VDDLDO
VDDLDO VVCORE
CORE
Cout2 VV reg
reg CEXT VV reg
reg
VSS
VSS (OFF)
(OFF) VSS
VSS (ON)
(ON)
Reset temporization
tRSTTEMPO(1) - - 377 - µs
after BOR0 released
Rising edge(1) 1.62 1.67 1.71
VBOR0 Brown-out reset threshold 0
Falling edge 1.58 1.62 1.68
Rising edge 2.04 2.10 2.15
VBOR1 Brown-out reset threshold 1
Falling edge 1.95 2.00 2.06
Rising edge 2.34 2.41 2.47
VBOR2 Brown-out reset threshold 2
Falling edge 2.25 2.31 2.37
Rising edge 2.63 2.70 2.78
VBOR3 Brown-out reset threshold 3
Falling edge 2.54 2.61 2.68
VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 1FF1E860 - 1FF1E861
Table 31. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Cortex-M7 core, and Flash memory for Cortex-M4
(ART accelerator ON), LDO regulator ON(1)(2)
Arm Arm Max(3)
Cortex- Cortex-
Symbol Parameter Conditions M7 M4 Typ Unit
Tj= Tj= Tj= Tj=
fCPU1 fCPU2
25 °C 85 °C 105°C 125°C
(MHz) (MHz)
Table 32. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Arm Cortex-M7 and Flash memory for Arm Cortex-M4,
ART accelerator ON, SMPS regulator(1)
Arm Arm Max
Cortex- Cortex-
Symbol Parameter Conditions M7 M4 Typ Unit
Tj= Tj= Tj= Tj=
fCPU1 fCPU2 25 °C 85 °C 105°C 125°C
(MHz) (MHz)
Table 33. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache ON,
ART accelerator ON, LDO regulator ON(1)
Arm Arm Max(2)
Cortex Cortex-
Symbol Parameter Conditions -M7 M4 Typ Unit
Tj= Tj= Tj= Tj=
fCPU1 fCPU2
25 °C 85 °C 105°C 125°C
(MHz) (MHz)
Table 34. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache OFF,
ART accelerator OFF, LDO regulator ON(1)
Arm Arm Max(2)
Cortex- Cortex-
Symbol Parameter Conditions M7 M4 Typ Unit
Tj= Tj= Tj= Tj=
fCPU1 fCPU2
25 °C 85 °C 105°C 125°C
(MHz) (MHz)
Table 35. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, only Arm Cortex-M7 running, LDO regulator ON(1)(2)
Max(3)
fCPU1
Symbol Parameter Conditions Typ Unit
(MHz) Tj=25 Tj=85 Tj=105 Tj=125
°C °C °C °C
Table 36. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, only Arm Cortex-M7 running, SMPS regulator(1)
Max
fCPU1
Symbol Parameter Conditions Typ Unit
(MHz) Tj=25 Tj=85 Tj=105 Tj=125
°C °C °C °C
Table 37. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M7 running, cache ON,
LDO regulator ON(1)
Max(2)
fCPU1
Symbol Parameter Conditions Typ Unit
(MHz) Tj=25 Tj=85 Tj=105 Tj=125
°C °C °C °C
Table 38. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M7 running, cache OFF,
LDO regulator ON(1)
Max(2)
fCPU1
Symbol Parameter Conditions Typ Unit
(MHz) Tj=105 Tj=125
Tj=25°C Tj=85°C
°C °C
Table 39. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON
Max(1)
fHCLK
Symbol Parameter Conditions Typ Unit
(MHz) Tj=105 Tj=125
Tj=25°C Tj=85°C
°C °C
Table 40. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M4 running, ART accelerator ON,
LDO regulator ON(1)
Max(2)
fCPU2
Symbol Parameter Conditions Typ Unit
(MHz) Tj=25 Tj=85 Tj=105 Tj=125
°C °C °C °C
Table 41. Typical and maximum current consumption in Run mode, code with data processing
running from Flash bank 2, only Arm Cortex-M4 running, ART accelerator ON,
SMPS regulator(1)
Max
Symbol Parameter Conditions Typ Unit
Tj=25 Tj=85 Tj=105 Tj=125
°C °C °C °C
Table 42. Typical and maximum current consumption in Stop, LDO regulator ON(1)
Max(2)
Symbol Parameter Conditions Typ Unit
Tj=105 Tj=125
Tj=25°C Tj=85°C
°C °C
Table 43. Typical and maximum current consumption in Stop, SMPS regulator(1)
Max
Symbol Parameter Conditions Typ Unit
Tj=105 Tj=125
Tj=25°C Tj=85°C
°C °C
Table 44. Typical and maximum current consumption in Sleep mode, LDO regulator (1)
Max(2)
fHCLK
Symbol Parameter Conditions Typ Unit
(MHz) Tj=25 Tj=85 Tj=105 Tj=125
°C °C °C °C
Table 45. Typical and maximum current consumption in Sleep mode, SMPS regulator(1)
Max
fHCLK
Symbol Parameter Conditions Typ Unit
(MHz) Tj=25 Tj=85 Tj=105 Tj=125
°C °C °C °C
3V
Symbol Parameter RTC Unit
Backup
and 1.2 V 2V 3V 3.4 V
SRAM Tj=25 Tj=85 Tj=105 Tj=125
LSE
°C °C °C °C
Figure 17. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = 30 °C
100
90
80
70
VDDSMPS =
60
1.8V, VOS1
VDDSMPS =
3.3V, VOS1
50
VDDSMPS =
1.8V, VOS2
VDDSMPS =
40 3.3V, VOS2
VDDSMPS =
1.8V, VOS3
30 VDDSMPS =
3.3V, VOS3
20
10
0
0.001 0.01 0.1 1
MSv62424V1
Figure 18. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = TJmax
100
90
80
70
VDDSMPS =
60
1.8V, VOS1
VDDSMPS =
3.3V, VOS1
50
VDDSMPS =
1.8V, VOS2
VDDSMPS =
40 3.3V, VOS2
VDDSMPS =
1.8V, VOS3
30 VDDSMPS =
3.3V, VOS3
20
10
0
0.001 0.01 0.1 1
MSv62425V1
Figure 19. Typical SMPS efficiency (%) vs load current (A) in low-power mode at
TJ = 30 °C
°
100
90
80
70
VDDSMPS =
60
1.8V, SVOS5
VDDSMPS =
3.3V, SVOS5
50
VDDSMPS =
1.8V, SVOS4
VDDSMPS =
40 3.3V, SVOS4
VDDSMPS =
1.8V, SVOS3
30 VDDSMPS =
3.3V, SVOS3
20
10
0
0.00001 0.0001 0.001 0.01 0.1
MSv62426V1
Figure 20. Typical SMPS efficiency (%) vs load current (A) in low-power mode at
TJ = TJmax
100
90
80
70
VDDSMPS =
60
1.8V, SVOS5
VDDSMPS =
3.3V, SVOS5
50
VDDSMPS =
1.8V, SVOS4
VDDSMPS =
40 3.3V, SVOS4
VDDSMPS =
1.8V, SVOS3
30 VDDSMPS =
3.3V, SVOS3
20
10
0
0.00001 0.0001 0.001 0.01 0.1
MSv62427V1
I SW = V DDx × f SW × C L
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDx is the MCU supply voltage
fSW is the I/O switching frequency
CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
CPU
tWUSLEEP(3) Wakeup from Sleep - 9 10 clock
cycles
VOS3, HSI, Flash memory in normal mode 4.4 5.6
VOS3, HSI, Flash memory in low-power
12 15
mode
VOS4, HSI, Flash memory in normal mode 15 20
VOS4, HSI, Flash memory in low-power
23 28
mode
VOS5, HSI, Flash memory in normal mode 39 71
VOS5, HSI, Flash memory in low-power
39 47
mode
(3)
tWUSTOP Wakeup from Stop
VOS3, CSI, Flash memory in normal mode 30 37
VOS3, CSI, Flash memory in low power
36 50
mode µs
VOS4, CSI, Flash memory in normal mode 38 48
VOS4, CSI, Flash memory in low-power
47 61
mode
VOS5, CSI, Flash memory in normal mode 68 75
VOS5, CSI, Flash memory in low-power
68 77
mode
tWUSTOP_ Wakeup from Stop, VOS3, HSI, Flash memory in normal mode 2.6 3.4
(3)
KERON clock kept running VOS3, CSI, Flash memory in normal mode 26 36
VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t
THSE
External fHSE_ext
IL
clock source OSC_IN
STM32
ai17528b
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t
TLSE
External fLSE_ext
OSC32_IN IL
clock source
STM32
ai17529b
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 23). CL1 and CL2 are usually
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MHz RF controlled
resonator
gain
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Resonator with
integrated capacitors
CL1
OSC32_IN fLSE
Bias
32.768 kH z RF controlled
resonator
gain
OSC32_OU T STM32
CL2
ai17531b
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
VDD=3.3 V,
fHSI48 HSI48 frequency 47.5(1) 48 48.5(1) MHz
TJ=30 °C
TRIM(2) USER trimming step - - 0.175 - %
USER TRIM
USER TRIMMING Coverage ± 32 steps ±4.79 ±5.60 - %
COVERAGE(3)
DuCy(HSI48)(2) Duty Cycle - 45 - 55 %
Accuracy of the HSI48 oscillator over
ACCHSI48_REL(3)(4) TJ=-40 to 125 °C –4.5 - 3.5 %
temperature (factory calibrated)
5. These values are obtained by using the formula: (Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) /
Freq(1.62V).
6. Jitter measurements are performed without clock source activated in parallel.
Figure 25. MIPI D-PHY HS/LP clock lane transition timing diagram
TCLK-POST TEOT
Clock VIL
Lane
Data VIL
Lane
MS38282V1
Figure 26. MIPI D-PHY HS/LP data lane transition timing diagram
Clock
Lane
TLPX THS-PREPARE THS-ZERO
Data
VIL
Lane
TREOT
LP-11 LP-01 LP-00 TEOT
THS-TRAIL THS-EXIT
MS38283V1
CEXT = 2.2 µF - 80 -
tWAKEUP Startup delay µs
CEXT = 3.3 µF - - 160
IINRUSH Inrush current on VDDDSI External capacitor load at start - 60 250 mA
1. Based on test during characterization.
2. CEXT recommended value is 2.2 μF to achieve a better dynamic performance of the regulator. A 1 μF capacitor can be
used only if the minimum value does not drop below 0.5 μF.
Table 64. Flash memory programming (single bank configuration nDBANK=1) (continued)
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
Program parallelism x 8
Program parallelism x 16 1.62 - 3.6
Vprog Programming voltage V
Program parallelism x 32
Program parallelism x 64 1.8 - 3.6
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 10K erase operations.
0.1 to 30 MHz 11
30 to 130 MHz 6
VDD = 3.6 V, TA = 25 °C, UFBGA240 package, dBµV
SEMI Peak level 130 MHz to 1 GHz 12
conforming to IEC61967-2
1 GHz to 2 GHz 7
EMI Level 2.5 -
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15,
5 0
PJ12, PB4
PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11 0 NA
IINJ mA
PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4,
0 0
PA5, PH4, PH5, BOOT0
All other I/Os 5 NA
1. Guaranteed by characterization.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 27.
2.5
-0.1
0.4VDD
VILmax=
n s im ulation
1 Based
o =0.3VDD
ment: VIL
max
require
CMOS
TLL requirement: VILmin = 0.8 V
0.5
0
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
MSv46121V3
Table 72. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8(1)
Symbol Parameter Conditions(3) Min Max Unit
CMOS port(2)
VOL Output low level voltage IIO=8 mA - 0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
VOH Output high level voltage IIO=-8 mA VDD−0.4 -
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOL(3) Output low level voltage IIO=8 mA - 0.4
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOH (3) Output high level voltage IIO=-8 mA 2.4 -
2.7 V≤ VDD ≤3.6 V
V
IIO=20 mA
VOL(3) Output low level voltage - 1.3
2.7 V≤ VDD ≤3.6 V
IIO=-20 mA
VOH(3) Output high level voltage VDD−1.3 -
2.7 V≤ VDD ≤3.6 V
IIO=4 mA
VOL(3) Output low level voltage - 0.4
1.62 V≤ VDD ≤3.6 V
IIO=-4 mA
VOH (3) Output high level voltage VDD−-0.4 -
1.62 V≤VDD<3.6 V
IIO= 20 mA
- 0.4
Output low level voltage for an FTf 2.3 V≤ VDD≤3.6 V
VOLFM+(3)
I/O pin in FM+ mode IIO= 10 mA
- 0.4
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
Table 73. Output voltage characteristics for PC13, PC14, PC15 and PI8(1)
Symbol Parameter Conditions(3) Min Max Unit
CMOS port(2)
VOL Output low level voltage IIO=3 mA - 0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
VOH Output high level voltage IIO=-3 mA VDD−0.4 -
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOL(3) Output low level voltage IIO=3 mA - 0.4
V
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOH (2)
Output high level voltage IIO=-3 mA 2.4 -
2.7 V≤ VDD ≤3.6 V
IIO=1.5 mA
VOL(2) Output low level voltage - 0.4
1.62 V≤ VDD ≤3.6 V
IIO=-1.5 mA
VOH(2) Output high level voltage VDD−0.4 -
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter
0.1 μF
STM32
ai14132d
Refer to Section 6.3.18: I/O port characteristics for more details on the input/output alternate
function characteristics.
tw(NE)
FMC_NE
FMC_NOE
FMC_NWE
tv(A_NE) t h(A_NOE)
FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)
FMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE) th(Data_NOE)
t su(Data_NE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
FMC_NEx
FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)
FMC_NWE
tv(A_NE) th(A_NWE)
FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)
FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
FMC_ NE
tv(NOE_NE) t h(NE_NOE)
FMC_NOE
t w(NOE)
FMC_NWE
tv(A_NE) th(A_NOE)
t v(NADV_NE) th(AD_NADV)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_CLK maximum values:
• For 2.7 V<VDD<3.6 V, FMC_CLK = 125 MHz at 20 pF
• For 1.8 V<VDD<1.9 V, FMC_CLK = 100 MHz at 20 pF
• For 1.62 V<VDD<1.8 V, FMC_CLK = 100 MHz at 15 pF
FMC_CLK
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:16]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)
FMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32757V1
FMC_CLK
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:16]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
td(CLKH-NBLH)
FMC_NBL
MS32758V1
2Tfmc_ker_ck –1
tw(CLK) FMC_CLK period, VDD = 2.7 to 3.6 V -
1
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x =0..2) - 1
FMC_CLK high to FMC_NEx high
td(CLKH-NExH) Tfmc_ker_ck +0.5 -
(x = 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
FMC_CLK low to FMC_Ax valid
td(CLKL-AV) - 2
(x =16…25)
FMC_CLK high to FMC_Ax invalid
td(CLKH-AIV) Tfmc_ker_ck -
(x =16…25)
Ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck +0.5 -
td(CLKL-ADV) FMC_CLK low to to FMC_AD[15:0] valid - 2.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
FMC_A/D[15:0] valid data after FMC_CLK
td(CLKL-DATA) - 2.5
low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck +0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 -
1. Guaranteed by characterization results.
tw(CLK) tw(CLK)
FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:0]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)
FMC_D[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32759V1
FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:0]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-Data) td(CLKL-Data)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL
MS32760V1
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
td(ALE-NOE) th(NOE-ALE)
FMC_NOE (NRE)
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
MS32767V1
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) th(NWE-ALE)
FMC_NWE
FMC_NOE (NRE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MS32768V1
Figure 38. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)
FMC_NWE
tw(NOE)
FMC_NOE
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
MS32769V1
Figure 39. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) tw(NWE) th(NOE-ALE)
FMC_NWE
FMC_N OE
td(D-NWE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MS32770V1
FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)
th(SDCLKL_AddC)
td(SDCLKL_SNDE) th(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)
FMC_SDNRAS
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
FMC_SDNCAS
FMC_SDNWE
tsu(SDCLKH_Data) th(SDCLKH_Data)
MS32751V2
2Tfmc_ker_ck
tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 1
+0.5
tsu(SDCLKH _Data) Data input setup time 2 -
th(SDCLKH_Data) Data input hold time 1 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL- SDNE) Chip select valid time - 1.5 ns
th(SDCLKL_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
1. Guaranteed by characterization results.
FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)
th(SDCLKL_AddC)
td(SDCLKL_SNDE) th(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)
FMC_SDNRAS
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
FMC_SDNCAS
td(SDCLKL_NWE) th(SDCLKL_NWE)
FMC_SDNWE
td(SDCLKL_Data)
td(SDCLKL_NBL) th(SDCLKL_Data)
FMC_NBL[3:0]
MS32752V2
2.7<VDD<3.6 V
- - 133
QUADSPI clock CL = 20 pF
Fck11/TCK MHz
frequency 1.62<VDD<3.6 V
- - 100
CL = 15 pF
2.7<VDD<3.6 V
- - 100
CL = 20 pF
Fck11/TCK QUADSPI clock frequency MHz
1.62<VDD<3.6 V
- - 100
CL = 15 pF
tw(CKH) QUADSPI clock high and PRESCALER[7:0] = TCK/2–0.5 - TCK/2
tw(CKL) low time Even division n = 0,1,3,5... TCK/2 - TCK/2+0.5
(n/2)*TCK/ (n/2)*TCK/
tw(CKH) -
QUADSPI clock high and PRESCALER[7:0] = (n+1)-0.5 (n+1)
low time Odd division n = 2,4,6,8... (n/2+1)*TCK/ (n/2+1)*TCK /
tw(CKL) -
(n+1) (n+1)+0.5
tsr(IN), tsf(IN) Data input setup time - 1.5 - -
thr(IN),thf(IN) Data input hold time - 3.5 - - ns
DHHC=0 - 5 6
tvr(OUT), DHHC=1
Data output valid time
tvf(OUT) PRESCALER[7:0] = - TCK/4+1 TCK/4+2
1,2…
DHHC=0 3 - -
thr(OUT), DHHC=1
Data output hold time
thf(OUT) PRESCALER[7:0]=1 TCK/4 - -
,2…
1. Guaranteed by characterization results.
Clock
tv(OUT) th(OUT)
Data output D0 D1 D2
ts(IN) th(IN)
Data input D0 D1 D2
MSv36878V1
Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output D0 D1 D2 D3 D4 D5
Data input D0 D1 D2 D3 D4 D5
MSv36879V1
Analog supply
VDDA voltage for ADC - 1.62 - 3.6 V
ON
Positive reference
VREF+ - 1.62 - VDDA V
voltage
Negative
VREF- - VSSA V
reference voltage
BOOST = 11 0.12 - 50
BOOST = 10 0.12 - 25
ADC clock
fADC 1.62 V ≤ VDDA ≤ 3.6 V MHz
frequency
BOOST = 01 0.12 - 12.5
BOOST = 00 - - 6.25
Resolution = 16 bits,
fADC=36 MHz SMP = 1.5 - - 3.60
VDDA >2.5 V TJ = 90 °C
Resolution = 16 bits fADC=37 MHz SMP = 2.5 - - 3.35
Sampling rate for Resolution = 14 bits fADC = 50 MHz SMP = 2.5 - - 5.00
Direct channels(4)
Resolution = 12 bits fADC = 50 MHz SMP = 2.5 - - 5.50
TJ = 125 °C
Resolution = 10 bits fADC = 50 MHz SMP = 1.5 - - 7.10
Resolution = 16 bits,
fADC=32 MHz SMP = 2.5 - - 2.90
VDDA >2.5 V TJ = 90 °C
Resolution = 16 bits fADC=31 MHz SMP = 2.5 - - 2.80
fs(3) MSps
Sampling rate for Resolution = 14 bits fADC = 33 MHz SMP = 2.5 - - 3.30
Fast channels
Resolution = 12 bits fADC = 39 MHz SMP = 2.5 - - 4.30
TJ = 125 °C
Resolution = 10 bits fADC = 48 MHz SMP = 2.5 - - 6.00
Resolution = 16 bits TJ = 90 °C - -
resolution = 14 bits - -
Sampling rate for
resolution = 12 bits fADC = 10 MHz SMP = 1.5 - - 1.00
Slow channels
TJ = 125 °C
resolution = 10 bits - -
resolution = 8 bits - -
External trigger 1/
tTRIG Resolution = 16 bits - - 10
period fADC
Conversion
VAIN(5) - 0 - VREF+ V
voltage range
Internal sample
CADC and hold - - 4 - pF
capacitor
conver
ADC Power-up
tSTAB LDO already started 1 - - sion
time
cycle
Offset and
tCAL linearity - 165010 - - 1/fADC
calibration time
Total conversion
ts + 0.5
tCONV time (including Resolution = N bits - - 1/fADC
+ N/2
sampling time)
fADC=3.125 MHz - - - 80 -
1. Guaranteed by design.
2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
3. These values are valid for UFBGA169 and one ADC. The values for other packages and multiple ADCs may be different.
4. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
5. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.
6. The tolerance is 10 LSBs for 16-bit resolution, 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions.
Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 6.3.17 does not affect the ADC accuracy.
(2)
ET
7 (3)
(1)
6
5
EO EL
4
3
ED
2
1L SBIDEAL
1
0
1 2 3 456 7 4093 4094 4095 4096
V SSA VDDA
ai14395c
VDD STM32
Sample and hold ADC
VT converter
0.6 V
RAIN(1) AINx RADC(1)
12-bit
converter
VT
VAIN
0.6 V C ADC(1)
Cparasitic
IL±1 μA
ai17534b
Figure 46. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32
VREF+(1)
1 μF // 100 nF
VDDA
1 μF // 100 nF
VSSA/VREF+(1)
MSv50648V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.
Figure 47. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32
VREF+/VDDA(1)
1 μF // 100 nF
VREF-/VSSA(1)
MSv50649V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.
No load,
middle µA
- 170 -
code
DAC output buffer (0x800)
ON
No load,
worst code - 170 -
(0xF1C)
No load,
DAC consumption from
IDDV(DAC) DAC output buffer middle/wor
VREF+ - 160 -
OFF st code
(0x800)
170*TON/
Sample and Hold mode, Buffer
- (TON+TOFF) -
ON, CSH=100 nF (worst code) (4)
160*TON/
Sample and Hold mode, Buffer
- (TON+TOFF) -
OFF, CSH=100 nF (worst code) (4)
Buffered/Non-buffered DAC
Buffer(1)
RL
12-bit DAC_OUTx
digital to
analog
converter
CL
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
VBRS in PWR_CR3= 0 - 5 -
RBC Battery charging resistor KΩ
VBRS in PWR_CR3= 1 1.5 -
CLOAD ≤ 50pf,
Normal RLOAD ≥ 4 kΩ,
- 0.8 3.2
mode follower
Wake up time from OFF configuration
tWAKEUP µs
state CLOAD ≤ 50pf,
High
RLOAD ≥ 4 kΩ,
speed - 0.9 2.8
follower
mode
configuration
PGA gain = 2 −1 - 1
Gain=2 - GBW/2 -
DFSDM
fDFSDMCLK 1.62 < VDD < 3.6 V - - 133
clock
SPI mode (SITP[1:0]=0,1),
External clock mode
- - 20
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1),
External clock mode
- - 20
(SPICKSEL[1:0]=0),
fCKIN Input clock 2.7 < VDD < 3.6 V MH
(1/TCKIN) frequency SPI mode (SITP[1:0]=0,1), z
Internal clock mode
- - 20
(SPICKSEL[1:0]¹0),
1.62 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1),
Internal clock mode
- - 20
(SPICKSEL[1:0]¹0),
2.7 < VDD < 3.6 V
Output clock
fCKOUT 1.62 < VDD < 3.6 V - - 20
frequency
Output clock
DuCyCKOU
frequency 1.62 < VDD < 3.6 V 45 50 55 %
T duty cycle
SPI mode (SITP[1:0]=0,1),
Input clock
twh(CKIN) External clock mode
high and low TCKIN/2-0.5 TCKIN/2 -
twl(CKIN) (SPICKSEL[1:0]=0),
time
1.62 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1),
Data input External clock mode
tsu 1.5 - -
setup time (SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
ns
SPI mode (SITP[1:0]=0,1),
Data input External clock mode
th 0.5 - -
hold time (SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Manchester Manchester mode (SITP[1:0]=2,3),
data period Internal clock mode (CKOUTDIV+1) (2*CKOUTDIV)
TManchester -
(recovered (SPICKSEL[1:0]¹0), * TDFSDMCLK * TDFSDMCLK
clock period) 1.62 < VDD < 3.6 V
DFSDM_CKINy (SPICKSEL=0)
SPI timing : SPICKSEL = 0
twl twh tr tf
tsu th
DFSDM_DATINy
SITP = 00
tsu th
SITP = 01
SPICKSEL=3
DFSDM_CKOUT
SPICKSEL=2
SPI timing : SPICKSEL = 1, 2, 3
SPICKSEL=1
twl twh tr tf
tsu th
DFSDM_DATINy
SITP = 0
tsu th
SITP = 1
SITP = 2
DFSDM_DATINy
Manchester timing
SITP = 3
recovered clock
recovered data 0 0 1 1 0
MS30766V2
1/DCMI_PIXCLK
DCMI_PIXCLK
tsu(HSYNC) th(HSYNC)
DCMI_HSYNC
tsu(VSYNC) th(HSYNC)
DCMI_VSYNC
tsu(DATA) th(DATA)
DATA[0:13]
MS32414V2
2.7<VDD<3.6 V
150
LTDC clock 20pF
fCLK output - MHz
frequency 2.7<VDD<3.6 V 133
1.62<VDD<3.6 V 90
DCLK LTDC clock output duty cycle 45 55 %
tw(CLKH),
Clock High time, low time tw(CLK)//2-0.5 tw(CLK)//2+0.5
tw(CLKL)
tv(DATA) 2.7<VDD<3.6 V 0.5 -
Data output valid time -
th(DATA) 1.62<VDD<3.6 V 5
tv(DATA) Data output hold time 0 -
tv(HSYNC), 2.7<VDD<3.6 V - 0.5
HSYNC/VSYNC/DE output
tv(VSYNC),
valid time 1.62<VDD<3.6 V - 5
tv(DE)
th(HSYNC),
th(VSYNC), HSYNC/VSYNC/DE output hold time 0 -
th(DE)
1. Guaranteed by characterization results.
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC) tv(HSYNC)
LCD_HSYNC
tv(DE) th(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7] Pixel Pixel Pixel
1 2 N
LCD_B[0:7]
th(DATA)
One line
MS32749V1
tCLK
LCD_CLK
tv(VSYNC) tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7] M lines data
LCD_B[0:7]
One frame
MS32750V1
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK = 1 - tTIMxCLK
240 MHz
tres(TIM) Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK = 1 - tTIMxCLK
120 MHz
Timer external clock
fEXT 0 fTIMxCLK/2 MHz
frequency on CH1 to CH4 f
TIMxCLK = 240 MHz
ResTIM Timer resolution - 16/32 bit
Maximum possible count 65536 ×
tMAX_COUNT - - tTIMxCLK
with 32-bit counter 65536
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 240 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
Frcc_pclkx_d2.
Standard-mode - 2
Analog Filtre ON
8
DNF=0
Fast-mode
Analog Filtre OFF MHz
I2CCLK 9
f(I2CCLK) DNF=1
frequency
Analog Filtre ON
17
DNF=0
Fast-mode Plus
Analog Filtre OFF
16 -
DNF=1
The SDA and SCL I/O requirements are met with the following restrictions:
• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDDIOx is disabled, but still present.
• The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load CLoad supported in Fm+, which is given by these formulas:
tr(SDA/SCL)=0.8473xRPxCLoad
RP(min)= (VDD-VOL(max))/IOL(max)
Where RP is the I2C lines pull-up. Refer to Section 6.3.18: I/O port characteristics for
the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog fil-
ter characteristics:
Refer to Section 6.3.18: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).
High
NSS input
tc(SCK)
SCK Output
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
MSB OUT B I T1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
ai14136c
NSS input
tc(SCK) th(NSS)
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MSv41658V1
Master mode
1.62<VDD<3.6 V 80
SPI1, 2, 3
Master mode
2.7<VDD<3.6 V 100
SPI1, 2, 3
Master mode
fSCK SPI clock frequency 1.62<VDD<3.6 V - - 50 MHz
SPI4, 5, 6
Slave receiver mode
100
1.62<VDD<3.6 V
Slave mode transmitter/full duplex
31
2.7<VDD<3.6 V
Slave mode transmitter/full duplex
29
1.62 <VDD<3.6 V
tsu(NSS) NSS setup time Slave mode 2 - -
th(NSS) NSS hold time Slave mode 1 - -
-
tw(SCKH),
SCK high and low time Master mode TPCLK-2 TPCLK TPCLK+2
tw(SCKL)
NSS input
tc(SCK) th(NSS)
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MSv41658V1
Figure 56. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tc(SCK)
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MSv41659V1
High
NSS input
tc(SCK)
SCK Output
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
MSB OUT B I T1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
ai14136c
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
SAI characteristics
Unless otherwise specified, the parameters given in Table 121 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 22: General operating conditions, with the following
configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• IO Compensation cell activated.
• Measurement points are done at CMOS levels: 0.5VDD
• VOS level set to VOS1.
Refer to Section 6.3.18: I/O port characteristics for more details on the input/output
alternate function characteristics (SCK,SD,WS).
Master mode
- 13
2.7≤VDD≤3.6
tv(FS) FS valid time
Master mode
- 20
1.62≤VDD≤3.6
tsu(FS) FS hold time Master mode 8 -
FS setup time Slave mode 1 -
th(FS)
FS hold time Slave mode 1 -
tsu(SD_A_MR) Master receiver 0.5 -
Data input setup time
tsu(SD_B_SR) Slave receiver 1 -
th(SD_A_MR) Master receiver 3.5 -
Data input hold time
th(SD_B_SR) Slave receiver 2 -
Slave transmitter (after enable
edge) - 14 ns
2.7≤VDD≤3.6
tv(SD_B_ST) Data output valid time
Slave transmitter (after enable
edge) - 20
1.62≤VDD≤3.6
Slave transmitter (after enable
th(SD_B_ST) Data output hold time 9 -
edge)
Master transmitter (after enable
edge) - 12
2.7≤VDD≤3.6
tv(SD_A_MT) Data output valid time
Master transmitter (after enable
edge) - 19
1.62≤VDD≤3.6
Master transmitter (after enable
th(SD_A_MT) Data output hold time 7.5 -
edge)
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With FS=192 kHz.
SAI_SCK_X
th(FS)
SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)
SAI_SD_X Slot n
(receive)
MS32771V1
SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)
SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)
SAI_SD_X Slot n
(receive)
MS32772V1
MDIO characteristics
td(MDIO)
tsu(MDIO) th(MDIO)
MSv40460V1
Table 123. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V(1)(2) (continued)
Symbol Parameter Conditions Min Typ Max Unit
CK
tOVD tOHD
D, CMD
(output)
ai14888
Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output D0 D1 D2 D3 D4 D5
Data input D0 D1 D2 D3 D4 D5
MSv36879V1
Clock
tSC tHC
Control In
(ULPI_DIR,
ULPI_NXT) tSD tHD
data In
(8-bit)
tDC tDC
Control out
(ULPI_STP)
tDD
data out
(8-bit)
ai17361c
Table 126. Dynamics characteristics: Ethernet MAC signals for SMI (1)
Symbol Parameter Min Typ Max Unit
ETH_MDC
td(MDIO)
ETH_MDIO(O)
tsu(MDIO) th(MDIO)
ETH_MDIO(I)
MS31384V1
Table 127. Dynamics characteristics: Ethernet MAC signals for RMII (1)
Symbol Parameter Min Typ Max Unit
RMII_REF_CLK
td(TXEN)
td(TXD)
RMII_TX_EN
RMII_TXD[1:0]
tsu(RXD) tih(RXD)
tsu(CRS) tih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
Table 128. Dynamics characteristics: Ethernet MAC signals for MII (1)
Symbol Parameter Min Typ Max Unit
MII_RX_CLK
tsu(RXD) tih(RXD)
tsu(ER) tih(ER)
tsu(DV) tih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
td(TXEN)
td(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
TCK
tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS
tov(TDO) toh(TDO)
TDO
MSv40458V1
tc(SWCLK)
SWCLK
tov(SWDIO) toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
7 Package information
G
Detail A
e2
E E
A e D
A2 e D
BOTTOM VIEW TOP VIEW
SIDE
VIEW A3 A2
BUMP
b
A1
FRONT VIEW
Z
ccc ZXY
ddd Z
DETAIL A SEATING
ROTATED 90 PLANE
A086_WLCSP156_ME_V1
A - - 0.58 - - 0.023
A1 - 0.17 - - 0.006 -
A2 - 0.38 - - 0.015 -
(2)
A3 - 0.025 - - 0.001 -
b 0.21 0.24 0.27 0.008 0.009 0.011
D 4.94 4.96 4.98 0.193 0.195 0.196
E 4.62 4.64 4.66 0.181 0.182 0.183
e1 - 4.20 - - 0.014 -
e2 - 3.85 - - 0.165 -
e - 0.35 - - 0.152 -
F - 0.380(3) - - 0.015 -
G - 0.395(3) - - 0.015 -
aaa - - 0.10 - - 0.004
bbb - - 0.10 - - 0.004
ccc - - 0.10 - - 0.004
ddd - - 0.05 - - 0.002
eee - - 0.05 - - 0.002
1. Values in inches are converted from mm and rounded to the 3rd decimal digits.
2. Back side coating. Nominal dimension rounded to the 3rd decimal place resulting from process capability.
3. Calculated dimensions are rounded to 3rd decimal place.
Dpad
Dsm
A086_WLCSP156_FP_V1
Pitch 0.35 mm
Dpad 0.210 mm
0.275 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.235 mm
Stencil thickness 0.100 mm
Ball A1
identifier
ES32H747ZI6
Product
identification(1)
Y WW R
MSv61385V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
A
F
D1 D
e
Y
N
13 1
Ball A1
identifier
ES32H747
Product identification(1)
AII6
Date code
Y WW
Revision code
MSv61387V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
C Seating plane
A
c
A1
A2
0.25 mm
gauge plane
k
A1
L
HD L1
PIN 1 D
IDENTIFICATION
ZE
E
HE
ZD
b
1T_ME_V2
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 - 1.450 0.0531 - 0.0571
b 0.170 - 0.270 0.0067 - 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
1.2
176 133
1 0.5 132
0.3
26.7
21.8
44 89
45 88
1.2
21.8
26.7
1T_FP_V1
Product identification(1)
ES32H747IIT6
Date code
Revision code
Y WW
R
Pin 1identifier
MSv61389V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
SEATING
PLANE
C
A2
A
A1
c
ccc C
0.25 mm
GAUGE PLANE
A1
K
L
D L1
D1
D3
156 105
157 104
b
E1
E3
208
53
PIN 1
IDENTIFICATION 1 52
e
UH_ME_V2
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 29.800 30.000 30.200 1.1811 1.1732 1.1890
D1 27.800 28.000 28.200 1.1024 1.0945 1.1102
D3 - 25.500 - - 1.0039 -
E 29.800 30.000 30.200 1.1811 1.1732 1.1890
E1 27.800 28.000 28.200 1.1024 1.0945 1.1102
E3 - 25.500 - - 1.0039 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
1 0.5
156
1.25
0.3
28.3
30.7
52 105
53 104 1.2
25.8
30.7
UH_FP_V2
Revision code
Product identification(1) R
ES32H747BIT6
Y WW
Pin 1 identifier Date code
MSv61391V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
ddd C
SEATING
PLANE
C
A2
A1
A
D1 A1 ball identifier D
e
A
E
E1
S
17 1
F
b (240 + 25 balls)
BOTTOM VIEW TOP VIEW
A07U_ME_V1
A - - 1.100 - - 0.0433
A1 0.150 - - 0.0059 - -
A2 - 0.760 - - 0.0299 -
b 0.350 0.400 0.450 0.0138 0.0157 0.0177
D 13.850 14.000 14.150 0.5453 0.5512 0.5571
D1 - 12.800 - - 0.5039 -
E 13.850 14.000 14.150 0.5453 0.5512 0.5571
E1 - 12.800 - - 0.5039 -
e - 0.800 - - 0.0315 -
F - 0.600 - - 0.0236 -
G - 0.600 - - 0.0236 -
ddd - - 0.100 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Dpad
Dsm
A07U_FP_V2
Pitch 0.8 mm
Dpad 0.225 mm
0.290 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.100 mm
Product
identification(1)
R
Date code
Ball
A1identifier Y WW
MSv61393V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
8 Ordering information
Example: STM32 H 747 X I T 6 TR
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
H = High performance
Device subfamily
747 = STM32H7x7 dual core MIPI-DSI line
Pin count
Z = 156 pins
A = 169 pins
I = 176 pins/balls
B = 208 pins
X = 240 balls
Package
T = LQFP ECOPACK®2
I = UFBGA pitch 0.5 mm ECOPACK®2
H = TFBGA ECOPACK®2
Y = WLCSP ECOPACK®2
Temperature range
6 = –40 to 85 °C
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
9 Revision history
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
Authorized Distributor
STMicroelectronics:
STM32H747XIH6 STM32H747XGH6 STM32H747BGT6 STM32H747AGI6 STM32H747IGT6 STM32H747ZIY6TR
STM32H747BIT6 STM32H747IIT6 STM32H747AII6