Wier sstictmetibenesecraon | SERS begin from the highest address (as shown ) and go downward, whereas GPRS must be used © and go upward. The first 96 bytes (i.e in 000H to OSFH) of the GPRs and the last 160 bytes ‘bank 15, FEOH to FFFH) of the SFRs are grouped into ‘a special bank called access bank ‘The PICI8 also has a 1KB of data EEPROM, which is Feadable and writable during normal operation with no ‘extra power supply. The data EEPROM memory is not directly mapped in the 4096 bytes of register file space; instead, it is indirectly addressed through a special function register. ‘A MOVLB instruction hat been instruction set to assist In selecting, ‘currently selected bank is not sand all writes are witl-return all status register bits will be set/cleared ay {for the instruction performed. 4.11.1(B) Special Function Registers @. Explain @. Explain the special function ‘with PICT8F microcontroller. (May 18, 6 1.11.1(A) Bank Select Register (BSR) — The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is Partitioned into sixteen banks. When using direct addressing, the BSR should be configured for the desired bank. = BSR<3:0> holds the upper 4 bits of the 12-bit RAM address, The BSR<7:4> bits will always read ‘0's and writes will have no effect. aes, — The SFRs begin from the highest address (as Fig. 1.11.2) and go downward, whereas GPRs used from address 0 and go upward, The first 96 (ie. in bank 0, O00H to OSFH) of the GPRs and the) 160 bytes (i.e. in bank 15, F6OH to FFFH) of the: are grouped into a special bank called access bank = The special function registers are basicaly the: includes modules like, reset control, timer serial port communication, parallel ‘communication etc. ~ Fig. 1.11.3 shows the detailed structure of $1 PIC18F458 microcontroller ‘Address | Name Address | Name | Address | Name Freh _| TOsU FoFh _| INDF2@) Ferh | CcPRIH Forh | IPRA ren | TOsH FoEh__| Postinc2”) | Feeh CoPRIL Foth | PIRL FoDh__| Postoec2"2) FBDh | ccPicon | F9ph_—| PIED PREINC22) FBCh | eccpriH) | roch | — Puusw2”) Fash | eccpru® | ropn | — FBah | EccPicon’s)SA difference between interrupt and polling. 6, Dec. 16, May 18, May 19, 05 Marks) are two methods to achieve this synchronization, polling method and interrupt-driven method. When a data is to be read from an input device the interface chip has to latch the data from the input device. While reading from the input devices using these methods are explained as follows 1, The polling method: In this case the interface chip uses a status flag to indicate whether it has read a data from the //O device and is ready for the processor to access it. Whenever the processor wants to access this device, it checks this flag to decide if new data has been received from the input device. The microprocessor may check this status flag continuously or periodically 2. Interrupt-driven method: In this case, the interface chip generates an interrupt signal to the microprocessor whenever it has received new data from the input device. The interrupt service routine is then executed which makes the microprocessor to read the input data. Similarly while writing data to the output device, the microprocessor has to make sure that the output ‘device is not busy. The two synchronization methods implement this as explained follows: methods directly in the hardware. If the user: can add an external parallel interface chip, such a5 ay Intel 8255, to the PIC18 microcontroller, to implement either of the two methods. Interrupt Service Routine (ISR) interrupt occurs and hence explain the ir vector. ee a. What are the different interrupt sot (May 19, 05 Marks) When an interrupt occurs, the processor services the same by executing a small program called a5 Interupt Service Routine (ISR). This ISR is stored in the memory, The address where the ISR is stored is called as an ISR. The interrupt vector addresses for PIC microcontol are as given in the Table 7.2.1 Table 7.2.1 : Interrupt vector table (IVT) forthe PICI Interrupt Power-on Reset [High priority interrupt Low priority interrupt Interrupt sources of PIC 18F listed as follows: me - 2PIC microcontroller can also be directly used as USART (Universal Synchronous or Asynchronous Receiver Transmitter). The different modes permit PIC microcontroller to be used in either of the modes. We need to understand the different registers before interfacing serial port of PIC microcontroller. ‘supports both the Asynd Te ones motes of the USAR. lg ‘bit Baud Rate Generator. SPORG regist rols the period of fer cont co ‘B-bit timer. In Asynchronous mode, bit (TXSTA register) also controls the baud ratg. Synchronous mode, bit BRGH is ignored. for Table 8.4.1 shows the formula ot maa rate for different USART modes which ony apply in Master Mode (internal clock). Given the desired baud rate and Fosc, the near integer value for the SPBRG register can be caleulateg using the formula in Table 8.4.1. From this, the emg in baud rate can be determined. Ex. 8.4.1 shows the calculation of the baud rate error for the following conditions Desired baud BRGH=0 SYNC=0 it may be advantageous to use the high baud rate (BRGH =1) even fo slower baud clocks. This is Because the Foxc/(16(X + 1)) equation can reduce the baud rate error in some cases Wrking a new value to the SPERG register causes ths ERG timer to be reset (or cleared). This ensures te SRG does not wait for a timer overflow before ‘outputting the new baud rate, 842 Sampling "= RC7/RX/DT pin is sampled three times Circuit to Setermine if a high or alow J[_smmc | snow=ous Olt h hero (Asynchronous)Baud rate=Fge/(64(X#1)) | Baud Rate=F/(16(X+2)) : Be | [synchronous)Baud rate= Fox /(4(X+1)) d: X=Value in SPBRG(0 to 255) Table 6.4.2 Value on all other resets (0000-010 0000 - 010 Pome [ome | con R/W-0 - 35 ona umeee patege) Te 5O=tow speed ‘Synchronous mode : ‘Unused in this mode. (bled [RMIT] : Transmit Shift Register Status bit L=TsRempty O=TSRfull ‘bit [Tx9D}: 8" bit of Transmit Data . Can be address/data bit ora parity bit. s Table 8.4.3 : Register associated with asynchronous transmission : 2. | ko [value on POR, BOR Value on al other resets i 0 (0000 000% (0000 000u PIR "| PSPIFE aa 0000 0000 (0000 0000 (EE as 0000 0000 0000 0000 1PR1_| PSPIPC mar 41.1111 qua ReSEEN. 0000 000x 0000 000u ae oe 0000 000 0 0000 0000 ™» TXEN | SYNC 0000-010 coon att ite generator register maaan sama STA (Receive Status and Control Register) a acer iia Sit eee ieee eis ae among other things: SL memeFraming error bit 1 = Framing error O= No Framing error TOERR] D1 = Overrun error bit 1= Overrun error = No overrun error [X09 DO: 9" bit of receive data (Because we use the 8.bit option, we make DO = 0) Can be used as an address/data or a parity bitin some applications. Table 8.4.4 : Registers associated with asynchronous reception 0000 000u 0000 0000 (0000 0000 ‘0000 0000 (0000 0000 q1a41111 1111 1111 ‘0000 000x_ (0000 000u 0000 000 0000 000 (0000 - 010 0000-010 ‘0000 0000 0000 0000 = The most common data format is & bits. An on-chip dedicated 8-bit Baud Rate Generator can be used to ive standard baud rate frequencies from the oscillator.x Transmit shift Rog, Gransmit shift 23 eee Fig. 8.6.2 : Asynchronous transmission Write to TXREG BRG output (Bhift clock) Word 1 Word 2 reg. flag) Word 1 —* Transmit shift ro9. TAMT bit (Transmit shit > __ See e e tog. empty fag) transmission (back to back) Fig. 8.6.3 : Asynchronous chronous Transmission ronous transmission baud rate. If g up Asyn: ow when setting up an async eed baud rates desired, set bit BRGH os . :IF Invorrupt Be Data bus ACIE Fig. 8.7.1 : USART receive block diagram The receiver block diagram is'shown in Fig. 8.7.1. The | 3. Ifinterrupts are desired, set enable bit RCI. Hata Is recelved on the RC7/RX/DT pin and drives the data | 4. 19-bit reception is desired, set bit RX, : recovery block. The data recovery block is actually a high- | 5. Enable the reception by setting bit CREN. ‘speed shifter, cece the a ee where | 6. Flag bit RCIF will be set when reception is cor ‘ receive s rates at the bit rate or Ah eas pe cereenteets “rl Be an interrupt wil be generated if enable systems, 2. Read the RCSTA register to get the ninth | 87.1 Setting up Asynchronous Reception enabled) and determine if any error occurred e reception. swhhow 8 Read the 8-bit received data by reading = Steps to follow when setting up an asynchronous register. aha SM any error occurred, for the appropriate baud fable ie cen “MT “8m baud rate is desired, set bithe BHVACHTONOUS Nevin OM by ce pit and wetting the SPLW ton _— pis are required, vet the Ic desired priory level woth the Rc oe “are she RX bit to enable 9.it reception the ADDEN bit S guate reception by setting the CREN bit Shia RCIF bit will be set when reception is complete the imerrupt will be acknowledged if the RCIE and “BEDI are set feat the RCSTA register to determine if any error © eoourred during reception, as well as read bit 9 of data if applicable) Read RCREG to determine if the device is being addressed, Wiany error occurred, clear the CREN bit. ‘ithe device has been addressed, clear the ADDEN bit tballow all received data into the receive buffer and Interrupt the CPU, enable address detect Programming the PIC18 to Transfer Data Serially ps that must be taken in programming oller to transfer character bytes: gram PIC18 serial port to transfer serial data, Ing steps are to be carried out: : (RCE) should be programmed as output pin bit of RCSTA register should be set to enable ES must be loaded with the count for required be loaded with 20H for asynchronous ud rate and transmission enable- ‘be loaded with the characte to be eanitee aie 6 ws te comet, me ‘ Pm Mi yrrpons se rhino em Stew Sat a oF AIRY Amr nt em FO a Program 8.8.2 : Write a PIC18 program to transter the letter ‘A’ serially at 9600 baud continuously. Let XTAL = 10 MM. Soln. : BCF TRISC,TX, Set TX pin as output pin BCFTRISGTX. ; Setserial portenable MOVLW D’'15’ ; Load the value of SPBRG in 3 Wreg for 9600 baud rate MOVWF SPBRG ; Load into SPBRG “MOVLW‘A’ —;_Load the value in W reg. OVW 'TXSTA ; Load into TXSTA Program 8.8.3: Write a program for PIC18 microcontroller to transfer a letter ‘T’ serially and continuously at a baud rate of 9600. Use BRGH = 0. Assume crystal frequency = 10 MHz Soln. :89 Programming the PIC18 to Receive Data Serially To program PIC18 serial port to receive serial data, the following steps are to be carried out » 1. RX pin (RCT) should be programmed as input pin. 2. RCSTA register should be set to 90H to enable serial _ reception. _ SBREG must be loaded with the count for required ‘baud rate. TA should be loaded with OOH for low baud rate. CIF bit is set, copy the contents of RCREG er Is to be received, goto step 5. ‘program to receive a character and ort D. Assume crystal frequency of 8.10 SPI (Serial Peripheral Interface) [Wii a hor nts on Serprocat — The SPI bus was developed by Motorola and is a, Synchronous bus 2. Full duplex, Bidirectional bus 3, Four wire bus Le. it uses 4 wires. It has @ single master with may be single or mul slave system which is commonly used for high speed serial communication between microcontroller and peripheral devices, such as EEPROMs, data convertors and display drivers. Although we may also have a system with multiple masters in the SPI system, but one of these works as @ master at any given time. As discussed earlier, there are SPI uses four signal lines for communication. They are: Master Out Slave In (MOS!) ; As the name says this signal carries the data from the master to the slave. In some cases this pin is also referred to as Slave Input/Slave Data In (SI/SDI). ‘ Master In Slave Out (MISO) : Similarly this pin is used to carry data from the slave to the master. In some cases this pin is also referred to as Slave Outpl Data Out (SO/SDO). Serial Clock (SCLK) : This is the synchronizing p the clock signal for synchronizing.:18 program: ee ine aia cg (0) Geer a inputs for the PICISF2X8 devices and eight for thePiciaraxa devices. This module has the ADCONOand ADCONI register definitions that are compatible with the PIC micro* midrange A/p module The A/D allows conversion of an analog input signal to a corresponding 10-bit digital number. The A/D module has four registers. These registers 1. A/D Result High Register (ADRESH) 2. A/D Result Low Register (ADRESL) 3. A/D Control Register 0 (ADCONO) 4. A/D Control Register 1 (ADCON1) The ADCONO register, shown in Fig. 9.8.1, controls the operation of the A/D module. The ADCON1 register, shown in Fig. 9.8.2, configures the functions of the port pins. 1 ADCONO Register | Explain in detail ADCON 0. Explain in detail the functions ¢ R/W-0 R/W-0 R/W-O R/W-OR/W-0 R/W-0 U-O R/WO jaDcs1)ADcso| cHs2 | cHs1 | cHSO GO/ Done | = |A20N bit7 bit 7-6 [ADCs1 : ADCSO} bito Fig.9.8.1 : ADCONO :A/ D Control Register 2 A/D Conversion Clock SelectFrc (Clock derived from the internal A/D RC oscillator) Channel 1 (AN1) = Channel 2 (AN2) = Channel 3 (AN3) = Channel 4 (AN4) = Channel 5 (ANS) = Channel 6 (AN6) Channel 7 (AN7) GO/DONE : A/D Conversion Status bit |ADON =1: 7 1=A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared by hardware when the A/D conversion is R/W-0 R/W-0 U-O U-OR/W-0 R/W-0 R/W-O R/W-O ADCS2 ae] PCrG3 |rcraz crea] perso] bit7 bit6 bits bita bits bit2 biti bitO ‘ADFM Fig. 982 : ADCONI : A/D Control register bit 7 ADFM : A/D Result Format Select bit 1 Right justified. Six(6) Most Significant bits of ADRESH are readas‘0’. 0 = Left justified. six (6) Least Significant bits of ADRESL are readas‘0’. bit 6 ADCS2 : A/D Conversion Clock Select bit (ADCON1 bits) rs ae