(h) Bootstrap Component Selection for IR2184 half bridge gate driver IC

with fixed dead time

The VBS voltage (the voltage difference between the VB and VS pins on the gate driver
IC) provides the supply to the high side driver circuitry of the control IC’s. This supply needs to
be in the range of 10- 20V to ensure that the gate driver IC can fully enhance the
MOSFET/IGBT being driven, some of International Rectifier’s Control IC’s include under
voltage detection circuits for VBS, to ensure that the IC does not drive the MOSFET/IGBT if
the VBS voltage drops below a certain voltage (VBSUV in the datasheet). This prevents the
MOSFET/IGBT from operating in a high dissipation mode.

This VBS supply voltage is a floating supply that sits on top of the VS voltage (which in most
cases will be a high frequency square wave). There are a number of ways in which the VBS
floating supply can be generated, one of these being the bootstrap method described here. This
method has the advantage of being simple and inexpensive but has some limitations; duty cycle
and on-time are limited by the requirement to refresh the charge in the bootstrap capacitor (long
on-times and high duty cycles require a charge pump circuit - see Application Note (AN978).
The bootstrap supply is formed by a diode and capacitor combination as shown in Figure 5.23.

Fig. 5.23: Bootstrap Diode/Capacitor circuit used with IR2184 IC.

The operation of the circuit is as follows. When VS is pulled down to ground (either
through the low side MOSFET or the load, depending on the circuit configuration), the
bootstrap capacitor (CBS) charges through the bootstrap diode (DBS) from the 15V Vcc supply.
Thus providing a supply to VBS.
(i) Calculating the value of bootstrap capacitor for driving IGBT
IRG4BC20UD
The following equation details the minimum charge which needs to be supplied by the
bootstrap capacitor:

𝐼𝑄𝐵𝑆(𝑀𝐴𝑋) 𝐼𝐶𝐵𝑆(𝐿𝐸𝐴𝐾)
𝑄𝐵𝑆 = 2𝑄𝐺 + 𝑓
+ 𝑄𝐿𝑆 + 𝑓
(5. 10)

(1)

Where:
QG = Gate charge of high side IGBT.
f = Frequency of operation or the switching frequency.
IQBS(MAX) = Quiescent current for high side driver circuitry.
ICBS(LEAK) = Bootstrap capacitor leakage current. (ICBS(LEAK) =0, if electrolytic capacitor is
not used.)
QLS = Level shift charge required per cycle = 5nC (500V/600V IC’s) or 20nC
(1200V IC’s).

The bootstrap capacitor must be able to supply this charge, and retain its full voltage,
otherwise there will be a significant amount of ripple on the VBS voltage, which could fall below
the VBSUV under voltage lockout, and cause the HO output to stop functioning. Therefore the
charge in the CBS capacitor must be a minimum of twice the above value. The minimum
capacitor value can be calculated from the equation below.

𝐼 𝐼
2⎡⎢2𝑄𝐺+ 𝑄𝐵𝑆𝑓(𝑀𝐴𝑋) +𝑄𝐿𝑆+ 𝐶𝐵𝑆(𝑓𝐿𝐸𝐴𝐾) ⎤⎥
⎣ ⎦
𝐶≥ 𝑉𝐶𝐶−𝑉𝐹−𝑉𝐿𝑆−𝑉𝑀𝐼𝑁
(5. 11)

Where,
VF = Forward voltage drop across the bootstrap diode.
VLS = Voltage drop across the low side IGBT (or load for a high side driver)
VMIN= Minimum voltage between VB and VS.

Calculations:
Bootstrap capacitor
(Parameters are taken by referring to the datasheets IR2184, IRG4BC20UD.)
QG = 41 nC.
 f = 2 KHz
IQBS(MAX) = 150 µA.
ICBS(LEAK) = 0 (as electrolytic capacitor is not used.)
QLG = 5nC (500V/600V IC’s)
VCC = 15V.
VF = 1.5 V
VLS = 1.85V
VMIN = 10 V
C ≥ 196 nF
Using thumb rule C = 15 x 196 nF = 3µF.
Therefore selecting a nearest available value i. e. 3.3 µF. 35 V tantalum capacitor.

IMPORTANT NOTE: The CBS Capacitor value obtained from the above (5.11) is the
absolute minimum required, however due to the nature of the bootstrap circuit operation, a low
value capacitor can lead to overcharging, which could in turn damage the IC. Therefore to
minimize the risk of overcharging and further reduce ripple on the VBS voltage the CBS value
obtained from the above equation should be should be multiplied by a factor of 15 (rule of
thumb).

The CBS capacitor only charges when the high side device is off, and the VS voltage is
pulled down to ground. Therefore the on time of the low side switch (or the off time of the high
side switch for a high side driver) must be sufficient to ensure that the charge drawn from the
CBS capacitor by the high side driver can be fully replenished. Hence there is inherently a
minimum on time of the low side switch (or off time of the high side switch in a high side
driver). Also in a high side switch configuration where the load is part of the charge path, the
impedance of the load can have a significant effect on the charging of the CBS bootstrap
capacitor: if the impedance is too high the capacitor will not be able to charge properly, and a
charge pump circuit may be required (see Application Note AN978). The Bootstrap capacitor
should always be placed as close to the pins of the IC as possible. Essentially it must be a low
ESR capacitor but ceramic or tantalum type can also be used.

(j) Selecting the bootstrap diode

The bootstrap diode (DBS) needs to be able to block the full power rail voltage, which is
seen when the high side device is switched on. It must be a fast recovery device to minimize the
amount of charge fed back from the bootstrap capacitor into the VCC supply, and similarly the
high temperature reverse leakage current would be important if the capacitor has to store charge
for long periods of time. The current rating of the diode is the product of the charge calculated
from equation (5.10) and the switching frequency. Therefore:

Diode Characteristics
VRRM = Power rail voltage
max trr = 100ns
IF = QBS x f
Bootstrap diode
QBS = 0.162 µC.
IF = 0.324 mA.
Therefore selecting an ultrafast diode UF4007, with VRRM = 1000 V, IF = 1 A and max.
trr = 75 nsec.

(k) 5-level inverter gate driver circuit diagram

Before explaining the complete circuit diagram of the multilevel inverter a simple block
diagram shown in the Figure 5.24 will be explained for clear understanding. A provision is made
to run this inverter from two types of gate pulse generation circuits: one is an analog circuit
which will be inside the cabinet of the inverter; another one is a digital circuit or microcontroller,
dSPACE, DSP, FPGA etc. The first block in Figure 5.24 may be any of the analog or digital pulse
generation blocks. The gate pulse inputs are first given to buffer. The is a circuit offers infinite
input impedance to the pulse generation circuit and draws negligible amount of current from the
gate pulse generation circuit. Hence, the buffer reduces the loading effect of the driver circuit on
the gate pulse generator circuit (microcontroller, dSPACE, DSP, FPGA etc. do not have capacity
to deliver high currents, so they may get damaged if no buffer stage is included.) The buffer
passes the pulses to the opto-coupler/opto-isolator which couples two circuits optically and
provides electrical isolation between the control circuit and power circuit. The output of
opto-coupler/opto-isolator is given to gate driver. Gate driver drives the inverter switches as per
the gate pulse pattern.
Fig. 5.24: Block diagram of gate driver circuit.
The input pulses are given to inverting buffer 74LS04. The 74LS04 is buffer with open
collector. Therefore a pull-up resistor R1 is required to connect between output terminal and the
VCC of buffer. As shown in Figure 5.25 the output of buffer is connected to the input of the
opto-coupler through a current limiting resistor R2. The buffer circuit is a very high impedance
circuit. The value of pull-up resistor R1 and the current limiting resistor R2 is decided as per the
input and output current requirement in the input of the opto-coupler. Input circuit is a light
emitting diode which emits light when current passes through it (If=forward current of the light
emitting diode). The photons emitted from light emitting diode falls on the base of the
photo-transistor in the output circuit. The amount of photons falling on the base produces the
base current; hence this decides the region of operation of the output transistor. The transistor is
to be operated in the quasi saturation or active region. The calculations are shown below to
decide values of R1 and R2 to operate the output transistor in the desired region. The input
current rating of the opto-coupler PC817 is If=20mA. Vf= 1.2V. Therefore resistance of the
diode at this current is,
𝑉𝑓 1.2
𝑅𝑑 = 𝐼𝑓
= 0.02
= 60Ω.

As no curve of dynamic resistance is shown for the light emitting diode the value of the
diode resistance calculate above will be used for all values of If.
To keep a safe current through the light emitting diode the If is taken as 8 mA.
Fig. 5.25: Buffer circuit and the opto-coupler circuit.

𝑉𝐶𝐶
𝐼𝑓 = 𝑅1+𝑅2+𝑅𝑑

5
0. 08 = 𝑅1+𝑅2+60

Therefore, 𝑅1 + 𝑅2 = 565

Let 𝑅2 = 100Ω

Then, 𝑅1 = 465Ω≈470Ω

The datasheet of PC817 shows that maximum output current rating of the opto-coupler
is 50mA. From collector current (IC) vs. collector-emitter voltage (VCE) graph at If=8mA and
IC=8mA, VCE = 1.2V.
Resistance of transistor (RT) at this current is,

𝑉𝐶𝐸 1.2
𝑅𝑇 = 𝐼𝐶
= 0.008
= 150Ω

An equivalent circuit of the output of opto-coupler is shown in the Figure 5.26. The equivalent
resistance between terminals ‘a’ and G2 is RE.
 (a) (b)

Fig. 5.26: (a) Equivalent circuit of the output of opto-coupler. (b) Voltage divider network for supplying voltage to
𝑆𝐷 pin of IR2184.

RE is [(1𝐾 + 150)∥1𝐾]

1150×1000
𝑅𝐸 = 2150
= 534. 88Ω

Current ‘I’ drawn from the 15V power supply is,

𝑉𝐶𝐶 15
𝐼 = 1000+𝑅𝐸
= 1000+534.88
= 9. 77𝑚𝐴

Current flowing through the transistor is calculated by current division rule,

𝐼×1000 0.00977×1000
𝐼𝐶 = 1000+150+1000
= 2150
= 4. 54𝑚𝐴

Therefore, at IF=8mA, VCE=0.45V and IC=4.54mA. The transistor is working in

quasi-saturation.

A complete circuit diagram of a gate driver for 5-level inverter is shown in the Figure
5.27. The terminals for the input gate signal are named as U, V, W, and X. These inputs are to be
given with respect to terminal G. The inverter signals are passed to gate driver through
opto-coupler. The input impedance of the gate driver is very high and it is a voltage driven IC.
So a high value resistance (5KΩ) is connected between opto-coupler output and gate driver
input.

The pin 𝑆𝐷 is a control pin of the gate driver IC. This pin need to supplied by 5V to
enable the gate driver otherwise the output of gate driver will be ceased. Generally this pin is
used to enable or disable the gate driver through programmable controller IC. This circuit is not
designed for such application. Therefore the 𝑆𝐷 pin has been given a continuous 5V supply. This
voltage is derived from the VCC (+15V) of the same gate driver using voltage divider network.
The circuit diagram is shown in the Figure 5.26(b).