Professional Documents
Culture Documents
M24C64-W M24C64-R M24C64-F M24C64-DF: 64-Kbit Serial I C Bus EEPROM
M24C64-W M24C64-R M24C64-F M24C64-DF: 64-Kbit Serial I C Bus EEPROM
M24C64-F M24C64-DF
64-Kbit serial I²C bus EEPROM
Features
• Compatible with all I2C bus modes:
– 1 MHz
– 400 kHz
PDIP8 (BN) – 100 kHz
• Memory array:
– 64 Kbit (8 Kbyte) of EEPROM
– Page size: 32 byte
– Additional Write lockable page (M24C64-D
order codes)
TSSOP8 (DW) SO8 (MN) • Single supply voltage:
169 mil width 150 mil width
– 1.7 V to 5.5 V over –40 °C / +85 °C
– 1.6 V to 5.5 V over 0 °C / +85 °C
• Write:
– Byte Write within 5 ms
– Page Write within 5 ms
UFDFPN8 (MC) UFDFPN5 (MH)
• Random and sequential Read modes
DFN8 - 2x3 mm DFN5 -1.7x1.4 mm
• Write protect of the whole memory array
• Enhanced ESD/Latch-Up protection
• More than 4 million Write cycles
• More than 200-years data retention
WLCSP (CS)
Thin WLCSP (CT) Packages
• PDIP8 ECOPACK2®
• SO8 ECOPACK2®
• TSSOP8 ECOPACK2®
• UFDFPN ECOPACK2®
WLCSP
Unsawn wafer • WLCSP ECOPACK2®
(CU)
• Unsawn wafer (each die is tested)
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.3 Write Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . 18
5.1.4 Lock Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . 18
5.1.5 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 18
5.1.6 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19
5.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.1 UFDFPN5 (DFN5) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2 UFDFPN8 (DFN8) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.3 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.5 PDIP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.6 WLCSP4 ultra thin package information . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.7 WLCSP5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.8 WLCSP8 thin package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
List of tables
List of figures
1 Description
9&&
(( 6'$
0[[[
6&/
:&
966
$,I
( :&
( 6&/
966 6'$
$,I
1. See Section 9: Package information for package dimensions, and how to identify pin 1
9&& :&
$%&'
966 966
;<=:
6'$ 6&/
7RSYLHZ %RWWRPYLHZ
PDUNLQJVLGH SDGVVLGH
069
1. Inputs E2, E1, E0 are not connected, therefore read as (000). Please refer to Section 2.3 for further
explanations.
0DUNLQJVLGH %XPSVLGH
WRSYLHZ ERWWRPYLHZ 06Y9
1. Inputs E2, E1, E0 are read as (000). Please refer to Section 2.3 for further explanations.
1 VCC SCL
2 VSS SDA
% 6'$ 6'$ %
0DUNLQJVLGH %XPSVLGH
WRSYLHZ ERWWRPYLHZ
069
1. Inputs E2, E1, E0 are internally connected to (001). Please refer to Section 2.3 for further explanations.
1 VCC - WC
2 - SDA -
3 VSS - SCL
% 6'$ ( ( 6'$ %
1 WC - SCL
2 - SDA -
3 VCC - VSS
4 - E0 -
5 E1 - E2
2 Signal description
9&& 9&&
0[[[ 0[[[
(L (L
966 966
$L
3 Memory organization
:&
( +LJKYROWDJH
( &RQWUROORJLF
JHQHUDWRU
(
6&/
6'$ ,2VKLIWUHJLVWHU
$GGUHVVUHJLVWHU 'DWD
DQGFRXQWHU UHJLVWHU
<GHFRGHU
SDJH
,GHQWLILFDWLRQSDJH
;GHFRGHU
069
4 Device operation
The device supports the I2C protocol. This is summarized in Figure 9. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
6&/
6'$
6'$ 6'$
67$57 ,QSXW &KDQJH 6723
&RQGLWLRQ &RQGLWLRQ
6&/
67$57
&RQGLWLRQ
6&/
^dKW
ŽŶĚŝƚŝŽŶ
069
b7 b6 b5 b4 b3 b2 b1 b0
When the device select code is received, the device only responds if the Chip Enable
address is the same as the value on its Chip Enable E2,E1,E0 inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, the device deselects itself from the bus, and goes into Standby
mode.
5 Instructions
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (tW), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 11.
:&
5:
:&
5:
:&FRQW¶G
$&. $&.
$,G
a.A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
:ULWHF\FOH
LQSURJUHVV
6WDUWFRQGLWLRQ
'HYLFHVHOHFW
ZLWK5:
12 $&.
UHWXUQHG
)LUVWE\WHRILQVWUXFWLRQ <(6
ZLWK5: DOUHDG\
GHFRGHGE\WKHGHYLFH
1H[W
12 2SHUDWLRQLV <(6
DGGUHVVLQJWKH
PHPRU\
6HQG$GGUHVV
5H6WDUW DQG5HFHLYH$&.
6WRS 12 <(6
6WDUW&RQGLWLRQ
'DWDIRUWKH 'HYLFHVHOHFW
:ULWHRSHUDWLRQ ZLWK5:
&RQWLQXHWKH &RQWLQXHWKH
:ULWHRSHUDWLRQ 5DQGRP5HDGRSHUDWLRQ
$,H
1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the figure) must be
identical to the seven most significant bits of the Device Select code of the Write (polling instruction in the figure).
$&. 12$&.
&XUUHQW
$GGUHVV 'HYVHO 'DWDRXW
5HDG
6WDUW
6WRS
5:
6WDUW
6WRS
5: 5:
6WRS
5:
6WDUW
5: 5:
$&. 12$&.
'DWDRXW1
6WRS
$,G
The device is delivered with all the memory array bits and Identification page bits set to 1
(each byte contains FFh).
When delivered in unsawn wafer, all memory bits are set to 1 (each memory byte contains
FFh) except the last byte located at address 1FFFh which is written with the value 22h.
7 Maximum rating
Stressing the device outside the ratings listed in Table 8 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
8 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
- Input and output timing reference levels 0.3 VCC to 0.7 VCC V
6##
6##
-36
During tW
ICC0 Supply current (Write)(3) - 1.5(4) mA
1.8 V ≤ VCC 2.5 V
Device not selected(5),
ICC1 Standby supply current - 1 µA
VIN = VSS or VCC, VCC = 1.8 V
Input low voltage
VIL 1.8 V ≤ VCC < 2.5 V –0.45 0.25 VCC V
(SCL, SDA)(6)
Input high voltage
1.8 V ≤ VCC < 2.5 V 0.75 VCC 6.5 V
(SCL, SDA)
VIH
Input high voltage
1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC+ 0.6 V
(WC)(7)
VOL Output low voltage IOL = 1 mA, VCC = 1.8 V(8) - 0.2 V
1. If the application uses the voltage range R device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 16 instead of this table.
2. Only for devices operating at fC max = 1 MHz (see note (1) in Table 20).
3. For devices identified with process letter K or T
4. Characterized value, not tested in production.
5. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
6. Ei inputs should be tied to Vss (see Section 2.3).
7. Ei inputs should be tied to Vcc (see Section 2.3).
8. IOL = 0.7 mA for devices identified by process letter P.
ICC0 Supply current (Write) During tW, VCC < 2.5 V - 1.5(3) mA
Device not selected(4),
ICC1 Standby supply current VIN = VSS or VCC, VCC = 1.6 V or - 1 µA
1.7 V
Input low voltage
VIL VCC < 2.5 V –0.45 0.25 VCC V
(SCL, SDA, WC, Ei)(5)
Input high voltage
VCC < 2.5 V 0.75 VCC 6.5
(SCL, SDA)
VIH V
Input high voltage
VCC < 2.5 V 0.75 VCC VCC+ 0.6
(WC, E2, E1, E0)(6)
VOL Output low voltage IOL =1mA, VCC = 1.6 V or 1.7 V - 0.2 V
1. If the application uses the voltage range F device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 16 instead of this table.
2. Only for devices identified by process letter K or T (see Table 20).
3. Characterized value, not tested in production.
4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
5. Ei inputs should be tied to VSS(see Section 2.3).
6. Ei inputs should be tied to VCC (see Section 2.3).
Figure 15. Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz
"US LINE PULL
UP RESISTOR
4HE 2 X # TIME CONSTANT
BUS BUS
MUST BE BELOW THE NS 6##
K
TIME CONSTANT LINE REPRESENTED
2 ON THE LEFT
BU
S §
#
BU 2BUS
(ERE 2BUS § #BUS NS S
K½ N
S
)£# BUS 3#,
-XXX
MASTER
3$!
P&
#BUS
"US LINE CAPACITOR P&
AIB
Figure 16. Maximum Rbus value versus bus parasitic capacitance Cbus) for
an I2C bus at maximum frequency fC = 1MHz
6##
"US LINE PULL
UP RESISTOR K
2BUS
2 4HE 2BUS § #BUS TIME CONSTANT
BUS § MUST BE BELOW THE NS
#
BUS 3#,
NS TIME CONSTANT LINE REPRESENTED )£# BUS -XXX
ON THE LEFT MASTER
3$!
(ERE
2 BUS § #BUS NS
#BUS
"US LINE CAPACITOR P&
-36
ƚy>ϭy>Ϯ ƚ,>
ƚy,ϭy,Ϯ ƚ>,
^>
ƚ>>
ƚy>ϭy>Ϯ
^/Ŷ
^
ƚ,> ƚy,ϭy,Ϯ /ŶƉƵƚ ƚ>y ^ ƚy, ƚ,, ƚ,>
ŚĂŶŐĞ
t
ƚt>> ƚ,t,
^ƚŽƉ
^ƚĂƌƚ
ĐŽŶĚŝƚŝŽŶ
ĐŽŶĚŝƚŝŽŶ
^>
^/Ŷ
ƚt
ƚ,, ƚ,>
tƌŝƚĞĐLJĐůĞ
ƚ,>
^>
ƚ>Ys ƚ>Yy ƚY>ϭY>Ϯ
/ϬϬϳϵϱŝ
9 Package information
3LQ
3LQ
E
;
( (
< H
' /
7RSYLHZ %RWWRPYLHZ
PDUNLQJVLGH SDGVVLGH
$
6LGHYLHZ $8.B0(B9
1. On the bottom side, pin 1 is identified by the specific pad shape and, on the top side, pin 1 is defined from
the orientation of the marking: when reading the marking, pin 1 is below the upper left package corner.
Table 21. UFDFPN5 - 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch
dual flat package, no lead - package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
Table 21. UFDFPN5 - 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch
dual flat package, no lead - package mechanical data (continued)
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
Y - 0.200 - - 0.0079 -
e - 0.400 - - 0.0157 -
L 0.500 0.550 0.600 0.0197 0.0217 0.0236
L1 - 0.100 - - 0.0039 -
k - 0.400 - - 0.0157 -
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip.
Figure 19. UFDFPN5 - 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch
dual flat package, no lead recommended footprint
3LQ
$8.B)3B9
>ϭ
>ϯ
WŝŶϭ
Ϯ
<
>
Ϯ
ĞĞĞ
ϭ =:B0(H9
Table 22. UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch dual flat package,
no lead - package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
ϴ ϱ
Đ
ϭ
ϭ ϰ
ϭ >
Ϯ
W >ϭ
ď Ğ
76623$0B9
Table 23. TSSOP8 – 3 x 4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline,
package mechanical data
millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.
A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
CP - - 0.100 - - 0.0039
D 2.900 3.000 3.100 0.1142 0.1181 0.1220
e - 0.650 - - 0.0256 -
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
E1 4.300 4.400 4.500 0.1693 0.1732 0.1772
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
α 0° - 8° 0° - 8°
1. Values in inches are converted from mm and rounded to four decimal digits.
H X
! !
C
CCC
B
E
PP
$ *$8*(3/$1(
K
% %
,
!
,
62$B9
Table 24. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width,
package mechanical data
millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.
A - - 1.750 - - 0.0689
A1 0.100 - 0.250 0.0039 - 0.0098
A2 1.250 - - 0.0492 - -
b 0.280 - 0.480 0.0110 - 0.0189
c 0.170 - 0.230 0.0067 - 0.0091
D 4.800 4.900 5.000 0.1890 0.1929 0.1969
E 5.800 6.000 6.200 0.2283 0.2362 0.2441
E1 3.800 3.900 4.000 0.1496 0.1535 0.1575
e - 1.270 - - 0.0500 -
h 0.250 - 0.500 0.0098 - 0.0197
k 0° - 8° 0° - 8°
L 0.400 - 1.270 0.0157 - 0.0500
L1 - 1.040 - - 0.0409 -
ccc - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
Figure 23. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width,
package recommended footprint
[
2B621B)3B9
B %
! !
! ,
B E C
E!
E"
$
%
0$)0
"
Table 25. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data
millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.
A - - 5.33 - - 0.2098
A1 0.38 - - 0.0150 - -
A2 2.92 3.30 4.95 0.1150 0.1299 0.1949
b 0.36 0.46 0.56 0.0142 0.0181 0.0220
b2 1.14 1.52 1.78 0.0449 0.0598 0.0701
c 0.20 0.25 0.36 0.0079 0.0098 0.0142
D 9.02 9.27 10.16 0.3551 0.3650 0.4000
E 7.62 7.87 8.26 0.3000 0.3098 0.3252
E1 6.10 6.35 7.11 0.2402 0.2500 0.2799
e - 2.54 - - 0.1000 -
eA - 7.62 - - 0.3000 -
eB - - 10.92 - - 0.4299
L 2.92 3.30 3.81 0.1150 0.1299 0.1500
1. Values in inches are converted from mm and rounded to four decimal digits.
%XPS
$
HHH =
=
E; 6HDWLQJSODQH
T FFF0 = ; <
TGGG0 =
'HWDLO$
5RWDWHG
$=%6&B0(B9
Table 26. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip
scale package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
Table 26. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip
scale package mechanical data (continued)
bbb - - 0.110 - - 0.0043
ccc - - 0.110 - - 0.0043
ddd - - 0.060 - - 0.0024
eee - - 0.060 - - 0.0024
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
Figure 26. Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale
package recommended footprint
[ E
$=%6&B)3B9
EEE =
' H
; <
&
H
( 'HWDLO$ % H
DDD 2ULHQWDWLRQ *
2ULHQWDWLRQ [ $ UHIHUHQFH )
UHIHUHQFH
$
:DIHUEDFNVLGH 6LGHYLHZ %XPSVLGH
%XPS
'HWDLO$
URWDWHGE\
HHH = $
=
E ; 6HDWLQJSODQH
FFF0 = ;<
GGG0 =
&GB0(B9
Table 27. WLCSP- 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
Figure 28. WLCSP - 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale
recommended footprint
&
H
% H
H
&GB)3B9
EEE =
' H
; <
'HWDLO$
( H
H )
DDD $
5HIHUHQFH ; 2ULHQWDWLRQ *
$
UHIHUHQFH
:DIHUEDFNVLGH 6LGHYLHZ %XPSVVLGH
%XPS
HHH = $
=
E
CCC - : 89 6HDWLQJSODQH
DDD - :
'HWDLO$
5RWDWHG 9GB0(B9
Table 28. Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale
package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
Figure 30. Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale
package recommended footprint
PP
PP
PP
PP
EXPSV[PP
2ULHQWDWLRQ
UHIHUHQFH
9GB)3B9
10 Ordering information
Device type
M24 = I2C serial access EEPROM
Device function
C64 = 64 Kbit (8192 x 8 bit)
Operating voltage
F = VCC = 1.7 V to 5.5 V
Process
T = F8H+
Delivery form
W = Wafer (bare die)
Wafer thickness
20 = Non-backlapped wafer
Wafer testing
I = Inkless test
Device grade
90 = -40°C to 85°C
1. For all information concerning the M24C64 delivered in unsawn wafer, please contact your nearest ST
Sales Office.
2. Unsawn wafer in preview.
Engineering samples
Parts marked as ES or E are not yet qualified and therefore not approved for use in
production. ST is not responsible for any consequences deriving from such use. In no event,
will ST be liable for the customer using of these engineering samples in production. ST’s
quality department must be contacted prior to any decision to use these engineering
samples to run qualification activity.
11 Revision history
Updated Figure 3, Figure 6, Table 15, Table 9, Table 17, Table 18 and
Table 27.
Updated ECOPACK info on front page.
Updated notes:
– (1) on Table 7, Table 8, Table 14, Table 18
– (2) merged with (3) on Table 15
– (8) on Table 15
– (2) on Table 16
21-Jul-2014 29
– (3) on Table 27
Added:
– note (1) on Table 9
Added:
– supply voltage level specification on Cover page.
– package UFDFPN5 on Cover page
– Table 18 and Figure 18 related to UFDFPN5 package.
– Note (1) on Section 5.1.5
Added:
– note 2 on Table 14
– note 2 on DW, MC and CS package on Table 27
– note 1on BN package on Table 27
– Figure 3
Updated:
– Section 1: Description
– Chapter 5.1.5
12-Nov-2014 30
– note 3 on Table 6
– note 1 on Table 9
– note 1 on Table 12
– note 1 on Table 13
– ICC0 max value and note 5 on Table 14
– ICC0 max value on Table 15
– ICC0 max value on Table 16
– note 2 on Table 27
Added WLCSP package.
30-Jul-2015 31
Updated Table 27.
18-Feb-2016 32 Updated Figure 4, Figure 18,Table 19 and added Table 2
Added Reference to unsawn wafer inside cover page and added
22-June-2016 33
Table 28: Ordering information scheme (unsawn wafer)
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.