IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL.
68, 2020
Energy- and Area-Efficient
Recursive-Conjugate-Gradient-Based MMSE
Detector for Massive MIMO Systems
Leibo Liu , Senior Member, IEEE, Guiqiang Peng , Pan Wang , Sheng Zhou , Member, IEEE,
Qiushi Wei, Shouyi Yin , Member, IEEE, and Shaojun Wei , Fellow, IEEE
Abstract—Minimum-mean-square-error (MMSE) detection is
increasingly relevant for massive multiple-input multiple-output
(MIMO) systems. MMSE suffers from high computational com-
plexity and low parallelism because of the increasing number of
users and antennas in massive MIMO systems. This paper proposes
a recursive conjugate gradient (RCG) method to iteratively esti-
mate signals. First, a recursive conjugate gradient detection algo-
rithm is proposed that achieves high parallelism and low complexity
through iteration. Second, a quadrant-certain-based initial method
that improves detection accuracy without added complexity is
proposed. Third, an approximated log likelihood ratio (LLR) com-
putation method is proposed to achieve simplified calculation. The
analyses show that compared with related methods, the proposed
RCG algorithm reduces computational complexity and exploits
the potential parallelism. RCG is mathematically demonstrated to
achieve low approximated error. Based on the RCG method, an ar-
chitecture is proposed in a 128 × 8 64-QAM massive MIMO system.
First, a parallel processing element array with single-sided input is
adopted; this array eliminates the throughput limitation. Second,
a deeply pipelined user-level method based on the recursive conju-
gate gradient method is proposed. Third, an approximated archi-
tecture is proposed to compute the soft output. The architecture is
verified on an FPGA and fabricated on 1.87 × 1.87 mm2 silicon with
TSMC 65 nm CMOS technology. The chip achieves 2.69 Mbps/mW
and 1.09 Mbps/kG energy efficiency (throughput/power) and
area efficiency (throughput/area), respectively, which are 2.39 to
10.60× and 1.15 to 8.81× those of the normalized state-of-the-art
designs.
Index Terms—Massive multiple-input multiple-output (MIMO),
detection, minimum mean square error (MMSE), recursive
conjugate gradient, very-large-scale integration (VLSI), wireless
communications.
Manuscript received January 2, 2019; revised July 5, 2019 and October 19,
2019; accepted January 1, 2020. Date of publication January 6, 2020; date of
current version January 24, 2020. The associate editor coordinating the review
of this manuscript and approving it for publication was Prof. Xinming Huang.
This work was supported in part by the National Natural Science Foundation
of China under Grant 61834002, in part by the National Key R&D Program of
China under Grant 2018YFB2202101. This article was presented in part at the
2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), Tainan, Taiwan,
November 2018 [1]. (Leibo Liu and Guiqiang Peng contributed equally to this
work.) (Corresponding author: Shaojun Wei.)
L. Liu, G. Peng, P. Wang, Q. Wei, S. Yin, and S. Wei are with the
Institute of Microelectronics, Tsinghua University, Beijing 100084, China
(e-mail: liulb@tsinghua.edu.cn; pgq13@mails.tsinghua.edu.cn; wp17@mails.
tsinghua.edu.cn; weiqs15@mails.tsinghua.edu.cn; yinsy@tsinghua.edu.cn;
wsj@tsinghua.edu.cn).
S. Zhou is with the Department of Electronic Engineering, Tsinghua Univer-
sity, Beijing 100084, China (e-mail: sheng.zhou@tsinghua.edu.cn).
Digital Object Identifier 10.1109/TSP.2020.2964234
1053-587X © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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573
I. INTRODUCTION
ASSIVE multiple-input multiple-output (MIMO), a key
M technology, can be used in next-generation wireless
communication systems, such as 5G [2]–[4]. However, massive
MIMO still faces various challenges, and one such challenge
exists in uplink massive system signal detection. Data detection
in MIMO generally involves low parallelism and high compu-
tational complexity, particularly when the number of antennas
increases; thus, data detection is a challenging task and compu-
tational complexity is extremely high. Consequently, an efficient
signal detection algorithm that satisfies the requirements of low
complexity, high parallelism, and high accuracy is considerably
important. Maximum likelihood (ML) detection [5], [6] is an
optimal detection algorithm. Nonetheless, the computational
complexity notably increases with the number of users and mod-
ulation orders, thus preventing the practical application of the
ML algorithm. Other nonlinear algorithms, such as K-best [7],
[8], sphere decoding (SD) [9], expectation-propagation detec-
tion (EPD) [10], message-passing detector (MPD) [11], [12], and
triangular approximate semidefinite relaxation (TASER) [13],
can achieve near-optimal ML detection performance. However,
K-best and SD involve QR decomposition when the chan-
nel matrix is large, and these two algorithms are difficult to
implement because of their high computational complexities.
In addition, there are complex low-parallelism iterations in
the EPD, MPD, and TASER algorithms. These nonlinear al-
gorithms also require abundant area and power for hardware
implementation. Various linear detection algorithms have been
proposed to reduce the computational complexity [14]–[17] and
can be employed in a massive MIMO system with a large but
finite number of antennas and a comparatively small number
of users. These linear methods can achieve near-optimal per-
formance with relatively low computational complexity com-
pared with nonlinear methods. Among these linear algorithms,
the minimum mean square error (MMSE) is one of the most
effective algorithms in reducing computational complexity with
minimal detection accuracy loss; consequently, it has signifi-
cant potential for use in practical massive MIMO systems [3],
[16], [17].
However, considering the hardware architecture, MMSE de-
tection involves complicated matrix inversions and multiplica-
tions, as well as low parallelism, causing difficulties for hardware
574
implementations with an increasing number of users. This issue
limits the application of hardware architectures (detectors) in
massive MIMO systems [16]–[19]. Consequently, many meth-
ods have been proposed to further reduce computational com-
plexity, improve the parallelism of MMSE and optimize hard-
ware architectures. In [16] and [17], Cholesky decomposition
(CHD)-based detectors and LU decomposition (LUD)-based
detectors were proposed and implemented in hardware with high
detection accuracy. However, the throughput is limited, and the
architecture requires a significant amount of hardware resources.
Neumann series approximation (NSA)-based architectures have
been proposed to achieve high throughput for massive MIMO
detection [18]–[20]. However, only a marginal reduction in
complexity can be achieved. To achieve a reasonable balance
of detection accuracy, throughput, and hardware resource con-
sumption, architectures based on approximation methods, such
as the Gauss-Seidel (GS) [21], [22], successive over-relaxation
(SOR) [23], [24], weighted Jacobi iteration (WeJi) [25], [26] and
Monte Carlo tree search (MCTS) [27] methods, have also been
proposed. However, the computations in the GS, SOR, WeJi,
and MCTS methods are difficult to parallelize due to high cor-
relations when estimating each symbol from users. To explore
the parallelism between each step, implicit methods have been
proposed, including optimized coordinate descent (OCD) [28],
parallelizable Chebyshev iteration (PCI) [29] and intraiterative
interference cancellation (IIC) [30]. However, these implicit
methods ignore the unique properties of massive MIMO systems
(e.g., channel hardening). Therefore, the same Gram matrix
needs to be calculated multiple times, which means that implicit
method architectures suffer from higher energy consumption
and latency than explicit methods.
Contributions: In this paper, we propose a recursive conjugate
gradient (RCG) method to achieve massive MIMO detection
with corresponding very-large-scale integration (VLSI) designs.
Our contributions are summarized as follows:
1) We propose a modified conjugate gradient method to
solve the detection problem with high parallelism and low
complexity in the massive MIMO system.
2) According to the property of the massive MIMO system,
we propose a quadrant-certain-based initial method and
an approximated log likelihood ratio (LLR) method, all of
which reduce the computational complexity while main-
taining high detection accuracy.
3) We mathematically analyze the approximated error, com-
plexity, and parallelism of the proposed RCG method.
RCG maintains its advantages in terms of these factors. In
addition, we provide symbol-error-rate (SER) simulation
results to show that compared with related methods, the
RCG method achieves high detection accuracy.
4) We develop a VLSI architecture for RCG that uses a paral-
lel processing element (PE) array and a deeply pipelined
user-level method to achieve high throughput with low
hardware consumption.
5) The architecture is verified on an FPGA and fabricated on
silicon. The chip achieves a 1.5 Gbps throughput under a
500 MHz working frequency while dissipating 557 mW
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IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 68, 2020
at 1.2 V. We show reference FPGA and ASIC implemen-
tation results and compare our designs to those of recently
reported massive MIMO detection implementations.
Our results demonstrate that RCG provides near-optimal
detection accuracy with high parallelism and low complexity,
and compared with other state-of-the-art architectures, the cor-
responding architecture achieves substantial improvements in
terms of energy and area efficiencies.
Notation: Bold uppercase, bold lowercase, and lowercase
letters denote matrices, vectors, and scalars, respectively. (·)i,j
denotes the element in the ith row and jth column of a matrix.
(·)i denotes the ith element of a vector. IM denotes the M × M
identity matrix. (·)H and (·)−1 denote conjugate transpose and
inversion, respectively.
Outline: The remainder of this paper is organized as follows.
Section II briefly introduces the system model and motivation.
Section III describes the proposed recursive conjugate gradient
method for a massive MIMO system. Section IV shows the
symbol-error-rate simulation results and comparisons. Section
V presents the proposed VLSI architecture. Section VI shows
the hardware implementation results and their comparisons with
state-of-the-art designs. Conclusions are drawn in section VII.
II. SYSTEM MODEL AND MOTIVATION
In an Nr × Nt MIMO system with Nt transmitters on the user
side and Nr antennas on the base station (BS) side (predomi-
nantly Nr  Nt [2]–[4]), the uplink system can be modeled
as [10]–[12]
y = Hs + n, (1)
where H ∈ C Nr ×Nt represents a Rayleigh flat-fading channel
matrix; s ∈ C Nt ×1 denotes the transmitted signal vector, which
is based on the 64-QAM modulation constellation set Ω in this
paper; n ∈ C Nr ×1 is an additive white Gaussian noise vector
with zero mean and variance σ 2 ; and y ∈ C Nr ×1 is the signal
vector received at the BS. In classical MMSE detection, the
estimation of the transmitted signal can be expressed as [16], [17]
 −1 H
ŝ = HH H + N0 Es −1 INt H y = W−1 yMF , (2)
where W = HH H + N0 Es −1 IM is the MMSE filtering
matrix with a noise power spectral density of N0 and a signal
power spectral density of Es and yMF = HH y denotes the
matched-filter vector. According to (1) and (2), the vector ŝ can
be described as
ŝ = W−1 HH Hs + W−1 HH n, (3)
where U = W−1 HH H and V = UW−1 are the equivalent
channel matrices, which can be used to compute the equivalent
channel gain and postequalization noise plus interference (NPI,
σ 2 ), respectively. The soft-output LLR for the b-th bit index
and i-th user satisfies
  2  2
2  ŝi   ŝi 
Ui,i
Li,b = 2 min0  − s − min1  − s = ζi2 ϕb (ŝi ),
σi s∈Sb Ui,i s∈Sb Ui,i
(4)
LIU et al.: ENERGY- AND AREA-EFFICIENT RECURSIVE-CONJUGATE-GRADIENT-BASED MMSE DETECTOR 575

where ζi2 is the signal-to-interference-plus-noise ratio (SINR) In addition, according to the Lanczos orthogonalization algo-
for the i-th user; ϕb (ŝi ) is a piecewise linear function for rithm [31], the residual vector z(k+1) can be expressed as
Gray mappings; and Sb0 and Sb1 denote the sets of modulation 
constellation symbols, where the i-th z(k+1) = ρ(k) z(k) − γ (k) η (k) + (1 − ρ(k) )z(k−1) , (8)
 t bits are 2
0 and 1,
respectively. In addition, there is σi2 = N
j=i |U i,j | E s +Vi,i N0 .
In massive MIMO systems, MMSE detection can achieve where ρ(k) , γ (k) , and η (k) = Wz(k) are iterative parameters.
near-optimal performance [3]. However, the result of large- When computing the iterative residual, the RCG algorithm im-
scale multiplication during the computation of the Gram matrix proves the original CG method by Lanczos orthogonalization
is required in the following computations. Considering hard- algorithm so as to improve the parallelism of inter-iteration
ware implementation, this limitation significantly influences the and intro-iteration computation. Combining (7) and (8), the
throughput of the entire detector and affects resource consump- estimation of the transmitted vector can be expressed as
tion [16], [19], [25]. Furthermore, the computational complex-  
ities of matrix inversion W−1 in (2) and LLR in (4) are high, ŝ(k+1) = ρ(k) ŝ(k) + γ (k) z(k) + 1 − ρ(k) ŝ(k−1) . (9)
particularly in systems with a large number of antennas [16],
[19], [25]. Considering hardware implementation, the computa- Next, it is important to compute the iterative parameters. Be-
tion of the matrix W−1 restricts system parallelism due to the cause the vectors z(k+1) , z(k) , and z(k−1) are mutually or-
high correlation of each computation. thotropic [31], there are
  
z(k+1) , z(k) = z(k−1) , z(k) = z(k−1) , z(k+1) = 0.
III. RECURSIVE CONJUGATE GRADIENT METHOD FOR
MASSIVE MIMO DETECTION (10)
Hence, combining (8) and (10), the parameters can be
First, this section describes a recursive conjugate gradient obtained as
detection algorithm that approximates an MMSE detector in a
massive MIMO system. For the formulation of this algorithm, ξ (k)
γ (k) = ;
an optimized conjugate gradient-based method is presented and φ(k)
a quadrant-certain-based initial method is proposed. In addi-
ξ (k−1)
tion, an approximate method of computing LLRs is presented. ρ(k) =  , (11)
Second, it is demonstrated that the proposed method has a low ξ (k−1) + γ (k) η (k) , z(k−1)
approximated error. Third, analyses of the proposed recursive
where ξ (k) and φ(k) can be computed as
conjugate gradient detection algorithm are presented to show

its advantages in terms of computational complexity and paral- ξ (k) = z(k) , z(k) ;
lelism in comparison with other algorithms.

φ(k) = η (k) , z(k) . (12)
A. Proposed Recursive Conjugate Gradient Detection
1) Optimized Iteration Method: Conjugate Gradient (CG) In addition, according to (8) and (10), there are
iteration is a promising method for solving linear equations  
such as (2) [31]. Therefore, CG iteration can be used in the η (k) , z(k−1) = z(k) , η (k−1) ,
MMSE detection algorithm to reduce computational complexity
z(k) z(k−1)
by avoiding large-scale matrix inversions. However, the tradi- η (k−1) = − (k−1) (k−1)
+ (k−1)
tional CG method still has some shortcomings. In the original ρ γ γ
 
algorithm, there is strong data dependency between each itera- 1 − ρ(k−1) z(k−2)
tion and between each element of the estimated vector in one + . (13)
ρ(k−1) γ (k−1)
iteration. To solve these problems, based on the CG method,
Recursive Conjugate Gradient (RCG) iteration can be expressed Therefore, the parameter ρ(k) can be computed as
as

−1
(k+1) (k) (k+1) (k+1) (k) γ (k) ξ (k) 1
ŝ = ŝ +α p , (5) ρ = 1 − (k−1) (k−1) (k−1) . (14)
γ ξ ρ
where p(k) is an orthogonal basis, k is the iteration number, and In this proposed algorithm, to compute the iteration and pa-
the parameter α(k) can be calculated as rameters, there are required initial settings, such as ρ(0) = 1,
 (0) (k)  z(−1) = z(0) , and ŝ(−1) = ŝ(0) .
(k) z ,p
α = . (6) After the iteration, points need to be found in the constellation
Wp(k) , p(k)
graph according to ŝ(k) . In the constellation graph, the round-off
In (6), z(k) represents the residual vector, which can be expressed method can be used to find the nearest points rather than calcu-
as lating all distances with all constellation points of an element
in ŝ(k) . In this way, the computational complexity is decreased
z(k) = yMF − Wŝ(k) . (7) from quadratic to linear.

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576
Fig. 1. Quadrant-certain-based initial solution.
2) Quadrant-Certain-Based Initial Solution: Any initial so-
lution can obtain the final solution, and the initial solution of
the iteration affects the detection accuracy and computational
complexity when the number of iterations is limited. The next
task in the signal detection method determines the initial solu-
tion, which is traditionally set as a zero vector because no a priori
information of the final solution is available. Note that for uplink
massive MIMO systems, the channel matrix H is asymptotically
orthogonal when Nr  Nt [2]–[4]; hence, there is
IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 68, 2020
initial solution method is better than the traditional method.
Additive noise has no effect on the distribution of the trans-
mitting signal points, so the transmitting signal is considered to
occur randomly among the 64 constellation points. The above
analysis shows that the proposed quadrant-certain initial points
method achieves better results in selecting the initial solutions of
52 constellation points than does the traditional initial solution
(zero vector). The simulation results (Fig. 3 in Section IV)
prove that the proposed method achieves better performance
than that of the traditional initial solution method. In addition,
the computational complexity does not increase. Hence, the
proposed method can reduce hardware resource consumption
and increase throughput.
3) Approximate LLR: According to (3) and (4), the compu-
tation of soft-output LLR requires the equivalent channel gain
(Ui,i ), NPI (σ 2 ), and estimated vector ŝ. The estimated vector ŝ
can be attained according the iteration; therefore, the following
work is focused on the computations of Ui,i and σ 2 . According
to (9), the estimated vector can be expressed as
 
ŝ(k+1) = ρ(k) ŝ(k) + γ (k) z(k) + 1 − ρ(k) ŝ(k−1)

 = ρ(k) 1 − γ (k) W ŝ(k)
Nr , i = j,
Wi,j ≈ (15) 
0, i = j.
+ 1 − ρ(k) ŝ(k−1) + ρ(k) γ (k) yMF . (18)
Therefore, the Gram matrix is diagonally dominant for an uplink
massive MIMO system, and all elements in the diagonal are Combining (2) and (18), let yMF = e(Nr ,1) ; the estimated of the
positive [21], [22]. Combining (2) and (15), there are inversion of matrix W can be expressed as
 −1 MF  1   
(k+1) (k)
Re (ŝi ) ≈ Re Wi,i yi ≈ Re yiMF ; Ŵinv = ρ(k) 1 − γ (k) W Ŵinv
Nr

 −1 MF  1   (k−1)
Im (ŝi ) ≈ Im Wi,i yi ≈ Im yiMF , (16) + 1 − ρ(k) Ŵinv + ρ(k) γ (k) e(Nr ,1) . (19)
Nr
(0) (0)
which means that the ith element of the vector ŝ(k) is located in According to (15), the Ŵinv in (19) can be computed as Ŵinv =
1
the same quadrant as the ith element of the vector yMF . Based Nr INt , which is diagonal matrix. Combining (3) and (19), the
on this property, the ith element of the initial solution vector ŝ(0) matrices U and V can be approximated as
can be chosen in a certain point of one quadrant according to 
Û(k+1) = ρ(k) 1 − γ (k) W Û(k)
the located quadrant of yMF rather than the conventional zero
vector, which is shown in Fig. 1. Hence, the ith row of the initial 
solution ŝ(0) for 64-QAM modulation can be expressed as + 1 − ρ(k) Û(k−1) + ρ(k) γ (k) HH H;
(0)

ŝi = ±4 ± 4i. (17) V̂(k+1) = ρ(k) 1 − γ (k) W Û(k) Ŵinv
For the problem of constellation points searching in the itera- 
tion process, the relative position between a constellation point + 1 − ρ(k) Û(k−1) Ŵinv + ρ(k) γ (k) HH HŴinv .
and the corresponding constellation point of the initial solution (20)
of the iteration will affect the performance of the iteration.
The equivalent channel gain Ui,i and NPI can be approximated
Below, the quadrant-certain initial points method proposed in
as
this paper is compared with traditional initial solution using the
(k+1)
zero vector method. Here, the advantages and disadvantages of Ui,i ≈ Ûi,i ;
each method are compared in terms of the distance between the
two initial solution methods and each constellation point. Taking

Nt
σi2 ≈ |Ui,j |2 Es +Vi,i N0 . (21)
64-QAM as an example, among the 64 constellation points, there
j=i
are 4 constellation points (±1 ± 1i) for which the traditional
zero initial solution method is better than the proposed initial Therefore, combining (19)–(21), the SINR ζi2 can be computed.
solution method, there are 8 constellation points (±1 ± 3i, However, these computations are complicated and computation-
±3 ± 1i) for which the two methods have same performance, ally complex. According to the properties of massive MIMO
and there are 52 constellation points for which the proposed systems, the Gram matrix and matrix U are diagonal dominant.

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LIU et al.: ENERGY- AND AREA-EFFICIENT RECURSIVE-CONJUGATE-GRADIENT-BASED MMSE DETECTOR 577

Hence, NPI can be approximated as

Algorithm 1: Proposed Recursive Conjugate Gradient
 (k+1) (RCG) Algorithm for Soft-Output MMSE Detection.
(k+1)
σi2 ≈ N0 Ûi,i Ŵinv . (22)
i,i 1: Inputs:
Combining (21) and (22), the SINR ζi2 in (4) can be approxi- 2: Nr × Nt flat Rayleigh fading channel matrix H;
mated as 3: Nr × 1 received signal vector at the BS y;
 2 4: parameters: iterative number k, noise power spectral
(k+1)
Ûi,i Nr density N0 , signal power spectral density Es ;
ζi2 ≈  (k+1) ≈ . (23) 5: Outputs:
(k+1) N0
N0 Ûi,i Ŵinv 6: LLR values;
i,i
7: Initialization:
These approximations avoid large-scale matrix multiplications 8: yMF = HH y, W = HH H + N0 Es −1 IM ;
and inversions, thereby reducing computational complexity and 9: for i = 1, 2, . . . , Nt do
increasing parallelism, which is suitable for hardware imple- 10: if Re(yiMF ) > 0, Im(yiMF ) > 0 then
mentations. Finally, the proposed algorithm is summarized in (0)
11: ŝi = 4 + 4i;
Algorithm 1. 12: else if Re(yiMF ) > 0, Im(yiMF ) < 0 then
[25] and [29] proposed two approximate methods for LLR (0)
13: ŝi = 4 − 4i;
calculation. [25] used the diagonal element of MMSE filtering
14: else if Re(yiMF ) < 0, Im(yiMF ) > 0 then
matrix W to approximate the value of SINR ζi2 to approximately (0)
calculate the value of the LLR. Since the diagonal elements of 15: ŝi = −4 + 4i;
matrix W are not exactly the same, the corresponding SINR ζi2 16: else if Re(yiMF ) < 0, Im(yiMF ) < 0 then
(0)
is different for each user (each diagonal element of matrix W). 17: ŝi = −4 − 4i;
Therefore, the SINR ζi2 for each user needs to be calculated. In 18: end if
addition, the SINR ζi2 needs to wait for the diagonal elements of 19: end for
matrix W to complete the calculation before starting. The data 20: ŝ(−1) = ŝ(0) , z(−1) = z(0) = yMF − Wŝ(0) ;
calculated before and after have certain correlations. Therefore, 21: Iteration:
considering the hardware implementation, the correlations will 22: for t = 0, 1, . . . , k − 1 do
affect the detector processing rate and throughput rate. [29] 23: η (t) = Wz(t) ;
approximates the values of SINR ζi2 and LLR by calculating 24: ξ (t) = (z(t) , z(t) ), φ(t) = (η (t) , z(t) );
(t)
the eigenvalues of matrix W. This method must calculate the 25: γ (t) = φξ (t) ;
eigenvalues of matrix W, which will introduce extra compu- 26: if t = 0 then
tational complexity to the RCG algorithm in this paper. In 27: ρ(0) = 1;
addition, the values of SINR ζi2 and LLR must be calculated 28: else  −1
(t) (t)
after calculating the value of matrix W and its eigenvalues. 29: ρ(t) = 1 − γγ(t−1) ξξ(t−1) ρ(t−1)1
;
Therefore, this method also has some data correlations, which 30: end if
will affect the processing rate and throughput rate of the detector. 31: ŝ(t+1) = ρ(t) (ŝ(t) + γ (t) z(t) ) + (1 − ρ(t) )ŝ(t−1) ;
In this paper, the value of SINR ζi2 is approximately calculated 32: z(t+1) = ρ(t) (z(t) − γ (t) η (t) ) + (1 − ρ(t) )z(t−1) ;
by Nr . The corresponding value of SINR ζi2 only needs one 33: end for
operation. Furthermore, there is no data dependency before and 34: LLR:
after the calculation. Therefore, compared with [25] and [29], 35: for i = 1, 2, . . . , Nt do
the approximate LLR method proposed in this paper is simple 36: for b = 1, 2, . . . , log2 Q do
and conducive to hardware implementation. 2
37: ϕb (ŝi ) = min0 | Uŝi,i
i
− s|
s∈Sb
B. Approximated Error 2
− min1 | Uŝi,i
i
− s| ;
s∈Sb
This section mathematically demonstrates that the proposed
RCG detection algorithm achieves a low approximate error. 38: ζi2 = N N0 ;
r

According to [31], the orthogonal basis p(k) and residual vector 39: Li,b (ŝi ) = ζi2 ϕb (ŝi );
z(k) in (5) satisfy: p(1) = z(0) and z(1) = z(0) − α(1) Wp(1) = 40: end for
z(0) − α(1) Wz(0) . Using mathematical induction, for the tth 41: end for
iteration, there are
m(t) − ŝ(0) be one vector of the space St ; then, there is

t−1
(t−1)

t−1
(t)
z(t−1) = ai Wi z(0) ; p(t) = bi Wi z(0) , (24)
t

i=0 i=0 m(t) − ŝ(0) = ci p(i) , (25)

i=1
(t−1) (t−1)
where ai and bi are constants. If z(t−1) is not zero, then
where ci is a constant. According to (5), there is
z(0) , Wz(0) , W2 z(0) , . . ., Wt−1 z(0) are linearly independent,
and p(1) , p(2) , . . ., p(t) can form t linear independent vectors.
t
ŝ(t) − ŝ(0) = α(i) p(i) . (26)
Therefore, these vectors have the same space, called St . Let
i=1

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578 IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 68, 2020

Combining (25) and (26), there are

Nt
2 2 2

Nt
 2  2 = |ci | |Pk (λi )|  max |Pk (λi )| |ci |2
 (t)   
m − s = m(t) − ŝ(t) + ŝ(t) − s
i
i=1 1
W W   2
 2  
 t
k  = max |Pk (λi )|2 Q(0) 
 (i) (i)  i W
= (ci − αi ) p − αi p   2
   
i=1 i=t+1 W  (0) 2
 t 2  k 2  max |Pk (x)| Q  . (34)
    λmin xλmax W
 (i)   (i) 
= (ci − αi ) p  +  αi p 
    Let ς = λmax +λmin −2x , and there is x=
i=1 W i=t+1 W λmax −λmin
 2  2  2 (λmax +λmin )−(λmax −λmin )ς λ + λ
      . Let d = ς|x=0 = max min ,
= m(t) − ŝ(t)  + ŝ(t) − s  ŝ(t) − s . (27) 2 λmax −λmin
W W W and there is d > 1. Therefore, Pk (x) in (34) can be rewritten as
In (27), there is a definition as xW =(Wx, x) 2 . When
1  
(λmax + λmin ) − (λmax − λmin ) ς
m(t) = ŝ(t) , the m(t) − ŝ2W in (27) reaches its minimum, Pk (x) = Pk = Rk (ς) ,
2
which can be expressed as (35)
   
 (t)   (t)  where Rk (ς) is a polynomial of ς. When x arises from λmin to
ŝ − s = (t)min m − s . (28)
W (0) m −ŝ ∈St W λmax , ς falls from 1 to −1. In addition, there are

Let ŝ(t) − s = Q(t) , there are Rk (d) = Pk (0) = 1;


min max |Pk (x)| = max |Rk (ς)|
z(0) = yMF − Wŝ(0) = W s − ŝ(0) = −WQ(0) . (29) Pk (x)∈Xk λmin xλmax −1ς1

Hence, combining (24), (25), and (29), (m(t) − ŝ) in (27) can 1 1
= =  , (36)
be expressed as Tk (d) Tk λ max +λmin
λmax −λmin

k
(ς)
m(t) − s = ŝ(0) + ci p(i) − s where Rk (ς) = TTkk (d) . According to the formula of the k times
i=1
Chebyshev polynomial, there is

k 

k
i−1
k−1 1  
2
k  
2
(i) Tk (x) = x+ x −1 + x− x −1 . (37)
= Q(0) + ci bj Wj z(0) = Q(0) + c i Wi r(0) 2
i=1 j=0 i=1
  Therefore, Tk ( λmax +λmin ) in (36) can be computed as (38)

k λmax −λmin
= I− c i W i Q(0) = Pk (W) Q(0) , (30) shown at the bottom of the next page. Hence, combining (31),
i=1
(33), (34), (36), and (38) there is
  √ √ k  
where c i is a constant, Pk (W) is the k-degree polynomial of  (k)  λmax − λmin  (0) 
ŝ − s  2 √ √ ŝ − s
matrix W, and Pk (0) = 1. All polynomials satisfying Pk (0) = W λmax + λmin W
1 are defined as a set Xk ; therefore, according to (30), (28) can √ k  
be expressed as κ−1  (0) 
=2 √ ŝ − s , (39)
    κ+1 W
 (k)   
ŝ − s = min Pk (W) Q(0)  . (31)
W Pk ∈Xk W where κ = λmax /λmin . Given the difficulty of determining the
Because W is a symmetric positive definite matrix, its eigen- eigenvalues of matrix W, the largest and smallest eigenvalues
values (λ1 , λ2 , . . . , λNt ) are all positive. Therefore, there are are approximated because of the properties of massive MIMO
eigenvectors ψ (1) , ψ (2) , . . . , ψ (Nt ) , which satisfy: systems. In a massive MIMO system, as Nr and Nt increase,
   the λmax and λmin of matrix W can be approximated as
  
ψ (i) , Wψ (j) = 0; ψ (i)  = 1, (32)
W λmax ≈ Nr + Nt + 2 Nr Nt ;

where i, j = 1, 2, . . . , Nt , and i = j. Suppose λmin ≈ Nr + Nt − 2 Nr Nt . (40)

Nt
Therefore, combining (39) and (40), (39) can be approximated
Q(0) = ci ψ (i) . (33)
as
i=1
   k/2  
Let λmax and λmin be the largest and smallest eigenvalues of  (k)  Nt  (0) 
ŝ − s  2 ŝ − s . (41)
matrix W, respectively. Hence, there are W Nr W
 2 According to (41), when the number of users (Nt ) is fixed, as the
 2  n 
   
Pk (W) Q(0)  =  ci Pk (λi ) ψ (i)  number of BS antennas Nr increases, the approximation error
W   will decrease. In other words, when the ratio between Nt /Nr
i=1 W

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LIU et al.: ENERGY- AND AREA-EFFICIENT RECURSIVE-CONJUGATE-GRADIENT-BASED MMSE DETECTOR 579

TABLE I
NUMBER OF REAL-VALUED MULTIPLICATIONS

TABLE II
NUMBER OF REAL-VALUED MULTIPLICATIONS IN A 128 × 8 MIMO SYSTEM

decreases, the approximation error of the proposed method will
decrease. For massive MIMO systems, the number of antennas at
the BS is much larger than the number of users, which indicates
that the proposed method achieves low approximation error.
In addition, according to (40) and (41), when the number of
iterations k increases, the approximation error further decreases.
Therefore, for large k, ŝ(k) − sW approaches zero. Hence, in
a massive MIMO system, the proposed method can achieve a
low approximation error that approaches zero.
C. Algorithm Analyses
The number of real-valued multiplications (RMUL) is gen-
erally used to evaluate the computational complexity of meth-
ods. In the proposed RCG iterative algorithm, the first set of
calculations consists of a series of computations of preiterative
parameters yMF , W, and z(0) . These computations are required
to achieve the computations of a conjugate transpose matrix of an
Nr × Nt channel matrix H with an Nr × 1 vector y, an Nt ×
Nr matrix HH with an Nr × Nt matrix H, and an Nt × Nt
symmetric matrix W with an Nt × 1 vector ŝ(0) . The second set
of calculations consists of a series of multiplications of a matrix
with a vector in an iterative process, that is, the multiplication
of an Nt × Nt matrix W with an Nt × 1 vector z. The third
set of calculations is two inner products of ξ (k) = (z(k) , z(k) )
and φ(k) = (η (k) , z(k) ) in an iterative process. The final set of
calculations consists of updating ŝ and z in an iterative process.
Note that when the iterative number k = 1, ρ(0) = 1. Therefore,
the multiplications in (9) can be ignored. Table I compares the
computational complexities of the various methods. Table II
shows the total number of real-valued multiplications for all
the algorithms with different k in a 128 × 8 MIMO system. The
proposed RCG method has a lower computational complexity
than that of the GS [21], CG [32], and conjugate gradient least
squares (CGLS) [33] methods. For example, when Nr = 128,
Nt = 8, and k = 2, the proposed RCG method requires 21632
RMULs, which is less than those of the GS (23152 RMULs),
CG (23304 RMULs), and CGLS (27232 RMULs) methods. The
OCD [28] and PCI [29] methods achieve large-scale matrix
multiplication and inversion in an implicit way. Compared with
other explicit methods, these implicit methods achieve low com-
putational complexity (16416 and 12344 RMULs, respectively),
as shown in Table I and Table II. However, these implicit meth-
ods ignore the channel hardening of a massive MIMO system.
Therefore, in an actual system, the same Gram matrix needs
to be calculated multiple times. Hence, the implicit methods
suffer from high computational complexity in an actual system,
which indicates high energy and area consumptions of implicit
architectures. As k increases, the computational complexity of
the NSA method increases. When k < 3, the NSA method [19]
had a lower complexity of O(Nt2 ). However, when k = 3, this
method had a computational complexity of O(Nt3 ) that was even
higher than that of exact MMSE detection for k > 3. In general,
to ensure detection accuracy, k should be greater than 3 in the
NSA method.
Additional important aspects of the hardware implementation
of the detection algorithm must still be considered. The paral-
lelism of a method is an important issue in both algorithm design

   √ k  √ k 
λmax + λmin 1 λmax + λmin 2 λmax λmin λmax + λmin 2 λmax λmin
Tk = + + −
λmax − λmin 2 λmax − λmin λmax − λmin λmax − λmin λmax − λmin
⎡ √ 2 k  √  2 k ⎤  √
√ √ √ k  √ √ k 
1⎣ λmax + λmin λmax − λmin 1 λmax + λmin λ max − λ min
= + ⎦= √ √ + √ √
2 λmax − λmin λmax − λmin 2 λmax − λmin λmax + λmin
√ √ k
1 λmax + λmin
 √ √ (38)
2 λmax − λmin

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580 IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 68, 2020

and hardware implementation. With regard to hardware imple-

mentation, there are strong correlations among all elements of
the estimated vectors in the GS, CHD, LUD, and WeJi methods,
which means that these methods have low parallelism [16],
[17], [21], [25], [29]. In the RCG method, all elements in the
matrices and vectors, such as matrix W in (2) and vector η (k)
in (8), can be computed in parallel. In addition to parallelism
for elements, steps can also be calculated in parallel, such as the
computations of φ(k) and ξ (k) in (11) and z(k) and ŝ(k) in (8)
and (9). In traditional CG and CGLS methods [32], [33], these
computations cannot be parallelized. Hence, the proposed RCG
method can be performed with high parallelism. Fig. 2. SER performance comparison between the proposed initial solution
and the traditional zero-vector initial solution (128 × 8 MIMO system).
The acronym RCG was introduced to distinguish it from
traditional CG algorithms. Conventional CG and CGLS methods
have been proposed to achieve massive MIMO detection [32],
[33]. Nonetheless, compared with the proposed RCG method,
the algorithm proposed in this paper has advantages in four
aspects: parallelism, complexity, iteration number and initial
solution design. First, the conventional CG [32] and CGLS [33]
methods compute linear equations with relatively low paral-
lelism. For example, in an iterative process, each step must be
calculated in sequence; no two steps can be calculated simultane-
ously [32], [33]. However, the proposed RCG method achieves
high parallelism between/in steps, as discussed above. This
advantage is important in hardware implementation. Second,
as shown in Table I and Table II, the proposed RCG method has
a lower computational complexity than that of the CG [32] and
CGLS [33] methods, as discussed above. Third, although the Fig. 3. SER performance comparisons between the proposed algorithm and
CG [32] and CGLS [33] methods can solve the linear equation other algorithms (128 × 8 MIMO system).
in massive MIMO detection, such as (2), they require a large
number of iterations (generally larger than three [32], [33]); thus,
these methods do not converge very rapidly. A large number fading across the coded symbols. At the receiver, LLRs were
of iterations corresponds to higher computational complexity, used as the soft input for Viterbi decoding. Additionally, as
which results in high energy and area consumptions. Finally, a in [18], [19], [21], the signal-to-noise ratio (SNR) was defined
zero vector is used as the initial solution in these methods [32], at the receiver.
[33]. A good initial solution in iterative steps can make the com- Fig. 2 compares the SER performances of the RCG method,
putation reach an accurate final solution with a relatively small the proposed initial solution and the conventional zero-vector
number of iterations; thus, choosing a proper initial solution can initial solution. According to Fig. 2, to have the same SER and
efficiently accelerate signal detection. The initial solution of the number of iterations (10−2 , k = 2), the proposed initial solution
proposed RCG method is obtained by using the property of the requires 1.74 dB less SNR than the traditional zero-vector initial
massive MIMO system, which converges faster than the zero solution. Hence, the proposed initial solution achieves a lower
vector in [32], [33]. In addition, there is no added computational loss in terms of detection accuracy for a given number of
complexity. Hence, the proposed method can reduce hardware iterations. In addition, the simulated SER performance obtained
resource consumption and increase throughput. for k = 2 using the proposed initial solution is very close to that
achieved for k = 3 using the conventional initial solution, which
indicates that the proposed initial method reduces computational
IV. SYMBOL-ERROR-RATE PERFORMANCE
complexity while maintaining a similar detection accuracy.
To evaluate the performance of the proposed RCG method, Fig. 3 shows the simulated SER results of the proposed
simulated SER results for RCG are compared with those of RCG method and different detection algorithms in a 64-QAM
state-of-the-art methods, such as NSA and WeJi. The SER 128 × 8 MIMO system. The proposed RCG method achieves
performance of exact MMSE detection based on the CHD high detection accuracy compared with recent methods. For
method is also provided for comparison. In these simulations, example, as shown in Fig. 3, when k = 2, the SNR required
the settings are adopted as a 64-QAM modulation scheme and a to achieve an SER of 10−2 was 10.16 dB, which was close
rate-1/2 industry standard convolutional code with a [133o 171o ] to the performance of the CHD-based MMSE (9.66 dB) [16],
polynomial along with a random interleaver. In addition, coding GS (10.10 dB) [21], [22] and OCD (10.11 dB) [28] detection
was performed over 120 symbols, and the number of frames was methods. In contrast, to achieve the same SER, the required
10,000. The channels were assumed to exhibit i.i.d. Rayleigh SNRs of the WeJi [25] and NSA [18]–[20] methods are 10.42 dB

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LIU et al.: ENERGY- AND AREA-EFFICIENT RECURSIVE-CONJUGATE-GRADIENT-BASED MMSE DETECTOR
Fig. 4. SER performance comparisons at different MIMO dimensions
(128 × 8 and 128 × 16 MIMO systems).
and >20 dB, respectively. All simulations presented above are
based on 128 × 8 MIMO systems and indicate that the proposed
RCG algorithm is advantageous in terms of SER performance.
To confirm that the proposed method maintains its advan-
tages for higher-order MIMO systems, Fig. 4 shows the SER
performances under different simulation settings (128 × 16 and
128 × 8 MIMO systems). According to Fig. 4, compared with
the MMSE detection algorithm, the proposed algorithm with
k = 3 suffers an SNR loss of 0.34 dB (achieving an SER of
10−2 ) in a 128 × 16 MIMO system. The proposed method
achieves better detection performance than those of the methods
of WeJi (>7 dB) and NSA (>7 dB) in [25] and [18]–[20].
Fig. 4 shows that, to achieve the same SER, the SNR required
by the proposed algorithm is also smaller than that required by
the NSA [18]–[20] and WeJi [25] methods, thus verifying that
the proposed algorithm can maintain its advantages at different
MIMO dimensions.
Different simulation results are shown in Fig. 2–4. Fig. 2 is
used to compare the SER performances of the proposed initial
solution in this paper with that of the traditional initial solution.
To have the same SER, the proposed initial solution requires
less SNR than the traditional zero-vector initial solution. Fig. 3
is used to compare the SER performances of RCG algorithm
and other related methods. The proposed RCG method achieves
high detection accuracy compared with related methods. Fig. 4 is
used to compare the SER performance of different algorithms at
different MIMO dimensions. The proposed method can maintain
its advantages at different MIMO dimensions. To show the SER
performance in a more realistic channel model, the Kronecker
channel model was used [21], [25], [29], [34]. In this channel
model, channel matrix H is influenced by a correlation ma-
trix. The correlation matrix is defined with a correlation factor
between the neighboring branches (ξ). In this simulation, the
correlated factor ξ is 0.2, 0.5 and 0.7, sequentially. Fig. 5 shows
that, to achieve the same SER, the SNR required by the proposed
RCG method is smaller than that required by the CG, RI and
NSA methods, which proves that the proposed algorithm can
maintain its advantages in a realistic model.
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581
Fig. 5. SER performance comparison for the Kronecker channel model
(128 × 8 MIMO system).
Fig. 6. Top-level block diagram of VLSI architecture.
V. VLSI ARCHITECTURE
In this section, a VLSI architecture is designed to achieve
massive MIMO detection based on a modified MMSE signal
detection algorithm. The architecture was designed for a case
study of a 64-QAM, 128 × 8 massive MIMO system. Fig. 6
shows the top-level block diagram of the proposed VLSI ar-
chitecture. To achieve high throughput with limited hardware
resources, the top-level architecture is fully pipelined. The VLSI
architecture is divided into three main modules. In the first
module, a PE array is used to compute the matched-filter yMF
and matrix W (Algorithm 1, line 8). These input data are stored
in different memories of the architecture. The outputs are used to
compute the initial solution s(0) of the estimated vector and other
parameters in the preiterative block (Algorithm 1, lines 9-20).
In the second module, a user-level pipeline module iteratively
estimates the transmitted vector s(k) by using the proposed
RCG method, which reduces computational complexity and
enhances the parallelism of each iteration. In this module, vector
η (k) (Algorithm 1, line 23) and parameters ξ (k) , φ(k) , and γ (k)
(Algorithm 1, lines 24–29) are computed. Then, the estimated
signal ŝ(k) (Algorithm 1, line 31) and residual vector z(k) are
computed (Algorithm 1, line 32). In the third unit, the final vector
ŝ(k) and the parameters Nr and N0 are computed to obtain the
soft outputs (LLRs) (Algorithm 1, lines 35-41). These blocks
are further described in the following subsections.
A. Processing Element Array
In the first module, a parallel PE array computes matrix W
and vector yMF , as shown in Fig. 7. In the array, there are two
2
types of PEs, including Nt PE-As and Nt +N 2
t
PE-Bs, and all
582
Fig. 7. Architecture of the processing element array.
Fig. 8. Architectures of the PE-A and PE-B.
PEs are deeply pipelined. For a 128 × 8 massive MIMO system,
the numbers of PE-As and PE-Bs are 8 and 36, respectively. The
PE-As are used to compute the diagonal elements of matrix W;
these elements are real-valued. The PE-Bs are used to compute
the off-diagonal elements of the matrix W (28 PE-Bs) and vector
yMF (8 PE-Bs). In one clock cycle, eight elements of HH and
y are input for computation, and the PEs exhibit echelonment
with a high processing speed because G is an asymmetric matrix.
The different types of calculations included in the PEs (all PEs
in this massive MIMO detector) are achieved through multiple
pipelines. The outputs, matrix W and vector yMF are transmitted
to the next module to iteratively computate the final vector, ŝ(k) .
As shown in Fig. 8(a), each PE-A includes eight groups of the
same arithmetic logical units (ALUs), one accumulator, and an
adder for the diagonal element. In each PE-A, there are total 16
multipliers, 16 adders and 8 subtracters in total. ALU is used to
compute part of the diagonal element in the Gram matrix. Then,
the results of all ALUs are accumulated to obtain the value Gi,i .
Fig. 8(b) shows the details of the PE-B, which computes the
complex-valued multiplications and accumulations. There are
eight groups of ALUs and two accumulators in a PE-B. In each
PE-B, there are 32 multipliers, 38 adders and 8 subtracters in
total. The real and imaginary parts of the output are computed
at the same time. The outputs of the PE-A are transmitted to
the next unit per clock cycle after the initial latency. Hence, this
parallel PE array can achieve high throughput, high hardware
utilization, and high energy and area efficiencies.
In [8], [18], [19], [22], [25], systolic arrays were used to
compute the Gram matrix G and matched-filter vector yMF .
In contrast to the proposed systolic array, the computations in
these architectures do not compute the diagonal and off-diagonal
elements of matrix G simultaneously. Hence, the computations
of the off-diagonal elements of matrix G are delayed. However,
these diagonal and off-diagonal elements are required at the
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IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 68, 2020
Fig. 9. Architecture of the user-level pipeline.
same time to achieve the following detection. The subsequent
user-level pipeline module unit must wait longer to receive its
inputs. Therefore, the throughput of the overall architecture
is reduced, and the latency is increased. In [18], [19], [22],
double-sided inputs for PE-A are used; however, in the proposed
architecture, single-sided inputs are used, which reduces the
number of registers on the input side by half. In architectures
based on implicit methods (such as OCD, PCI, and IIC), the
computations of the Gram matrices are transmitted to vector
multiplications [28]–[30]. Therefore, these implicit architec-
tures have advantages in terms of throughput, hardware resource
usage, and power consumption. However, in an actual system,
the same Gram matrix results as those in the implicit archi-
tectures are computed many times when considering channel
hardening. Hence, in an actual system, the energy consumption
and latency of the proposed architecture are lower than those
of these implicit architectures because of the reusability of the
Gram matrix result.
B. User-Level Pipeline Module
The user-level pipeline (Fig. 9) is designed to achieve RCG
iteration, which includes two blocks: a preiterative block and
an iterative block. The initial solution and some parameters are
computed in the preiterative block, as shown in Fig. 9(a). In the
preiterative block, there are Nt parallel PE-Cs (8 PE-Cs for a
128 × 8 MIMO system) to compute the initial solution by using
the proposed initial solution method. According to the elements
of the vector yMF , the initial solution vector ŝ(0) can be set. Then,
according to (7), the first residual vector z(0) can be computed by
using Nt parallel PE-Ds (8 PE-Ds for a 128 × 8 MIMO system).
In each PE-D, there are 8 multipliers, 8 adders and 8 subtracters
to multiply the matrix and vector. The details of PE-C and PE-D
are also shown in Fig. 9(a). The iterative block estimates and
updates the signal ŝ(k) and residual z(k) according to matrix
W. As shown in Fig. 9(b), the whole iterative block includes
two stages, which complete two iterations. The details of all
stages are shown in Fig. 10. In the first stage, there are Nt + 2
parallel PE-Bs (10 PE-Bs for a 128 × 8 MIMO system), which
are used for matrix-vector multiplications to obtain parameters
η (0) in (8) and ξ (0) , φ(0) , and η (0) in (11). In addition, there
are one PE-E and one PE-F to compute vectors ŝ(1) and z(1)
according to (8) and (9). In each PE-E (PE-F), there are 8 highly
parallel multipliers and 8 adders (subtracters). In the second
stage, similar PE-Bs are used to compute the parameters in the
LIU et al.: ENERGY- AND AREA-EFFICIENT RECURSIVE-CONJUGATE-GRADIENT-BASED MMSE DETECTOR
Fig. 10. Architecture of the iterative block.
second iteration. In addition, there are additional operators used
to compute the parameter ρ(1) in (14). Then, two PE-Es can be
used to update the signal ŝ(2) according to the outputs of the first
stage. The calculations of these two stages were deeply pipelined
based on the user level, resulting in high parallelism. Moreover,
the hardware utilizations of PE-B, PE-E and PE-F are high.
In [28], the GS iteration is achieved in this architecture. Com-
pared with [28], the proposed user-level parallel architecture can
be utilized in this iterative module. Therefore, this module can
be used to obtain a fully pipelined architecture that achieves high
throughput of the complete system. In [18], [19], similar iterative
computations were performed in eight groups of lower triangular
systolic arrays. In those architectures, the pipeline delay was
determined by the time consumption of the lower triangular
systolic arrays. Hence, the throughput of the entire system was
limited because of resource limitations. The proposed architec-
ture can perform the iterations using highly parallel vector mul-
tiplications in place of the matrix multiplications, which results
in high throughput and low area and power consumptions. In [8],
[25], the iterations are achieved by one-row-based systolic ar-
rays. These architectures reduced the hardware consumption by
using these one-row-based systolic arrays. However, compared
with the proposed architecture, these architectures increased the
pipeline delay because of the transmission of data between the
PEs in the systolic arrays. Hence, throughput will be limited to
some extent in these architectures.
C. LLR Module
Fig. 11 shows the block diagram of the approximated LLR
module, which includes 12 log2 Q PE-Fs in this architecture
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583
Fig. 11. Architecture of the approximated LLR processing unit.
TABLE III
BIT-WIDTH OF ALL RCG VARIABLES
for Q-QAM modulation. According to (4), the computation of
the LLR values requires the channel gain, Ui,i ; NPI, σi2 ; and
SINR, ζi2 . Based on (4), the function ϕb (ŝi ) is reformulated
as a piecewise linear function for Gray mapping, which can
be efficiently achieved in the hardware architecture. In this
architecture, each of the linear equation coefficients, ϕb (ŝi ), are
stored in a correction LUT. To achieve the computation of the
approximate LLRs for each transmitted bit, the next problem is
the values of SINR ζi2 . In this architecture, the approximated
methods in (23) are used to calculate the SINR ζi2 using Nr and
N0 . In addition, the reciprocal of Nr is achieved by the LUT.
Next, the bit LLR values, Li,b , are calculated using the SINR ζi2 .
The block allows the computations of the LLRs to be simplified,
which increases the processing speed and reduces both the area
and power consumptions in the architecture.
VI. IMPLEMENTATION AND COMPARISON
The proposed hardware architecture is verified on an FPGA
platform (Xilinx Virtex-7) and implemented using TSMC 65 nm
CMOS technology. Details of the hardware features, derived
from the FPGA and silicon implementations, are compared to
those of state-of-the-art designs. In addition, the fixed-point
design and the SER performance with fixed-point are also
presented.
A. Fixed-Point Design
In order to facilitate hardware implementation, fixed-point
arithmetic is used in the whole detector. Based on the large
amount of simulations, the detector data are fixed. Additionally,
the bit-widths of the real and imaginary parts are the same for
the complex computation. The bit-widths are 12-bit for input
matrix H, received signal y and N0 . The bit-width of the output,
estimated signal s, is 13-bit, and the bit-width of the LLR value
is 12-bit. The bit-width precision of all RCG variables are listed
in Table III. The SER performance with fixed-point is shown in
584
TABLE IV
COMPARISON OF RESOURCE USAGE ON A XILINX VIRTEX-7 FPGA
a
SNR values are targeted to an SER of 10−2 with floating-point designs, and the iteration number is listed for each algorithm in the simulation. In this work, the SNR
is 10.38 dB with a fixed-point design. The SNR in this work is close to the performance of other algorithms. In the case of similar detection accuracy, the throughput,
resource consumption and hardware efficiency are compared with related designs.
b
Hardware efficiency is defined as throughput/normalized source consumption (NSC), which is computed as NSC = LUTs+FFs+DSP × 280 [30].
Fig. 12. SER performance of the fixed-point design and comparison with other
detectors (128 × 8 MIMO system).
Fig. 12 (labeled ‘fp’) for a 128 × 8 MIMO system. In addition,
related designs with k = 2 are also included in Fig. 12, such as
NSA, GS, OCD, WeJi, IIC, and CHD. In this architecture, the
SNR required to achieve an SER of 10−2 was 10.38 dB, 0.21 dB
less than that of the floating-point design. The fixed-point SNR
is comparable with related designs, such as NSA, GS, OCD,
WeJi, and IIC. Notably, these results are based on floating-point
design.
B. FPGA Implementation
Table IV lists the key results of the FPGA implementation
of the proposed architecture and other state-of-the-art designs
in [13], [19], [22], [25], [28], [30], [33]. In this table, the iteration
numbers and SNR values (targeting an SER of 10−2 ) are listed
for all the algorithms, and the SNR values are based on floating-
point designs with the listed iteration number in each algorithm.
The SNR in this work (10.16 dB) is close to the performances of
other algorithms (9.66–10.47 dB). Note that the TASER [13] is a
nonlinear algorithm. In massive MIMO systems (predominantly
Nr  Nt ), linear algorithms can achieve near-optimal perfor-
mance compared with nonlinear algorithms [2]–[4], [18]–[22].
In addition, the SNR is 10.38 dB in this architecture with the
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fixed-point design. Based on the similar SER performances,
the throughputs and efficiencies are compared. The throughput
in this architecture is similar to that in the CHD architecture
in [16], but the resource consumption is noticeably reduced.
According to [30], the normalized source consumption (NSC)
can be computed as NSC = LUTs+FFs+DSP×280. Hence, the
hardware efficiency (throughput/NSC) of the RCG architecture
is increased by 2.92× compared with that of the CHD architec-
ture in [16]. Compared with the CHD architecture, the architec-
tures in this work and recent works [19], [22], [25], [28], [30],
[33] achieve massive MIMO detection with reduced complexity.
Compared with the WeJi [25], OCD [28], NSA [19], GS [22], and
CG [33] architectures, the proposed RCG architecture achieves
2.05×, 1.68×, 1.04×, 13.13×, and 31.5× increases in through-
put, respectively. Considering that there are different hardware
consumptions in these architectures, hardware efficiency is used
to achieve a fair comparison. Compared with the WeJi [25],
OCD [28], NSA [19], GS [22], and CG [33] architectures, the
RCG architecture achieves 1.66×, 1.60×, 2.32×, 4.44×, and
1.75× increases in throughput, respectively. Note that com-
pared with the RCG architecture, the IIC architecture achieves
a 1.45× increase in throughput. However, the IIC architec-
ture requires more resources; therefore, the RCG architecture
achieves 1.33× greater hardware efficiency than the IIC ar-
chitecture. In the TASER architectures, there is less hardware
resource consumption than in the RCG architecture. However,
compared with these two TASER architectures, the RCG ar-
chitecture achieves 16.58× and 12.6× increases in throughput.
Considering hardware efficiency, the RCG architecture achieves
1.20× and 2.88× greater efficiency than the two architectures.
C. Silicon Implementation
The proposed MMSE detector was implemented on
1.87 × 1.87 mm2 silicon using TSMC 65 nm CMOS technology.
Fig. 13 shows the die micrograph and the measured frequency
and power consumption for different supply voltages of the
chip. This chip was able to achieve a 1.5 Gbps data rate with
a 500 MHz working frequency while dissipating 557 mW at
1.2 V. The measured results show that under supply voltages of
LIU et al.: ENERGY- AND AREA-EFFICIENT RECURSIVE-CONJUGATE-GRADIENT-BASED MMSE DETECTOR 585

TABLE V
COMPARISON OF ASIC IMPLEMENTATION RESULTS

a
SNR values are targeted to an SER of 10−2 with floating-point designs, and the iteration number is listed for each algorithm in the simulation. In this work, the SNR
is 10.38 dB with a fixed-point design. The SNR in this work is close to the performance of other algorithms. In the case of similar detection accuracy, the throughput,
area, power consumption, energy and area efficiencies are compared with related designs.
b
Energy and area efficiencies are defined as throughput/power and throughput/area (gate count), respectively.
c
There are two kinds of normalized aspects. (1) Technology normalized to 65 nm technology. According to [9], [13], [25], [28], frequency and power are increased
V log2 Nt
by s and 1s × ( dd 2 8
 ) , respectively. (2) MIMO size normalized to 128 × 8. According to [12], throughput is increased by N × log 8 , and power and area are
V t 2
dd
128 8 log2 Nt
increased by Nr × Nt × log2 8 .

near-optimal performance compared with nonlinear algorithms,

Fig. 13. (a) Die micrograph; (b) Measured frequency and power consumption
for different supply voltages.
0.9 V, 1.0 V, and 1.1 V, the proposed chip achieves frequencies
of 310 MHz, 330 MHz, and 390 MHz and power consumptions
of 194 mW, 283 mW, and 409 mW, respectively. In [10], under
supply voltages of 0.7 V and 1.0 V, the frequencies are 238 MHz
and 569 MHz and the power consumptions are 23.4 mW and
127 mW, respectively. In [12] and [16], the supply voltages
are both 0.9 V, and in [17] and [25], the supply voltages are
both 1.0 V. The measured results of these circuits are shown
in Table V. Table V lists the detailed hardware features of the
RCG architecture and the state-of-the-art designs in [10], [12],
[16], [17], [19], [20], [25], [27]. In Table V, the SNR values
targeted to an SER of 10−2 are listed for all these algorithms.
In addition, these SNR values are based on floating-point de-
signs with the listed iteration number in each algorithm. This
work (10.16 dB) achieves performance close to that of the
state-of-the-art designs (9.66–10.42 dB). In massive MIMO sys-
tems (predominantly Nr  Nt ), linear algorithms can achieve
such as EPD [10], MPD [12], and MCTS [27]. [2]–[4],
[18]–[22]. Based on the similar SER performances, the en-
ergy and area efficiencies are compared. In this chip, the
core area is 3.50 mm2 , and the energy and area efficiencies
are 2.693 Mbps/mW and 1.093 Mbps/kGE, respectively. The
energy and area efficiencies of related designs are 1.096–
52.038 Mbps/mW and 0.3–3.974 Mbps/kGE. The architecture
in [17] achieves high efficiency because of the small MIMO
size, which is used in traditional MIMO system. Hence, consid-
ering that different MIMO size and technology influence these
efficiencies, the energy and area efficiencies are normalized to
the same MIMO size and technology (using the full-scaling
approach) to achieve fair comparisons. The same normalization
method is also used in [12]. The RCG architecture achieves
2.47×, 2.39×, 10.60×, and 7.09× greater normalized energy
efficiency (throughput/power) than the WeJi [25], LUD [17],
NSA [19], [20], and MCTS [27] architectures, respectively. In
addition, the normalized area efficiency (throughput/gate count)
of RCG is 1.15×, 8.81×, 5.25×, and 1.18× that in the WeJi [25],
LUD [17], NSA [19], [20], and MCTS [27] architectures, respec-
tively. Note that the values of the NSA and MCTS architectures
are layout results without silicon proof. Note that the proposed
RCG architecture includes preprocessing. To achieve fair com-
parisons with recent preprocessing-excluded architectures [10],
[12], [16], the results of RCG without preprocessing are listed
in Table V. Despite the preprocessing in the detector (only con-
sidering postpreprocessing design), the proposed architecture
achieves 1.62 mm2 core area, 12.5 Mbps/mW energy efficiency,
and 2.517 Mbps/kGE area efficiency, respectively. The state-of-
the-art designs without preprocessing achieve 0.58-2.00 mm2

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586
core area, 14.173-102.7 Mbps/mW energy efficiency, and 0.499-
6.855 Mbps/kGE area efficiency, respectively. Like [17], the
architecture in [12] achieves high efficiency because of the
small MIMO size. Hence, the energy and area efficiencies are
normalized to the same MIMO size and technology to achieve
fair comparisons. The RCG architecture achieves 6.85×, 7.18×,
and 2.29× the normalized energy efficiency in the EPD [10],
CHD [16], and MPD [12] architectures, respectively. In addi-
tion, the normalized area efficiency of the RCG architecture is
11.7×, 2.88×, and 2.39× that of the designs in the EPD [10],
CHD [16], and MPD [12] architectures, respectively. Note that
the architectures in [10] and [16] support higher modulation
schemes.
The proposed architecture has a throughput of 1.5 Gbps, and
the throughput of the related works are 0.3-8 Gbps [12], [16].
Notably, the frequency of the architecture proposed in [19], [20]
reaches 1 GHz. Because the throughput related to the amount of
resource provision, area (gate count) and power are both critical
data for evaluating efficiency. In the proposed architecture, the
gate count is 1372 kGE, and the power consumption is 557 mW.
In related works, the gate counts are 347-6650 kGE [17], [19],
[20], and the power consumptions are 26.5-1720 mW. Without
considering preprocessing, the gate count of the proposed archi-
tecture is 596 kGE, and the power consumption is 120 mW. The
gate counts of architectures in [17], [19], [20] are 148-3607 kGE,
and the power consumptions are 18-127 mW. [10] and [16] adopt
28 nm technology, [12] adopts 40 nm technology, [19] and [20]
adopt 45 nm technology. This paper adopts 65 nm technology.
The normalized methodology used in this paper has two aspects:
(1) technology normalized to 65 nm technology. (2) MIMO
size normalized to 128 × 8. These two normalized methods are
commonly used in related research and could provide reasonable
information. The normalized energy efficiency of the proposed
architecture is higher than that of [19], [20], and the normalized
area efficiency is higher than that of [10], [16], [25]. The pro-
posed architecture has advantages over related works in terms
of throughput, power consumption, area, normalized energy and
area efficiencies, owing mainly to the following reasons: (1)
Low complexity of the algorithm: According to Table I and
Table II, the proposed RCG algorithm has lower complexity
than the other algorithms, such as NSA [19], [20] and CHD [16].
When compared with nonlinear algorithms, such as EPD [10]
and MPD [12], the RCG algorithm also maintains its complexity
advantage. Therefore, the RCG algorithm will consume fewer
hardware resources than other algorithms when realizing similar
throughput. Additionally, higher normalized energy and area
efficiencies can be achieved. Complexity is one consideration
for the algorithm design in this paper. (2) High parallelism of
the algorithm: According to the analysis of Section III-C, the
proposed RCG algorithm has high parallelism in the iterative
process and therefore has higher throughput and normalized
energy and area efficiencies. The other related designs, such
as CHD [16], LUD [17], and WeJi [25], face problems with
parallelism. High parallelism is also an important consideration
for the algorithm design of this paper. (3) Optimized co-design
of the algorithm and architecture: The design of the algorithm
fully considers the hardware implementation. In other words,
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algorithm is a hardware-friendly design. Meanwhile, the ar-
chitecture design fully utilizes the advantage of the proposed
algorithm, which improves the hardware utilization and reduces
resource consumption. (4) Optimized fixed-point design: The
fixed-point design of the proposed architecture is determined by
a large number of simulations. The fixed-point design achieves
a short bit-width with an acceptable SER performance loss. (5)
Deep pipeline design: In the whole architecture, a deep pipeline
is designed to improve the throughput according to the prop-
erties of the proposed algorithm. For example, the processing
element array and user-level pipeline module in Section V-A
and Section V-B implement deep pipelines according to the
characteristics of the algorithm. Therefore, high throughput and
hardware utilization are achieved, which results in high energy
and area efficiencies. Based on the optimized design of both the
algorithm and architecture, the proposed architecture achieves
advantages over related works in terms of normalized energy
and area efficiencies.
VII. CONCLUSION
We have proposed a modified massive MIMO detection al-
gorithm based on the RCG method. In addition, according to
the properties of massive MIMO systems, a quadrant-certain-
based initial method is proposed. Moreover, an approximated
LLR computation method is proposed in RCG to simplify
the calculations. Then, we theoretically demonstrate that the
proposed RCG method achieves low approximated error. Sim-
ulation results shows that the SNR required to achieve an SER
of 10−2 is 10.16 dB, which is close to that of the state-of-the-
art designs (9.66-10.42 dB). To demonstrate the effectiveness
of our algorithm, we have proposed a VLSI architecture that
consists of a parallel processing element array and a deeply
pipelined user-level method. We have verified the architecture
on FPGA and fabricated a chip on silicon with TSMC 65 nm
CMOS technology. The chip achieves 1.5 Gbps throughput
with 3.5 mm2 silicon area and 557 mW power consumption
at 1.2 V. This architecture achieves 2.69 Mbps/mW energy
efficiency and 1.09 Mbps/kG area efficiency, respectively, which
are 2.39 to 10.60× and 1.15 to 8.81× those of state-of-the-art
designs. In future work, we plan to consider algorithms and VLSI
architectures for situations with imperfect channel information.
In addition, algorithms and architectures for higher modulation
schemes will be considered.
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Leibo Liu (Senior Member, IEEE) received the B.S.
degree in electronic engineering and the Ph.D. de-
gree from the Institute of Microelectronics, Tsinghua
University, Beijing, China, in 1999 and 2004, respec-
tively. He is currently a Professor with the Institute
of Microelectronics, Tsinghua University. His cur-
rent research interests include reconfigurable com-
puting, mobile computing, and VLSI digital signal
processing.
Guiqiang Peng received the B.S. degree from the
School of Micro-Electronics and Solid-State Elec-
tronics, University of Electronic Science and Tech-
nology of China, Chengdu, China, in 2013. He is
currently working toward the Ph.D. degree with
the Institute of Microelectronics, Tsinghua Uni-
versity, Beijing, China. His current research inter-
ests include reconfigurable computing, mobile com-
puting, and VLSI signal processing and wireless
communications.
Pan Wang received the B.S. degree in microelec-
tronics science and engineering from Central South
University, Changsha, China, in 2017. He is currently
working toward the master’s degree with the Institute
of Microelectronics, Tsinghua University, Beijing,
China. His current research interests include recon-
figurable computing, mobile computing, and VLSI
signal processing and wireless communications.
588
Sheng Zhou (Member, IEEE) received the B.E. and
Ph.D. degrees in electronic engineering from Ts-
inghua University, Beijing, China, in 2005 and 2011,
respectively. From January to June 2010, he was a
Visiting Student with the Wireless Systems Labora-
tory, Department of Electrical Engineering, Stanford
University, Stanford, CA, USA. He is currently an As-
sociate Professor with the Department of Electronic
Engineering, Tsinghua University. His research inter-
ests include cross-layer design for multiple-antenna
systems, edge computing and caching, and green
wireless communications.
Qiushi Wei received the B.S. degree from the School
of Physical Electronics, University of Electronic Sci-
ence and Technology of China, Chengdu, China, in
2015. He is currently working toward the master’s
degree with the Institute of Microelectronics, Ts-
inghua University, Beijing, China. His current re-
search interests include reconfigurable computing,
mobile computing, and VLSI signal processing and
wireless communications.
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IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 68, 2020
Shouyi Yin (Member, IEEE) received the B.S., M.S.,
and Ph.D. degrees in electronic engineering from
Tsinghua University, Beijing, China, in 2000, 2002,
and 2005, respectively. He was with Imperial College
London as a Research Associate. He is currently with
the Institute of Microelectronics, Tsinghua Univer-
sity, as an Associate Professor. His research interests
include mobile computing, wireless communications,
and SoC design.
Shaojun Wei (Fellow, IEEE) was born in Beijing,
China, in 1958. He received the Ph.D. degree from
La Faculté Polytechnique de Mons, Mons, Belgium,
in 1991.
He became a Professor with the Institute of Mi-
croelectronics, Tsinghua University, in 1995. He is
currently a Senior Member of the Chinese Institute of
Electronics. His main research interests include VLSI
SoC design, EDA methodology, and ASIC design for
communications.