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  • Lecture16a Digital Watch

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    Zain Alamgir
    17 views12 pages
    The document describes the design and implementation of a digital watch using Verilog code. It includes: 1. A block diagram showing the major components of the digital watch core including counters for hours, minutes, seconds and a clock divider. 2. Verilog code snippets for counters with enable and overflow signals. 3. The digital watch core is implemented using instances of the counter modules to keep track of hours, minutes and seconds. 4. A test bench is used to simulate and verify the functionality of the digital watch core module.

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    lecture16a_digital_watch

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    The document describes the design and implementation of a digital watch using Verilog code. It includes: 1. A block diagram showing the major components of the digital watch core including counters for hours, minutes, seconds and a clock divider. 2. Verilog code snippets for counters with enable and overflow signals. 3. The digital watch core is implemented using instances of the counter modules to keep track of hours, minutes and seconds. 4. A test bench is used to simulate and verify the functionality of the digital watch core module.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    17 views12 pages

    Lecture16a Digital Watch

    Uploaded by

    Zain Alamgir
    The document describes the design and implementation of a digital watch using Verilog code. It includes: 1. A block diagram showing the major components of the digital watch core including counters for hours, minutes, seconds and a clock divider. 2. Verilog code snippets for counters with enable and overflow signals. 3. The digital watch core is implemented using instances of the counter modules to keep track of hours, minutes and seconds. 4. A test bench is used to simulate and verify the functionality of the digital watch core module.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 12

    Digital_Watch_Core 1.

    all clk ports will be connected to clk of digital_watch_core

    23:59:59 min_digit Sec_digit


    hrs_digit

    clkdiv_cnter

    hrs1_cnter min1_cnter sec10_cnter sec1_cnter


    hrs10_cnter min10_cnter

    ovflw_10sec ovflw_1sec
    ovflw_1min
    ovflw_10min
    ovflw_10hrs ovflw_1hrs

    Digital Watch Block diagram

    soft_reset
    reset_sig
    rst_p

    assign reset_sig = rst_p | soft_reset;


    Verilog code of counter with enable and overflow

    clk cnt_val

    rst_p
    overflow
    enable

    cnter_enb_ovf
    verilog code of digital watch implemented using counter instances

    clk
    second_digits
    rst
    min_digits
    enable
    hrs_digits
    digital_watch_core
    verilog code of digital watch implemented using counter instances
    verilog code of digital watch implemented using counter instances
    verilog code of digital watch test bench
    digital_watch_core:1 Block digaram generated from ISE RTL schematic

    cnter_enb_ovf_1 cnter_enb_ovf_2
    clk clk cnt_val(1:0) clk cnt_val(3:0) hrs_digits(7:0)

    enable enable enable

    rst_p rst_p overflow rst_p overflow

    clkdiv_cnter hrs1_cnter

    cnter_enb_ovf_3
    clk cnt_val(3:0)

    enable

    rst_p overflow

    hrs10_cnter

    cnter_enb_ovf_2
    clk cnt_val(3:0) min_digits(7:0)

    enable

    rst_p overflow

    min1_cnter

    cnter_enb_ovf_3
    clk cnt_val(3:0)

    enable

    rst_p overflow

    min10_cnter

    cnter_enb_ovf_2
    clk cnt_val(3:0) sec_digits(7:0)

    enable

    rst_p overflow

    sec1_cnter

    cnter_enb_ovf_3
    clk cnt_val(3:0)

    enable

    rst_p overflow

    sec10_cnter

    digital_watch_core
    /digital_watch_core_tb/clk

    /digital_watch_core_tb/rst_p

    /digital_watch_core_tb/enable

    /digital_watch_core_tb/sec_digits

    /digital_watch_core_tb/min_digits 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

    /digital_watch_core_tb/hrs_digits 00 01

    hrs increment
    sec_digits
    min_digits reperesented in hexa decimal notation to represent both unit and ten place digits e.g. {sec10,sec1}
    hrs_digits

    0 10 us 20 us 30 us 40 us

    Entity:digital_watch_core_tb Architecture: Date: Tue Apr 27 12:51:00 Pakistan Standard Time 2021 Row: 1 Page: 1
    /digital_watch_core_tb/clk

    /digital_watch_core_tb/rst_p

    /digital_watch_core_tb/enable

    /digital_watch_core_tb/sec_digits 00 01 02 03 04 05 06 07 08 09 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 41 42 43 44 45 46 47 48 49 51 52 53 54 55 56 57 58 59 01 02 03 04 05 06 07 08 09

    /digital_watch_core_tb/min_digits 00 01

    /digital_watch_core_tb/hrs_digits 00

    minutes increment

    0 100 ns 200 ns 300 ns 400 ns 500 ns

    Entity:digital_watch_core_tb Architecture: Date: Tue Apr 27 12:53:30 Pakistan Standard Time 2021 Row: 1 Page: 1
    /digital_watch_core_tb/clk

    /digital_watch_core_tb/rst_p

    /digital_watch_core_tb/enable

    /digital_watch_core_tb/sec_digits

    /digital_watch_core_tb/min_digits

    /digital_watch_core_tb/hrs_digits 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 00

    soft reset

    0 200 us 400 us 600 us

    Entity:digital_watch_core_tb Architecture: Date: Tue Apr 27 12:49:26 Pakistan Standard Time 2021 Row: 1 Page: 1
    digital_watch_core:1

    and4b3
    I3
    and2 inv PRE
    fdp and2 cnter_enb_ovf_2
    I1 I1
    I O
    O O
    I2 clk cnt_val(3:0) hrs_digits(7:0)
    I0 I0
    O D Q
    I1 soft_reset_mux0000_imp_soft_reset_mux00001 enable
    soft_reset_and0000_imp_soft_reset_and00001 reset_sig_imp_reset_sig1
    I0 rst_p overflow
    C

    soft_reset_cmp_eq0001_imp_soft_reset_cmp_eq00011
    hrs1_cnter
    soft_reset
    rst_p

    clk

    and4b3
    I3
    cnter_enb_ovf_1 cnter_enb_ovf_3
    I2 clk cnt_val(1:0) clk cnt_val(3:0)
    O
    I1 enable enable

    I0 rst_p overflow rst_p overflow

    soft_reset_cmp_eq0000_imp_soft_reset_cmp_eq00001
    clkdiv_cnter hrs10_cnter
    enable

    cnter_enb_ovf_2
    Technology schematic Digital Watch clk cnt_val(3:0) min_digits(7:0)

    from synthesis using ISE enable

    rst_p overflow

    min1_cnter

    cnter_enb_ovf_3
    clk cnt_val(3:0)

    enable

    rst_p overflow

    min10_cnter

    cnter_enb_ovf_2
    clk cnt_val(3:0) sec_digits(7:0)

    enable

    rst_p overflow

    sec1_cnter

    cnter_enb_ovf_3
    clk cnt_val(3:0)

    enable

    rst_p overflow

    sec10_cnter

    digital_watch_core

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