NuMicro

Timer & WDT & WWDT & RTC & UART

NuMicro@nuvoton.com

1
 Agenda
• Four sets of 24-bit Timer with 8-bit prescale
• A 18-bit Watch dog timer
• A Window watch dog timer
• Real time clock with calendar
• Five fully programmable UART channels.
• Two sets fully function UART controller
• Support Auto Flow Control Function
• Support IrDA SIR Function
• Support LIN break Function
• Three sets Smart-Card host support UART mode

2
 Timer Feature
• Four sets of 24-bit up-counting timer
• Five selections of clock source and a prescale for
every timer
• Timeout period = (Period of timer clock input) * (8-bit
Prescale + 1) * (24-bit TCMP)
• Support wake-up CPU from power-down mode
• Support GPIO port value shadow register
• Four operation modes of counting
• One-shot, Periodic, Toggle and Continuous Counting mode

3
 Timer Clock Source

CLKSEL1. TMRx_S

APBCLK. TMRx_EN
HIRC
111
EXT_ TMx( GPB)
011 TMRx_ CLK
LIRC
010
LXT
001
HXT
000

4
 Timer Block Diagram (1/2)
TMRx_CLK TMRx_DR[23:0] TMRx_CMPR[23:0] TMRx_CTL.MODE_SEL=0x2

TMRx Clock TMRx_CTL.TMR_EN

D
SET
Q

Counter Logic
+ “0”
TMRx_TOGGLE
& Event Input
0
EXT_TMRx 0 =
CLR Q
Counting - 1
Toggle
Enable
1
8-bit 24-bit D
SET
Q

TMRx_CTL.EVENT_EDGE Prescale Up-Counter Reset

Counter CLR Q TMRx_INT
TMRx_CTL. TMRx_ISR.
TCAP_EDGE = 2'b00 TRM_IS

TMRx_CTL.
~TMRx_CTL.TCAP_MODE TMRx_IER.TMR_IE
Capture
TCAP_EDGE = 2'b01
TCapture_x
TMRx_CTL.
Input
TMRx_TCAP[23:0]
TCAP_MODE TMRx_IER.TCAP_IE
TMRx_CTL.
TCAP_EDGE =
Q
SET
D
2'b10
TMRx_CTL.
TCAP_EDGE = 2'b11 CLR Q Interrupt
INTR_TMR_TRG TMRx_ISR.
TCAP_IS

TMRx+1_CLK TMRx+1_DR[23:0] TMRx+1_CMPR[23:0] TMRx+1_CTL.MODE_SEL=0x2

TMRx+1_CTL.TMR_EN
Q
SET
D
+ “0” 0 TMRx+1_TOGGLE
EXT_TMRx+1 0 =
CLR Q
Counting - 1
Toggle
Enable
1
8-bit 24-bit D
SET
Q

TMRx+1_CTL.EVENT_EDGE Prescale Up-Counter Reset

Counter CLR Q TMRx+1_INT
TMRx+1_CTL. TMRx+1_ISR.
TCAP_EDGE = 2'b00 TRM_IS

TMRx+1_CTL. TMRx+1_IER.TMR_IE
TCAP_EDGE = 2'b01 ~TMRx+1_CTL.TCAP_MODE
1

TCapture_x+1 TMRx+1_CTL. TMRx+1_TCAP[23:0]

TCAP_MODE TMRx+1_IER.TCAP_IE
0
TMRx+1_CTL.TCAP
_EDGE = 2'b10
Q
SET
D
TMRx+1_CTL. TMRx+1_CTL.
INTR_TRG_EN TCAP_EDGE = 2'b11 CLR Q
TMRx+1_ISR. Where X=0, 2
TCAP_IS

5
 Timer Block Diagram (2/2)
TMRx_CLK TMRx_DR[23:0] TMRx_CMPR[23:0] TMRx_CTL.MODE_SEL=0x2

TMRx_CTL.TMR_EN

Timer0
Q
SET
D
+ “0” 0 TMRx_TOGGLE
EXT_TMRx
Event Input
0 =
CLR Q
Counting - 1
Toggle
Enable
1
8-bit 24-bit D
SET
Q

TMRx_CTL.EVENT_EDGE Prescale Up-Counter Reset

Counter CLR Q TMRx_INT
TMRx_CTL. TMRx_ISR.
TCAP_EDGE = 2'b00 TRM_IS

TMRx_CTL.
~TMRx_CTL.TCAP_MODE TMRx_IER.TMR_IE
TCAP_EDGE = 2'b01
TCapture_x
TMRx_CTL. TMRx_TCAP[23:0]
TCAP_MODE TMRx_IER.TCAP_IE
TMRx_CTL.
TCAP_EDGE =
Q
SET
D
2'b10
TMRx_CTL.
TCAP_EDGE = 2'b11
Inter-Timer Trigger Mode
CLR Q

INTR_TMR_TRG TMRx_ISR.
TCAP_IS

TMRx+1_CLK TMRx+1_DR[23:0] TMRx+1_CMPR[23:0] TMRx+1_CTL.MODE_SEL=0x2

TMRx+1_CTL.TMR_EN
Q
SET
D
+ “0” 0 TMRx+1_TOGGLE
EXT_TMRx+1 0 =
CLR Q
Counting - 1
Toggle
Enable
1
8-bit 24-bit D
SET
Q

TMRx+1_CTL.EVENT_EDGE Prescale Up-Counter Reset

Counter CLR Q TMRx+1_INT
TMRx+1_CTL. TMRx+1_ISR.
TCAP_EDGE = 2'b00 TRM_IS

TMRx+1_CTL. TMRx+1_IER.TMR_IE
TCAP_EDGE = 2'b01 ~TMRx+1_CTL.TCAP_MODE
1

TCapture_x+1 TMRx+1_CTL. TMRx+1_TCAP[23:0]

TCAP_MODE TMRx+1_IER.TCAP_IE
0

Timer1 TMRx+1_CTL.TCAP
_EDGE = 2'b10
D
SET
Q

Capture TMRx+1_CTL.
INTR_TRG_EN
TMRx+1_CTL.
TCAP_EDGE = 2'b11 CLR Q
TMRx+1_ISR. Where X=0, 2
TCAP_IS

6
 Timer Function Mode Lists
• Timer Counting Mode (1)
• Event Counting Mode (2)
• Timer Counter Capture Function:
• Free Counting Mode (3)
• Trigger Counting Mode (4)
• Timer Counter Reset Function (5)
• Inter-Timer Trigger Mode (6)
• Counting from TMR0/TMR2 external event pin
• Trigger TMR1/TMR3 latch counter value to TMRx_CAP

7
 Timer Function Mode: TMRx_CTL Setting
Counter Input
TMRx_CTL register
TMRx clock Input Event Pin Input *1
INTR_TRG_EN

TCAP_CNT_MOD

TCAP_MODE

TCAP_EN

TMR_EN

MODE_SEL
EVENT_EN = 0 EVENT_EN = 1

[24] [20] [17] [16] [0] [5:4] [12] [12]

0 x x 0 1 0,1,2,3 Timer Counting Mode Event Counting Mode

0 0 0 1 1 0,1,2,3 Timer Counter Capture Function: “Free Counting Mode”

0 1 0 1 1 x Timer Counter Capture Function: “Trigger Counting Mode” *2

0 x 1 1 1 0,1,2,3 Timer Counter Reset Function

x (TMR0, TMR2)
1 x x 0 x x
Inter-Timer Trigger Mode *2
0 x x 1 x x
(TMR1, TMR3) x

*1 If use “event pin input”, timer cannot set to toggle mode (MODE_SEL=2)
*2 If use “Trigger Counting Mode” or “Inter-Timer Trigger Mode”, the MODE_SEL are don’t
care 8
 Four Operation Modes of Counting
Ex: TCMPR=100
Interrupt

One shot 0 100

Reset counter

Periodic 0 100
Toggle Output :
Reset counter
TM0→PB8 , TM1→PB9
Toggle 0 100 TM2→PB10 , TM3→PB11
Overflow

Auto-reload counting 0 100 101 224-1

9
 Timer Counter Capture Function:
Free Counting Mode
TMRx Counter 5 6 7 8 9 10 11 12 13 14 15
TH

TCx pin 2
(TCAP_EDGE=0x03)
Clear by software

TCAP_IS

1 1 Clear with TCAP_IS

NCAP_DET_IS

3
TMRx_TCAP XX 6 10 13

1. Any rising/filling edge event always latch the TMRx counter value to TMRx_TCAP
register and set TCAP_IS status
2. High level time, TH = (10 – 6) / TMRx_CLK
3. When edge event occur in TCAP_IS period, the timer will drop the new capture value
and set NCAP_DET_IS flag

10
 Timer Counter Capture Function:
Trigger Counting Mode
TMRx Counter 5 6 0 1 2 3 4 0 1 2 3
TH

TCx pin 3
(TCAP_EDGE=0x03)

1 Clear by software

TCAP_IS

2
NCAP_DET_IS

TMRx_TCAP XX 2 2

1. An rising edge event, reset the TMRx counter value to zero and trigger counter counting
2. An filling edge event, latch the TMRx counter value to TMRx_TCAP register and set
TCAP_IS status
3. High level time, TH = 2 / TMRx_CLK

11
 Timer Counter Reset Function

TMRx Counter 5 6 0 1 2 3 0 1 2 3 0

TCx pin
(TCAP_EDGE=0x03)
Clear by software

TCAP_IS

1 1
1. Any rising/filling edge event always reset the TMRx counter value to zero and set
TCAP_IS status

12
 1
Inter-Timer Trigger Mode (1/2)
TM0 pin
(TMR0_CLK=10k)

TMR0_CTL.
INTR_TRG_EN

TMR0_CTL.
EVENT_EN

TMR0 Counter 0 1 2 3 99 100 0

TMR0_CMPR 100

INTR_TMR_TRG

TMR1 Counter
0 1 2 998 999
(TMR0_CLK=100k)

TMR1_TCAP 999

TMR1_ISR.TMR_IS
2

1. Enable TMR0_CTL.INTR_TRG_EN will start TM0 pin event counting and generate a
“INTR_TMR_TRG” signal to trigger TMR1
2. When TMR0 counter equal to TMR0_CMPR, the “INTR_TMR_TRG” signal will stop and
latch TMR1 counter value to TMR1_TCAP register and set TMR1_ISR.TCAP_IS status
13
 Inter-Timer Trigger Mode (2/2)
TM0 pin
(TMR0_CLK=10k)

TMR0_CTL. TTM0 3
INTR_TRG_EN
4
TMR0_CTL.
EVENT_EN

TMR0 Counter 0 1 2 3 99 100 0

TMR0_CMPR 100

INTR_TMR_TRG

TMR1 Counter
0 1 2 998 999
(TMR0_CLK=100k)

TMR1_TCAP 999

TMR1_ISR.TMR_IS

3. At the same time TMR0 INTR_TRG_EN bit will set to 0, TMR0 and TMR1 stop counting
4. TTM0 = TMR1_TCAP / TMR1_CLK / TMR0_CMPR = 999 / 100kHz / 100 = 100 us
FTM0 = TMR1_CLK / TMR1_TCAP × TMR0_CMPR = 100kHz / 999 × 100 = 10 kHz
14
 Internal Trigger Event (1/3)
• Functional description
• When timer timeout or capture interrupt, generate an
internal trigger event to start peripherals working
• Support ADC, DAC, PDMA and Touch-key
• Event source from timer interrupt status
• Timer timeout interrupt status, TMR_IS
• Timer capture interrupt status, TCAP_IS
• Wake-up Touch-key from power-down mode
• Without wake-up CPU
• This mode support the wake-up event from TMR0 TMR_IS
flag
15
 Internal Trigger Event (2/3)

LXT

FLASH P LIRC
Cortex-M0
EBI 123/64/ PDMA CLK_CTL L
42 MHz L HXT
32 KB HIRC

1.8V LDO
(input: 1.8 ~ 3.6V)

1. When timer timeout or capture POR (1.8V)

interrupt, generate an internal

BOD (1.7/2.0/2.5 V)
ISP 4KB SRAM GPIO
trigger event to start working the 16/8 KB A,B,C,D,E,F

peripherals I2C 1 I2C 0

12-b ADC

12-b DAC
PWM 1 PWM 0
1.8/2.5V REF
Timer 2/3 Timer 0/1

2. When CPU on power-down mode, UART 1 UART 0 Touch key

TEMP Sensor
TMR0 support generate timeout SPI 1 SPI 0 LCD Booster
wake-up trigger to Touch-key LCD COM/SEG
controller I2S SPI 2 LCD
Up to
(TMR0 clock source from 32kHz SC 0/UART3 RTC USB -512B
4x40/6x38

or 10kHz) SC 1/UART4 WDT

USB PHY

SC 2/UART5 Peripherals with PDMA

NOTE: BOD can wake up system.
External interrupts, included in GPIO, can wake up system, too. Peripherals with wake up

16
 Internal Trigger Event (3/3)

Internal Trigger Event

(Target Peripherals) PDMA_TEEN = 1 DAC_TEEN = 1 ADC_TEEN = 1 TK_TEEN = 1
(PDMA) (DAC) (ADC) (Touch Key)
Trigger State

CAP_TRG_EN = 0 Trigger with TMR_IS

Trigger with
TMR_IS or
TCAP_IS *1
CAP_TRG_EN = 1 Trigger with TCAP_IS

*1 TCAP_IS event not support wake-up Touch-key from power-down mode, only TMR_IS
event support it.

17
 Timer Example
• Timer sample code
• Enable TM0 function pin
• Enable Timer0 toggle mode
• Setting timeout period is 1 second
• Timer0 interrupt handler example

18
 Timer Sample Code (1/2)
//----------------------------------------------------------------------------
// MAIN function
//----------------------------------------------------------------------------
volatile uint32_t TMR0_Counter = 0;
int32_t main (void)
{
UNLOCKREG();
CLK->PWRCTL |= CLK_PWRCTL_HXT_EN;
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_HXT_STB));
LOCKREG();
Setting TMR0 clock source
//Setting TMR0 Clock Source and Enable TMR0 Clock
CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_TMR0_MASK) | CLK_CLKSEL1_TMR0_HXT;
CLK->APBCLK |= CLK_APBCLK_TMR0_EN;

//Enable TM0 pin (@PB.8) Enable TM0 pin

GCR->PB_H_MFP = (GCR->PB_H_MFP & ~ PB8_MFP_MASK) | PB8_MFP_TMR0_EXT;

//Setting TMR0 to Toggle Mode

TIMER_Init(TIMER0, 11, 1000000, TIMER_CTL_MODESEL_TOGGLE);
TIMER_EnableInt(TIMER0, TIMER_IER_TMRIE);
TIMER_Start(TIMER0);

Timeout period = 12 MHz * (11 + 1) * 1000000 = 1.0 second

while(1);
}
Setting TMR0 to Toggle Mode, interrupt and start TMR0

19
 Timer Sample Code (2/2)
//----------------------------------------------------------------------------
// TMR0 IRQ handler
//----------------------------------------------------------------------------
void TMR0_IRQHandler(void)
{
//TMR0 Timeout Interrupt Status is Set
When TMR0 timeout interrupt
if(TIMER0->ISR&TIMER_ISR_TMRIS)
{
TIMER0->ISR |= TIMER_ISR_TMRIS; //Clear TMR0 Timeout Interrupt Status
TMR0_Counter++;
printf("TMR0 Timeout: %d\n", TMR0_Counter);
}

//TMR0 Capture Interrupt Status is Set

if(TIMER0->ISR&TIMER_ISR_TCAPIS)
{
printf("TMR0 Capture: %d\n", TIMER0->TCAP); //Clear TMR0 Capture Interrupt Status
TIMER0->ISR |= TIMER_ISR_TCAPIS;
}
}

When TMR0 capture interrupt

20
 Watch Dog Timer Feature
• 18-bit up counter
• 8 selections of timeout interval
• 4 selections of WDT reset delay period
• Support function:
• WDT interrupt
• WDT reset
• WDT wakeup

21
 WDT Clock Source

WDT_EN (APBCLK [0])

WDT CLK
10K Hz

22
 WDT Block Diagram
WDT can cause a WDT Interrupt or WDT Reset to CPU after a fixed delay period.
WDT also can wakeup CPU form Power-down mode

WTR(WDT_CTL[0])
Reset WDT WDT_IS Watchdog
Counter (WDT_ISR[0])
18-bit WDT Count Interrupt
WDT_IE
1 .. 4 …... 16 17 18
(WDT_IER[0])
000
001 Delay
: Time-
WTRDSEL
: out Watchdog reset [Note1]
110 WDT
Select WTRE
111 Clocks
WDT_CLK (WDT_CTL[1])
WDT_RST_IS
WTE (WDT_ISR[1])
(WDT_CTL[3]) WTIS
Note : (WDT_CTL [6:4]) Wake-up CPU from
1. Watchdog timer resets CPU and lasts 64 WDT_CLK. power-down mode
2. If user intends to use WDT to wake-up power-down mode, it is recommended WTWKE
that CPU clock source is set as the same as WDT clock source before CPU (WDT_CTL[2])
enters in power-down mode. WDT_WAKE_IS
3. The WTRDSEL can be 1026 / 130 / 18 / 3 WDT clocks (WDT_ISR[2])

23
 WDT Timeout Interval Select

WDT Timeout WDT Timeout Interval WDT Reset Interval

WTIS *1 WDT Reset Interval *2
Interval (WDT_CLK = 10kHz) (WDT_CLK = 10kHz)

0 24 × TWDT_CLK (24 + Delay Clock) × TWDT_CLK 1.6 ms 1.9 ms ~ 104.2 ms

1 26 × TWDT_CLK (26 + Delay Clock) × TWDT_CLK 6.4 ms 6.7 ms ~ 109.0 ms
2 28 × TWDT_CLK (28 + Delay Clock) × TWDT_CLK 25.6 ms 25.9 ms ~ 128.2 ms
3 210 × TWDT_CLK (210 + Delay Clock) × TWDT_CLK 102.4 ms 102.7 ms ~ 205.0 ms
4 212 × TWDT_CLK (212 + Delay Clock) × TWDT_CLK 409.6 ms 409.9 ms ~ 512.2 ms
5 214 × TWDT_CLK (214 + Delay Clock) × TWDT_CLK 1.6384 s 1.6387 s ~ 1.7410 s
6 216 × TWDT_CLK (216 + Delay Clock) × TWDT_CLK 6.5536 s 6.5539 s ~ 6.6562 s
7 218 × TWDT_CLK (218 + Delay Clock) × TWDT_CLK 26.2144 s 26.2147 s ~ 26.3170 s

*1 WTIS(WDT_CTL[6:4]) is timeout interval for the watchdog timer.

*2 “Delay Clock” selection has 3, 18, 130 and 1026, select by WTRDSEL(WDT_CTL[9:8])

24
 WDT Example
• WDT sample code
• Setting WDT timeout interval is “216 × TWDT_CLK”
• Setting WDT reset event delay is “1026 WDT_CLK cycle”
• WDT interrupt handler example
• Check WDT wake-up event example
• Check WDT reset event example

25
 WDT Sample Code (1/2)
//----------------------------------------------------------------------------
// MAIN function
//----------------------------------------------------------------------------
int main (void) Enable internal 10kHz RC
{
UNLOCKREG();
CLK->PWRCTL |= CLK_PWRCTL_HXT_EN | CLK_PWRCTL_LIRC_EN;
while(!(CLK->CLKSTATUS & (CLK_CLKSTATUS_HXT_STB | CLK_CLKSTATUS_LIRC_STB )));
LOCKREG();

//Checking WDT Reset Flag of System Reset Source Register

if(GCR->RST_SRC & GCR_RSTSRC_WDT)
{
GCR->RST_SRC |= GCR_RSTSRC_WDT; //Clear WDT Reset Status
printf(“System Reset from WDT Timeout !\n”);
} Check WDT reset status
on system power-on
//Enable Watchdog Timer
WDT_Init(WDT_CTL_WTIS_2POW14, WDT_CTL_WTRDSEL_1026CLK);
WDT_EnableInterrupt(); WDT Timeout Interval = 214 WDT clocks
WDT_START;
WDT reset delay: 1026 WDT clocks
Enable WDT interrupt
while(1); and start WDT
}

26
 WDT Sample Code (2/2)
//----------------------------------------------------------------------------
// WDT IRQ handler
//----------------------------------------------------------------------------
void WDT_IRQHandler(void)
{ When WDT interrupt
//WDT Interrupt Status is Set
if(WDT->ISR & WDT_ISR_WDTIS)
{
WDT->ISR |= WDT_ISR_WDTIS; //Clear WDT Interrupt Status
WDT_RESET_TIMER; //Reset WDT Timer Counter
printf("WDT interrupt !!!\n”);
}

//WDT Wake-up Status is Set

if(WDT->ISR & WDT_ISR_WDTWAKEIS)
{
WDT->ISR |= WDT_ISR_WDTWAKEIS; //Clear WDT Wake-up Status
printf("WDT Wake-up!\n”);
}
} When WDT after Wake-up

27
 Window Watchdog Timer Feature
• 6-bit down counter and comparator
• To make the WWDT reload window period flexible
• 16 selections WWDT pre-scale counter
• To make WWDT timeout interval variable
• Only one times to setting WWDT controller after chip
power-on or reset
• Software cannot to disable WWDT, or change any setting
• WWDT and WDT share a single IRQ handler
• Support function:
• WWDT interrupt
• WWDT reset
28
Window Watchdog Timer Clock Source

WDT_EN(APBCLK[0])

WWDT_CLK
HCLK/2048

29
 Window Watchdog Timer Block Diagram

WWDT can cause a WWDT Interrupt or WWDT Reset to CPU

16 selections WWDT pre-scale

PERIODSEL Reload
(WWDTCR[11:8]) 0x3F WWDT counter
Write
WWDTCNT = 0 WWDT
WWDTRLD = Reset
Write WWDTRLD
0x00005AA5

WWDT_CLK 11-bit
6-bit down counter WWDTRF
Prescale WWDTCNT > WINCMP
(WWDTSTS[1])
comparator
6-bit compare value WWDTCNT = WINCMP
(WINCMP) WWDT
WWDTIF Interrupt
Reload window setting (WWDTSTS[0])
6-bit down
synchronizer counter value INTEN
(WWDTVAL) (WWDT_IER[0])

30
 WWDT Counter Reload Timing
WWDTEN=1 Set WWDTRLD=0x5AA5,
(WWDTCR[1]) When WWDT Counter > WINCMP

0x3f WWDTCNT(WWDTVAL[5:0])

1
4
0x20 WINCMP(WWDTCR[21:16])
Reload 3
Window
0 Time

2 WWDTIF(WWDTSTS[1])
Set WWDTRLD=0x5AA5,
When
0 < WWDT Counter <= WINCMP

WWDTRF(WWDTSTS[2])
4
1. Start counting WWDTCNT counter
2. When WWDTCNT equal to WINCMP, the WWDTTIF status is set
3. When reload WWDTCNT inside the window, then WWDT continuous counting;
( 0 < WWDTCNT <= WINCMP )
4. When reload WWDTCNT outside the windows, then chip will reset and set WWDTRF
flag; ( WWDTCNT > WINCMP )
31
 WWDT Counter Reload Timing
WWDTEN=1
(WWDTCR[1])

0x3f WWDTCNT(WWDTVAL[5:0])

0x20 WINCMP(WWDTCR[21:16])
Reload When WWDT Counter = 0

Window
0 Time

1 WWDTIF(WWDTSTS[1])

Set WWDTRLD=0x5AA5,
When WWDT Counter <= WINCMP

WWDTRF(WWDTSTS[2])

1. If WWDTCNT count down to 0, the chip will reset and set WWDTRF flag;
( WWDTCNT == 0 )

32
 WWDT Reload Window Calculate
WWDT Reload Window WWDT Reload Window
PERIODSEL *1 Prescaler Value (WINCMP = 32,
WWDT Compare Period *2 WWDT Timeout Period *3 WWDT_CLK = 12MHz/2048)
0 1 1 × WINCMP × TWWDT 1 × 64 × TWWDT 5.5 ms ~ 10.9 ms
1 2 2 × WINCMP × TWWDT 2 × 64 × TWWDT 10.9 ms ~ 21.8 ms
2 4 4 × WINCMP × TWWDT 4 × 64 × TWWDT 21.8 ms ~ 43.7 ms
3 8 8 × WINCMP × TWWDT 8 × 64 × TWWDT 43.7 ms ~ 87.4 ms
4 16 16 × WINCMP × TWWDT 16 × 64 × TWWDT 87.4 ms ~ 174.8 ms
5 32 32 × WINCMP × TWWDT 32 × 64 × TWWDT 174.8 ms ~ 349.5 ms
6 64 64 × WINCMP × TWWDT 64 × 64 × TWWDT 349.5 ms ~ 699.1 ms
7 128 128 × WINCMP × TWWDT 128 × 64 × TWWDT 699.1 ms ~ 1.3981 s
8 192 192 × WINCMP × TWWDT 192 × 64 × TWWDT 1.0486 s ~ 2.0972 s
9 256 256 × WINCMP × TWWDT 256 × 64 × TWWDT 1.3981 s ~ 2.7962 s
10 384 384 × WINCMP × TWWDT 384 × 64 × TWWDT 2.0972 s ~ 4.1943 s
11 512 512 × WINCMP × TWWDT 512 × 64 × TWWDT 2.7962 s ~ 5.5924 s
12 768 768 × WINCMP × TWWDT 768 × 64 × TWWDT 4.1943 s ~ 8.3886 s
13 1024 1024 × WINCMP × TWWDT 1024 × 64 × TWWDT 5.5924 s ~ 11.1848 s
14 1536 1536 × WINCMP × TWWDT 1536 × 64 × TWWDT 8.3886 s ~ 16.7772 s
15 2048 2048 × WINCMP × TWWDT 2048 × 64 × TWWDT 11.1848 s ~ 22.3696 s
*1 PERIODSEL(WWDTCR[11:8]) is pre-scale period select for the WWDT
*2 Start time of WWDT reload window, WINCMP(WWDTCR[11:8) is WWDT compare value
*3 End time of WWDT reload window 33
 WWDT Example
• WWDT sample code
• Setting WWDT prescaler value is 512 to control WWDT
count-down speed
• Setting WWDT reload window value is 0x20
• Check WWDT interrupt in WDT IRQ handler example
• Reload WWDT prescaler & counter value example

34
 WWDT Sample Code(2/2)
uint32_t volatile wwdt_cnt = 0;
//----------------------------------------------------------------------------
// MAIN function
//----------------------------------------------------------------------------
int main (void)
{
UNLOCKREG();
CLK->PWRCTL |= CLK_PWRCTL_HXT_EN;
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_HXT_STB));
LOCKREG();

//Enable Window Watchdog Timer

Enable WWDT
WWDT_Init(WWDT_CR_PERIODSEL_512, 0x20);
WWDT_EnableInterrupt();
and interrupt

while(1)
{
//After WWDT interrupt 4 times to setup reload WWDT counter chip will reset
if(wwdt_cnt >= 4)
WWDT->RLD = WWDT_RELOAD_KEY;
}
}

35
 WWDT Sample Code(2/2)
//----------------------------------------------------------------------------
// WDT and WWDT share a single IRQ handler
//----------------------------------------------------------------------------
void WDT_IRQHandler(void)
{ Chack the WWDT interrupt
//WWDT Interrupt Status Flag is Set
if((WWDT->STS&WWDT_STS_IF))
{
Reload WWDT counter
WWDT_RELOAD; //Reload WWDT Prescaler & Counter Value
WWDT->STS = WWDT_STS_IF; //Clear WWDT Interrupt Status

wwdt_cnt++;
printf("INT: %d\n", wwdt_cnt); //Print WWDT Interrupt Times
printf("WWDTVAL: %d\n", WWDT->VAL); //Print WWDT Counter Value
}
}

36
 RTC Feature
• One set RTC counter and alarm register
Register BCD Value (24-hour) Written Description
RTC_TLR 0x00093043 AM 09:30:43 Time Counter
RTC_CLR 0x00120229 2012/02/29 Calendar Counter
RTC_DWR 0x00000003 Wednesday Day of the Week Counter
RTC_LIR 0x00000001 Leap year Leap Year Indication
RTC_TAR 0x00100000 AM 10:00:00 Time Alarm Value
RTC_CAR 0x00120301 2012/03/01 Calendar Alarm Value
• Support alarm and time tick interrupt
• Support wake-up function
• 32 kHz frequency compensation
• 80 bytes RTC spare register to store information
• And a snoop pin function to cleared RTC spare register

37
 RTC Block Diagram
INIR
(0xA5EB1357) Time Alarm Calendar Alarm
AIER(RIER[0])
Register (TAR) Register (CAR)
AIF(RIIR[0]) Alarm
AER Compare
Operation
Interrupt

(0xA965) Time Load Calendar Load Wake-up CPU from

512 RTC clock Register (TLR) Register (CLR) Power-down mode

≒15msec
Leap Year (Second) TWKE(TTR[3])
1/128 change 111
Indicator (LIP)
1/64 change 110
TSSR.24H_12H
1/32 change 101
Day of Week RTC Time Counter 1/16 change 100
(DWR) Control Unit TIF(RIIR[1]) Periodic
1/8 change 011
Interrupt
Initation/Enable 1/4 change 010
Frequency TIER(RIER[1])
(INIR/AER) 1/2 change 001
Compensation
Clock Source 1 change 000
32776~32761
TTR(TTR[2:0)
Frequency
Compensation
Register (FCR)

38
 RTC Register Access Enable Password

• Write AER[15:0]=0xA965 to access RTC register

AER[16] = 1 AER[16] = 0
Register Description
(Access Enabled) (Access Disabled)
RTC_INIR RTC Initiation Register (0xA5EB1357) R/W R/W
RTC_AER RTC Access Enable Register (0xA965) R/W R/W
RTC_FCR RTC Frequency Compensation Register R/W -
RTC_TLR Time Loading Register R/W R
RTC_CLR Calendar Loading Register R/W R
RTC_TSSR Time Scale Selection Register R/W R/W
RTC_DWR Day of the Week Register R/W R
RTC_TAR Time Alarm Register R/W -
RTC_CAR Calendar Alarm Register R/W -
RTC_LIR Leap Year Indicator Register R R
RTC_RIER RTC Interrupt Enable Register R/W R/W
RTC_RIIR RTC Interrupt Indication Register R/W R/W
RTC_TTR RTC Time Tick Register R/W -
RTC_SPRCTL RTC Spare Functional Control Register R/W -
RTC_SPR0 ~
RTC Spare Register 0 ~ 19 R/W -
RTC_SPR19
39
 RTC Frequency Compensation Register
• Make digital compensation for 32kHz crystal input
• Crystal input range: 32776 Hz to 32761 Hz
• Frequency compensation resolution: ±0.4768 ppm
• RTC_FCR register, setting Input_Clock value
• RTC_FCR.INTEGER = [Input_Clock(integer part) – 32768] +7
• RTC_RCR.FRACTION = Input_Clock(fraction part) × 64
• Example
• External crystal measurement: 32773.66 Hz
• RTC_FCR.INTEGER = (32773 – 32768) + 7 = 12 => 0x0C
• RTC_RCR.FRACTION = 0.66 × 64 = 39.6 => 0x27

40
 RTC Example
• RTC sample code
• Enable RTC and set date and time
• Date: 2012 / 7 / 1
• Time: 13:20:00
• Enable alarm interrupt and set alarm date and time
• Alarm date: 2012 / 7 / 1
• Alarm time: 13:20:10
• Enable time tick interrupt
• Display RTC current time in time tick interrupt event

41
 RTC Sample Code (1/2)
//----------------------------------------------------------------------------
// MAIN function
//----------------------------------------------------------------------------
int32_t main (void)
{
S_DRVRTC_TIME_DATA_T sInitTime, sCurTime;

RTC_Init(); // RTC Initialize

// Time Setting
sInitTime.u32Year = 2012;
sInitTime.u32cMonth = 7;
sInitTime.u32cDay = 1;
sInitTime.u32cHour = 13;
sInitTime.u32cMinute
sInitTime.u32cSecond
= 20;
= 0; Initial RTC
sInitTime.u32cDayOfWeek = DRVRTC_TUESDAY;
sInitTime.u8cClockDisplay = DRVRTC_CLOCK_24;
while(RTC_Open(&sInitTime) != E_SUCCESS); // Initial RTC current time

// The alarm time setting

sCurTime.u32cSecond = sCurTime.u32cSecond + 10;
RTC_WriteAlarm(&sCurTime); // Set the alarm time
RTC_EnableInt(RTC_RIER_AIER); // Enable RTC Alarm Interrupt
RTC_EnableInt(RTC_RIER_TIER); // Enable RTC Tick Interrupt

while(1);
} Enable RTC alarm and time tick interrupt

42
 RTC Sample Code (2/2)
//----------------------------------------------------------------------------
// RTC IRQ handler
//----------------------------------------------------------------------------
void RTC_IRQHandler(void)
{
S_DRVRTC_TIME_DATA_T sInitTime, sCurTime;
When RTC alarm interrupt
if (RTC->RIIR & RTC_RIIR_AIS) // Alarm interrupt
{
RTC->RIIR |= RTC_RIIR_AIS;
printf("Alarm!!\n");
}

if (RTC->RIIR & RTC_RIIR_TIS) // Tick interrupt

{
RTC->RIIR |= RTC_RIIR_TIS;
RTC_Read(&sCurTime); // Read current time

// Display current time

printf("Current Time: %d/%02d/%02d %02d:%02d:%02d\n",
sCurTime.u32Year, sCurTime.u32cMonth, sCurTime.u32cDay,
sCurTime.u32cHour, sCurTime.u32cMinute, sCurTime.u32cSecond);
} When RTC time tick interrupt,
}
print RTC current time

43
 UART Feature
• Two fully programmable UART channels
• Supports baud rate generator and auto-baud rate detect
• Support auto flow control function (/CTS, /RTS)
• 16-bytes entry FIFO for TX/RX data payloads
• Incoming data and /CTS pin for wake-up function
• All channels can be served by the PDMA controller
• UART function mode select
• UART, IrDA, LIN and RS-485 interface

44
 UART Clock Source

CLKSEL1.UART_S[1:0]

APBCLK.UART0_EN[16]

HIRC
11 UART0_CLK
PLL
10
÷ (UART_N+1)
LXT
01 CLKDIV0.UART_N[11:8]
HXT UART1_CLK
00
APBCLK.UART1_EN[17]

HIRC support hardware auto trim function (need 32 kHz external crystal)
and three target frequency (11.0592 MHz / 12 MHz / 12.288 MHz)

45
 UART Block Diagram
APB_BUS

Status & Control Status & Control

TX_FIFO Control and Status RX_FIFO

Registers

TX Shift Register Baud Rate RX Shift Register

Baud Out Baud Out
Generator

Serial Data Out Serial Data In

UART_CLK
IrDA Encode IrDA Decode

UART / IrDA / LIN / RS-485 Device or Transceiver

Note: 16-bytes TX_FIFO and 16-bytes RX_FIFO

46
 UART Baud Rate Setting(1/2)
• Fully programmable serial interface
Even, odd or no-parity

START DATA (5-8) PARITY STOP(1-2) START

5 ~ 8bits 1 ~ 2bits

• Baud rate generator (UARTx_BAUD register)

Mode DIV_16_EN *1 Baud rate equation
Mode 0 0 (Disable) UART_CLK / (BRD + 1), BRD must > 8 *2
Mode 1 1 (Enable) UART_CLK / [(BRD + 1) × 16]
*1 DIV_16_EN is baud rate divider base number at register UARTx_BAUD[31] bit
*2 BRD is baud rate divider number at register UARTx_BAUD[15:0] bits

47
 UART Baud Rate Setting(2/2)
UART clock source = 12 MHz
Mode 0 Mode 1
Baud rate
(DIV_16_EN=0) *1 (DIV_16_EN=1)
921600 BRD=12 *2 Not Supported
460800 BRD=25 Not Supported
230400 BRD=51 BRD=2
115200 BRD=103 BRD=6
57600 BRD=207 BRD=12
38400 BRD=311 BRD=19
19200 BRD=624 BRD=38
9600 BRD=1249 BRD=77
4800 BRD=2499 BRD=155
*1 DIV_16_EN is baud rate divider base number at register UARTx_BAUD[31] bit
*2 BRD is baud rate divider number at register UARTx_BAUD[15:0] bits
48
 UART Auto-Baud Rate Detect
• If enable auto-baud rate detection
• Controller will measure the start bit time of the received
data stream (LSB must be “1”)
• And auto set the divisor latch registers UARTx_BARD
Bit Period*2 LSB must be “1”

UARTx_CLK*1

RX Start Bit LSB*3

INT_ABOUD

UARTx_BAUD[15:0] XX BRD=1249
*1 UARTx_CLK = 12 MHz
*2 Bit Period = 1 / (9600 bps)
*3 LSB must be high

49
 UART Auto Flow Control Function
• Support auto flow control function (/CTS, /RTS)
• Wake up from /CTS pin

TX
Parallel to Serial RX

Tx FIFO
/CTS
Flow Control /RTS

Chip 2
BUS
RX
Serial to Parallel TX

Rx FIFO
/RTS
Flow Control /CTS

/RTS can trigger /CTS to control when can transfer data.

50
 UART Wake-up Function (1/2)
• UART CTS pin wake-up, case 1
sleep mode
CLK
CTSn

WAKE_SYSTEM
1
INT_WAKE
2

• UART CTS pin wake-up, case 2

sleep mode
CLK
CTSn

WAKE_SYSTEM
1
INT_WAKE
2
1. UART CTS pin can wake-up system, when the rising or filling edge event
2. After wake-up signal, the UART clock will start and set interrupt flag

51
 UART Wake-up Function (2/2)
• UART RX data wake-up
sleep
mode
CLK
SIN Start D0 D1 D2 D3 D4 D5

WAKE_SYSTEM 1
INT_WAKE
2

1. UART incoming data can wake-up system, when the “Start Bit” enter
2. After wake-up signal, the UART clock will start and set interrupt flag

52
 IrDA Function Mode(1/2)
• Support IrDA transmitter or receiver
• Support Inverse function for IR_SOUT and IR_SIN

SOUT TX pin Emit Infra red ray

TX IR_SOUT
IrDA IR
UART
SIR Transceiver
SIN RX pin Detect Infra red ray
RX IR_SIN

BAUDOUT

IrDA_enable
TX_select
IRCR INT_TX
INV_RX

53
 IrDA Function Mode(2/2)
START Bit STOP Bit

SOUT
1 0 0 1 0 1 1 1 0 0 1
(From UART TX)
TX
Timing
IR_SOUT
(Encoder Output)

3/16 Bit Width

IR_SIN
(Decorder Input)
RX 3/16 Bit Width
Timing

SIN
1 0 1 0 0 1 0 1 0 0 1
(To UART RX)

START Bit STOP Bit

Bit Pulse Width

54
 RS-485 Function Mode
• Supports hardware or software controls RTSn or
software control GPIO to control transfer direction
• Supports RS-485 hardware address detection
• Normal Multi-Drop Operation Mode (NMM)
• Auto Address Detection Operation Mode (AAD)
• Auto Direction Mode (AUD)
RX

UART/RS-485 Differenitial Bus

TX
Controller

RS-485 Transceiver

RTS
Drive Enable

STOP
TX S D0 D1 D2 D3 D4 D5 D6 D7 P

RTS Drive Enable

55
 LIN Function Mode
• Support LIN master/slave node mode
• LIN header selection
• Break field + Sync field + Identifier field
• LIN break field count setting (master only)
• 8-bits ~ 15-bits
• Support LIN header and bit error detect interrupt
Frame slot
Frame

Response Inter-
space frame
Header Response space

Break Field Synch field Protected Data 1 Data 2 Data N Check

Identifier Sum
field

START DATA (8 bits) STOP(1 bit) START

56
 UART Example
• UART0 sample code
• Baudrate:115200
• Date length: 8 bits
• Parity : Disable
• Stop: 1 bit

57
 UART Sample Code (1/2)
//----------------------------------------------------------------------------
// MAIN function
//----------------------------------------------------------------------------
int32_t main (void)
{
STR_UART_T sParam;
uint8_t u8data;

UNLOCKREG();
CLK->PWRCTL |= CLK_PWRCTL_HXT_EN;
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_HXT_STB));
LOCKREG();
Setting UART clock source and divider
// Select UART clock source and Enable UART0 clock
CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_UART_MASK) |
CLK_CLKSEL1_UART_HXT;
CLK->CLKDIV0 &= ~CLK_CLKDIV0_UART_MASK;

// Enable UART0 clock Enable UART0 clock

CLK->APBCLK |= CLK_APBCLK_UART0_EN;

// Enable UART0 function pin Enable UART0 function pin

MFP_FULL_UART0_TO_PORTA();

58
 UART Sample Code (2/2)
// Setting and Initial UART0
sParam.u32BaudRate = 115200;
sparam.u32cDataBits = DRVUART_DATABITS_8;
sparam.u32cStopBits = DRVUART_STOPBITS_1;
sparam.u32cParity = DRVUART_PARITY_NONE;
sparam.u32cRxTriggerLevel = DRVUART_FIFO_1BYTES;
sParam.u8EnableDiv16 = DISABLE;

//UART0 Initialize
UART_Init(UART0, &sParam); Setting UART baud rate and serial format

//UART transmit and receive test

printf(“Please press any key...\n”);
scanf("%c", &u8data);
printf(“Enter key is: %c\n”, u8data);
Transmit and receive test
while(1);
}

59
 Sample Code Timer_WDT_RTC

Nano100BSeriesBSP_CMSIS

NuMicro NANO100B
Document Driver Reference Guide

Sample

Nu_LB

Timer_WDT_RTC

Timer_WDT_RTC. uvproj
KEIL

60
 Timer_WDT_RTC Condition
• TIMER setting
• Clock source: 12MHz
• Operation mode: Periodic mode
• Time out period = (1/12000000)*(255+1)*(46875) = 1 second
• WDT setting
• Clock source: 10KHz
• WTIS: 0x06
• WDT timeout interval for interrupt = 6.55 s
• RTC setting
• Clock source: 32KHz
• Current time setting: Date09/1/19, time13:20:00
• Alarm time setting: Date09/1/19, time13:20:20
61
Timer_WDT_RTC Result

On-board Nu-Link-Me connect to

KEIL-IDE debug or programming

UART port:
transmit Timer, WDT and RTC
information

Reset key, press to reboot

Nano100 chip

62
 Q&A

Thank You

63