Ccopt Rak For Beginners: Product - Innovus 16.20 April 2017

CCOpt RAK for Beginners
Product – Innovus 16.20

April 2017
© 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

Agenda
1. CCOpt script
2. Clock Tree Debugger (CTD) before CTS
3. Cluster CTS
4. Trial CTS
5. CCOpt
6. Worst chain report after ccopt_design with the RAK
Note: RAK Testcase Database can be downloaded from the 'Attachments' section at the
bottom of this PDF. This RAK can also be searched on the support portal i.e.
https://support.cadence.com, using the ‘Title’ of the RAK.
2 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

1. CCOpt script
 Design
 runLab.tcl
 config.tcl
 ccopt.spec

Design: leon (./DATA/prects.enc.dat/leon.v.gz)
 3 clocks
Period: 8ns
div_clk
clk_div_out_mux
Period: 4ns
A
Y
B
Period: 8ns

./SCRIPTS/runLab.tcl
source ./DATA/prects.enc
source ./SCRIPTS/config.tcl Go to next slide
create_ccopt_clock_tree_spec -file ccopt.spec; Go to the slide after next
source ./ccopt.spec
set_ccopt_property -delay_corner slow_max -net_type trunk target_max_trans 150ps
set_ccopt_property -delay_corner fast_min -net_type trunk target_max_trans 150ps
set_ccopt_property -delay_corner slow_max -net_type leaf target_max_trans 150ps
set_ccopt_property -delay_corner fast_min -net_type leaf target_max_trans 150ps
set_ccopt_property -skew_group div_clk/functional_func_slow_max -delay_corner fast_min target_skew 200ps
set_ccopt_property -skew_group my_clk/functional_func_slow_max -delay_corner fast_min target_skew 200ps
set_ccopt_property -skew_group test_clk/functional_func_slow_max -delay_corner fast_min target_skew 200ps
setOptMode –usefulSkewCCOpt medium; # set_ccopt_effort –medium in 15.x
ccopt_design
saveDesign ./DBS/postcts.enc
report_ccopt_worst_chain

./SCRIPTS/config.tcl
update_constraint_mode -name functional_func_slow_max -sdc_files [list DATA/leon_func_slow_max_postcts.sdc]

setAnalysisMode -analysisType onChipVariation -cppr both
set_ccopt_property buffer_cells {CLKBUFX8 CLKBUFX12 CLKBUFX16 CLKBUFX20}
set_ccopt_property inverter_cells {CLKINVX8 CLKINVX12 CLKINVX16 CLKINVX20}
set_ccopt_property clock_gating_cells {TLAT*}
set_ccopt_property target_skew 0.200
set_ccopt_property target_max_trans 0.200 *For timing_corner slow_max:setup, late:
Slew time target (leaf): 0.150ns
setNanoRouteMode -drouteUseMultiCutViaEffort "high" Slew time target (trunk): 0.150ns
Slew time target (top): 0.200ns
setRouteMode -earlyGlobalMaxRouteLayer 9
create_route_type -name leaf -top_preferred_layer 5 -bottom_preferred_layer 4 -preferred_routing_layer_effort high

create_route_type -name trunk -top_preferred_layer 6 -bottom_preferred_layer 5 -preferred_routing_layer_effort high
set_ccopt_property route_type -net_type top trunk
set_ccopt_property route_type -net_type trunk trunk
set_ccopt_property route_type -net_type leaf leaf
set_ccopt_property primary_delay_corner slow_max

set_ccopt_property route_type_autotrim false

./ccopt.spec
# Command: create_ccopt_clock_tree_spec -file ccopt.spec

# The following pins are on the boundary of the STA clock network
# These pins are ignore skew pins # This is a -constrains "none" skew group (reporting only) for generated clock:div_clk in
set_ccopt_property sink_type -pin mcore0/a0/g1626/B ignore #timing_config:functional_func_slow_max (sdc DATA/leon_func_slow_max_postcts.sdc)
set_ccopt_property sink_type_reasons -pin mcore0/a0/g1626/B no_sdc_clock # because it corresponds to a generated clock that is synchronous to its master clock and will balanced as part
#of the skew group corresponding to one of its master clocks.
create_ccopt_clock_tree -name test_clk -source scan_clk -no_skew_group # immediate master: clock:my_clk in timing_config functional_func_slow_max
# balancing master: clock:my_clk in timing_config functional_func_slow_max
set_ccopt_property source_max_capacitance -clock_tree test_clk 1.000 # ultimate master: clock:my_clk in timing_config functional_func_slow_max
# Clock period setting for source pin of test_clk create_ccopt_skew_group -name div_clk/functional_func_slow_max -sources clk_div_reg/Q -auto_sinks
set_ccopt_property clock_period -pin scan_clk 8 set_ccopt_property include_source_latency -skew_group div_clk/functional_func_slow_max true
set_ccopt_property constrains -skew_group div_clk/functional_func_slow_max none
# Clocks present at pin clk set_ccopt_property extracted_from_clock_name -skew_group div_clk/functional_func_slow_max div_clk
# my_clk (period 4.000ns) in timing_config set_ccopt_property extracted_from_constraint_mode_name -skew_group div_clk/functional_func_slow_max \
#functional_func_slow_max([DATA/leon_func_slow_max_postcts.sdc]) functional_func_slow_max
create_ccopt_clock_tree -name my_clk -source clk -no_skew_group set_ccopt_property extracted_from_delay_corners -skew_group div_clk/functional_func_slow_max {slow_max
fast_min}
set_ccopt_property source_max_capacitance -clock_tree my_clk 1.000
# Clock period setting for source pin of my_clk # Skew group to balance non generated clock:my_clk in timing_config:functional_func_slow_max (sdc
set_ccopt_property clock_period -pin clk 4 #DATA/leon_func_slow_max_postcts.sdc)
create_ccopt_skew_group -name my_clk/functional_func_slow_max -sources clk -auto_sinks
# Clocks present at pin clk_div_reg/Q set_ccopt_property include_source_latency -skew_group my_clk/functional_func_slow_max true
# div_clk (period 8.000ns) in timing_config set_ccopt_property extracted_from_clock_name -skew_group my_clk/functional_func_slow_max my_clk
#functional_func_slow_max([DATA/leon_func_slow_max_postcts.sdc]) set_ccopt_property extracted_from_constraint_mode_name -skew_group my_clk/functional_func_slow_max \
# my_clk (period 4.000ns) in timing_config functional_func_slow_max
#functional_func_slow_max([DATA/leon_func_slow_max_postcts.sdc]) set_ccopt_property extracted_from_delay_corners -skew_group my_clk/functional_func_slow_max {slow_max fast_min}
create_ccopt_generated_clock_tree -name div_clk -source clk_div_reg/Q -
generated_by clk_div_reg/CK # Skew group to balance non generated clock:test_clk in timing_config:functional_func_slow_max (sdc
#DATA/leon_func_slow_max_postcts.sdc)
# Clock period setting for source pin of div_clk create_ccopt_skew_group -name test_clk/functional_func_slow_max -sources scan_clk -auto_sinks
set_ccopt_property clock_period -pin clk_div_reg/Q 8 set_ccopt_property include_source_latency -skew_group test_clk/functional_func_slow_max true
set_ccopt_property extracted_from_clock_name -skew_group test_clk/functional_func_slow_max test_clk
set_ccopt_property extracted_from_constraint_mode_name -skew_group test_clk/functional_func_slow_max \
functional_func_slow_max
set_ccopt_property extracted_from_delay_corners -skew_group test_clk/functional_func_slow_max {slow_max \
fast_min}

Part 1: ccopt.spec (1/6)
# Command: create_ccopt_clock_tree_spec -file ccopt.spec
# The following pins are on the boundary of the STA clock network
# These pins are ignore skew pins Why did ccopt extract the
pin as an ignore pin?
set_ccopt_property sink_type -pin mcore0/a0/g1626/B ignore
set_ccopt_property sink_type_reasons -pin mcore0/a0/g1626/B no_sdc_clock
innovus> report_property [get_pins mcore0/a0/g1626/B] no_sdc_clock means the SDC clock is

… stopped at this pin for other reasons.
escaped_name | mcore0/a0/g1626/B So, the SDC clock phase doesn’t
is_clock | false
propagate beyond the ignored pin.
is_clock_gating | false
is_clock_gating_clock | false
is_clock_gating_enable | false
is_clock_used_as_clock | false
is_clock_used_as_data | true
…

innovus> all_fanin -to mcore0/a0/g1626/B

mcore0/a0/g1626/B clk_div_out_mux/Y clk_div_out_mux/S0 clk_div_out_mux/B clk_div_out_mux/A clk_div_reg/Q tm scan_clk
0x15ca
innovus> report_fanin -to mcore0/a0/g1626/B

…
Fanin Network for View: func_slow_max
Fanin Network for Pin: mcore0/a0/g1626/B
+-------------------------------------------------------------------------------------------------------+
| Source Pin | Sink Pin | Cell Type | Timing Sense | Arc | Case |
| | | | | Disabled | Analysis |
|----------------------+----------------------+-----------------+-----------------+----------+----------|
| clk_div_out_mux/Y | mcore0/a0/g1626/B | (net) | - | - | - |
| -- | -- | -- Clock|Mux
-- Used | -- | -- |
| clk_div_out_mux/S0 | clk_div_out_mux/Y | MX2X4 | - | - | - |
| clk_div_out_mux/B | clk_div_out_mux/Y | MX2X4 | positive_unate | - | - |
| clk_div_out_mux/A | clk_div_out_mux/Y | MX2X4 | positive_unate | - | - |
| -- | -- | -- | -- | -- | -- |
| tm | clk_div_out_mux/S0 | (net) | - | - | - |
| scan_clk | clk_div_out_mux/B | (net) | - | - | - |
| clk_div_reg/Q | clk_div_out_mux/A | (net) | - | - | - |
| -- | -- | -- | -- | -- | -- |
+-------------------------------------------------------------------------------------------------------+

Data pin of a FF
innovus> all_fanout -from mcore0/a0/g1626/B -endpoints_only
proc0/c0/dcache0/r_reg_req/DFF/D proc0/c0/dcache0/r_reg_burst/DFF/D proc0/c0/icache0/r_reg_req/DFF/D
proc0/c0/icache0/r_reg_burst/DFF/D proc0/c0/icache0/r_reg_valid_3/DFF/D proc0/c0/icache0/r_reg_valid_2/DFF/D
proc0/c0/icache0/r_reg_valid_1/DFF/D proc0/c0/icache0/r_reg_valid_0/DFF/D proc0/cmem0/itags0/u0/id0/WE1 …
innovus> report_fanout -from mcore0/a0/g1626/B

Fanout Network for View: func_slow_max
Fanout Network for Pin: mcore0/a0/g1626/B
+---------------------------------------------------------------------------------------------------------------------------+
|--------------------------------+--------------------------------+-----------------+-----------------+----------+----------|
| mcore0/a0/g1626/B | mcore0/a0/g1626/Y | NOR2BX4 | negative_unate | - | - |
| -- | -- | -- | -- | -- | -- |
| mcore0/a0/g1626/Y | mcore0/a0/g1549/B | (net) | - | - | - |
| mcore0/a0/g1626/Y | mcore0/a0/g975/B | (net) | - | - | - |
| mcore0/a0/g1626/Y | mcore0/a0/g985/AN | (net) | - | - | - |
| mcore0/a0/g1626/Y | mcore0/a0/g1090/A | (net) | - | - | - |
| -- | -- | -- | -- | -- | -- |

• Fanin logics at the ignore pin mcore0/a0/g1626/B

div_clk(8ns)
clk_div_out_mux
clk_div_reg
D Q A
Y To sync pins
^
CK B S0
DFFX1 MX2X2
mcore0/a0/g1626
clk_out_mux
CGIC_INST B To data pins
clk_en E GCK A
Y
ICG S0
B
^
CK
MX2X8
TLATNTSCAX6
clk
my_clk(4ns)
scan_clk
test_clk(8ns) tm

• Ignore pin is a part of Structural Clock Network Elements

Root pins
– The starting pin of a clock signal
R R R R
Clock trees
–The transitive fanout of a root pin R Internal pins
–A sink can belong to more than one clock tree –Any pin that is not a root or a sink
IGNORE
IGNORE
STOP
Sink pins
–The terminal points for a clock signal
–Sequential element pins
–Stop pins
–Ignore pins

Structural Elements – Identifying ignore pin

 Manually define a sink by labeling it as a “stop pin” or “ignore pin”
– set_ccopt_property sink_type –pin <pin> stop
– set_ccopt_property sink_type –pin <pin> ignore
– Ex. get_ccopt_property sink_type –pin <sink_pin> R
 Ignore pins can be defined for just selected skew groups (skew group-specific Stop pin
ignore pins) or
Ignore Pin
– Use the modify_ccopt_skew_group command
– After creating skew_groups one can add ignore pin by using
modify_ccopt_skew_group
Ex. modify_ccopt_skew_group -skew_group div_clk/functional_func_slow_max \

macro
-add_ignore_pins xy/z
get_ccopt_property -skew_group div_clk/functional_func_slow_max ignore_pins Stop pin= Balance like a normal sink
Ignore pin= Do not balance. Minimize ID

Part 2: ccopt.spec
create_ccopt_clock_tree -name test_clk -source scan_clk -no_skew_group Define clock tree on scan_clk
set_ccopt_property source_max_capacitance -clock_tree test_clk 1.000

# Clock period setting for source pin of test_clk Define clock period of
set_ccopt_property clock_period -pin scan_clk 8 scan_clk
# Clocks present at pin clk

# my_clk (period 4.000ns) in timing_config functional_func_slow_max([DATA/leon_func_slow_max_postcts.sdc])
create_ccopt_clock_tree -name my_clk -source clk -no_skew_group Define clock tree on clk
set_ccopt_property source_max_capacitance -clock_tree my_clk 1.000

# Clock period setting for source pin of my_clk
Define clock period of clk
set_ccopt_property clock_period -pin clk 4
# Clocks present at pin clk_div_reg/Q

# div_clk (period 8.000ns) in timing_config functional_func_slow_max([DATA/leon_func_slow_max_postcts.sdc])
# my_clk (period 4.000ns) in timing_config functional_func_slow_max([DATA/leon_func_slow_max_postcts.sdc])
create_ccopt_generated_clock_tree -name div_clk -source clk_div_reg/Q -generated_by clk_div_reg/CK
Define clock tree on
clk_div_reg/Q
# Clock period setting for source pin of div_clk
set_ccopt_property clock_period -pin clk_div_reg/Q 8
Define clock period of
clk_div_reg/Q

# This is a -constrains "none" skew group (reporting only) for generated clock:div_clk in timing_config:functional_func_slow_max (sdc
DATA/leon_func_slow_max_postcts.sdc)
# because it corresponds to a generated clock that is synchronous to its master clock and will balanced as part of the skew group
corresponding to one of its master clocks.
# immediate master: clock:my_clk in timing_config functional_func_slow_max
# ultimate master: clock:my_clk in timing_config functional_func_slow_max Define skew group on
create_ccopt_skew_group -name div_clk/functional_func_slow_max -sources clk_div_reg/Q -auto_sinks clk_div_reg/Q
set_ccopt_property include_source_latency -skew_group div_clk/functional_func_slow_max true
set_ccopt_property constrains -skew_group div_clk/functional_func_slow_max none
set_ccopt_property extracted_from_clock_name -skew_group div_clk/functional_func_slow_max div_clk
set_ccopt_property extracted_from_constraint_mode_name -skew_group div_clk/functional_func_slow_max functional_func_slow_max
set_ccopt_property extracted_from_delay_corners -skew_group div_clk/functional_func_slow_max {slow_max fast_min}
# Skew group to balance non generated clock:my_clk in timing_config:functional_func_slow_max (sdc

DATA/leon_func_slow_max_postcts.sdc) Define skew group on clk
create_ccopt_skew_group -name my_clk/functional_func_slow_max -sources clk -auto_sinks
set_ccopt_property include_source_latency -skew_group my_clk/functional_func_slow_max true
set_ccopt_property extracted_from_clock_name -skew_group my_clk/functional_func_slow_max my_clk
set_ccopt_property extracted_from_constraint_mode_name -skew_group my_clk/functional_func_slow_max functional_func_slow_max
set_ccopt_property extracted_from_delay_corners -skew_group my_clk/functional_func_slow_max {slow_max fast_min}
# Skew group to balance non generated clock:test_clk in timing_config:functional_func_slow_max (sdc

DATA/leon_func_slow_max_postcts.sdc) Define skew group on scan_clk
create_ccopt_skew_group -name test_clk/functional_func_slow_max -sources scan_clk -auto_sinks
set_ccopt_property include_source_latency -skew_group test_clk/functional_func_slow_max true
set_ccopt_property extracted_from_clock_name -skew_group test_clk/functional_func_slow_max test_clk
set_ccopt_property extracted_from_constraint_mode_name -skew_group test_clk/functional_func_slow_max functional_func_slow_max
set_ccopt_property extracted_from_delay_corners -skew_group test_clk/functional_func_slow_max {slow_max fast_min}

# This is a -constrains "none" skew group (reporting only) for generated clock:div_clk in
timing_config:functional_func_slow_max (sdc DATA/leon_func_slow_max_postcts.sdc)
# because it corresponds to a generated clock that is synchronous to its master clock and will balanced as
part of the skew group corresponding to one of its master clocks.
# immediate master: clock:my_clk in timing_config functional_func_slow_max
# ultimate master: clock:my_clk in timing_config functional_func_slow_max
create_ccopt_skew_group -name div_clk/functional_func_slow_max -sources clk_div_reg/Q -auto_sinks
set_ccopt_property include_source_latency -skew_group div_clk/functional_func_slow_max true
set_ccopt_property constrains
set_ccopt_property constrains -skew_group
-skew_group div_clk/functional_func_slow_max
div_clk/functional_func_slow_max none
none
Define skew group on
clk_div_reg/Q
(reporting only)

Structural Elements – Tracing Exceptions
R
Tracing Exception #1
 Extraction traces through a clock gate
G  Will automatically recognize non-integrated clock gates too
R
Tracing Exception #2
 Extraction traces all paths from the parent clock to the
generated clock root – even through sequential elements
Divider
 Sequential elements in the generator source path
R
Generated automatically become ignore pins
Clock

2. CTD before CTS
 To analyze clock structures and check any missing or wrong clocks
 Csh% innovus –log ./LOGS/runInit.log –init ./SCRIPT/runInit.tcl
innovus> source ./DATA/prects.enc;

innovus> source ./SCRIPTS/config.tcl
innovus> create_ccopt_clock_tree_spec -file ccopt.spec;
innovus> source ./ccopt.spec; ctd_win
innovus> saveDesign ./DBS/preCTS.ctsspec.enc
innovus> ctd_win

2. CTD before CTS
 On clock tree debugger

 Please put your mouse to a symbol to see its pin/port name, arrival time, and cell type
3 clock roots (2 master clocks, 1 generated clock)

clk scan_clk
CGIC_INST/CK (TLATNCSTACAX2) clk_div_req/CK (DFFX1)
0ns 0ns
0.0216ns 0.0225ns
Cell type: Clock Cell type: Clock
Cell type: Clock gate root Cell type: Other root
clk_div_req/Q (DFFX1)
0.0225ns
Cell type: Clock root

2. CTD before CTS
 Clock MUXs (clk_out_mux, clk_div_out_mux)
clk_out_mux/A (MX2X4) clk_out_mux/B (MX2X4)

0.2623ns 0.0233ns
Cell type: Mux Cell type: Mux
clk_div_out_mux/A (MX2X4) clk_div_out_mux/B (MX2X4)

0.332ns 0.0203ns
Cell type: Mux Cell type: Mux

2. CTD before CTS
Full View
scan_clk
0ns
clk_div_req/CK (DFFX1) Generated clock Cell type: Clock
0.0225ns root
Cell type: Other
clk_div_req/Q (DFFX1)
0.0225ns
Cell type: Clock root
clk_div_out_mux/A
0.3321ns clk_div_out_mux/B (MX2X4)
Cell type: Mux 0.0203ns
Cell type: Mux clk_out_mux/B (MX2X4)
0.0233ns
Cell type: Mux

2. CTD before CTS
 Where is the ignore pin mcore0/a0/g1626/B?

innovus> get_ccopt_property sink_type -pin mcore0/a0/g1626/B
ignore
 Click the icon Find
mcore0/a0/g1626/B (NOR2BX4)
0.5386ns
Cell type: Other sink

2. CTD before CTS
 Cell type
 Clock root
 Clock gate
 Clock sink
• Flop pin
• Latch pin
• RAM pin
• Enable latch pin
• ILM stop pin
• Other sink
- I/O pins
- combinational logic pins (ignored pins)
- macros with no library definition (i.e. black box macros).
 Clock driver
• Buffer
• Inverter
 Clock balancing
 Clock delay
 Clock logic
• AND
• Mux
 Other
3. Cluster CTS
 Fast DRV cleaning of whole clock network

 Do not perform skew-balancing
 Focusing on minimum latency
 Useful to debug latency based on Floorplan/DRV constraints
 Please run “innovus –log ./LOGS/runCluster.log –init ./SCRIPTS/runCluster.tcl”
 innovus> set_ccopt_property balance_mode cluster

 innovus> ccopt_design –cts
 innovus> saveDesign ./DBS/postcts.cluster.enc

3. Cluster CTS
 Fixing DRV fixing -> buffers added with some naming rules *ccl* and *ccd*
 Removing unnecessary buffering and minimizing Insertion Delay
clk scan_clk clk scan_clk
G G
2 2
Cluster CTS
0 1 0 1 0 1 0 1
G
G
Ignore pin G
G
G
G G G
G G G G G
Buffer named *ccl*

G ICG cell Buffer named
*ccd*

3. Cluster CTS
 restore ./DBS/postcts.cluster.enc
 On GUI, please select Clock->CCOpt Clock Tree Debugger…
Ignore pin: mcore0/a0/g1626/B
mcore0/a0/CTS_ccd_BUF_div_clk_G0_L2_2/A
(CLKBUFX20)
0.5636ns
CGIC_INST/CK (TLATNTSCAX6) Cell type: Buffer
0.0153ns
Cell type: Clock gate
mcore0/a0/g1626/B (NOR2BX4)
clk_out_mux/A (MX2X4) 0.6634ns
0.2748ns Cell type: Other sink
Cell type: Mux
Buffers added
CTS_ccl_BUF_my_clk_G1_L3_1/A (CLKBUFX20)
to meet DRV 0.4718ns
constraints Cell type: Buffer

3. Cluster CTS
innovus> report_fanin -to mcore0/a0/g1626/B

Fanin Network for View: func_slow_max
Fanin Network for Pin: mcore0/a0/g1626/B
+---------------------------------------------------------------------------------------------------------------------------+
|--------------------------------+--------------------------------+-----------------+-----------------+----------+----------|
| mcore0/a0/CTS_ccd_BUF_div_clk_ | mcore0/a0/g1626/B | (net) | - | - | - |
| G0_L2_2/Y | | |
The buffer is added | | |
| -- | -- | -- | -- | -- | -- |
| mcore0/a0/CTS_ccd_BUF_div_clk_ | mcore0/a0/CTS_ccd_BUF_div_clk_ | CLKBUFX20 | positive_unate | - | - |
| G0_L2_2/A | G0_L2_2/Y | | | | |
| -- | -- | -- | -- | -- | -- |
| clk_div_out_mux/Y | mcore0/a0/CTS_ccd_BUF_div_clk_ | (net) | - | - | - |
| | G0_L2_2/A | | | | |
| -- | -- | -- | -- | -- | -- |
| clk_div_out_mux/S0 | clk_div_out_mux/Y | MX2X8 | - | - | - |
| clk_div_out_mux/B | clk_div_out_mux/Y | MX2X8 | positive_unate | - | - |
| clk_div_out_mux/A | clk_div_out_mux/Y | MX2X8 | positive_unate | - | - |
| -- | -- | -- | -- | -- | -- |
| tm | clk_div_out_mux/S0 | (net) | - | - | - |
| CTS_ccl_BUF_test_clk_G0_L1_1/Y | clk_div_out_mux/B | (net) | - | - | - |
| clk_div_reg/Q | clk_div_out_mux/A | (net) | - | - | - |
| -- | -- | -- | -- | -- | -- |
| CTS_ccl_BUF_test_clk_G0_L1_1/A | CTS_ccl_BUF_test_clk_G0_L1_1/Y | CLKBUFX20 | positive_unate | - | - |
| -- | -- | -- | -- | -- | -- |
| scan_clk | CTS_ccl_BUF_test_clk_G0_L1_1/A | (net) | - | - | - |
| -- | -- | -- | -- | -- | -- |
+---------------------------------------------------------------------------------------------------------------------------+

3. Cluster CTS
• Fanin logics at the ignore pin mcore0/a0/g1626/B

div_clk(8ns)
clk_div_out_mux
clk_div_reg
D Q A
Y To sync pins
^
CK B
DFFX1 MX2X2
mcore0/a0/CTS_ccd_BUF_div_clk_G0_L2_2
clk_out_mux
CGIC_INST mcore0/a0/g1626
clk_en E GCK A CLKBUF20 To data pins
Y B
ICG
B
^
CK
MX2X8
TLATNTSCAX6
clk
my_clk(4ns)
scan_clk
test_clk(8ns)

3. Cluster CTS
wall: Elapsed time

Runtime Summary:
================ % time: % of the wall
--------------------------------------------------------------------------------------------------------
wall % time children called name
--------------------------------------------------------------------------------------------------------
133.66 100.00 133.66 0
133.66 100.00 133.11 1 Runtime
0.46 0.35 0.46 1 CCOpt::Phase::Initialization
0.46 0.35 0.46 1 Check Prerequisites
0.46 0.35 0.00 1 Leaving CCOpt scope - CheckPlace CCOpt::Phase::Initialization done
3.58 2.68 0.00 1 Leaving CCOpt scope - optDesignGlobalRouteStep
5.83 4.36 0.00 1 Validating CTS configuration
0.58 0.44 0.00 1 Preparing To Balance
102.78 76.90 102.78 1 CCOpt::Phase::Clustering
40.10 30.00 34.26 1 Stage::DRV Fixing
29.87 22.35 2.09 1 Clustering
2.09 1.56 0.00 1 Leaving CCOpt scope - RefinePlacement
1.28 0.96 0.00 1 Leaving CCOpt scope
1.99 1.49 0.00 1 Fixing clock tree slew time and max cap violations
1.12 0.83 0.00 1 Fixing clock tree slew time and max cap violations - detailed pass
62.68 46.90 62.56 1 Stage::Insertion Delay Reduction
0.88 0.66 0.00 1 Removing unnecessary root buffering
0.73 0.55 0.00 1 Removing unconstrained drivers
1.32 0.99 0.00 1 Reducing insertion delay 1
2.57 1.92 0.00 1 Removing longest path buffering
7.65 5.72 1.26 1 CCOpt::Phase::Implementation
CCOpt::Phase::Clustering done
1.26 0.94 0.00 1 Leaving CCOpt scope CCOpt::Phase::Implementation done
12.23 9.15 0.00 1 Tidy Up And Update Timing
--------------------------------------------------------------------------------------------------------

3. Cluster CTS
 ./LOGS/runCluster.log
<CMD> ccopt_design -cts

Runtime...
(ccopt_design): CTS Engine: auto. Used Spec: pre-existing CCOPT spec.
Placement constraints of type 'region' or 'fence' will not be downgraded to 'guide' because the property change_fences_to_guides has been
set to false.
Set place::cacheFPlanSiteMark to 1
CCOpt::Phase::Initialization...
Check Prerequisites...
Leaving CCOpt scope - CheckPlace...
…
Begin checking placement ... (start mem=1025.8M, init mem=1025.8M)
*info: Placed = 35773 (Fixed = 4)
*info: Unplaced = 0
Placement Density:40.40%(149177/369239)
Placement Density (including fixed std cells):40.40%(149177/369239)
Finished checkPlace (cpu: total=0:00:00.5, vio checks=0:00:00.1; mem=1025.8M)
Leaving CCOpt scope - CheckPlace done. (took cpu=0:00:00.5 real=0:00:00.5)
Innovus will update I/O latencies
All good
Check Prerequisites done. (took cpu=0:00:00.5 real=0:00:00.5)
CCOpt::Phase::Initialization done. (took cpu=0:00:00.5 real=0:00:00.5)
…

3. Cluster CTS
Executing ccopt post-processing.

Synthesizing clock trees with CCOpt...
Leaving CCOpt scope - optDesignGlobalRouteStep...
[NR-eGR] honorMsvRouteConstraint: false
[NR-eGR] honorClockSpecNDR :0
[NR-eGR] minRouteLayer :2
[NR-eGR] maxRouteLayer :9
[NR-eGR] numTracksPerClockWire : 0
[NR-eGR] Layer1 has no routable track
…
[NR-eGR] Layer9 has single uniform track structure
[NR-eGR] numRoutingBlks=0 numInstBlks=1812 numPGBlocks=26919 numBumpBlks=0 numBoundaryFakeBlks=0
[NR-eGR] numPreroutedNet = 0 numPreroutedWires = 0
[NR-eGR] Read numTotalNets=36370 numIgnoredNets=0
[NR-eGR] There are 41 clock nets ( 0 with NDR ).
[NR-eGR] ============ Routing rule table ============
[NR-eGR] Rule id 0. Nets 36370
[NR-eGR] id=0 ndrTrackId=0 ndrViaId=-1 extraSpace=0 numShields=0 maxHorDemand=1 maxVerDemand=1
[NR-eGR] Pitch: L1=240 L2=400 L3=380 L4=400 L5=380 L6=400 L7=570 L8=400 L9=760
[NR-eGR] ========================================
[NR-eGR] Layer group 1: route 36370 net(s) in layer range [2, 9]
[NR-eGR] earlyGlobalRoute overflow of layer group 1: 0.00% H + 0.00% V. EstWL: 1.411292e+06um
[NR-eGR] Overflow after earlyGlobalRoute (GR compatible) 0.00% H + 0.00% V
[NR-eGR] Overflow after earlyGlobalRoute 0.00% H + 0.00% V
[NR-eGR] Layer1(Metal1)(F) length: 0.000000e+00um, number of vias: 157508
[NR-eGR] Layer2(Metal2)(V) length: 2.060970e+05um, number of vias: 205495
…
[NR-eGR] Total length: 1.445020e+06um, number of vias: 484567
[NR-eGR] End Peak syMemory usage = 1036.0 MB
[NR-eGR] Early Global Router Kernel+IO runtime : 3.55 seconds
Leaving CCOpt scope - optDesignGlobalRouteStep done. (took cpu=0:00:03.7 real=0:00:03.6) …

3. Cluster CTS
Using cell based legalization.

Validating CTS configuration...
Non-default CCOpt properties:
buffer_cells is set for at least one key
clock_gating_cells is set for at least one key
balance_mode: cluster (default: full)
inverter_cells is set for at least one key
primary_delay_corner: slow_max (default: )
route_type is set for at least one key
route_type_autotrim: 0 (default: true)
source_max_capacitance is set for at least one key
target_max_trans is set for at least one key
target_skew is set for at least one key
…
Rebuilding timing graph...
Using master clock 'my_clk' for generated clock 'div_clk' in view 'func_slow_max'
Rebuilding timing graph done.
AAE DB initialization (MEM=1080.05 CPU=0:00:00.1 REAL=0:00:00.0)
Library trimming buffers in power domain auto-default and half-corner slow_max:setup.late removed 0 of 4 cells
Library trimming inverters in power domain auto-default and half-corner slow_max:setup.late removed 0 of 4 cells
Library trimming clock gates in power domain auto-default and half-corner slow_max:setup.late removed 0 of 8 cells
To disable library trimming, set_ccopt_property library_trimming false.
Library Trimming done.
Library Trimming...
To disable library trimming, set_ccopt_property library_trimming false.
Library Trimming done.
…

3. Cluster CTS
Clock tree balancer configuration for clock_trees div_clk my_clk test_clk:

Non-default CCOpt properties for clock tree div_clk:
route_type (leaf): leaf (default: default)
route_type (trunk): trunk (default: default)
route_type (top): trunk (default: default)
Library Trimming...
For power_domain auto-default and effective power_domain auto-default:
Buffers: CLKBUFX20 CLKBUFX16 CLKBUFX12 CLKBUFX8
Inverters: CLKINVX20 CLKINVX16 CLKINVX12 CLKINVX8
Clock gates: TLATNTSCAX20 TLATNTSCAX16 TLATNTSCAX12 TLATNTSCAX8 TLATNTSCAX6 TLATNTSCAX4 TLATNTSCAX3 TLATNTSCAX2
Unblocked area available for placement of any clock cells in power_domain auto-default: 412094.800um^2
Top/Trunk Routing info:
Route-type name: trunk; Top/bottom preferred layer name: M6/M5;
Unshielded; Mask Constraint: 0.
Leaf Routing info:
Route-type name: leaf; Top/bottom preferred layer name: M5/M4;
Unshielded; Mask Constraint: 0.
For timing_corner slow_max:setup, late:
Slew time target (leaf): 0.150ns
Slew time target (trunk): 0.150ns
Slew time target (top): 0.200ns
…

3. Cluster CTS
Clock tree balancer configuration for skew_group my_clk/functional_func_slow_max:

Sources: pin clk
Total number of sinks: 11537
Delay constrained sinks: 11536
Non-leaf sinks: 0
What is the missing one?
Ignore pins: 0 innovus> report_ccopt_skew_groups -summary
Timing corner slow_max:setup.late: Skew Group Structure:

=====================
Skew target: 0.200ns
Timing corner fast_min:hold.late: ---------------------------------------------------------------------------------
Skew Group Sources Constrained Sinks Ignore Sinks
Skew target: 0.200ns ---------------------------------------------------------------------------------
div_clk/functional_func_slow_max 1 1922 1
Clock tree balancer configuration for skew_group test_clk/functional_func_slow_max:
my_clk/functional_func_slow_max 1 11536 1
test_clk/functional_func_slow_max 1 11536 1
Sources: pin scan_clk ---------------------------------------------------------------------------------
…
Total number of sinks: 11537
Delay constrained sinks: 11536
Non-leaf sinks: 0
Ignore pins: 0 innovus> get_ccopt_property -skew_group my_clk/functional_func_slow_max ignore_pins
innovus> foreach sink [get_ccopt_property -skew_group my_clk/functional_func_slow_max sinks] {
Timing corner slow_max:setup.late: + if {[get_ccopt_property sink_type -pin $sink] == "ignore"} {
+ puts "$sink"
Skew target: 0.200ns + }
+ }
Timing corner fast_min:hold.late: mcore0/a0/g1626/B
Skew target: 0.200ns
…

3. Cluster CTS
Primary reporting skew group is skew_group my_clk/functional_func_slow_max with 11537 clock sinks.
Via Selection for Estimated Routes (rule default):
--------------------------------------------------------------
Layer Via Cell Res. Cap. RC Top of Stack
Range (Ohm) (fF) (fs) Only
--------------------------------------------------------------
M1-M2 VIA12_1C_H 8.860 0.010 0.089 false
M2-M3 VIA23_1C_V 8.860 0.009 0.076 false
M3-M4 VIA34_1C_H 8.860 0.009 0.076 false
M4-M5 VIA45_1C_H 8.860 0.009 0.076 false
M5-M6 VIA5_0_VH 8.860 0.010 0.091 false
M6-M7 VIA6_0_HV 8.860 0.070 0.621 false
M7-M8 VIA7_0_VH 8.860 0.070 0.621 false
M8-M9 VIA8_0_VH 0.376 0.127 0.048 false
--------------------------------------------------------------
No ideal nets found in the clock tree

Validating CTS configuration done. (took cpu=0:00:05.8 real=0:00:05.8)
…

3. Cluster CTS
…
Synthesizing clock trees...
Preparing To Balance...
…
Summary of the merge of duplicate siblings
----------------------------------------------------------
Description Number of occurrences
----------------------------------------------------------
Total clock gates 36
Globally unique enables 34
Potentially mergeable clock gates 2
Actually merged clock gates 0
----------------------------------------------------------
-----------------------------------------------------
Description Number of occurrences
-----------------------------------------------------
Total clock logics 2
Actually merged clock logics 0
-----------------------------------------------------
--------------------------------------------------------
Cannot merge reason Number of occurrences
--------------------------------------------------------
ClockGateMergingDisabledOnTree 2
ClockLogicMergingDisabledOnTree 2
--------------------------------------------------------
…
Preparing To Balance done. (took cpu=0:00:00.9 real=0:00:00.6)

3. Cluster CTS
CCOpt::Phase::Clustering...
Stage::DRV Fixing...
Clustering...
Clock DAG stats before clustering:
cell counts : b=0, i=0, icg=36, nicg=0, l=2, total=38
cell areas : b=0.000um^2, i=0.000um^2, icg=541.728um^2, nicg=0.000um^2, l=11.628um^2, total=553.356um^2
Clock DAG library cell distribution before clustering {count}:
ICGs: TLATNTSCAX20: 36
Logics: MX2X8: 2
Computing max distances from locked parents...
Computing distance_from_locked_parent_restrictions for 0 nodes driven by 0 locked parents
Computing max distances from locked parents done.
Clustering clock_tree test_clk...
…
Clustering clock_tree test_clk done.
Clustering clock_tree my_clk...
Clustering clock_tree div_clk...
Clustering clock_tree div_clk done.
Clustering clock_tree my_clk done.
Clock DAG stats after bottom-up phase:
Clock DAG library cell distribution after bottom-up phase {count}:
Bufs: CLKBUFX20: 97 CLKBUFX16: 42 CLKBUFX12: 6 CLKBUFX8: 2
ICGs: TLATNTSCAX20: 8 TLATNTSCAX16: 1 TLATNTSCAX12: 1 TLATNTSCAX8: 2 TLATNTSCAX6: 6 TLATNTSCAX4: 1 TLATNTSCAX3: 3 TLATNTSCAX2: 14
Logics: MX2X8: 2
Legalizing clock trees...
Resynthesising clock tree into netlist...
Reset timing graph...
Reset timing graph done.
Resynthesising clock tree into netlist done.
Leaving CCOpt scope - RefinePlacement...
*** Starting refinePlace (0:01:01 mem=1275.8M) ***
…
Runtime: CPU: 0:00:01.6 REAL: 0:00:01.0 MEM: 1275.8MB
*** Finished refinePlace (0:01:03 mem=1275.8M) ***
Leaving CCOpt scope - RefinePlacement done. (took cpu=0:00:02.6 real=0:00:02.1)

3. Cluster CTS
…
Post-Clustering Statistics Report
=================================
Fanout Statistics:
=================================
Fanout Statistics:
-----------------------------------------------------------------------------------------------------------
Net Type Count Mean Min. Max. Std. Dev. Fanout
Fanout Fanout Fanout Fanout Distribution
-----------------------------------------------------------------------------------------------------------
Trunk 34 5.618 1 22 4.736 {25 <= 8.400, 8 <= 16.800, 1 <= 25.200}
Leaf 156 73.955 1 100 35.453 {36 <= 39.600, 21 <= 79.200, 99 <= 118.800}
-----------------------------------------------------------------------------------------------------------
Clustering Failure Statistics:
-------------------------------------------------------------
Net Type Clusters Clusters Capacitance Transition
Tried Failed Failures Failures
-------------------------------------------------------------
Trunk 58 8 5 8
Leaf 1141 53 18 53
-------------------------------------------------------------
…

3. Cluster CTS
CCOpt::Phase::Clustering done. (took cpu=0:01:44 real=0:01:43)

CCOpt::Phase::Implementation...
Legalizer releasing space for clock trees...
…
Routing unrouted datapath nets connected to clock instances...
Routed 522 unrouted datapath nets connected to clock instances
Routing unrouted datapath nets connected to clock instances done.
Leaving CCOpt scope...
Extraction called for design 'leon' of instances=35919 and nets=53680 using extraction engine 'preRoute' .
...
Clock DAG stats after routing clock trees:
…
skew_group my_clk/functional_func_slow_max: insertion delay [min=0.904, max=1.117, avg=1.060, sd=0.068], skew [0.212 vs 0.200*, 93% {0.912, 1.112}]
(wid=0.065 ws=0.044) (gid=1.065 gs=0.197)
skew_group test_clk/functional_func_slow_max: insertion delay [min=0.662, max=0.865, avg=0.817, sd=0.052], skew [0.203 vs 0.200*, 100% {0.666,
0.865}] (wid=0.075 ws=0.047) (gid=0.803 gs=0.197)
Clock network insertion delays are now [0.662ns, 1.117ns] average 1.060ns std.dev 0.068ns
…
CCOpt::Phase::Implementation done. (took cpu=0:00:07.6 real=0:00:07.6)
Tidy Up And Update Timing...
Connecting clock gate test enables...
Connecting clock gate test enables done.
Innovus updating I/O latencies
…
Setting all clocks to propagated mode.
AAE_INFO: 1 threads acquired from CTE.
Calculate early delays in OCV mode...
Calculate late delays in OCV mode...
…
End delay calculation. (MEM=1394.54 CPU=0:00:04.6 REAL=0:00:04.0)

4. Trial CTS
 Cluster (DRV buffering), virtual delay balance, switch to propagated clocks

 Useful to debug latency meeting MMMC skew constraints
 Permits rapid evaluation and debugging of CTS constraints
 Please run “innovus –log ./LOGS/runTrial.log –init ./SCRIPTS/runTrial.tcl”
 innovus> set_ccopt_property balance_mode trial

 innovus> ccopt_design –cts
 innovus> saveDesign ./DBS/postcts.trial.enc
 innovus> ctd_win

4. Trial CTS
 restore ./DBS/postcts.trial.enc
 On GUI, please select Clock->CCOpt Clock Tree Debugger…
CGIC_INST/CK (TLATNTSCAX6)
0.0153ns
clk_out_mux/A (MX2X4)
0.2748ns
Cell type: Mux
mcore0/a0/CTS_ccd_BUF_div_clk_G0_L2_1/A (CLKBUFX20)
CTS_ccl_BUF_CLOCK_NODE_UID_A34477/A
(CLKBUFX12) 0.57515ns
0.9743ns Cell type: Buffer
Cell type: Buffer

mcore0/a0/g1626/B
(NOR2BX4)
0.67495ns

4. Trial CTS
 Virtual Delay ( ) is shown
Virtua
l
delay

4. Trial CTS
 Virtual Balancing
clk scan_clk clk scan_clk
G
G 2
2
0 1 0 1 0 1
Trial CTS 0 1 clk_div_out_mux

G
G G
G G G
G
G G
G
G G
G G
G ICG cell Virtual delay

Buffer named *ccl*
Buffer named
Arrival to the sink at 1.1148ns Arrival to the sink at 1.07725
*ccd*

Clock Tree Cells’ Names
• Naming rule: CTS_<a>_<b>_<c>_<d>_<e>_<f>

• <a>: CCOpt’s internal stage. ccl or cwb or ccg …
• <b>: cell type. BUF or INV
• <c>: clock tree name
• <d>: Level of Clock Gating cells. G0 or G1 or G2 …
• <e>: Level of logic gates. L1 or L2 or …
• <f>: Number of cells with same levels. 1 or 2 or …
• Example
• CTS_ccl_BUF_my_clk_G1_L5_9
create_ccopt_clock_tree -name my_clk -source clk -no_skew_group

What is the naming convention used for cells inserted by Native CCOpt ?
https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000uvJTEAY&pageName=ArticleContent&sq=005d0000001T44zAAC_20171811598

What is the naming convention used for cells inserted by Native CCOpt ?

Example
+-----------------------------------------
| Instance
|
|-----------------------------------------
Level of Clock Gating Cells
Existing Cells | clk_I_CLOCK_BUF
| CTS_ccl_BUF_clk_G0_L2_1
Existing Cells | igp_ICG_CELL_0_U0
| CTS_cdb_BUF_clk_G1_L10_7
| CTS_cfo_BUF_clk_G1_L12_60
| CTS_cdb_BUF_clk_G1_L14_287
Existing Cells | cp_reg_ff_ | CK ^ -> Q ^
Level of Logic Gate Cells

4. Trial CTS
Runtime Summary:
================
--------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------
136.63 100.00 136.63 0
136.63 100.00 136.08 1 Runtime
0.45 0.33 0.00 1 Leaving CCOpt scope - CheckPlace
4.08 2.99 0.00 1 Leaving CCOpt scope - optDesignGlobalRouteStep
40.52 29.66 34.61 1 Stage::DRV Fixing
29.81 21.82 2.07 1 Clustering
3.97 2.91 0.00 1 Adding trial balancing virtual delays
11.86 8.68 0.00 1 Tidy Up And Update Timing
--------------------------------------------------------------------------------------------------------

4. Trial CTS
 ./LOGS/runTrial.log
<CMD> ccopt_design –cts

…
Updating netlist done.
Adding trial balancing virtual delays...
Resolving skew group constraints...
Solving LP: 2 skew groups; 11 fragments, 11 fraglets and 10 vertices; 87 variables and 240 constraints; tolerance 1
Resolving skew group constraints done.
Inserting virtual delay into clock tree...
Inserting virtual delay into clock tree done.
Clock DAG stats after 'Adding trial balancing virtual delays':
cell capacitance : b=0.484pF, i=0.000pF, icg=0.022pF, nicg=0.000pF, l=0.003pF, total=0.509pF
sink capacitance : count=11537, total=7.196pF, avg=0.001pF, sd=0.003pF, min=0.001pF, max=0.150pF
wire capacitance : top=0.000pF, trunk=1.060pF, leaf=7.398pF, total=8.458pF
wire lengths : top=0.000um, trunk=10796.184um, leaf=61727.762um, total=72523.946um
Clock DAG net violations after 'Adding trial balancing virtual delays':
Transition : {count=6, worst=[0.003ns, 0.003ns, 0.003ns, 0.002ns, 0.002ns, 0.002ns]} avg=0.002ns sd=0.000ns sum=0.014ns
Clock DAG primary half-corner transition distribution after 'Adding trial balancing virtual delays':
Trunk : target=0.150ns count=32 avg=0.078ns sd=0.027ns min=0.000ns max=0.137ns {1 <= 0.030ns, 5 <= 0.060ns, 16 <= 0.090ns, 8 <=
0.120ns, 2 <= 0.150ns}
Leaf : target=0.150ns count=156 avg=0.123ns sd=0.015ns min=0.043ns max=0.153ns {1 <= 0.060ns, 5 <= 0.090ns, 49 <= 0.120ns, 95
<= 0.150ns, 6 > 0.150ns}

4. Trial CTS
Clock DAG library cell distribution after 'Adding trial balancing virtual delays' {count}:
Bufs: CLKBUFX20: 99 CLKBUFX16: 39 CLKBUFX12: 6 CLKBUFX8: 2
ICGs: TLATNTSCAX20: 3 TLATNTSCAX16: 2 TLATNTSCAX12: 1 TLATNTSCAX8: 3 TLATNTSCAX6: 8 TLATNTSCAX4: 2
TLATNTSCAX3: 3 TLATNTSCAX2: 14
Logics: MX2X8: 1 MX2X4: 1
Primary reporting skew group after 'Adding trial balancing virtual delays':
skew_group my_clk/functional_func_slow_max: insertion delay [min=1.076, max=1.117, avg=1.110, sd=0.015], skew [0.040 vs 0.200,
100% {1.076, 1.117}] (wid=0.065 ws=0.044) (gid=1.085 gs=0.056)
Skew group summary after 'Adding trial balancing virtual delays':
skew_group my_clk/functional_func_slow_max: insertion delay [min=1.076, max=1.117, avg=1.110, sd=0.015], skew [0.040 vs 0.200,
100% {1.076, 1.117}] (wid=0.065 ws=0.044) (gid=1.085 gs=0.056)
skew_group test_clk/functional_func_slow_max: insertion delay [min=0.865, max=0.865, avg=0.865, sd=0.000], skew [0.000 vs 0.200,
100% {0.865, 0.865}] (wid=0.075 ws=0.047) (gid=0.837 gs=0.047)
Clock network insertion delays are now [0.865ns, 1.117ns] average 1.110ns std.dev 0.015ns
Legalizer calls during this step: 0 succeeded with DRC/Color checks: 0 succeeded without DRC/Color checks: 0
Adding trial balancing virtual delays done. (took cpu=0:00:03.9 real=0:00:04.0)
…

5. CCOpt
 Cluster (DRV buffering), virtual delay balance, switch to propagated clocks

 Concurrent clock and datapath optimization
 Slack-based CTS and Skew balancing
 Please run “innovus –log ./LOGS/runCCOpt.log –init ./SCRIPTS/runCCOpt.tcl”
 innovus> set_ccopt_property balance_mode full

 innovus> ccopt_design
 innovus> saveDesign ./DBS/postcts.enc
 innovus> ctd_win

5. CCOpt
 CTD
CGIC_INST/CK (TLATNTSCAX6)
0.0138ns
clk_out_mux/A (MX2X1)
mcore0/a0/CTS_ccd_BUF_div_clk_G0_L3_2/A (CLKBUFX8)
0.265ns
0.6977ns
Cell type: Mux
Cell type: Buffer
mcore0/a0/g1626/B
(NOR2BX4)
0.7976ns

5. CCOpt
 restore ./DBS/postcts.enc
proc0/cmem0/itags0/u0/CTS_csf_BUF_my_clk_G1_L8_3/A (CLKBUFX20)
1.0896ns
Cell type: Buffer
CTS_cdb_BUF_div_clk_G0_L2_1/A (CLKBUFX8)
0.5811ns
Cell type: Buffer
mcore0/ioport0/r_reg_pin1_14/CTS_csk_BUF_div_clk_G0_L6_2/A (CLKBUFX20)
1.1318ns
Cell type: Buffer

5. CCOpt
Runtime Summary:
================
--------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------
691.98 100.00 691.98 0
691.98 100.00 691.86 1 Runtime
0.85 0.12 0.00 1 Leaving CCOpt scope - CheckPlace
688.59 99.51 431.12 1 External::optDesign
43.34 6.26 36.57 1 Stage::DRV Fixing
31.95 4.62 2.16 1 Clustering

5. CCOpt
Runtime Summary:
================
--------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------
…
57.47 8.31 56.49 1 Stage::Balancing
18.10 2.62 0.00 1 Reducing clock tree power 1
15.86 2.29 14.02 1 Approximately balancing fragments step
14.02 2.03 0.00 1 Approximately balancing fragments bottom up
9.18 1.33 0.00 1 Improving fragments clock skew
1.32 0.19 0.00 1 Approximately balancing step
0.68 0.10 0.00 1 Fixing clock tree overload
5.79 0.84 0.00 1 Approximately balancing paths
62.36 9.01 62.36 1 Stage::Polishing
32.00 4.62 0.00 1 Improving clock skew
11.79 1.70 0.00 1 Reducing total underdelay
0.83 0.12 0.00 1 Improving insertion delay
100.85 14.57 84.10 1 Stage::Routing
2.74 0.40 0.00 1 Leaving CCOpt scope - ClockRefiner
80.06 11.57 0.00 1 Leaving CCOpt scope - NanoRouter
54.37 7.86 29.78 1 Stage::PostConditioning
3.39 0.49 0.00 1 Fixing DRVs
7.35 1.06 0.00 1 Buffering to fix DRVs
2.74 0.40 2.73 1 Refining placement
2.73 0.39 0.00 1 Leaving CCOpt scope - ClockRefiner
--------------------------------------------------------------------------------------------------------

6. Worst chain report after ccopt_design
 innovus> source ./SCRIPTS/runCCOpt.tcl

 innovus> report_ccopt_worst_chain

report_ccopt_worst_chain after ccopt_design
x clk_en
| slack 2.658ns .../clk_en -> .../E (distance: 304.085um)
| delays=(launch: 0.000ns, datapath: 0.099ns, capture: -1.143ns, adjust: 3.900ns) This chain is one kind of Input
| launch no clock to Loop chain
Input
| capture clock my_clk in analysis view func_slow_max
| path group default
g CGIC_INST
| .../CK @+0.015ns constraint=(-0.000ns,+0.000ns) chosen=(-0.097ns,+0.000ns) …
| location=(503.100,402.515) slew=(launch: 0.045ns, capture: 0.032ns) | slack 0.382ns .../Q -> .../D (distance: 235.890um)
| clock gate above | delays=(launch: 0.050ns, datapath: 3.884ns, capture: -0.008ns, adjust: 3.958ns)
o proc0/cmem0/dtags0/u0/id0 | launch clock my_clk in analysis view func_slow_max
| .../CK2 @+0.716ns constraint=(-0.150ns,+0.579ns) chosen=(-0.192ns,+0.035ns) | capture clock test_clk in analysis view func_slow_max
| location=(723.635,162.785) slew=(launch: 0.132ns, capture: 0.132ns) | path group reg2reg
| slack 0.136ns .../Q1[23] -> .../D (distance: 635.040um) ,-o proc0/iu0/ex_reg_rs1data_31/DFF
| delays=(launch: 0.023ns, datapath: 3.759ns, capture: -0.040ns, adjust: 3.958ns) | | .../CK @+0.716ns constraint=(-0.096ns,+0.579ns) chosen=(-0.015ns,+0.311ns)
| launch clock my_clk in analysis view func_slow_max | | location=(497.900,393.395) slew=(launch: 0.127ns, capture: 0.127ns)
| capture clock test_clk in analysis view func_slow_max | | slack 0.587ns .../Q -> .../D (distance: 297.830um)
| path group reg2reg | | delays=(launch: 0.050ns, datapath: 3.855ns, capture: -0.009ns, adjust: 3.958ns)
o proc0/c0/dcache0/r_reg_req/DFF | | launch clock my_clk in analysis view func_slow_max
| .../CK @+0.716ns constraint=(-0.175ns,+0.579ns) chosen=(-0.079ns,+0.000ns) | | capture clock test_clk in analysis view func_slow_max
| location=(383.700,328.795) slew=(launch: 0.136ns, capture: 0.136ns) | | path group reg2reg
| slack 0.854ns .../Q -> .../D (distance: 368.320um) | o proc0/iu0/ex_reg_rs1data_23/DFF
| delays=(launch: 0.018ns, datapath: 3.127ns, capture: -0.101ns, adjust: 4.099ns) | | .../CK @+0.716ns constraint=(-0.096ns,+0.579ns) chosen=(-0.039ns,+0.150ns)
| launch clock my_clk in analysis view func_slow_max | | location=(511.900,402.325) slew=(launch: 0.127ns, capture: 0.127ns)
| capture clock test_clk in analysis view func_slow_max | | slack 0.094ns .../Q -> .../D (distance: 231.580um)
| path group reg2reg Loop | | delays=(launch: 0.049ns, datapath: 3.885ns, capture: -0.008ns, adjust: 3.958ns)
o mcore0/ahb0/r_reg_hslave_1/DFF chain | | launch clock my_clk in analysis view func_slow_max
… | | capture clock test_clk in analysis view func_slow_max
| | path group reg2reg
`-o proc0/iu0/ex_reg_rs1data_31/DFF

report_ccopt_worst_chain (1/5)
x clk_en
| slack 2.658ns .../clk_en -> .../E (distance: 304.085um)
| delays=(launch: 0.000ns, datapath: 0.099ns, capture: -1.143ns, adjust: 3.900ns)
| launch no clock
| path group default
g CGIC_INST
| .../CK @+0.015ns constraint=(-0.000ns,+0.000ns) chosen=(-0.097ns,+0.000ns)
| location=(503.100,402.515) slew=(launch: 0.045ns, capture: 0.032ns)
| clock gate above
symbol <port name or instance name>
The symbol is “x”, “g”, or “o”.

• “x” indicates a pin that can’t be adjusted because it is outside the defined clock trees. This is commonly an IO pin.
• “g” indicates a clock gate.
• “o” indicates a clock tree sink that can be skewed.

o proc0/cmem0/dtags0/u0/id0
| .../CK2 @+0.716ns constraint=(-0.150ns,+0.579ns) chosen=(-0.192ns,+0.035ns)
| slack 0.136ns .../Q1[23] -> .../D (distance: 635.040um)
| launch clock my_clk in analysis view func_slow_max
| capture clock test_clk in analysis view func_slow_max
| path group reg2reg
o proc0/c0/dcache0/r_reg_req/DFF <-node
| .../CK @+0.716ns constraint=(-0.175ns,+0.579ns) chosen=(-0.079ns,+0.000ns) <-window info
| location=(383.700,328.795) slew=(launch: 0.136ns, capture: 0.136ns) <-sink info
| slack 0.854ns .../Q -> .../D (distance: 368.320um)
| launch clock my_clk in analysis view func_slow_max <-path info

o mcore0/ahb0/r_reg_hslave_1/DFF
Indicates that the scheduled delay to the clock tree sink mcore0/ahb0/r_reg_hslave_1/DFF/CK
is | slack The
0.513ns. 0.196ns .../Q delay
scheduled -> .../D (distance:
is the 505.685um)
insertion delay that CCOpt is aiming to implement for
this sink. The actual insertion delay of this particular clock tree sink (as reported by
report_timing and CTD) may well differ from the scheduled delay, but will hopefully be close.
@ indicates
| the parent node clock
launch of thediv_clk
fragment which hasview
in analysis the func_slow_max
sink.

Chosen Window
| The range of delays at which the sink can be put
path group reg2reg
without degrading the WNS of the design
o proc0/iu0/de_reg_inst_22/DFF
| slack 0.038ns Constraint
.../Q -> .../D (distance: 762.370um)
Window
| It is calculated0.014ns,
delays=(launch: based ondatapath:
the following physical
3.898ns, limits:
capture: -0.008ns, adjust: 3.958ns)
• User skew group constraints
| •launch clockinsertion
The auto my_clk indelay
analysis
limitview func_slow_max
• Minimum insertion delays
Why are the scheduled delays (@+0.513ns and @+0.716ns different?

o proc0/iu0/ex_reg_rs1data_1/DFF
| *WNS* 0.007ns .../Q -> .../D (distance: 297.740um)
o proc0/iu0/ex_reg_rs2data_22/DFF
| From ->
slack 0.382ns .../Q CTE.../D
(report_timing)
(distance: 235.890um)

,-o proc0/iu0/ex_reg_rs1data_31/DFF
| | .../CK @+0.716ns constraint=(-0.096ns,+0.579ns) chosen=(-0.015ns,+0.311ns)
| | location=(497.900,393.395) slew=(launch: 0.127ns, capture: 0.127ns)
| | slack 0.587ns .../Q -> .../D (distance: 297.830um)
| | delays=(launch: 0.050ns, datapath: 3.855ns, capture: -0.009ns, adjust: 3.958ns)
| | launch clock my_clk in analysis view func_slow_max
| | capture clock test_clk in analysis view func_slow_max
| o proc0/iu0/ex_reg_rs1data_23/DFF
| | .../CK @+0.716ns constraint=(-0.096ns,+0.579ns) chosen=(-0.039ns,+0.150ns)
| | location=(511.900,402.325) slew=(launch: 0.127ns, capture: 0.127ns)
| | slack 0.094ns .../Q -> .../D (distance: 231.580um)
| | delays=(launch: 0.049ns, datapath: 3.885ns, capture: -0.008ns, adjust: 3.958ns)
| | Loop launch clock my_clk in analysis view func_slow_max
chain
| | capture clock test_clk in analysis view func_slow_max
`-o proc0/iu0/ex_reg_rs1data_31/DFF

x clk_en
Slack= capture + adjust – (launch + datapath)

= -1.144 + 3.9 – (0 + 0.098) = 2.658ns
x clk_en datapath= data path delay + setup
| slack 2.658ns .../clk_en -> .../E (distance: 304.085um) = 0.005 + 0.093 = 0.098ns
innovus> report_timing –from clk_en –path_type full_clock -net
| launch no clock Path 1: MET Clock Gating Setup Check with Pin CGIC_INST/CK
Endpoint: CGIC_INST/E (^) checked with leading edge of 'my_clk'
Beginpoint: clk_en (^) triggered by leading edge of '@'
Path Groups: {clock_gating_default}
| path group default Analysis View: func_slow_max
Other End Arrival Time -1.143
- Clock Gating Setup 0.093
g CGIC_INST + Phase Shift 4.000
+ CPPR Adjustment 0.000 adjust = 4.0+0.0-0.1=3.900ns
| .../CK @+0.015ns constraint=(-0.000ns,+0.000ns) -chosen=(-0.097ns,+0.000ns)
Uncertainty 0.100
= Required Time 2.663
- Arrival Time 0.005
= Slack Time 2.658
CGIC_INST Clock Rise Edge 0.000
5ps + Input Delay 0.000
clk_en E GCK = Beginpoint Arrival Time 0.000
datapath 93ps Timing Path:
launch ICG +----------------------------------------------------------------------------------+
^
CK
| Instance | Arc | Net | Cell | Slew | Delay | Arrival | Required |
| | | | | | | Time | Time |
Network latency |-----------+----------+--------+-------------+-------+-------+---------+----------|
11ps
| | clk_en ^ | clk_en | | 0.004 | | 0.000 | 2.658 |
| CGIC_INST | | clk_en | TLATNTSCAX6 | 0.014 | 0.005 | 0.005 | 2.663 |
clk +----------------------------------------------------------------------------------+
Clock Rise Edge 0.000
my_clk (4ns) + Source Insertion Delay -1.155
-1.155ns = Beginpoint Arrival Time -1.155
Source latency Other End Path:
+----------------------------------------------------------------------------+
Capture= source latency + network latency | Instance | Arc | Net | Cell | Slew | Delay | Arrival | Required |
| | | | | | | Time | Time |
= -1.155+0.011 |-----------+-------+-----+-------------+-------+-------+---------+----------|
| | clk ^ | clk | | 0.004 | | -1.155 | -3.813 |
= -1.144 | CGIC_INST | | clk | TLATNTSCAX6 | 0.032 | 0.011 | -1.143 | -3.801 |
+----------------------------------------------------------------------------+

g CGIC_INST
g CGIC_INST
| clock gate above
innovus> get_property [get_pins CGIC_INST/CK] slew_max_rise

0.045
innovus> get_property [get_pins CGIC_INST/CK] slew_min_rise
0.032
innovus> get_property [get_pins CGIC_INST/CK] x_coordinate
503.100
innovus> get_property [get_pins CGIC_INST/CK] y_coordinate
402.515

o proc0/cmem0/dtag0/u0/id0
o proc0/cmem0/dtags0/u0/id0
| .../CK2 @+0.716ns constraint=(-0.150ns,+0.579ns) chosen=(-0.192ns,+0.035ns)
| slack 0.136ns .../Q1[23] -> .../D (distance: 635.040um)
| path group reg2reg * Scheduled latency from clk_out_mux/Y
to proc0/cmem0/dtags0/u0/id0/CK2
o proc0/c0/dcache0/r_reg_req/DFF
proc0/cmem0/dtag0/u0/id0
clk_out_mux A1[2] Q1[23] proc0/c0/dcache0/r_reg_req/DFF

CGIC_INST
D Q
Slack=0.136ns
clk_en E GCK A
ICG Y CK2 CK
^
^
CK
B
clk
my_clk (4ns)

Circuit Diagram of the worst chain before CTS
proc0/cmem0/dtags0/u0/id0
A1[*] Q1[23]
clk_out_mux
^
CGIC_INST CK2
clk_en E GCK A
ICG Y proc0/c0/dcache0/r_reg_req/DFF
B
clk
^
CK D Q
MX2X4
^
TLATNTSCAX2 CK
my_clk (4ns)
clk_div_out_mux mcore0/ahb0/r_reg_inst_22/DFF
clk_div_reg D Q
D Q A
^
Y CK
^
CK B
div_clk proc0/iu0/de_reg_inst_22/DFF
(8ns) MX2X4
proc0/iu0/RC_CG_HIER_INST27/RC_CG_INST D Q
^
E GCK CK
ICG
proc0/iu0/ex_reg_rs1data_1/DFF
^
CK
D Q
TLATNTSCAX2
^
CK
^
CK
E GCK
ICG proc0/iu0/ex_reg_rs1data_31/DFF
^
CK
D Q
TLATNTSCAX2
^
CK
Fragment 1 D Q
^
CK
Fragment 2

Circuit Diagram of the worst chain after cluster CTS
A1[*] Q1[23]
@+0.472ns
clk_out_mux
^
CGIC_INST CK2
clk_en E GCK A
B
clk
^
CK D Q
CLKBUFX20
MX2X4 @+0.45ns
^
TLATNTSCAX6 CK
my_clk (4ns)
clk_div_reg D Q
A @+0.35ns
^
D Q Y CK
B
^
CK
div_clk
CLKBUFX20 proc0/iu0/de_reg_inst_22/DFF
MX2X8
(8ns) proc0/iu0/RC_CG_HIER_INST27/RC_CG_INST D Q
@+0.494ns
^
E GCK CK
ICG
^
CK
D Q
TLATNTSCAX6 @+0.538ns
^
CK
proc0/iu0/RC_CG_HIER_INST28/RC_CG_INST
D Q
@+0.534ns
^
E GCK CK
ICG
^
CK
D Q
TLATNTSCAX2
@+0.534ns
^
CK
Fragment 1 D Q
@+0.534ns
^
CK
Fragment 2

Circuit Diagram of the worst chain after trial CTS
A1[*] Q1[23]
@+0.645ns
^
CGIC_INST clk_out_mux CK2
clk_en E GCK A
B
clk
^
CK D Q
CLKBUFX20
MX2X4 @+0.645ns
^
TLATNTSCAX6 CK
my_clk (4ns)
clk_div_reg D Q
D Q A @+0.503ns
^
Y CK
^
CK B
div_clk
MX2X8
(8ns) D Q
@+0.646ns
^
E GCK CK
ICG
^
CK
D Q
^
CK
@+0.646ns
^
E GCK CK
^
CK
D Q
TLATNTSCAX2
@+0.534ns
^
CK
Fragment 1 D Q
@+0.534ns
^
CK
Fragment 2
Virtual Scheduling

Fragment Scheduling during full CTS
A1[*] Q1[23]
@+0.645ns @+0.716ns constraint=(-0.150ns,+0.579ns)
^
chosen=(-0.192ns,+0.035ns)
clk_en E GCK A
B
clk
^
CK D Q
CLKBUFX20
MX2X4 @+0.645ns
^
TLATNTSCAX6 CK @+0.716ns constraint=(-0.175ns,+0.579ns)
chosen=(-0.079ns,+0.000ns)
my_clk (4ns)
clk_div_reg D Q
D Q A @+0.503ns @+0.513ns constraint=(-0.164ns,+0.661ns)
^
Y CK
chosen=(-0.173ns,+0.038ns)
^
CK B
div_clk
MX2X8
(8ns) D Q
^
E GCK CK
chosen=(-0.149ns,+0.002ns)
ICG
^
CK
D Q
@+0.716ns constraint=(-0.091ns,+0.579ns)
^
CK
chosen=(-0.016ns,+0.020ns)
@+0.646ns
@+0.716ns constraint=(-0.096ns,+0.579ns)
^
E GCK CK
chosen=(-0.020ns,+0.221ns)
^
CK
D Q
TLATNTSCAX2
^
CK
chosen=(-0.015ns,+0.311ns)
Fragment 1 D Q
@+0.534ns
^
CK
Fragment 2 Virtual Scheduling @+0.716ns constraint=(-0.096ns,+0.579ns)
chosen=(-0.039ns,+0.150ns)

Circuit Diagram of the worst chain after CCOpt
A1[*] Q1[23]
@+0.704ns
^
CLKBUFX20
clk_en E GCK A
B
clk
^
CK CLKBUFX12 CLKBUFX8 CLKBUFX12 D Q

MX2X1 @+0.699ns
^
TLATNTSCAX6 CK
my_clk (4ns) CLKBUFX12
clk_div_reg D Q
D Q A @+0.551ns
^
Y CK
^
CK B
div_clk
MX2X8
(8ns) D Q
@+0.695ns
^
E GCK CK
ICG
^
CK
D Q
^
CK
@+0.731ns
^
E GCK CK
ICG
^
CK
D Q
TLATNTSCAX16
^
@+0.731ns CK
Fragment 1 D Q
^
CK
Fragment 2 @+0.73ns

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks
are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Ccopt Rak For Beginners: Product - Innovus 16.20 April 2017

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Ccopt Rak For Beginners: Product - Innovus 16.20 April 2017

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CCOpt RAK for Beginners

Product – Innovus 16.20

© 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

2 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

3 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

4 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

5 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

update_constraint_mode -name functional_func_slow_max -sdc_files [list DATA/leon_func_slow_max_postcts.sdc]

create_route_type -name leaf -top_preferred_layer 5 -bottom_preferred_layer 4 -preferred_routing_layer_effort high

set_ccopt_property primary_delay_corner slow_max

6 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

# Command: create_ccopt_clock_tree_spec -file ccopt.spec

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# Command: create_ccopt_clock_tree_spec -file ccopt.spec

innovus> report_property [get_pins mcore0/a0/g1626/B] no_sdc_clock means the SDC clock is

8 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

innovus> all_fanin -to mcore0/a0/g1626/B

innovus> report_fanin -to mcore0/a0/g1626/B

9 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

innovus> report_fanout -from mcore0/a0/g1626/B

10 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

• Fanin logics at the ignore pin mcore0/a0/g1626/B

11 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

• Ignore pin is a part of Structural Clock Network Elements

12 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

Structural Elements – Identifying ignore pin

Ex. modify_ccopt_skew_group -skew_group div_clk/functional_func_slow_max \

Ignore pin= Do not balance. Minimize ID

13 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

set_ccopt_property source_max_capacitance -clock_tree test_clk 1.000

# Clocks present at pin clk

set_ccopt_property source_max_capacitance -clock_tree my_clk 1.000

# Clocks present at pin clk_div_reg/Q

14 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

# Skew group to balance non generated clock:my_clk in timing_config:functional_func_slow_max (sdc

# Skew group to balance non generated clock:test_clk in timing_config:functional_func_slow_max (sdc

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16 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

17 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

 To analyze clock structures and check any missing or wrong clocks

 Csh% innovus –log ./LOGS/runInit.log –init ./SCRIPT/runInit.tcl

innovus> source ./DATA/prects.enc;

18 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

 On clock tree debugger

3 clock roots (2 master clocks, 1 generated clock)

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 Clock MUXs (clk_out_mux, clk_div_out_mux)

clk_out_mux/A (MX2X4) clk_out_mux/B (MX2X4)

clk_div_out_mux/A (MX2X4) clk_div_out_mux/B (MX2X4)

20 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

21 © 2017 Cadence Design Systems, Inc. All Rights Reserved Worldwide.

 Where is the ignore pin mcore0/a0/g1626/B?

 Click the icon Find

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 Fast DRV cleaning of whole clock network

 innovus> set_ccopt_property balance_mode cluster

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clk scan_clk clk scan_clk

Buffer named *ccl*

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Ignore pin: mcore0/a0/g1626/B

constraints Cell type: Buffer

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Buffer named ccl