Save trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.vturesource.com usN” | ong; ‘Third Semester B.E. Degree Examinat Logic Design in, June / July 0: iene: 3 hee Max. Note: Answer any FIVE full questions, choosing atteast wo frgiiPeacWRGA. 1a. What are universal gates? Implement the following function using univeti gate) only (A+B twrks) b. Simplify the following using K — mapP(A.B,C.D)= ATIC + AD RD + Cg aC + AB (os Maris) ©. What are the drawbacks of Kemap? Simplify the folk pression using Quine ~ Me Clusky Method. F(A, B,C,D) = 2(1,2,8,9,10,12,13,14). (40 Marks) 2a Show that using a 3 — to ~ 8 decoder and multi ~input O} flowing Boolean expressions ean be realized. F,(A.B,C)= Em(0,4,6), *3(A,B,C) = Em(0,5), Fy ) = SA(1,23,7). (04 marks) b. Design Decimal - to ~ BCD encoder? (os marks) ©. What are the different types of PLD’s and impleme; segment decoder usin PLA? ‘08 Maris) d. Write a verilog code for 4: 1 multiplexer using case st {04 Marks) “15 in 2°s complement. 3 a. i) Perform 8 ~ bit addition of the decimal num! 8 and + 65 in 2's complement (06 Marks) b._ i) Find the binary addition of (7510),0 andl bit numbers, ii) Find the binary subtraction of (200),o 1 sing 8— bit numbers. (10 Marks) « the binary Adder ~ subtractes example. (04 Marks) 4a Schmitt trigger? Explain S sfer characteristic. co marks) >. Explain the different types of flip yvith their truth table. Also explain the race ~ around condition in a flip flop. ¢. Differentiate between combi 3d sequential circuit (10 Marks) 5a. a in detail and give its timing diagram. (10 Marks) b y oa fr using JK flip flop. (10 Maris) 6 a Explain Moore model thesis table and also obtain the cigcuit diagram for Moore model. <10 Marks) b. Desig an asynebrono ial logic circuit for state warsition diagram shown in Fig. 60), ee Fig. Q 6(b) a0 Marks) 7 ie laddez? Explain the binary ladder with a digital input of 1000. (10 Marks) = bit simultaneous A/D converter. 10 Marks) 8 a circuit diagram, explain the operation of the CMOS NAND gate. (10 Maris) EDIBIe 2 2— input NAND gate TTL with Totem — pole output witha neat diagram, | ‘a Man BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Vturesource Go Green initiative