Available online at www.sclencedirect. com SciVerse ScienceDirect Procedia Engineering ELSEVIER Proceila Engineering 38 (2012) 610 ~ 646 ‘wawickeviercomfocate/procedia International Conference on Modeling, Optimization and Computing (ICMOC 2012) Design and Analysis of Linear Feedback Shift Register based on Various Tap connections °s Saravanan, "M.Lavanya, °R.Vijay Sai, “Ravi Kumar, School of Computing (SoC), SASTRA University, Mhanlavar, Tanilnadu ~ 613 401, INDIA “MTech VISI Design, SoC, SASTRA Universi, Thanjavur, Tamilnadu ~ 613 401, INDIA Abstract Systems-on-Chip (SoC) based design rapidly involves various challenges like huge test data volume, test transition time, area overhead and test data storage. This huge test data volume and its transition time is becoming one of the major problems in association with SoC design testing. This paper considers Linear Feedback Shift Register (LFSR) with various tap to address the above problem. Using the advantages of LFSR in producing pseudorandom pattern, it is considered for SoC testing. This proposed approach is based on considering various taps associated with Slow LFSR and Normal LFSR modules. This proposed method is targeted to XILINX Virtex-6 FPGA. Experimental result shows significant reduction in test data volume, area and transition time. © 2012 Published by Elsevier Ltd, Selection and/or peer-review under responsibility of Noorul Islam Centre for Higher Education ope ses ander 6 BY-NCND hen Keywords: Test data volume, Transition Time, Area overhead, Liner Feedback Shift Register, and Tap 1877-7058 © 2012 Published by Elsevier Lid. Open sews under CC BY-NCND lees do:10,1016)) proeng.2012.06.079‘8 Saravanan etal / Procedia Engineering 38 1. Introduetion Present semiconductor manufacturing industries are involved in various challenges in reducing test data volume and its corresponding transition time. An LFSR [1] is a shift register that, when clocked, advances the signal through the register from one bit to the next most-significant bit. Some of the outputs are combined in exclusive-OR configuration to form a feedback mechanism. A LFSR can be formed by performing exclusive-OR on the outputs of two or more of the flip-flops together and feeding those outputs back into the input of one of the flip-flops as shown in Figure | that generates an exhaustive or pseudo-random pattern sequence of test patterns, and also is used as a response compacter. This frequently requires a sequence of 1 million or more tests to obtain high fault coverage, but the method uses very little hardware and is currently the preferred in BIST pattern generation method.'S. Sarvanan etal. / Procedia Engineering 38 (2012) 640 ~ 646 FrLour Frz_our Four cK Figure 1. Basic block diagram for Linear Feedback Shift Register LFSR is more suitable to generating pseudorandom pattern. When the outputs of the flip-flops are loaded with a seed value (anything except all 0’s, which would cause the LFSR to produce all the patterns) and when the LFSR is clocked, it will generate a pseudorandom pattern of 1s and 0°s. Note that the only signal necessary to generate the test patterns is the clock. LFSR are designed in two ways, they are Standard LFSR and Modular LFSR. The Standard LFSR is an external exclusive-OR LFSR because the feedback network of XOR gates feed externally from XO to Xn-I in that Figure 2. The Modular LFSR is an internal exclusive-OR LFSR because the feedback networks are located between adjacent flip-flops as shown in Figure 3. Proposed block of normal speed LFSR and slow speed LFSR is the extension work of [2]. Pseudorandom Testability is discussed in [3] and LFSR reseeding is shown in [4][5]. Low power test pattern generator in BIST i @-—@-< 9 re 6 AniG - Figure 2. Standard LFSR Figure 3. Modular LFSR 3. Proposed Techniques In this paper LFSR is discussed with various tap connections. Proposed technique is also associated with Dual speed configuration of LFSR design. Various internal block modules of proposed designs are Normal mode LFSR (N-LFSR), slow mode LFSR (S-LFSR), Controller module and Reseeding module. In this proposed method, test data size is considered for N-LFSR and S-LFSR as shown in the Figure 4 and Figure 5 respectively. N-LFSR is designed by NCLK and S- LFSR is designed by SCLK, which has been rationed from NCLK. The controller has been designed to coordinating the function of both N-LFSR and S-LFSR. The basic idea of designing controller is that the function of N- LFSR is followed by S-LFSR. This has been performed by counter for both LFSR that enables the transition among any one of it. Appropriate tapping is based on value of n and s, which is size of N-LFSR and S-LFSR respectively.‘8 Saravanan etal / Procedia Engineering 38 NCLK RESET Normal Speed LFSR LOAD ENN Figure 4, Normal speed LFSR SCLK RESET LOAD ENS s }—<——» s paT Slow Speed LFSR Figure S. Slow speed LFSR 3. RESEEDING Earlier, using ROM as storage element for test pattern, techniques have been developed for storing LFSR seeds that can be used to generate the test patterns. The term is also used for generating the deterministic patterns by reseeding it with computed seeds. The seeds can be computed with linear algebra, since the seeds are smaller than for an LFSR with a fixed characteristics polynomial, it may not always be possible to find a seed that will efficiently generate the required deterministic test patterns. A solution to that problem was proposed in which a multiple- polynomial LFSR is illustrated. A polynomial identifier is stored with each seed to select the characteristics polynomial that will be used for that seed as in [4]. Techniques for further reduction in storage can be achieved by using variable length seeds likewise. The reseeding techniques are studied for generating the maximum patterns of number 2"-1, where n is the size of LFSR. The predefined tapping for single LFSR provides the maximal possibilities Incase of dual speed LFSR, reseeding techniques play important role for efficient design. Let us consider the dual speed LFSR, designed by the concatenation of n-bit normal speed LFSR and s-bit slow speed LFSR. With proper tapping both LFSR generate their own maximum possibilities individually. If we verify the number of total patterns generated by dual speed LFSR of M bits, we have a lack of x pattem, where M is addition of both normal (n) and slow LFSR (s). This lack of generating the data is unavoidable, so we go for reseeding. In reseeding here we implemented the self reseeding technique where their entire required control signal is generated. This is done through implemes counter for both N-LFSR and S-LFSR which has been checked for the maximum possibilities. After getting the maximal data of both LFSR, the reseed signal for N-LFSR followed by S-LFSR is enabled, thus retrieving the balance data to be generated, Table | and Table 2 shows missed pattern retrieval from S-LFSR and N-LFSR, 3.2 CONTROLLER The design of controller is constructed through the state diagram, as initial step, get the Dual speed LFSR into Idle by making reset (SZ) signal high, after the idle state controller moves to Load state without any constraints, In that load state if load (LD) is high, then both the LFSR is loaded by its respective seed value thereafter keeping the same signal low and the controller reaching Normal LFSR to be active which is the gateway of transition loop. The transition loop has four states they are: Normal LFSR, slow LFSR, Reseed Normal and Reseed Slow. State diagram is shown in figure 6. a3'S. Sarvanan etal. / Procedia Engineering 38 (2012) 640 ~ 646 ‘Table 1. Missed pattern retrieval from S-LFSR CNTR S-LFSR N-LFSR ool 000 Sreen 100 000 inactive mode o10 000 & 101 000 oe 10 000 active mode | Ha oul 000 ‘Table 2. Missed pattern retrieval from N-LFSR CNTRL S-LFSR N-LFSR 000 001 N-LFSR iu had active mode 000 O10 & 000 101 S-LFSR 00 10 inactive mode as a 000 on The state Normal LFSR keeps the Normal speed LFSR to be active and slow speed LFSR to be inactive, which means EN_N is HIGH and EN_S is LOW. These enable signals can be controlled by counting the pattern generated for fixed slow LESR pattern, then simply COUNT_N is. less than or equal to 2"-1 where n is Normal LFSR size. If the counter reaches the limit then the controller enables the slow LFSR for single slow clock then back to previous state. This process can be done when slow LFSR reaches their own limit as COUNT_S'is less than or equal to 2°-1 where s is the size of Slow LFSR. Then the controller moves to reseeding state of normal LFSR. Here the slow LFSR has all zero’s in their register and normal LFSR generates theit maximum data, likewise the reseeding state of slow LFSR keeps all zero’s for normal LFSR register and generate all possibilities of slow speed LFSR. This transition loop never gets an end until triggering the reset (RST) ot load (LD). Figure 6. State representation of Conteller.8. Saravanan etal. Procedia Engineering 38 (2012) 640~ 686 as 4, Experimental Results There are different types of c follows, Type —I: Both the Normal speed LFSR and Slow speed LFSR are of san to makes the counter length of normal LFSR equal to the slow LFSR. Type —II: Slow LFSR having higher length than the normal LFSR with factor of k. Then the counter length of slow LFSR is also increased to n* k. Type -III: Slow LFSR having shorter length than the normal LFSR to the factor of k. Then the counter length of slow LFSR will decrease to n-k. Figure 7 represents simulation result of above said three proposed methods, -atenating normal LESR with slow LESR which is to be explained as ¢ size. The simple chai a tad Figure 7, Simulation results of proposed method 4.1 Comparison The proposed design of various tap based connection LFSR has been targeted to xe6slx4l-IL [7] (ailine virtex-6 low power device) using Xilinx ISE suite 12.1 Table 3. Area efficiency comparison of different Taps stno: ‘Area Parameter T Number of Slice Registers 2 29 2 2 Number of Slice LUTs 8 1 83 3 Number of LUTs-FF pairs B Is 2 4 Number of bonded IOBs 20 20 20 Number of BUFGs/BUFGCTRLs 2 3 aos 'S. Sarvanan etal. / Procedia Engineering 38 (2012) 640 ~ 646 Table 4. Performance comparison of different Taps Timing Parameter 7 Timing details ba Typet ‘Type-II Type H Minimum period T3.078ns 13.622n8 16.S69ns 2 Maximum Frequency 76.464MHz. 7B4lIMHz — 60.352MHz 3 Minimum input arrival time 18.272ns 18.856ns 19.488ns before clock 4 Maximum output required time —_7.20Sns 7.125ns 7.205ns after clock Table 3 shows the summary of resources occupied by the design of all three different taps. Likewise Table 4 shows the timing report about the design of all three types while targeting to the same device. From the comparison table, the type shows to be more efficient mode to design various tap connection LFSR due to the operating frequency which is reasonably increased among mode of modeling, LFSR. 5. Conclusion ‘The design of LFSR is very important for SoC based testing. This paper shows the importance of various tapping connection of LFSR by means of both area and performance, As per discussion, the three different taps are experimented with Virtex family of Xilinx devices. From the above three taps, Type-1 is, ‘more efficient in terms of performance. As for area concem, the Type-II will be good enough and then the Type-I. Finally it is concluded that the length of Slow speed LFSR should be greater than or equal to Normal speed LFSR. 6. Reference [1] Laung-Terg Wang, Cheng-Wen Wu and Xiaoging Wen “VLSI TEST PRINCIPLES AND ARCHITECTURES” July 07 2006. [2] Seongmoon Wang, and Sandeep K. Gupta “DS-LFSR: A BIST TPG for Low Switching Activity” IEEE TRANSACTIONS ON COMPUTER: AIDED DESIGN OF INTERGRATED CIRCUITS AND SYSTEMS, Vol 21, No.7, JULY 2002. [3] Fiser, P, Kubatova, H, “Pseudorandom Testability - Study of the Effect of the Generator Type”, ECT'04, 200-205, 2004 [4] Mahmut Yilmaz and Krishnendu Chakrabarty “Seed Selection in LFSR-Reseeding- Based test Compression for the Detection of Small-Delay Defects”, Design, Automation & Test in Europe Conierence & Exhibition, DATE, APRIL. 2009 [5] E.Kalligeros, X_Kavousianos, D. Bakalis and D.Nikolos, “ A new reseeding for LFSR based test pattern generation”, IEEE, 2001 [6] Youbean Kim, Myung-Hoon Yang, Yong Lee, and Sungho Kang, “A new low power test pattern Generator using a transition monitoring window based on BIST architecture”, Test Symposium, 2005 [7] wwwaxilinx.com