The document describes a two-input, one-output multiplexer (mux) module and a testbench module to test it. The mux module uses two AND gates, one OR gate, and an inverter to select either the x_in or y_in input for the m_out output depending on the value of the sel input. The testbench module instantiates the mux module and applies a stimulus of different input combinations over time to verify the mux functionality.
The document describes a two-input, one-output multiplexer (mux) module and a testbench module to test it. The mux module uses two AND gates, one OR gate, and an inverter to select either the x_in or y_in input for the m_out output depending on the value of the sel input. The testbench module instantiates the mux module and applies a stimulus of different input combinations over time to verify the mux functionality.
The document describes a two-input, one-output multiplexer (mux) module and a testbench module to test it. The mux module uses two AND gates, one OR gate, and an inverter to select either the x_in or y_in input for the m_out output depending on the value of the sel input. The testbench module instantiates the mux module and applies a stimulus of different input combinations over time to verify the mux functionality.