Memristor-assisted Background Calibration for

Analog-to-Digital Converter
Zhaoguang Si∗ , Chaohan Wang∗ , Adil Malik∗ , Shiwei Wang† , Themis Prodromakis‡ , Christos Papavassiliou∗
∗
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) | 978-1-6654-0105-0/22/$31.00 ©2022 IEEE | DOI: 10.1109/NEWCAS52662.2022.9842108

†
Centre for Electronics Frontiers, Electronics and Computer Science, University of Southampton, SO17 1BJ, UK
‡
Institute for Integrated Micro and Nano Systems, School of Engineering, University of Edinburgh, EH9 3JL, UK
Corresponding email: zhaoguang.si20@imperial.ac.uk

Abstract—This paper proposes a memristor-assisted sign-based Input

S/H Output
background calibration scheme for analog-to-digital converters SAR Logic
(ADC). A R-2R digital-to-analog converter (DAC) was imple-
mented with a memristor array and other peripheral circuits. Main Error detection
The background calibration detects the error caused by DAC mis- DAC /Cal. algorithm
match and corrects it by adjusting the memristor’s memristance1 +
Correction Cal. Register
in a feedback loop. The implemented circuit takes advantage of DAC (memory)
the memristor’s small area and multi-state switching property.
Simulation results show the feasibility of using memristors to (a)
correct mismatch in high-resolution ADC design. The proposed
Input
system has been designed in a TSMC 180nm process. Memristors S/H Output
SAR Logic
will be laid on the top of the chip via Metal 5 and Metal 6.

Main
I. I NTRODUCTION DAC
Error Sign ? :
The concept of memristor, a device that represents the +
relationship between charge and flux, was first postulated ...
by Leon Chua in 1971 [1]. In 2008, Hewlett-Packard (HP)
Laboratory first realised a two-terminal memristor physically, Memristor-array

which exhibit a resistance switching behaviour correlates to the (b)

amplitude, polarity, and frequency of the applied voltages [2].
Since then, memristors made from different materials have
been the focus of many studies. In recent years, memristors
have been integrated with CMOS technology to design next-
generation electronics applications. The memristor offers non-
volatility, multi-state resistive switching, and small size. Re-
cent studies show how memristors have been applied to non-
volatile memory [3] and computing devices [4]. The possibility
of inducing gradual and non-volatile resistance changes with
low-voltage programming pulses makes memristors an excel-
lent candidate for calibration in analog circuits. This has been
previously explored in precision neural amplifier designs [5].
The successive approximation register (SAR) ADC is
known for its good power efficiency at a moderate speed
and resolution [6] [7]. Nevertheless, the element matching in
the digital-to-analog converter (DAC) becomes challenging for
high resolution (≥ 10b) SAR ADC design. The area of the
intrinsic DAC has to be scaled up four times for one more
extra effective bit to meet the matching requirements [6]. This
bottleneck is possibly overcome by integrating the memristor
technology to an ADC.
In this paper, we propose a memristor-assisted sign-
based background calibration scheme for ADC. We develop
1 Memristance is defined as the resistance value of the memristor
Fig. 1: (a) The sign-based calibration scheme in [7]. Unlike post-processing
the output of the ADC in [9], the sign-based calibration can keep running
parallelly with the normal ADC operation and calibrate the output immediately
when there is an error detected. (b) The proposed memristor-assisted calibra-
tion scheme where a memristor array is used as the correction elements and
the memory at the same time owing to its non-volatile multi-state switching
property. The calibration can be conducted easily by applying positive or
negative voltage pulses on the correction memristor according to the sign of
the error.
the calibration scheme based on the device model of a
Pt/TiOx/AlxOy/Pt stack-based memristor used in [8]. We
validate the concept of the memristor-assisted calibration for
element mismatches in a 12-bit R-2R DAC, and the proposed
architecture is applied to a 12-bit SAR ADC.
The paper is organised as follows: Section II introduces the
sign-based background calibration scheme for the ADC and
the model of the multi-state memristor. Section III presents
our proposed memristor-assisted DAC mismatch calibration
method. Section IV shows the simulation results and discusses
the tape-out plan, and Section V concludes the paper.
II. S IGN - BASED BACKGROUND CALIBRATION FOR ADC
A. Sign-based Background Calibration
Figure 1(a) is an example of the sign-based background
calibration in [7], the SAR ADC is implemented with a sign-

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 Comparator calibration scheme
Programming Comparator
Pulses correction
Read the value
Vin
S/H SAR Logic 14-bit
(14 cycles)
12-bit DAC
Code
DAC
Generator
output 12-bit
Mode set
Memristor-based
DAC R-2R DAC Detection Circuit
calibration Calibration
scheme Control signal
Programming
Pulses (Correction Circuit)
Calibrated output
Fig. 2: The architecture of the memristor-assisted 12-bit SAR ADC
error detection circuit and a trimming circuit. The sign-error
detection is enabled by introducing redundancy to the conver-
sion scheme. With the assistance of redundancy cycles, the
sign error can be directly detected by the detection circuit and
output a sign-based feedback signal. The sign-based feedback
signal is used to control the trimming circuit, which provides
the trimming value as an output to the ADC, and finally
calibrates the error to zero. Rather than detecting the error
of the full-bit output of the ADC in the digital domain [9],
detecting the sign error in an analog way can reduce the
overhead in power, area, and latency [7].
Figure 1(b) shows the proposed calibration scheme, which
applies a memristor array to intrinsic DAC. The memristance
of the memristor can be incrementally or decrementally pro-
grammed by applying positive or negative low-voltage pulses.
This can be used to trim the DAC element mismatch [10].
The memristor itself can store the calibration code due to
its non-volatility. Therefore, it does not need any additional
memory (e.g. the cal. register in [7]). The polarity of the
programming pulses can be determined by the sign-based
feedback signal. Hence, the sign-based background calibration
is a suitable design choice for a memristor-assisted ADC
calibration system.
B. Proposed Architecture of the ADC
Figure 2 shows the proposed architecture of the ADC, which
is developed from the block diagram shown in Figure 1(b).
With the assistance of redundancy, the SAR logic is expanded
from 12-bit to 14-bit. Thus, there are four 14-bit codes which
represent the same 12-bit value. When the DAC calibration
is activated, one more cycle will be added to the original 14
converting cycles. In the additional cycle, the DAC output will
be compared with the DAC output in the previous cycle. These
two outputs have the same 12-bit value but are represented
by different 14-bit codes. The mismatch detection circuit
generates the ‘sign-based feedback’ and ‘calibration control’
signals based on the comparison results. Then, the pulse
generator will trim the memristor in the memristor-based R-
2R DAC according to the sign of the error. The DAC output
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Comparator
offset detection
Digital Code 12-bit out
Processor
1 more cal. cycle added
Calibration
Control Circuit
Activation
Mismatch
Sign-based
feedback
Pulse Generator
Fig. 3: Simulation result of the Pt/TiOx/AlxOy/Pt memristor model. Rmax
is 74kΩ±1kΩ, and Rmin is 43kΩ±1kΩ. Memristance can be increased or
decreased to different states by applying positive or negative voltage pulses.
Every programming cycle consists of 500 pulses, and each pulse width is
10µs.
can be continuously adjusted in the background by trimming
the memristance of the memristor in the DAC.
C. The Model of the Multi-state Memristor
The memristor model used for simulations has been in-
troduced and verified in [8]. The static characteristics of
the model consists of a bi-directional hyperbolic sine, whilst
the rate-of-change of memristance exhibits an exponential
dependence on the applied voltage. The parameters used for
the simulations were extracted from physical device and can
be found in [8].
The model was programmed in Verilog-A and simulated in
Cadence to ensure the design is realistic. Figure 3 shows the
transient response of the model when applying voltage pulses
with different amplitudes and polarities.
III. D ESIGN AND I MPLEMENTATION OF THE DAC
A. DAC mismatch detection
The DAC mismatch detection circuit is the most important
building block of the DAC design. It detects the sign error and
controls the correction circuit. A truth table of the detection
logic is shown in Table I.
TABLE I: Truth Table of sign error detection and correction logic
B1 B2
Q(N) Q(N-1)
(Calibration Control Signal) (Sign-based Feedback Signal)
1 0 0 X
0 1 0 X
1 1 1 1
0 0 1 0
Figure 4 shows the detection circuit developed from the
logic in Table I. Figure 5 shows the timing diagram of the
detection circuit. ‘Calibrated’ signal is a flag that represents the
completion of calibration. Once the DAC output is calibrated
to the desired reference value, which is described by one of the
other 14-bit codes, the ‘Calibrated’ will be set to ‘1’. ‘Switch’
signal is used to activate the detection.
471
 Q(N-1) S1
CLK Q CLK Q S2
OR Switch 1-bit input
AND
Vref DFF DFF
Initialisation Memristor
D -Q D<11> ... D<0>
Read DAC XOR D -Q
output Calibrated
Q Cal. Ctrl. Signal Programming
... Pulses
... Programming
CLK Q CLK Q Switch Memristor Cell Memristor Cell
S3
in
Sign-based 55LQLW Pulses
Switch ...
DFF DFF Switch feedback + DC 5
- DAC output
signal 55LQLW
Port 1
D -Q D -Q GND Port 2

Calibration
Initialisation DeLayed CLK
Control Signal
Fig. 6: Implementation of the memristor-assisted 12-bit DAC. The memristor
Switch AND
model has an initial memristance Rinit = 43kΩ±1kΩ.

Fig. 4: Implementation of the sign-error detection circuit Sign-based

feedback signal

S2 S3
Reference
Voltage Generated Cal. Ctrl. S1
DAC output Programming Signal
Pulses
-
Clock +
Vpulse

S4 S5
Q(N)

Q (N-1) Fig. 7: Implementation of the correction circuit. The design is based on an

H-bridge.
Calibrated Switch = ((Q(N)
XOR Q(N − 1))
|| Calibrated)
Switch
& Initialisation to generate either positive or negative programming pulses
Calibration
td Calibration
Control Signal
based on ‘sign-based feedback signal’ and programmed the
Control = Delayed memristor. When the Q(N) and Q(N-1) became different,
Signal Clock& !Switch
the calibration process was stopped, the DAC output was
Sign-based Sign-based
Feedback feedback signal calibrated to 449.95 mV and the memristance was calibrated to
= Q(N)
Signal 38.69 kΩ, which means the implemented circuits can perform
Initialisation the proposed calibration logic correctly.
Figure 9 shows the simulation results of applying different
Fig. 5: The timing diagram of the detection circuit
digital codes and different mismatches to the DAC. In Fig-
ure 9(a), with the same input but different mismatches, the
B. Memristor-assisted R-2R Cell in the DAC initial DAC outputs were different, and the initial memris-
tances were the same in all conditions (43kΩ±1kΩ). After the
Memristor-assisted R-2R DAC is designed by cascading
calibration, all the DAC outputs in different conditions were
memristor cells. As shown in Figure 6, all switches in the
calibrated to their corresponding VREF value, and the mem-
memristor cell are controlled by ‘Calibration Control Signal’,
ristances in different conditions were calibrated to different
which is used to isolate the memristor from the system when
values. In Figure 9(b), three different inputs were applied to the
the memristor is being programmed.
calibration system as an example. By performing the calibra-
C. Correction Circuit tion, the outputs of the DAC with different inputs were all cal-
As shown in Figure 7, switches S2, S3, S4 and S5 are ibrated to their corresponding VREF value. These calibration
controlled by ‘Sign-based Feedback Signal’. Switch S1 is processes are repeatable. Results show that the implemented
controlled by ‘Calibration Control Signal’. The correction DAC based on the memristor-assisted background calibration
circuit can output positive or negative programming pulses scheme is capable of performing the correct calibration.
based on the outputs from the detection circuit. The proposed DAC was tested in a conventional 12-bit
SAR ADC used in [11]. The charge-redistribution DAC was
IV. S IMULATION R ESULTS replaced by the proposed memristor-assisted R-2R DAC and
The bias voltage was set to 1V for all simulations. The ref- other circuits. The simulation results show that the memristor-
erence voltage corresponding to different inputs is calculated based background calibration scheme successfully calibrates
by: the DAC mismatches in the SAR ADC. A prototype chip
Digital Input is being developed in 180nm CMOS process. The final
VDACout = Vbias · , N = 12 (1)
2N fabricated chip will have integrated Pt/TiOx/AlxOy/Pt stack-
Figure 8 shows the detection and correction result of based memristors through wafer-level CMOS back-end of line
the implemented DAC. As shown in Figure 8(a), the initial (BEOL) post-processing. The ADC performance including
memristance was 43kΩ±1kΩ and the initial DAC output was DNL, INL and effective number of bits will be measured
437 mV. When Q(N) and Q(N-1) were both ‘0’ or ‘1’, the to validate the efficacy of the proposed calibration method.
‘calibration control’ signal activated the correction circuit Additionally, further in-depth characterisation of the dynamic

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 (a)
(a)

(b)
2
(b)
3
1.5
Fig. 9: Simulation of the memristor-based 12-bit DAC with background
Amplitude of Programming Pulses(V)

2.5 Positive Pulses

1
calibration. The amplitude and pulse width of the programming pulses were
the same as the one in Fig. 8. (a) A 12-bit input code ’010011001100’ is
2
0.5 demonstrated as an example. The VREF was set to 300 mV. The period of
LOGIC LEVEL

the system clock was set to twice of the pulse width. Only the MSB memristor
1.5
0 was presented for clarity. Three different mismatches were added by varying
Negative
1 Pulses
the resistance of the resistors in the R-2R cells. (b) Three different input codes
-0.5
were applied to the DAC. VREF was calculated by equation (1).
Sign-based feedback signal
0.5
Programming Pulses -1

0 -1.5
-0.5
0 0.5 1 1.5 2 2.5 3 3.5
time(s)
(c)
Fig. 8: Simulation to validate DAC mismatch detection and pulse generator
circuits. The programming pulse width was set to 1µs. The amplitude of the
programming pulses was set to 2 V. 3% mismatch was emulated. The VREF
was set to 500 mV. An input code of ’010011001100’ is demonstrated as an
example. Only MSB memristor was presented for clarity. In (b) (c), when
Q(N) and Q(N-1) were the same, programming pulses were generated with
a polarity defined by ‘sign-based feedback signal’. After Q(N) and Q(N-1)
became different at 0.35ms, the calibration process was stopped. DAC output
and memristance in (a) entered the reading region became stable.
behavior of memristors will be available through inference
based on the ADC results. This will enhance the maturity of
existing Verilog-A device models incorporating comprehensive
information on dynamic switching characteristics and device-
to-device/cycle-to-cycle variations, which will in return con-
tribute to more precise designs in the future.
V. C ONCLUSION AND F UTURE WORK
10-4 A memristor-assisted sign-based background calibration
scheme for ADC is presented based on a stacked
Pt/TiOx/AlxOy/Pt memristor. The architecture of the
memristor-assisted calibration for element mismatches in a
12-bit R-2R DAC is validated by circuit-level simulation.
The calibration architecture has been implemented in a 12-bit
SAR ADC. The proposed technique proves the feasibility
of using memristors to calibrate high-resolution ADCs. We
anticipate memristor-based circuit can be used as a new
approach in the calibration circuit and will be characterised
and benchmarked with the SAR ADC state of the art in the
future.
ACKNOWLEDGMENT
This work was supported by FORTE, which is a UKRI En-
gineering and Physical Sciences Research Council Programme
under Grant EP/R024642/1.

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 R EFERENCES
[1] L. Chua, “Memristor-the missing circuit element,” IEEE Transactions
on Circuit Theory, vol. 18, no. 5, pp. 507–519, 1971.
[2] S. D. Strukov DB, Snider GS and W. RS, “The missing memristor
found,” Nature, vol. 453, no. 7191, pp. 80–83, 2008.
[3] G. Papandroulidakis, I. Vourkas, A. Abusleme, G. C. Sirakoulis, and A.
Rubio, “Crossbar-based memristive logic-in-memory architecture,” IEEE
Transactions on Nanotechnology, vol. 16, no. 3, pp. 491–501, 2017.
[4] M. A. Zidan, A. Chen, G. Indiveri, and W. D. Lu, “Memristive
computing devices and applications,” Journal of Electroceramics, vol.
39, no. 4-20, 2017.
[5] Wang J, Serb A, Papavassiliou C, et al., 2021, Analysing and measur-
ing the performance of memristive integrating amplifiers, International
Journal of Circuit Theory and Applications, ISSN:0098-9886.
[6] B. Murmann. (2021) Adc performance survey 1997-2021. [Online].
Available: http://web.stanford.edu/ murmann/adcsurvey.html.
[7] M. Ding, P. Harpe, Y.-H. Liu, B. Busze, K. Philips, and H. de Groot,
“A 46 µW 13b 6.4 ms/s sar adc with background mismatch and offset
calibration,” IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp.
423–432, 2017.
[8] S. Maheshwari et al., ”Design Flow for Hybrid CMOS/Memristor
Systems—Part I: Modeling and Verification Steps,” in IEEE Transactions
on Circuits and Systems I: Regular Papers, vol. 68, no. 12, pp. 4862-
4875, Dec. 2021, doi: 10.1109/TCSI.2021.3122343.
[9] J. Shen et al., ”A 16-bit 16MS/s SAR ADC with on-chip calibration
in 55nm CMOS,” 2017 Symposium on VLSI Circuits, 2017, pp. C282-
C283, doi: 10.23919/VLSIC.2017.8008509.
[10] Stathopoulos, S., Khiat, A., Trapatseli, M. et al. Multibit memory
operation of metal-oxide bi-layer memristors. Sci Rep 7, 17532 (2017).
https://doi.org/10.1038/s41598-017-17785-1.
[11] C. Wang, L. Xie, X. Jiang, R. Ge and C. Papavassiliou, ”Design
of a Multi-State Memristive Memory,” 2021 28th IEEE International
Conference on Electronics, Circuits, and Systems (ICECS), 2021, pp.
1-6, doi: 10.1109/ICECS53924.2021.9665450.

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