162 IEEE JOURNAL OF SOLID-STATECIRCUITS. VOL. 28, NO.

2, FEBRUARY 1993

A New Waveform-Reshaping Circuit: An

Alternative Approach to Schmitt Trigger
Daejeong Kim, Joongsik Kih, and Wonchan Kim

Abstract- This paper introduces a new waveform-reshaping

circuit that is conceived as an alternative to the conventional
Schmitt trigger. This circuit employs ratioless inverters, which
requires no standby current and is adequate for high-speed
operations. Two different logic threshold voltages of CMOS
inverters in the circuit determine the hysteresis characteristics.

I. INTRODUCTION

C ONVENTIONAL CMOS Schmitt triggering circuits usu-

ally employ either a differential pair based on the positive
feedback [l], or different threshold voltages for NMOS and
PMOS transistors [2] as shown in Fig. 1.
The switching points in the circuit of Fig. l(b) cannot be
defined precisely because this circuit is based on a ratioed
operation. The NMOS inverter M5, M6 and the PMOS inverter
M I ,M3 are ratioed circuits. The driving transistors M2 and
M4 show racing conditions when the transition begins. In
Fig. 2, we suggest a new waveform-reshaping circuit that can
replace the conventional Schmitt triggers.

11. CIRCUITDESCRIPTION
To describe the operation of the circuit, first, assume that the
logic threshold voltages for M3, M4 and M5, M6 are vT1 and
v ~ 2respectively,
, and vT1 > v ~ 2 When . the input voltage
vin is less than V T ~A41 , is off and M2 pulls the output node (b)
down to 0 V. As vn rises to the level between vT2 and v&, Fig. 1. Conventional Schmitt trigger circuits: (a) based on feedback and
(b) based on different threshold voltages.
both A 4 1 and M2 are tumed off. The output node retains 0
V, since the latch output node X has been charged to VDD.
When V;, is above vT1, the pull-up transistor M I is on and VDD
charges the output node to VDD.The same is true as the input 1 I 1

voltage Kn decreases from VDD to 0 V. Here the transition

occurs when V,, falls to V T ~where the pull-down transistor
M 2tums on. Thus, the positive-going transition voltage VT+
corresponds to V T ~and , the negative-going transition voltage
VT- is equivalent to v-2.
The frequency response of the proposed circuit depends on
the gate delay of the CMOS inverter. In order to compare
the transient response of the proposed circuit with that of the
circuit in Fig. l(b), we have performed SPICE simulations for
one directional triggering. For the justice of the comparison,
the W / L values of and M6 in Fig. l(b) and Fig. 2 are
made equivalent and those of M4 in Fig. I(b) and M2 in
Fig. 2. Proposed waveforn-reshaping circuit.
Fig. 2 are made equivalent. The same sized transistors are
used in the latch. ~e simulated results with the variable load
capacitances are shown in Fig. 3. The applied input signal is a 1-MHz triangular waveform,
and the reference voltage for the gate delay is observed
Manuscript received April 27, 1992; revised October 13, 1992. at half the full swing voltage. In the figure, the proposed
The authors are with the Department of Electronics Engineering, Seoul
National University, Seoul 151-742, Korea. circuit shows smaller gate delays and the difference becomes
IEEE Log Number 9205749. larger as the load capacitance increases. When the driving
0018-9200/93$03.00 0 1993 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 2, FEBRUARY 1993 I63

-
- 60
150
-
- conventional
proposed
5.0 -

4.0 -
?--
100 - 0
>
m
C 3.0 -
Y (U
m
0
x
0
5 2.0
- -
9
.-
(Y
a
50 - 3 1.0 -
U

c3 0.0 J
10
' - ' ' T ' ' l ' - ' ' ' * " ' " ' ' ' . s ' ' L -1.0 I I I I I I I

Fig. 4. Chip microphotograph of the proposed circuit.

'
Fig. 6. Photograph of the output voltage with a 100-kHz sinusoidal input
of a 4-V amplitude
transistor M4 in the conventional circuit begins to pull the
node X down, series-connected M4 and M5 increase the tum-
on resistance compared with the pull-down mechanism by the
5.0

- t
single transistor. Also, only the transistors in the latch drive the 4.0

t
output node in Fig. l(b). On the other hand, both the driving
transistor M2 and the transistors in the latch drive the output . .
. . . . . .. . . .
3.0 VT+
*
node in the proposed circuit. v
m

5 2.0
111. EXPERIMENTAL
RESULT
1.0 . . . . . v1-. . . . .
We have fabricated the proposed circuit in a 1.2-pm double-
metal CMOS process. The threshold voltages of NMOS and , , , ,,,,,I , , , , ,,,,, , , ,
0. 0_
PMOS transistors are 0.66 and -0.72 V, respectively. The 102 103 104 105 106 to7
W / L values of M3, M4, M5, and MS are 20 pm/5 pm, 5 Frequency [Hz]
pm/lO pm, 5 pm/20 pm, and 10 pm/5 pm, respectively. Fig.
Fig. 7. Measured frequency responses from 100 Hz to 10 MHz.
4 shows the chip microphotograph of the proposed circuit. Fig.
5 shows a measured dc characteristic of the circuit.
IV. CONCLUSION
Measurements on the fabricated samples have been done
with sinusoidal input signals of a 4-V amplitude from 100 Hz A new waveform-reshapingcircuit that acts like the Schmitt
to 10 MHz. As we have shown in Section 11, the hysteresis trigger is presented. The hysteresis feature is clear and less
voltage becomes larger with the frequency increase of the sensitive to the process and supply-voltage variations com-
input signal because of the gate delay. Fig. 6 shows one of pared with other CMOS Schmitt triggers, since it employs
the output waveforms with a 100-kHz sinusoidal input of a the ratioless circuit concept. The circuit, implemented with
4-V amplitude. a 1.2-pm double-metal CMOS process, shows an adequate
In Fig. 7, we show the experimental frequency responses of hysteresis feature and fast transition responses to the input
the proposed circuit. signals.
161 lEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 2, FEBRUARY 1993

ACKNOWLEDGMENT REFERENCES
The authors would like to thank the Inter-University Semi-
conductor Research Center for allowing them to use the design
,,
M. S. Smith, the circuit ma,ysis of the Schmitt trigger,., IEEE
I , Soljd-S~atecircuits, 23, pp, 292-294, Feb. 1988.
tools and Hyundai Electronics Industries Co., Ltd. for the [2] D. A. Hodges and H. G. Jackson, Analysis and Design of Digiral
fabrication of the test chip. Integrated Circuits. New York: McGraw-Hill, 1983, ch. 8.