UNIT -1

1) The CPU built on a single IC is called as a _____.

(a) Microprocessor b)Macroprocessor
c) Micro preprocessor d)Macro preprocessor
2) A digital computer in which one microprocessor acts as a CPU is called a _____.
(a) Macrocomputer b)Minicomputer
c)Microcomputer d)Supercomputer
3) _____is the first microprocessor.
(a) Intel 4001 b)Intel 4002
c)Intel 4003 d)Intel 4004
4) Intel 8085 uses_____ technology.
(a) CMOS b)PMOS
c)NMOS d)DMOS
5) _____bus is used to carry the address to the memory to fetch either instruction or data.
(a) control bus b)connection bus
c) data bus d)address bus
6) _____bus is used to carry the data from the memory.
(a) address bus b)data bus
c)control bus d)connection bus
7) _____bus is used to carry the control signals like RD/WR, select etc…
(a) address bus b)connection bus
c)control bus d)data bus
8) Various input output devices and memory devices are connected to CPU by groups of
lines called_____.
(a) Register b)buses
c)accumulator d)controller
9) Intel 8085 has_____ op codes.
(a) 246 b)380
c)154 d)310
10) Which is not the control bus signal?
(a) READ b)WRITE
c)RESET d)READ/WRITE
11) BIU stands for:
(a) Bus Interface Unit b)Bess Interface Unit
c)Bus Interactive Unit d)Bass Interface Unit
12) 8bit microprocessor has a/an _____bit data bus.
(a) 16 b)8
c)2 d)0
13) The _____bus is unidirectional.
(a) address bus b)data bus

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 c)control bus d)system bus
14) The _____bus is called A-bus.
(a) status bus b)data bus
c)control bus d)address bus
15) The bit of the data bus is same as the word length of the_____.
(a) IO/M b) CPU
c)memory d)I/O
16) When CPU sends an low_______ signal, the activated device understands that CPU
wants to read information
(a) RD b)WR
c)I/O d)Memory
17) A sequence of instruction is called a _____.
(a) Register b)buses
c)program d)counter
18) The _____cycle consists of fetch cycle and execute cycle.
(a) innovation cycle b)instruction cycle
c)address cycle d)data bus
19) The first part of the instruction is_____.
(a) Operand b)op code
c)option d)operation
20) The clock cycle for which the CPU waits is called_____.
(a) instruction cycle b)anti clock cycle
c)wait cycle d)timing cycle
21) A read cycle is similar to the _____cycle.
(a) instruction cycle b)fetch cycle
c)wait cycle d)low cycle
22) The necessary steps carried out to perform a fetch, read or write operation constitute a
_____cycle.
(a) fetch cycle b) machine cycle
c)instruction cycle d)low cycle
23) Flag registers are connected to the_____.
(a) ALU b)parity
c)accumulator d)interrupt
24) _____is also known as “Status registers” (or) “program status word”.
(a) General purpose register b)Special purpose register
(b) Flag register d)Flash memory
25) How many flip flops are present in the flag register?
(a) 3 b)4
c)2 d)5
26) If sign flag D7 is 1, the number is _____.

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 (a) positive b) negative
c) zero d)carry
27) If sign flag D7 is 0, the number is _____.
(a) positive b) negative
c) zero d) carry
28) What is the expansion for CPU?
(a) Computer Processing Unit b)Control Processing Unit
c)Central Programming Unit d)Computer Programming Unit
29) The _____fetches one instruction at a time, decodes it and then executes it.
(a) CPU b)register
c)stack d)memory
30) The _____performs arithmetic and logic operation.
(a) ALU b)TCU
c)register d)Buses
31) Intel 8085 doesn’t have_________ operations.
(a) addition, subtraction b)subtraction, multiplication
c) multiplication, division d)division, addition
32) The _____register contains one operand of an instruction to be executed.
(a) accumulator b)general purpose registers
c) special purpose registers d)flag registers
33) _____used to store data.
(a) Accumulator b)General purpose registers
c)Special purpose registers d)Flag
34) _____is/are not accessible to users.
(a) Accumulator b)General purpose registers
c) Special purpose registers d)Flag register
35) The ROM is a _____memory.
(a) volatile b)semiconductor
c)non-volatile d) flash
36) PROM stands for_____.
(a) Preset ROM b)Process ROM
c)Pointer ROM d)Programmable ROM
37) RAM stands for_____.
(a) Random Access Memory b)Read Accept memory
c)Read Access Memory d)Random Accept Memory
38) How many pins are there in Intel 8085?
(a) 40 b)10
c)20 d)49
39) Intel 8085 has a maximum frequency of_____.
(a) 10HZ b)3MHZ

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 c)90HZ d)10MHZ
40) How many bits are there in the address bus?
(a) 2 b)4
c)5 d)8
41) Expand: ALE.
(a) Address Latch Enable b)Add Latch Enable
c)Address Line End d)Address Lock Enable
42) INTR is expanded as_____.
(a) Interrupt Read b)Interrupt Request
c) Intel Request d)Intel Read
43) INTA is expanded as_____.
(a) Interrupt Acknowledge b)Interrupt Again
c)Intel Acknowledge d)Intel Again
44) Timing diagram is a _____representation.
(a) timing b)graphical
c)machine d)memory
45) The 8085 microprocessor has _____basic machine cycle
(a) 8 b)10
c)5 d)2
46) In memory WRITE operation, IO/M=0, s1=0 and s2=?
(a) 0 b)1
c)5 d)8
47) The first machine cycle is the_____.
(a) memory read cycle b)op code fetch
c)memory write d)set
48) One byte instruction requires _____m/c cycle(s).
(a) only one b)two
c)three d)four
49) An instruction is a _____pattern designed inside a microprocessor to perform a specific
function.
(a) Binary b)decimal
c)hexa decimal d)octal
50) One clock period is called as a ______________.
(a) Flag b)frequency
c) state d)speed

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Answers
1) ( a)Microprocessor 27) ( a)positive
2) (c )Microcomputer 28) ( b)Control Processing Unit
3) ( d)Intel 4004 29) ( a)CPU
4) (c) NMOS 30) (a)ALU
5) (d)address bus 31) ( c)multiplication, division
6) (b)data bus 32) ( a)Accumulator
7) ( c)control bus 33) ( b)General purpose
8) (b)buses 34) ( c)special purpose
9) (a)246 35) ( c)non-volatile
10) ( c)RESET 36) ( d)Programmable ROM
11) (a)Bus interface Unit 37) ( a)Random Access Memory
12) ( b)8 38) ( a)40
13) (a)address bus 39) ( b)3MHZ
14) (d)Address bus 40) ( d)8
15) (b)cpu 41) (a)Address Latch Enable
16) ( a)RD 42) ( b)Interrupt Request
17) (c )program 43) ( a)Interrupt Acknowledge
18) (b)Instruction cycle 44) ( b)graphical
19) ( b)opcode 45) ( c)5
20) ( c)wait cycle 46) (b)1
21) ( b)fetch cycle 47) ( b)opcode fetch
22) ( b)machine cycle 48) ( a)only one
23) ( c)accumulator 49) (a)binary
24) ( c)flag register 50) (c) )State
25) ( d)5
26) ( b)negative

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 UNIT-II
1) In _____ addressing mode, the address of the operand is given in the instruction itself.
(a) Direct b)Register
c)Register indirect d)Immediate
2) In _____ addressing mode, the operands are in the general purpose registers.
(a) Direct bRegister
c)Register indirect d)Immediate
3) In _____ addressing mode, the address of the operand is specified by a register pair.
(a) Direct b)Register
c)Register indirect d)Immediate
4) In_____ addressing mode, the operand is specified within the instruction itself.
(a) Direct b)Register
c)Register indirect d)Immediate
5) In _____ addressing mode, instructions do not require the address of the operand.
(a) Register b)Implicit
c)Immediate d)Indirect
6) CMA is an example of _____addressing.
(a) Register b)Immediate
c) Implicit d)Indirect
7) _____ is a one-word CALL instruction.
(a) Set b)Reset
c)Restart d)Halt
8) The execution of the _____instruction stops the microprocessor.
(a) SET b)RST
c)RET d)HLT
9) The_____ instruction is used to transfer data from one register to another register.
(a) data transfer b)logical
c) branch d)arithmetic
10) _____is the instruction to move the content of one register to another.
(a) MOV r,m b)MVI r,data
c)MOV r1,r2 d)MOV m,r
11) MVI m,data is the instruction used to move_____.
(a) immediate data to memory b)memory to immediate data
c)immediate data to register d)register to data
12) _____is the instruction used to exchange the content of H-L with D-E pair.
(a) LHLD b)XCHG
c)SHLD d)LDAX
13) STA addr is the instruction used to_____.
(a) load accumulator b)exchange accumulator
c)store accumulator d)store accumulator indirect

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14) A machine language instruction format consists of _____.
(a) operand field b)operation code field
c)operation code field & operand field d)none
15) The length of the one-byte instruction is _____.
(a) 2byte b)1byte
c)3byte d)4byte
16) The instruction “JUMP” belongs to_____.
(a) sequential control flow b)control transfer instruction
c)branch instruction d)control transfer & branch
17) The instruction that subtracts 1 from the contents of the specified registered memory
location is_____.
(a) INC b)SUBB
c)SUB d)DEC
18) The instruction that enables subtraction with borrow is_____.
(a) DEC b)SUB
c)SBB d)None
19) The instruction CMP to compare source and destination operands, performs_____.
(a) Addition b)subtraction
c)division d)multiplication
20) During compare operation, the result of comparison or subtraction is stored in_____.
(a) memory b)register
c)stack d)no where
21) The instruction that is used to convert the result of the addition of two packed BCD
number to a valid BCD number is_____.
(a) DDA b)DAA
c)AAA d)AAS
22) The instruction “INC” increases the contents of the specified register or memory location
by_____.
(a) 2 b)0
c)1 d)3
23) The flag that acts as borrow flag in the instruction SBB is_____.
(a) direction flag b)carry flag
c)parity flag d)trap flag
24) The mnemonic that is placed before the arithmetic operation is performed is_____.
(a) AAA b)AAS
c)AAM d)AAD
25) Stack follows the sequence_____.
(a) first in first out b)first in last out
c)last in first out d)last in last out
26) Stack is useful for_____.

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 (a) storing the register status b)temporary storage of data
c)storing contents of register d)parameter storage
27) Data is transferred from _____ to destination in data transfer group.
(a) Destination b)source
c)memory d)register
28) Which instruction performs arithmetic operation?
(a) logical group b)arithmetic group
c)data transfer group d)all of the above
29) Arithmetic operations are _____.
(a) Addition b)subtraction
c)increment or decrement d)all the above
30) Which instruction performs the logical operation?
(a) arithmetic group b)logical group
c)branch control group d)none
31) Logical operations are_____.
(a) AND b)OR
c)compare d)all
32) Example of branch control group_____.
(a) JMP b)CALL
c)Both a &b d)none
33) RAL means:
(a) Rotate accumulator left through carry b)Rotate accumulator right through
carry
c)Compare memory with accumulator d)Rotate accumulator
34) EI means:
(a) Enable Interrupts b)Disable interrupts
c)No operation d)Read interrupt masks
35) Logical operations are_____.
(a) AND,OR b)+,-
c)if_ _ _else d)break
36) AND register with accumulator is_____.
(a) ORA r b)ANA r
c)XRA r d)CMP r
37) RLC means_____.
(a) rotate and compare the register b)rotate accumulator left
c)rotate left and carry d)rotate accumulator left to carry
38) RRC is rotated _____ by_____ bit
(a) right, one b)right, two
c)right, three d)left, eight
39) RAL instruction is used to_____.

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 (a) rotate accumulator left b)rotate accumulator left to carry
c)rotate accumulator right d)rotate accumulator right to carry
40) HLT op code means_____.
(a) load data into accumulator b)store result in memory
c)load accumulator with contents of register d)end of program
41) The_____ group instructions, changes the normal sequence of the program.
(a)Arithmetic b)branch
c)logical d)data transfer
42) ORA r is an example of _____ group instructions.
(a) Arithmetic b)branch
c)logical d)data transfer
43) The_____ flag is set to 1, if the result of an arithmetic or logical operation contains even
number of 1’s.
(a) CS b)P
c)AC d)Z
44) The_____ flag is set, if there is a carry out from bit number three to bit number four.
(a) Z b)CS
c)P d)AC
45) If the result of an arithmetic or logical operation is negative, the sign flag is set to_____.
(a)0 b)1
c)2 d)3
46) The_____ flag is set to 1, if the result of an arithmetic operation contains zeros.
(a)CS b)P
c)AC d)Z
47) The_____flag is set, if there is a carry out after the execution of an arithmetic instruction.
(a)Z b)CS
c)P d)AC
48) ADI data belongs to the _____group of instruction.
(a) Arithmetic b)logical
c)data transfer d)branch and control
49) LDA addr belongs to the _____group of instruction.
(a) Arithmetic b)logical
c)data transfer d)branch and control
50) XRA r belongs to the_____ group of instruction.
(a) Arithmetic b)logical
c)data transfer d)branch and control

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Answers
1) ( a)Direct 26) ( b)temporary storage of data
2) (b)Register 27) ( b)source
3) ( c)Register indirect 28) ( b)arithmetic group
4) (d)Immediate 29) (d)all the above
5) (b)Implicit 30) (b)logical group
6) ( c)Implicit 31) (d)all
7) ( c)Restart 32) ( c)botha &b
8) (d)HLT 33) ( a)Rotate accumulator left through
9) ( a)data transfer carry
10) ( c)MOV r1,r2 34) ( a)Enable Interrupts
11) ( a)immediate data to memory 35) ( a)AND,OR
12) ( b)XCHG 36) (b)ANA r
13) ( d)store accumulator indirect 37) (b)rotate accumulator left
14) ( c)operation code field & operand 38) ( a)right, one
field 39) (b)rotate accumulator left to carry
15) (b)1byte 40) (d)end of program
16) (d)control transfer & branch 41) (b)Branch
17) (d)DEC 42) ( c)Logical
18) ( c)SBB 43) (b)P
19) (b)subtraction 44) (d)AC
20) (d)no where 45) (b)1
21) ( b)DAA 46) (d)Z
22) ( c)1 47) (b)CS
23) (b)carry flag 48) ( a)arithmetic
24) ( c)data transfer 49) ( c)data transfer
25) ( c)last in first out 50) (b)logical

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 UNIT 3
1. The instruction MVI B, 05 moves the 05 into _________.
(a) Register B b)Accumulator
c)Temporary register d)CPU
2. The code for _______ is 76.
(a) HLT b)GO
c)STOP d)MOVE
3. The symbol ________ after a digit denotes that it is in hexadecimal system.
(a) H b)B
c)I d)X
4. ________ instruction loads the accumulator.
(a) MVI b)MOV
c)LDA d)HLT
5. In the instruction LXI H, the address H is the ___________ of the location.
(a) Data b)Address
c)Temporary data d)loading
6. _________ transfers the content of the memory location whose address is in H-L pair, to
register C.
(a) MOV A,B b)MVI B,05
c)LDA ,05 d)MOV C,M
7. The instruction INX H, will _________ H-L pair by one.
(a) Increment b)Decrement
c)Add d)subtract
8. MOV B,M moves the content of memory location to register _______.
(a) B b)C
c)M d)H
9. _____ A increases the content of the accumulator by one.
(a) INR b)DCR
c)MVI d)ADD
10. STA FC50H _______ result in FC50 H.
(a) Adds b)Stores
c)Halts d)loads
11. HLT stand for ______.
(a) Halt b)Stop
c)Load d)add
12. ________ instruction adds two numbers.
(a) ADD b)MOV
c)MIV d)LDA
13. SUB instruction _________ two numbers.
(a) Subtracts b)Stores

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 c)Loads d)moves
14. MSB stand for ___________.
(a) Mnemonic Standard Block b)Most Significant Bits
c)Most Signed Bits d)Major Significant Bits
15. _____ stand for Least Significant Bits.
(a) LSB b)LBS
c)LLB d)LFB
16. _______instruction adds two numbers in register pair.
(a) DAD b)ADD
c)MOV d)MVI
17. __________ stores LSBs of sum in L register.
(a) SHLD b)HLD
c)STA d)LDA
18. ______ decrements the content of H-L pair.
(a) SUB b)DCX H
c)DCR d)MOV
19. CMA complements _______ of the numbers.
(a) 8 MSBs b)Data
c)Count d)Content
20. _______ do the 2’s complement of 8 LSBs of the number.
(a) ADI b)ADD
c)MVI d)CMA
21. The address of the memory locations is in _________.
(a) Numbers b)Characters
c)Hexadecimals d)addresses
22. _______ increases the content of H-L pair by one.
(a) INX H b)INC
c)INR H d)ADD
23. _______ compares the content of memory location with the content of the accumulator.
(a) CMP M b)CMP
c)SUB M d)SUB
24. ___________ is a looping instruction.
(a) CMP b)INR
c)JNZ d)IN
25. The instruction _____ is a subroutine call.
(a) CALL b)INX
c)INR d)JNZ
26. ___________ instruction stores the result in the memory location.
(a) STAX b)MOV
c)STA d)MVI

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27. Looping instruction _____ is executed when there is a carry in the result.
(a) JZ b)JNC
c)NC d)MOV
28. ______is the first step in the evolution of programming languages.
(a) Machine language b) Assembly language
c) Code language d) Data
29. Mnemonic represent __________.
(a) Operation codes b)Strings
c)Address d) Data
30. Assembly language program is called_______
(a) Object program b)Source program
c)Oriented program d)All of these
31. Which register is memory pointer ___________
(a) Program counter (c) Stack pointer
(b) Instruction register (d) Source index
32. A ________ is written as separate unit, apart from main and called whenever necessary
(a) Subroutine b)Code
c)Block d)None of these

33. Call instruction is written in the ______program.

(a) Main b)Procedures
c)Program d)Memory
34. Opcode is the machine instruction obtained from decoding instruction stored in ______.
(a) Stack pointer b)Address pointer
c)Instruction register d)Incrementer
35. BCD stands for______
(a) Binary coded decimal b)Based coded decimal
c)Both A and B d)None of these
36. _______ instruction stores result in memory.
(a) HLD b)STA
c)SHLD d)DAD
37. RAL _______ the content of the accumulator by one bit.
(a) Adds b)Deletes
c)Rotates d)inserts
38. __________ instruction gets the byte of 2nd number in accumulator.
(a) LDAX b)LDA
c)STA d)HLD
39. Decimal digits are adjusted for the instruction __________.
(a) DAA b)ADJ
c)DAD d)MOV
nd st
40. _________ subtracts byte of 2 number from 1 number with borrow.
(a) SBB b)SUB
c)DEL d)MOV
41. _______ instruction jumps to label LOOP.

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 (a) JNZ LOOP b)JNC
c)MVI d)SBB
42.The instruction _________ complements the content of the accumulator.
(a)CAM b)CMA
c)CMP d)COM
43. _______ is the break point for the instructions.
(a)BRK b)RST
c)HLT d)HLD.
44.The program is ended when ______ instruction is executed.
(a)END b)STOP
c)HLT d)HLD.
45.A sequence of instructions to which a name is assigned is called a ________.
(a)Micro b)Macro
c)Stop d)help.
46.A small task is called _________.
(a)Subroutine b)SBRT
c)SUB d)MOV.
47.The last instruction of the subroutine is ________.
(a)LAST b)HLT
c)RET d)LOOP.
48.___________ adds the content of register to the content of accumulator with the carry
(a)ADC r b)ADD
c)ADA d)CMP A.
49.ADI data adds _________ data to the accumulator.
(a) Immediate b)Indirect
c)Memory d)No
50. The instruction _________ writes into control word register.
(a) OUT b)IN
c)MOV d)MVI

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Answers – Unit 3
1. (a) Register B 25. (a) CALL
2. (a) HLT 26. (a) STAX
3. (a) H 27. (a) JZ
4. (c) LDA 28. (b) Assembly language
5. (b) Address 29. (a) Operation codes
6. (d) MOV C,M 30. (b) Source program
31. (a) Program counter
7. (a) Increment
32. (a) Subroutine
8. (a) B 33. (a) Main
9. (a) INR 34. (c) Instruction register
10. (b) Stores 35. (a) Binary coded decimal
11. (a) Halt 36. (c) SHLD
12. (a) ADD 37. (c) Rotates
13. (a) Subtracts 38. (a) LDAX
39. (a) DAA
14. (b) Most Significant Bits
40. (a) SBB
15. (a) LSB 41. (a) JNZ LOOP
16. (a) DAD 42. (b) CMA
17. (a) SHLD 43. (b) RST
18. (b) DCX H 44. (a) END
19. (a) 8 MSBs 45. (a) Micro
20. (a) ADI 46. (a) Subroutine
47. (c) RET
21. (c) Hexadecimals
48. (a) ADC r
22. (a) INX H 49. (a) Immediate
23. (a) CMP M 50. (a) OUT
24. (c) JNZ

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 UNIT -IV
1. The device that enables the microprocessor to read data from the external devices is
_____.
a) printer b) joystick
c) display d) reader

2. The example of output device is _____.

a) CRT display b) 7-segment display
c) printer d) all of the mentioned

3. The input and output operations are respectively similar to the operations _____.
a) read, read b) write, write
c) read, write d) write, read

4. While performing read operation, one must take care that much current should not be
____.
a) sourced from data lines b) sinked from data lines
c) sourced or sinked from data lines d) sinked from address lines

5. To avoid loading during read operation, the device used is ____.

a) latch b) flipflop
c) buffer d) tristate buffer

6. Programmable peripheral input-output port is other name for _____.

a) serial input-output port b) parallel input-output port
c) serial input port d) parallel output port

7. The data bus buffer is controlled by _____.

a) control word register b) read/write control logic
c) data bus d) none

8. The input provided by the microprocessor to the read/write control logic is _____.
a) RESET b) A1
c) WR(ACTIVE LOW) d) all of the mentioned

9. Which one of the following is not a vector interrupt?

a) TRAP b) INTA
c) RST 7.5 d) RST 3

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10. In 8085 microprocessor, the RST6 instruction transfer programme execution to following
location.
a) 0030H b) 0024H
c) 0048H d) 0060H

11. In direct memory access mode, the data transfer takes place _____.
a) directly b) indirectly
c) directly and indirectly d) none of the mentioned

12. In 8257 (DMA), each of the four channels has _____.

a) a pair of two 8-bit registers b) a pair of two 16-bit registers
c) one 16-bit register d) one 8-bit register

13. The common register(s) for all the four channels of 8257 are _____.
a) DMA address register b) terminal count register
c) mode set register and status register d) none of the mentioned

14. In 8257 register format, the selected channel is disabled after the terminal count condition
is reached when _____.
a) auto load is set b) auto load is reset
c) TC STOP bit is reset d) TC STOP bit is set

15. The register of 8257 that can only be written in is _____.

a) DMA address register b) terminal count register
c) mode set register d) status register

16. The IOR (active low) input line acts as output in ____.
a) slave mode b) master mode
c) master and slave mode d) none of the mentioned

17. The pin that disables all the DMA channels by clearing the mode registers is _____.
a) MARK b) CLEAR
c) RESET d) READY

18. The pin that requests the access of the system bus is ____.
a) HLDA b) HRQ
c) ADSTB d) none of the mentioned

19. The pin that is used to write data to the addressed memory location, during DMA write
operation is _____.

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 a) MEMR (active low) b) AEN
c) MEMW (active low) d) IOW (active low)

20. The pin that strobes the higher byte of the memory address, generated by the DMA
controller into the latches is ____.
a) AEN b) ADSTB
c) TC d) none of the mentioned

21. Which of the following is not a mode of data transmission?

a) simplex b) duplex
c) semi duplex d) half duplex

22. If the data is transmitted only in one direction over a single communication channel, then
it is of ____.
a) simplex mode b) duplex mode
c) semi duplex mode d) half duplex mode

23. If the data transmission takes place in either direction, but at a time data may be
transmitted only in one direction then, it is of _____.
a) simplex mode b) duplex mode
c) semi duplex mode d) half duplex mode

24. In 8251A, the pin that controls the rate at which the character is to be transmitted is ____.
a) TXC(active low) b) TXC(active high)
c) TXD(active low) d) RXC(active low)

25. TXD(Transmitted Data Output) pin carries serial stream of the transmitted data bits along
with _____.
a) start bit b) stop bit
c) parity bit d) all of the mentioned

26. The signal that may be used either to interrupt the CPU or polled by the CPU is _____.
a) TXRDY(Transmitter ready) b) RXRDY(Receiver ready output)
c) DSR(active low) d) DTR(active low)

27. The disadvantage of RS-232C is _____.

a) limited speed of communication b) high-voltage level signaling
c) big-size communication adapters d) all of the mentioned

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28. The USB supports the signaling rate of _____.
a) full-speed USB 1.0 at rate of 12 Mbps b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps d) all of the mentioned

29. The bit packet that commands the device either to receive data or transmit data in
transmission of USB asynchronous communication is _____.
a) handshake packet b) token packet
c) PRE packet d) data packet

30. High speed USB devices neglect _____.

a) handshake packet b) token packet
c) PRE packet d) data packet

31. The number of hardware interrupts that the processor 8085 consists of is _____.
a) 1 b) 3
c) 5 d) 7

32. The register that stores all the interrupt requests in it in order to serve them one by one on
priority basis is _____.
a) Interrupt Request Register b) In-Service Register
c) Priority resolver d) Interrupt Mask Register

33. The register that stores the bits required to mask the interrupt inputs is _____.
a) In-service register b) Priority resolver
c) Interrupt Mask register d) none

34. The interrupt control logic _____.

a) manages interrupts b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal d) all of the mentioned

35. In cascaded mode, the number of vectored interrupts provided by 8259A is _____.
a) 4 b) 8
c) 16 d) 64

36. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can
be used as a _____.
a) input to designate chip is master or slave b) buffer enable
c) buffer disable d) none

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37. Once the ICW1 is loaded, then the initialization procedure involves _____.
a) edge sense circuit is reset b) IMR is cleared
c) slave mode address is set to 7 d) all of the mentioned

38. When non-specific EOI command is issued to 8259A it will automatically _____.
a) set the ISR b) reset the ISR
c) set the INTR d) reset the INTR

39. In the application where all the interrupting devices are of equal priority, the mode used
is _____.
a) automatic rotation b) automatic EOI mode
c) specific rotation d) EOI

40. The operation that can be performed on control word register is _____.
a) read operation b) write operation
c) read and write operations d) none

41. The mode that is used to interrupt the processor by setting a suitable terminal count is
_____.
a) mode 0 b) mode 1
c) mode 2 d) mode 3

42. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes
low for _____.
a) 1 clockcycle b) 2 clockcycles
c) 3 clockcycles d) 4 clockcycles

43. The generation of square wave is possible in the mode _____.

a) mode 1 b) mode 2
c) mode 3 d) mode 4

44. In control word register, if SC1=0 and SC0=1, then the counter selected is _____.
a) counter 0 b) counter 1
c) counter 2 d) none

45. In control word format, if RL1=1, RL0=1 then the operation performed is _____.
a) read/load least significant byte only b) read/load most significant byte only
c) read/load LSB first and then MSB d) read/load MSB first and then LSB

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46. If BCD=0, then the operation is _____.
a) decimal count b) hexadecimal count
c) binary count d) octal count

47. The counter starts counting only if _____.

a) GATE signal is low b) GATE signal is high
c) CLK signal is low d) CLK signal is high

48. The control word register contents are used for _____.
a) initializing the operating modes b) selection of counters
c) choosing binary/BCD counters d) all of the mentioned

49. To indicate the I/O device that its request for the DMA transfer has been honoured by the
CPU, the DMA controller pulls _____.
a) HLDA signal b) HRQ signal
c) DACK (active low) d) DACK (active high)

50. The priority of the channels varies frequently in _____.

a) rotating priority scheme b) fixed priority scheme
c) rotating priority and fixed priority scheme d) none of the mentioned

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Answers:
1. b) joystick 26. b) RXRDY(Receiver ready output)
2. d) all of the mentioned 27. d) all of the mentioned
3. c) read, write 28. d) all of the mentioned
4. c) sourced or sinked from data lines 29. b) token packet
5. d) tristate buffer 30. c) PRE packet
6. b) parallel input-output port 31. c) 5
7. b) read/write control logic 32. a) Interrupt Request Register
8. d) all of the mentioned 33. c) Interrupt Mask register
9. d) RST 3 34. d) all of the mentioned
10. a) 0030H 35. d) 64
11. a) directly 36. b) buffer enable
12. b) a pair of two 16-bit registers 37. d) all of the mentioned
13. c) mode set register and status register 38. b) reset the ISR
14. d) TC STOP bit is set 39. a) automatic rotation
15. c) mode set register 40. b) write operation
16. b) master mode 41. a) mode 0
17. c) RESET 42. a) 1 clockcycle
18. b) HRQ 43. c) mode 3
19. c) MEMW (active low) 44. b) counter 1
20. b) ADSTB 45. c) read/load LSB first and then MSB
21. c) semi duplex 46. b) hexadecimal count
22. a) simplex mode 47. b) GATE signal is high
23. d) half duplex mode 48. d) all of the mentioned
24. a) TXC(active low) 49. c) DACK (active low)
25. d) all of the mentioned 50. a) rotating priority scheme

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 UNIT -V
1. A microcomputer built on a single semiconductor chip is called _____.
a) embedded controller b) macro controller
c) RAM d) microcontroller

2. When microcontrollers are embedded in a system they are called _____.

a) embedded controller b) macro controller
c) RAM d) microcontroller

3. The ROM/EPROM/OTPROM of a microcontroller is known as _____.

a)controller memory b) data memory
c) program memory d) register memory

4. When data and intermediate results are stored in RAM, it is called ____.
a)controller memory b) data memory
c) program memory d) register memory

5. The 8051 series of microcontrollers are ____bit.

a) 8-bit b) 32-bit
c) 16-bit d) 64-bit

6. The 8096 series of microcontrollers are _____bit.

a) 8-bit b) 32-bit
c) 16-bit d) 64-bit

7. The _____ contains a boolean processor, full duplex serial port and power saving
circuitry.
a) 8086 b) 8085
c) 8071 d)8051

8. A _____ is a dedicated internal timer which resets the system when the software does not
operate properly.
a) interrupt b)watch dog timer
c) trap d) controller

9. The 8051 microcontroller has _____ versions.

a)4 b) 3
c) 2 d) 1

10. ______ are versions of 8051 microcontrollers.

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 a) COMMERCIAL & EXPRESS b) COMMAND & EXPRESS
c) COMMERCIAL & EXPERT d) COMMAND & EXPERT

11. The operating temperature range for commercial version is _____.

a) 0° to 40° C b) 0° to 50° C
c) 0° to 60° C d) 0° to 70° C

12. The operating temperature range for commercial version is _____.

a) 0° to 40° C b) 40° to +85° C
c) -85° to 40° C d)4 0° to 0° C

13. _____ is an accumulator based microcontroller.

a) 8086 b) 8085
c) 8071 d)8051

14. The _____ of 8051 is used during multiply and divide operations.
a) Register D b) Register C
c) Register B d) Register A

15. The 8051 is provided with _____ banks of working registers.

a) 1 b) 2
c) 3 d) 4

16. The 8051 microcontroller contains ____ 8-bit parallel ports.

a) 4 b) 3
c) 2 d) 8

17. All ports in 8051 are _____.

a) bi directional b) unidirectional
c) serial d) parallel

18. The 8051 microcontrollers has ____ level priority interrupts.

a)2 b) 3
c) 4 d) 5

19. The function register IE is expanded as _____.

a) Interrupt Enable b) Internal Enable
c) Internal Exchange d) Interrupt Exchange

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20. The ____ register contains a global disable bit.
a) Interrupt Exchange b) Internal Enable
c) Internal Exchange d) Interrupt Enable

21. The IE has a global disable bit that____ all the interrupts.
a)enables b) disables
c) neutralizes d) ignores

22. The ____processor posses Boolean processing capability.

a)8086 b) 8056
c) 8051 d) 8085

23. The carry flag serves as accumulator when 8051 performs _____logical operations.
a) 1bit b) 2bit
c) 3bit d) 4bit

24. The carry flag serves as accumulator when 8051 performs1bit _____ operations.
a) arithmetic b) logical
c) data transfer d) stack and I/O

25. The 8051 has _____instructions.

a) 11111 b) 1111
c) 11 d) 111

26. The 8051 takes 1microsecond for _____.

a) addition b) subtraction
c) multiplication d) division

27. The 8051 takes _____microseconds for multiplication or division.

a) 1 b) 2
c) 3 d) 4

28. PWM is expanded as _____.

a) pulse window modulation b) pulse width modulation
c) pulse wave modulation d) none of the mentioned

29. Where true analog signal is required _____can be employed.

a) packet b) pulse
c) modulation d) filter

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30. A _____ can be employed to give smooth analog signal.
a) packet b)filter
c) modulation d) pulse

31. Digital to analog conversion can be achieved by employing _____.

a) PWM technique b) filters
c) microcontroller d)interrupt enable

32. The term _____means that it can transmit and receive simultaneously.
a) duplicate b) full duplex
c) half duplex d) modulation

33. The _____mode is used to interface standard i/o devices like crt, teletypewriter, modem
etc.
a) HSIO b) OTP
c)EPA d) UART

34. The 8051 has_____ power saving modes.

a) 2 b) 3
c)4 d) 5

35. The _____series of microcontrollers has register to register architecture.

a)8085 b) 8086
c) 8096 d) 8088

36. The CPU contains a 256-byte RAM which is called _____.

a) RAM file b) register file
c) data file d) ROM file

37. The power saving modes are_____.

a) idle and power down b) wait and power down
c) wait and power on d) idle and power on

38. OTP is expanded as _____.

a) One Time Password b) One Time Programmable
c) On Time Password d) On Time Programmable

39. HSIO is expanded as_____.

a) High Specific Input Output b) Heavy Speed Input Output
c) Heavy Specific Input Output d) High Speed Input Output

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40. EPA is expanded as _____.
a) Enable Processor Array b)Enable Program Array
c) Event Processor Array d) Event Program Array

41. The _____ performs input event capture an output event generation function.
a) EPA b) PWM
c) HSIO d) OTP

42. PTS is expanded as _____.

a) Peripheral Timer Server b)Peripheral Transaction Server
c) Port Timer Server d) Port Transaction Service

43. _____ is an interface between the microcontroller and a host microprocessor.

a) EPA b) PWM
c) HSIO d) Slave Port

44. _____ is a micro coded hardware interrupt processor.

a) EPA b)PTS
c) HSIO d) Slave Port

45. SSIO is expanded as _____.

a) Serial Synchronous I/O Port b) Synchronous Service I/O Port
c) Synchronous Serial I/O Port d) Service Synchronous I/O Port

46. _____gives PWM output and three phase sinewave output with minimal cpu interaction.
a) EPA b) PTS
c) HSIO d)Waveform generator

47. SFR is expanded as _____.

a) Slow Function Register b) Special Formula Register
c) Special Function Register d) Synchronous Flow Register

48. The _____is a 32 bit RISC microcontroller.

a) 8085 b) 8086
c) 8051 d) MPC505

49. The _____is an 8-bit microcontroller with on chip serial communication controller.
a)RUPI44 b) 8086
c) 8051 d) MPC505

27
50. The _____belong to the RUPI44 family of processors.
a) Intel 8044,8344 &8744 b) Intel 8085,8344 &8744
c) Intel 8051,8344 &8744 d) Intel 8044,8344 &8085

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Answers:
1. d) microcontroller 26. a) addition
2. a) embedded controller 27. d) 4
3. c) program memory 28. d) all of the mentioned
4. b) data memory 29. d) filter
5. a) 8-bit 30. b)filter
6. c) 16-bit 31. a) PWM technique
7 d) 8051 32. b) full duplex
8. b)watch dog timer 33. d) UART
9. c) 2 34. a) 2
10. a) COMMERCIAL & EXPRESS 35. c) 8096
11. d) 0° to 70° C 36. b) register file

12. b) 40° to +85° C 37. a) idle and power down

38. b) One Time Programmable
13. d)8051
39. d) High Speed Input Output
14. c) Register B
40. c) Event Processor Array
15. d) 4
41. a) EPA
16. a) 4
42. b)Peripheral Transaction Server
17. a) bi directional
43. d) Slave Port
18. c) 4
44. b) PTS
19. a) Interrupt Enable
45. c) Synchronous Serial I/O Port
20. d) Interrupt Enable
46. d)Waveform generator
21. b) disables
47. c) Special Function Register
22. c)8051
48. d) MPC505
23. a) 1bit
49. a)RUPI44
24. b) logical
50. a) Intel8044,8344 &8744
25. d) 111

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