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OSCA-Buses
SECTION A
Multiple Choice Questions
3. The ALU is the component of the CPU where __________ and ________.
a) data is stored; instructions are interpreted
b) data is held temporarily; calculations are made
c) calculations take place; instructions are executed
d) programs are decoded; instructions are fetched
5. A register is a single permanent storage location within the CPU use for _________
a) specifically designed for fetching instructions
b) specifically designed for arithmetic operations
c) specifically designed for I/O operations
d) a particular, defined purpose
13. The Memory Data Register (MDR) and the Memory Address Register (MAR) are
designed such that it
a) the MDR activates the Bus Interface Unit while the MAR reads bits that are
activated
b) the MDR activates the desired address line while the MAR reads bits that are
activated
c) the MAR activates the desired address line while the MDR reads bits that
are activated
d) the MAR copies the contents of a line into a buffer while the MDR processes
the buffer
15. When retrieving or storing data at a particular memory location, the first step in the
CPU memory interaction is to __________.
a) allocate the MAR the necessary number of bits to retrieve the address line
b) transfer data from some register to the MDR (for a WRTE) OR transfer data
from the MDR to some register (for a READ)
c) send a message to the Control Unit stating there is a READ (or WRITE
condition)
d) copy an address from some register to the MAR
16. When retrieving or storing data at a particular memory location, the two actions that
occur simultaneously are___________.
a) (1) copy an address from some register to the MAR and (2) send a message to
the control unit stating there is a READ (or WRITE condition)
b) (1) copy an address from some register to the MAR and (2) send a
message to the memory unit stating there is a READ (or WRITE
condition)
c) (1) copy an address from some register to the MDR and a message to the
memory unit stating there is a READ (or WRITE condition)
d) (1) Load (or read) the MAR with data to be transferred, and (2) send a
message to the memory unit stating there is a READ (or WRITE condition)
17. The two factors that determine the capacity of the address space are ________.
a) the number of bits in the memory address register and the number of bits
in the address field
b) the size of memory and the number of bits in the address field
c) the number of bits in the memory address register and the size of memory
d) the word length format and the hardware
18. The number of address that the MAR can access is ________ the size of the address
field
a) always 2k where k is the number of bits
b) at least 2k where k is the number of bits
c) at most 2k where k is the number of bits
d) at least 2k -1 where k is the number of bits
25. The physical connection that makes it possible to transfer data from one location to
another is called a _________.
a) registers
b) bus interface unit
c) bus
d) control unit
27. When a bus connects a specific source to a specific destination they are called
_______ buses.
a) 'source – destination'
b) integrated
c) dedicated
d) point-to-point
28. The cable that connects the serial or parallel port to the printer is an example of a
______bus.
a) 'source – destination'
b) integrated
c) dedicated
d) point-to-point
Pipeline
SECTION A
Review Questions - Answer True or False
3. ___F___ Throughput is the time it takes for an instruction to get through the pipeline.
SECTION B
Multiple Choice Questions