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    10 views16 pages

    Untitled

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    Victor Richard

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    © All Rights Reserved
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    of 16
    6 os) a oO ey (2 (3) (60) United States Patent Casady et al. SELF-AL NED TRANSISTOR AND DIODE, IES IN SILICON CARBIDE OF SELECTIV! CTIVE IMPLANTATION Inventors: Jeffrey B. Casady, (US); Geoffrey B. Carter, Sahllo, MS (US); Yaroslav Koshk, Starkville, MS (US); Michael S. Mazzola, Starkville, MS (US); Igor Sankin, Starkville, MS (vs) Starkville, MS Assignee: Mississippt State Unlversity-Researeh and Technology Corporation (RTO), Us Mississippi State, MS Notice: Subject to any disclaimer, the term ofthis patent is extended or adjusted under 35 USC. I54tb) by O days Appl. No. Filed: 10/193,108 Jul. 12, 2002 Prior Publication Data US 2003041195 AL Feb, 20,2008, Related U.S. Application Data Provisional application No. 607304423, filed on Jul. 12, ‘US00676778382 US 6,767,783 B2 (10) Patent No. (5) Date of Patent: Jul. 27, 2004 G1) Int HOLL 21/8239 (2) US.CL “438/234; 438/235; 438,256; 438/237, 438/238 (58) Fleld of Search 438/285-238 6s References Cited US. PATENT BOCUMENTS Soom A” 4200 Se asset bt ame2 Aaa * cited by examiner Primary Esaminer—Loog, Phase (74) Attorney, Agent, or Firm—Piper Rudnick L.LLPs even B. Kelber 6 ABSTRACT ‘A method of making vertical diodes and transistors in SiC is provided. The method avcording to the invention uses a ‘mask (et, 2 mask that has been previously used for etching Features into the device) for selective epitaxial growth or selective ion implantation. In this manner, the gate and base regions of sale induction tansisors and bipolar junction {ransistors can be formed ina sell-aligned process. Ametod of making planar diodes and planar edge termination struc tures (eg. guard rings) i aso provided. 27 Claims, 8 Drawing Sheets CLLLLLLL LLL LLL LLL LTT LLL LL U.S. Patent Jul. 27, 2004 Sheet 1 of 8 US 6,767,783 B2 Ge] ies] 18 | FIG.1A 0 2 FIG.1C U.S. Patent Jul. 27, 2004 Sheet 2 of 8 US 6,767,783 B2 U.S. Patent Jul. 27, 2004 Sheet 3 of 8 US 6,767,783 B2 wf =] (pf { i SS. a 3 F if fa at A 2B FIG.3B q "7 FIG.3C U.S. Patent Jul. 27, 2004 Sheet 4 of 8 US 6,767,783 B2 FIG.4C U.S. Patent Jul. 27, 2004 Sheet 5 of 8 US 6,767,783 B2 U.S. Patent Jul. 27, 2004 Sheet 6 of 8 US 6,767,783 B2 g 18 is EJ FIG.6A a | 88 ® | 86 2 EJ a FIG.6B iC C Ta U.S. Patent Jul. 27, 2004 Sheet 7 of 8 US 6,767,783 B2 108 108 Yio# | wm | tot) 102 Po FIG.7A FIG.7B FIG.7C US 6,767,783 B2 Sheet 8 of 8 Jul. 27, 2004 US. Patent 6'9l4 <7 LUI II Vee Sfb On Ov Onl Ov Om CLR RRR RRR zt: LCR KOs, Da WW el $ gel SN US 6,767,783 B2 1 SELF-ALIGNED TRANSISTOR AND DIODE TOPOLOGIES IN SILICON CARBIDE THROUGH THE USE OF SELECTIVE EPITAXY OR SELECTIVE IMPLANTATION (CROSS-REFERENCE TO RELATED "APPLICATIONS, ‘This application claims priority from US. Provisional Application Serial No. 60/304,423 fled Jul 12, 2001. The entirety of tha provisional application is incorporated her by reference, BACKGROUND OF THE INVENTION 1. Field of the Invention This invention applies to advanced SiC deviees for high- speed, high-power applications such as compact efficient power amplifiers im radar transmitters in airborne and ‘ground-based radar systems and high-power density switeh- ‘ng applications such as high-vollage DC-DC converters and 2, Background of the Technology ‘Two of the most common types of vertical SiC poswer teunsistors are the Static Haduetion Transistor (SIT) and the Bipolar Junction Transistor (BIT). These devices are described in more detail below. ‘The SIT is a vertical MESFET or JFET type device ‘wherein the gates ae close together resulting in space charge limited curent conduction. The device characteristics look much like triode rather than a conventional FET. The advantages of using an SIT area result of its high vollage fain and good impedance characteristics, which reslt in & high power gain. In SiC, the device performance is further ‘enhanced by the high savration velocity (e 8. 1.5-2x that of Si) and high electri field breakdewa siength (6. 10 thal ‘of Si), Based on SiC’s high thermal conductivity and suit ability for use at high-emperatures, a silicon carbide SIT ‘device should produce substantial improvements over Si technology. ‘An SIT can have either PN or Schottky gates Aadlitionally, current in an SIT is controlled by the electric field applied to the dean and gate regions. Most SITs in SiC have used Schottky metal gates. Se, for example, U.S. Pat. Nos. 5,945,701; 5,903,020, 5,807,773; and 5,0123547. See also Henning et al, “A Novel Self Aligned Fabrication Process for Microwave Static Induction Transistors in Sili- ‘con Carbide” Electton Device Letters, 21, 578-580 ( Using a Schottky gate in an SIT or MESFET will typically Timit the junction temperature 10 about 250° C. because leakage cirents exponentially increase through the Schot- tky gate with ineeasing temperatuce, ‘Mach of the early work on the SIT in SiC focused on ‘developing highly uniform, highly controlled epitaxy layers forthe drift and channel regions, The early successes of the device were direct result of improved epitaxy vniformity through the wse of wafer rotation and a better understanding ‘of epitaxial growth mechanisms. ‘Most of the fabrication difculies cureenly being expe= rienced in low-cost volume manufacturing ean be traced level processing steps. Fis, the eurrent- iy ofthe SIT is highly sensitive tothe width ‘of the channel regions, which i se by patterned reactive ion ‘etching (RIE). However, after RIE, itis usally necessary to perform theemal oxidation in order to form a high

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