Subject and Code: 'Digital Techniques (22320)’ Academic Year: 2022-23

Course Name: COMPUTER ENGINEERING Semester: THIRD

A STUDY ON

‘Design a Circuit using Full Adder ’

MICRO PROJECT REPORT
Submitted in December 2022 by the group of students

Sr.N Roll Names of Students Enrollment Seat no

o no no
1 49 Anurag Dwivedi 2216020125
2 50 Yash Gabhale 2216020132
3 51 Darpan patil 2216020126
4 52 Diksha Warke 2216020138

Under the Guidance of

Prof.

Three Years Diploma Programme in Engineering & Technology of Maharashtra

State Board of Technical Education, Mumbai (Autonomous) ISO 9001:2008
(ISO/IEC-27001:2013)

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION,

MUMBAI

1
 CERTIFICATE

This is to certify that Anurag dwivedi

Roll No: 49 of THIRD Semester of SECOND year Diploma in COMPUTER
ENGINEERING at ST. JOHN COLLEGE OF ENGINEERING & MANAGEMENT
has completed the Micro Project satisfactorily in Subject ‘Digital Techniques (22320)’in
the academic year 2022-2023 as prescribed in the MSBTE prescribed curriculum of I
Scheme.

Place: Palghar Enrollment No:

Date: / / Exam. Seat No: ___________

Project Guide Head of the Department Principal

Seal of
Institute

2
 CERTIFICATE
This is to certify that Yash Gabhale

Roll No: 50 of THIRD Semester of SECOND year Diploma in COMPUTER

ENGINEERING at ST. JOHN COLLEGE OF ENGINEERING &
MANAGEMENT has completed the Micro Project satisfactorily in Subject
‘Digital Techniques (22320)’in the academic year 2022-2023 as prescribed in the
MSBTE prescribed curriculum of I Scheme.

Place: Palghar Enrollment No:2116020050

Date: / / Exam. Seat No: ___________

Project Guide Head of the Department Principal

Seal of
Institute

3
 CERTIFICATE
This is to certify that Darpan Patil

Roll No: 51 of THIRD Semester of SECOND year Diploma in COMPUTER

ENGINEERING at ST. JOHN COLLEGE OF ENGINEERING &
MANAGEMENT has completed the Micro Project satisfactorily in Subject 'Digital
Techniques(22320)’in the academic year 2022-2023 as prescribed in the MSBTE
prescribed curriculum of I Scheme.

Place: Palghar Enrollment No:

Date: / / Exam. Seat No:

Project Guide Head of the Department Principal

Seal of
Institute

4
 CERTIFICATE
This is to certify that Diksha Warke

Roll No: 52 of THIRD Semester of SECOND year Diploma in COMPUTER

ENGINEERING at ST. JOHN COLLEGE OF ENGINEERING &
MANAGEMENT has completed the Micro Project satisfactorily in Subject ‘Digital
Techniques (22320)’in the academic year 2022-2023 as prescribed in the
MSBTE prescribed curriculum of I Scheme.

Place: Palghar Enrollment No:

Date: / / Exam. Seat No:

Project Guide Head of the Department Principal

Seal of
Institute

INDEX
5
Sr Topic Pg
No. no.
1. Abstract
2. Introduction
3. Circuit diagram
4. Output
5. Resources used
6. Conclusion
7. Weekly report

6
 Abstract

Our group micro project is to implement a circuit using a full adder.

The following report details for Full Adder, an Adder is digital logic
circuit in electronics implement the addition of number. Basically it
consist of XOR and AND Gate where XOR is used to calculate sum
and AND is used carry. The full adder circuit has three inputs: A, B and
Cin and two outputs sum and carry. This three input are added to
generate a carry and sum. Binary Adders are arithmetic circuits in the
form of full-adders used to add two binary digits.

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 Introduction
Definition:
Full Adder is the adder that adds three inputs and
produces two outputs. The first two inputs are A and B and the
third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S
which is SUM. A full adder logic is designed in such a manner
that can take eight inputs together to create a byte-wide adder
and cascade the carry bit from one adder to another. we use a
full adder because when a carry-in bit is available, another 1-bit
adder must be used since a 1-bit half-adder does not take a carry-
in bit. A 1-bit full adder adds three operands and generates 2-bit
results.

Block Diagram:

Block Diagram

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 Truth Table:

Circuit Diagram

9
 Output:

Pin Diagram:

10
K-maps :

1. Sum:

2.Carry:

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 Resource used

Sr Name of Specification Quantity Remarks

No Resource
.
1 Hardware: Comp(i3-i5) 1
Computer RAM mini
System 2GB
2 Operating Window 11 1
system
3 Software Turbo c 1

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 Conclusion

We have successfully implemented a Full adder circuit and carried out

the addition of three-bit binary digits using AND (IC 7408 ), XOR(IC
7486), and OR(IC 7432). We have proved the truth table of a full adder
by performing the practical. We have also used Karnaugh Map to get
the Boolean expression for sum and carry.

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 Weekly report

Sr. Date Timing Work or activity Sign of

No. Performed the
From To Duration Guide
in hours

1 20/11/2022 1:30 2:30 One hour Discussion and

Finalization of the Project
Title

2 22/11/2022 1:30 2:30 One hour Preparation and

Submission of Abstracts

3 24/11/2022 1:30 2:30 One Literature Review

hour

4 26/11/2022 1:30 2:30 One hour Collection of Data

5 28/11/2022 1:30 2:30 One Collection of Data

hour

6 30/11/2022 1:30 2:30 One hour Discussion and Outline of

Content

7 01/12/2022 1:30 2:30 One Rough Writing of the

Hour Projects Contents

8 02/12/2022 1:30 2:30 One hour Editing and Proof Reading

of the Contents

9 03/12/2022 1:30 2:30 One Final Completion of the

hour Project

10 04/12/2022 1:30 2:30 One hour Seminar Presentation,

viva-vice,
Assessment and
Submission of Report

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