UART

ASIC 2023

PROJECT REPORT - UART

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S.No Topic Page No.

1. PROJECT STATEMENT 3
2. FUNCTIONAL SPECIFICATIONS 3
INTRODUCTION 3
BASIC CONCEPT 3
APPROACH 4
SYSTEM DIAGRAM 4
3. WORKING 5
4. SIMULATIONS 6
5. RTL SCHEMATIC 11
6 REFERENCES 14
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PROJECT STATEMENT

The problem at hand is to design and implement a UART (Universal Asynchronous

Receiver/Transmitter) protocol using Verilog, which can be integrated into digital systems to
enable serial data transmission. The UART protocol is widely used for its simplicity and versatility
in communicating with various peripheral devices, and its implementation using Verilog will
enable the design of efficient and reliable digital systems. The main challenges in this project will
include generating accurate baud rates, implementing start and stop bit detection, and ensuring
correct data transmission through error detection and correction techniques. The developed
UART protocol should be verified through simulation and testing to ensure its correctness and
compatibility with standard communication protocols.

FUNCTIONAL SPECIFICATIONS

Introduction

UART (Universal Asynchronous Receiver/Transmitter) is a popular communication interface used for

serial communication between devices. It is commonly found in microcontrollers, embedded systems,
and communication modules.
UART communication typically involves two devices: a transmitter and a receiver. The transmitter
sends data to the receiver by converting parallel data into a serial stream of bits. The receiver converts
the serial stream of bits back into parallel data.
UART communication is widely used for interfacing microcontrollers with other devices, such as
sensors, displays, and communication modules. It is a simple and reliable communication interface
that can operate over short distances and at low data rates.

Basic Concept

UART works by sending and receiving data in a sequential manner, bit by bit, over a single
communication line. It uses two signal lines, one for transmitting data (TX) and one for receiving data
(RX). The data is transmitted in a series of bits, with each bit being sent one at a time, starting with the
least significant bit.
The UART protocol uses a start bit, a specified number of data bits, an optional parity bit, and one or
more stop bits to define each data frame. The start bit is always a low level signal, and the stop bit or
bits are always high level signals. The number of data bits and the use of a parity bit depend on the
specific application requirements.
UART can be configured for different baud rates, which determine the speed of communication. The
baud rate is the number of bits per second that can be transmitted over the communication line. The
two devices communicating must use the same baud rate to ensure reliable data transmission.
The basic frame structure is shown in the below figure 1.
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Fig. 1 Basic UART Frame Structure

Approach

To develop a UART protocol, we should be first clear with full understanding of the UART protocol
before coding, so we started with specification reading from specification document and extracted
the different features of UART protocol.
Next we planned a top module design of UART protocol and created a test plan to verify the
design. Best way to create a complex design is using the Finite State Machine(FSM) approach so
we created FSMs for both transmitter and receiver design.
We implemented many testcases which were used to verify the design, and find many bugs in the
design and debugged the design using waveforms.

System Diagram
System for transmitter side is shown in the figure 2 below and receiver side is shown in figure 3.
Working of each module is described in the subsequent topics.

Fig. 2 UART Transmitter System

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Fig. 3 UART Receiver System

WORKING
Transmitter
Transmitter module will work with the use of finite state machine, FSM state diagram is shown in the
figure 4 below. FSM or transmitter will be in the IDLE state and will start the transmission when the
start control signal is activated. Next state will be LOAD where data from either FIFO memory or data
bus will be loaded based on the mode.

Fig. 4 FSM for Transmitter Module

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FIFO will be used to store the data in the FIFO mode and then UART can transmit the data at lower
speed one by one. The FIFO write side will be working with high frequency input clock and read side
will be working with baud clock generated by clock generator.
Next in the START state, start bit will be sent with desired baud rate and oversampling rate. Next
based on the length of the data, data bits will be sent one by one on the same baud rate.
Next step will be parity which is optional so based on the input provided by the user, parity will be
calculated and will be transmitted along with data if required. And at last stop bit will be transmitted
based on user’s choice and FSM will be moved to IDLE or START state.

Receiver
Receiver module will also work similar way with the use of finite state machine, FSM state diagram is
shown in the figure 5. Initially FSM will be in the IDLE state and will start to receive the signal as soon
as the start control signal is activated. Next state will be START state, where constantly line will be
checked for start condition generation.

Fig. 5 FSM for Receiver Module

So next state will be DATA_RX state, where data will be sampled at certain time period and will be
stored in the receiver FIFO memory, which can be read by top module using read signals.
Next based on the parity enable conditions, parity will be checked error will be throwed in case if
parity mismatches. And at the end stop conditions will be detected and data received will be stored in
the FIFO.

SIMULATIONS

To verify our RTL design, we created a test bench with different testing scenarios. We instantiated both
transmitter and receiver in the single testbench file, where we gave the output of transmitter to receiver’s
input. There are lots of possible testcases available to test the design, here we have mentioned some of
the testcases.
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1. Sanity Test for single later transfer
2. Sanity Test for multiple later transfer with FIFO Mode
3. Sanity Test for multiple later transfer with Non-FIFO Mode
4. Variable data length transfer check
5. Variable stop bit transfer check
6. Parity and error check scenario
7. Noise effect Test

1. Sanity Test for single later transfer

Fig. 6 Output on Terminal

Fig. 7 Output waveform on gtkwave

2. Sanity Test for multiple later with FIFO Mode

Fig. 8 Output on Terminal

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Fig. 9 Output waveform on gtkwave

3. Sanity Test for Multiple later transfer with non-FIFO Mode

Fig. 10 Output on Terminal

Fig. 11 Output waveform on gtkwave

4. Variable Data Length Transfer Check

Fig. 12 Output on Terminal

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Fig. 13 Output on gtkwave

5. Variable Stop Bit Transfer Check

Fig. 14 Output on terminal

Fig. 15 Output waveforms on gtkwave

6. Parity and error checking sequence

Fig. 16 Output on terminal

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Fig. 17 Output waveforms on gtkwave

7. Noise Effect Check

Fig. 18 Output on terminal

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RTL SCHEMATIC

RTL Schematic for both module is shown in below figures, which shows the top level diagram of the
circuit.

Fig. 19 RTL Schematic for Transmitter Module

Fig. 20 RTL Schematic for FIFO Memory

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Fig. 21 RTL Schematic for UART_Tx module

Fig. 22 RTL Schematic for Receiver Module

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Fig. 23 RTL Schematic for UART_Rx module

Fig. 24 RTL Schematic for Clock Generator

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REFERENCES

• https://www.realdigital.org/doc/7d93df01f5ae9bcb7a0e6859badee09c

• UART: A Hardware Communication Protocol Understanding Universal Asynchronous

Receiver/Transmitter | Analog Devices

• https://www.circuitbasics.com/basics-uart-communication/