STANDARD CELL LIBRARY CHARACTERIZATION USING

STATIC CMOS
STANDARD CELL LIBIRARY:

A standard cell library is a collection of well defined and pre characterized logic cells of fixed
height with multi drive strength and multi threshold voltage cells in the form of a predefined standard cell
layout. It also consists of set of library files required by place and route tool for automatic placement and
routing.

LIBRARY CHARACTERIZATION:

Library characterization is a process of simulating a standard cell to extract input load, speed, and
power data under both best and worst PVT conditions.

PROCEDURE TO CREATE OWN STANDARD CELL LIBRARY:

1. Create a folder and open a terminal and invoke the cadence tool using the following commands
and CIW window opens

2. In CIW window Click file → new →library a window opens provide a new user defined library
name and select attach to the existing technology library then click ok
3. A new window will open in which select the umc90nm as technology library

4. After creating library click file →new→cellview a window will open select the library created
and provide the cell name for the schematic then click ok

5. The schematic window opens draw the schematic diagram of a logic gate and save it.
6. The next step is to create the symbol for the schematic for that click create option on the
toolbar→cellview→from cellview a window opens check for the correct library, cellview name
and select tool type as schematicsymbol click ok

7. Provide the pin specification and click ok. Symbol for the logic gate will be created
Pre-layout Simulation:

• Create a new cellview for testing the created schematic using the symbol
• Simulate the symbol by doing the analyses through ADE environment
8. For layout creation click launch→ layout XL→a window opens select create new click ok then a
layout window opens generate the layout of same height and width.
9. Then check for the DRC and LVS clean

10. Then run the QRC for parasitic extraction

Post -layout simulation:

• After running QRC av_extracted file is created consisting of resistor and capacitor parasitic in
layout.
• This av_extraced file is placed in symbol to do the simulation.
• For this create a config file go to file→ new → provide the same cell name created for pre
simulation → in type select config click ok

• Then new configuration window opens click on use template in that select spectre click ok and
select view as schematic

• A new window opens provide the file name av_exracted in view to use of schematic file of logic
gate click ok now the symbol will have the parasitic information of the logic gate to do post
simulation
GENERATION OF LEF FILE :

1. In CIW window click tools → select technology file manager→Technology tool box window
opens in that click new →Provide a new technology library name and browse the technology file
2. In the technology tool box window click attach and change the technology library to newly
created technology library name

3. Creation of header part of lef file, in CIW click on file→ export→LEF anew window opens
provide the name with .lef extension and select the user defined library name in which logic cells
were created then click ok. Pop up messages with warning can ignore them.

4. Click file→export→stream a window opens in that library browse select the library, cell and cell
view as layout then select technology library as umc90nm
5. Then click show options in that select geometry click on flatten cells, click ok and then translate
repeat the steps for all the logic cells to generate .gds file for each of it

6. In the terminal invoke the abstract tool

7. Abstract window opens

8. Click on file→ library → open and select the user defined library which consist of logic gates
then click ok

9. File→ attach technology library select newly created technology library click ok
10. Click on file→import → stream →browse all the logic cells .gds file one by one then browse the
layer map file then click ok

11. Generating the abstract view in the abstract, select all the cells and click on the pin icon a window
opens in that map provide the necessary pin information
12. Next click on boundary in same window provide the necessary information and click run
13. Click on the extract icon no need to modify anything in that window click run ignore the
warnings

14. Click abstract icon provide the power rail geometries by clicking add for offset value measure the
metal height from origin to lower most height using scale
15. In blockage delete the unused metal layer and via information also enable the pin cutout of all
pins

16. In the site option provide the site name as core since all the cells are of same height, if different
height cells are the group the separately then click run
17. Finally click on the verify icon change the target system to encounter and routing engine to
wroute and click run

18. Go to file → export →LEF go with default name click ok the abstract.lef file will be created
19. Copy the macro information of all the logic cells and paste it in the created .lef file in step 3 after
M1_POLY line and type the core information after the manufacturing grid linein same .lef file
GENERATION OF LIB FILE:

1. Open a cellview in same folder using the name timing and it place all the logic cell symbols
created and save it.

2. Go to launch → ADE L →a window opens in it click setup→a new window pop up in it change
the simulator to spectre and click ok

3. Then go to setup → environment→in switch view list insert the word “analog_extracted” before
the predefined name
4. Then click simulation → netlist → create → save the file as ship_cells.scs

5. Download the characterize.tgz file from the website http://sites.cs.ship.edu/vlsi

6. In the terminal type the command tar xvfz ~/Downloads/characterize.tgz to unzip the folder
7. Names of the cells inside the ship_cells.scs file will be displayed copy it.
8. Then open the template.tcl file in the template folder which is in characterize folder consists of
the default delay, power, pin and much information about the logic cells edit them according to
the need
9. There is one more file named areas.txt open it and edit them by providing actual measured area of
the created cells
10. Then give the command perl area < area.txt a new file named userdata.lib will be created in
LIBRARY folder

11. Then type perl char.tcl the file will be opened check the information provided it
12. Then invoke the tool liberate and then type liberate char.tcl it should run without error and thus
liberty files ship_ccs.lib and ship_ecsm.lib are created in LIBRARY folder
SYNTHESIS THE CREATED STANDARD CELLS:

1. Write the verilog code using the created standard cell

2. Synthesis it using the genus tool by the following command
• set_db library path
• read_hdl modulename.v
• elaborate
• syn_generic
3. Following are the power, area, memory reports generated