11.1. In the circuit of Fig. 11.60, we wish to achieve a — 3-dB bandwidth of 1 GHz with a load capacitance of 2 pF. What is the maximum (low-frequency) gain that can be achieved with a power dissipa- tion of 2 mW? Assume Voc =2.5 V and neglect the Early effect and other ca- pacitances. Vee Ri fout nea Te Figure 11.6011.3. Determine the —3 dB bandwidth of the cir- cuits shown in Fig. 11.62. Assume V4 = co but 2 > 0. Neglect other capacitances. Ye Ye ee ee Yoo Yoo Qe Qe Yeu. Vin’ My, Re Vout Vou Vout Vout Vin Qi TC, Vin Qi re. Vine, = c. Mm, =C, I I tT Lt @ 0) C) @ Figure 11.62 11.6. Anamplifier exhibits two poles at 100 MHz and 10 GHz and azero at 1 GHz. Construct the Bode plot of |Vou/Vin|-*41.10.In Problem 11.9, derive the transfer func- tion of the circuit, substitute s = jw, and obtain an expression for |Viu0/Vin|. De- termine the —3 dB bandwidth of the circuit. 11.9. Figure 11.63 illustrates a cascade of two identical CS stages. Neglecting channel- length modulation and other capacitances, construct the Bode plot of |Vour/Vin|. Note that Vou/Vin = (Vx/Vin)(Vou/Vx)- Ypp Vine My T Cc, Figure 11.63