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ABSTRACT
In higher power applications to utilize the full line power and reduce line current harmonics PFC
Pre-regulators are generally required. In these high power applications interleaving PFC stages can
reduce inductor volume and reduce input and output capacitor ripple current. This results in smaller overall
magnetic volume and filter capacitor volume increasing the converters overall power density. This is made
possible through distributing the power over two interleaved boost converters and the inductor ripple
current cancellation that occurs with interleaving, reference [5]. This application note will review the design
of a 300W two-phase interleaved power factor corrected (PFC) pre-regulator. This power converter
achieves PFC with the use of the UCC28070 interleaved PFC controller, reference [7].
1 Design Goals
The specifications for this design were chosen based on the power requirements of a medium power LCD
TV.
SLUA479B – August 2008 – Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review 1
2 Schematic
UCC28070 PFC controller in a two-phase average current mode control interleaved PFC pre-regulator.
DB
L1
Vin IIN IL1 D1 VOUT
– +
DPA2
DRA
RFA
COUT
T1
1k
CFA RSA CRR RR T1
220pF
GDA ROA
RTA
DRB
RFB Q1
VCC=13V 4.7pF
DPA1
CTA 1k
CFB RSB CRR RR T2
ROB
220pF
4.7pF L2
DPB2
RA1 D2
CTB
UCC28070
RTB
1 CDR DMAX 20
IL2
2 RDM RT 19
DPB1
T2
3 VAO SS 18
RA2
4 VSENSE GDB 17
GDB
5 VINAC GND 16
12V to 21V Q2 CB4
6 IMO VCC 15
RB2
7 RSYNTH GDA 14 1.2nF
8 CSB VREF 13
CCDR
9 CSA CAOA 12
RB1
10 PKLMT CAOB 11
CZV
RIMO RZCB RZCA
RPK1
CB1 CPV CPCB CPCA
CB2 CB3 CSS RRT RDMX
RRDM
1.2nF RSYN
0.1uF 0.1uF CZCB CZCA
RZV RPK2
2 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B – August 2008 – Revised July 2010
3 Inductor Selection
One of the benefits of interleaved PFC boost pre-regulators is inductor ripple current reduction that is seen
at the input of the converter. The following equations and Figure 2 show the ratio of input ripple current
(ΔIIN) to individual inductor ripple current (ΔIL1) in a two-phase interleaved PFC as a function of duty cycle
(D). Because of this inductor ripple current cancellation, the designer can allow each inductor to have
more inductor ripple current than in a single stage design.
DIIN
K(D) =
DIL1
(1)
1- 2D
K(D) = if D is < 05 = 0.5
1- D
(2)
2D - 1
K(D) = if D is > 0.5
D
(3)
K(D)=DIIN/DIL1
D - Duty Cycle
The boost inductors (L1 and L2) are selected based on the maximum allowable input ripple current. In
universal applications (e.g., 85 V to 265 V RMS input) the maximum input ripple current occurs at the
peak of low line and for this design the maximum input ripple current was set to 30% of the peak nominal
input current at low line.
SLUA479B – August 2008 – Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review 3
The following calculations are used to select the appropriate inductance for L1 and L2. Where, variable
DPLL is the converter’s duty cycle at the peak of low line operation. Variable K(DPLL) is the ratio of input
current to inductor ripple current at the peak of low line operation. ∆IL is the boost inductor ripple current
at the peak of low line based on the converters input ripple current requirements.
VOUT - VIN_MIN 2 390V - 85V 2
DPLL = = » 0.69
VOUT 390 V
(4)
2 ´ 0.69 - 1
K(DPLL ) = = 0.55
0.69
4 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B – August 2008 – Revised July 2010
(11)
Two 100-mF capacitors were used in parallel for the output capacitor.
COUT = 200 μF
(12)
For this size capacitor the output peak to peak voltage ripple (VRIPPLE) is:
2 ´ 300W
2 ´ POUT 1 0.90
VRIPPLE = = » 14.5V
h VOUT ´ 2p ´ 2fLINE ´ COUT 390V ´ 2π ´ 2 ´ 47Hz ´ 200 μF
(13)
In addition to holdup requirements, a capacitor must be selected so that it can withstand both the
low-frequency RMS current (ICOUT_LF) and the high-frequency RMS current (ICOUT_HF). High-voltage
electrolytic capacitors generally have both low frequency (100 Hz to 120 Hz) and high frequency RMS
current ratings on their data sheets.
POUT 300W
ICOUT_LF = = » 0.604A
h VOUT 2 0.90 ´ 390V ´ 2
(14)
2
æ P 16 ´ VOUT ö 2
2
ICOUT_HF = ç OUT
ç h VOUT 6p ´ VIN_MIN 2 ÷
(
- h ÷ - ICOUT_LF )
è ø
(15)
2
æ 300W 16 ´ 390V ö 2
ICOUT_HF = ç - (0.90)2 ÷ - (0.604 ) » 1.0A
ç 0.90 ´ 390V 6p ´ 85V 2 ÷
è ø
(16)
SLUA479B – August 2008 – Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review 5
6 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B – August 2008 – Revised July 2010
6 Current Sense Transformers Setup and Selection (T1, T2, DRA, DRB)
The current sense transformer is selected to handle IPEAK and have a peak current sense signal (IRS) of
roughly 100 mA.
NS I 5.1A
NCT = ³ PEAK = = 51
NP IRS 0.1A
(20)
For this design a current sense transformer with a turns ratio (NCT) of 50 was chosen for the design.
NCT = 50
(21)
The magnetizing inductance (LM) of the current sense transformer should be selected or designed so the
magnetizing current is less than 2% of the maximum current sense signal. The following equation
calculates the minimum LM where VS is the maximum current sense signal voltage. For this design a
current sense transformer was designed by Cooper Electronic Technologies (CTX16-18294) with a
magnetizing inductance of 8.25 mH.
VS VOUT - VIN_MIN 2 3.7V 390V - 85V 2
LM ³ ´ = ´ » 6.24mH
IPEAK VOUT 5.1A 390V
´ 0.02 ´ f s ´ 0.02 ´ 200kHz
NCT 50
(22)
LM = 8.25 mH
(23)
Selection of the current sense resistors (RSA and RSB ) is based on the peak current limit signal (VS) and
the peak current on the secondary side of the current sense transformer. A factor of 0.9 was multiplied by
the current sense signal to leave room for the 10% PWM ramp that is used to make this design more
noise immune at lighter loads.
0.9 ´ VS 0.9 ´ 3.7V ´ 50
RSA = RSB = = » 32.5 W
IPEAK 0.102A
NCT
(24)
Select a standard resistor for the design:
RS = 33.2 W
(25)
Resistor RR is used to reset the current sense transformer:
RS ´ DMAX 33.2 W × 0.97
RR ³ = ; 1 kW
1 - DMAX 1 - 0.97
(26)
Current sense transformer’s rectifying diodes (DR) need to be designed to withstand the current sense
transformers reset voltage (VR):
NP 5.1A ´ 1 kW
VR = IPEAK ´ ´ RR = ³ 103V
NS 50
(27)
SLUA479B – August 2008 – Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review 7
To improve noise immunity at extremely light loads, a PWM ramp with a dc offset is recommended to be
added to the current sense signals. Electrical components RTA, RTB, CTA, CTB, DPA1, DPA2, DPB1, and DPB2
form a PWM ramp that is activated and deactivated by the gate drive outputs of the UCC28070. Resistor
ROA and ROB add a DC offset to the CS resistors (RSA and RSB).
When the inductor current becomes discontinuous the boost inductors ring with the parasitic capacitances
in the boost stages. This inductor current rings through the CTs causing a false current sense signal.
Refer to the following graphical representation of what the current sense signal looks like when the
inductor current goes discontinuous. Note that the inductor current and VRSA may vary from this graphical
representation depending on how much inductor ringing is in the design when the unit goes discontinuous.
GDA
IL1
0A
VRSA
VOFF
0V
8 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B – August 2008 – Revised July 2010
To properly select the offset (VOFF) just requires adjusting resistors ROA and ROB to add a dc offset to the
current sense resistors, that is high enough to block DRA and DRB from conducting when a false current
sense signals is present. This occurs when the inductors are operating with discontinuous inductor current
and was described above in detail. Setting the offset to 200 mV is a good starting point and may need to
be adjusted based on individual design criteria and the amount of noise and parasitic elements present in
the system.
VOFF = 0.2 V
(28)
(VVCC - (Vs ´ 0.1- VOFF +VDPA2 )RSA (13V - (3.7V ´ 0.1- 0.2V)+0.6V )´ 33.2
RTA =RTB = = » 2.62 kW
Vs ´ 0.1- VOFF 3.7V ´ 0.1- 0.2V
(31)
Chose a standard resistor for the design:
RTA = RTB = 2.49 kW
(32)
1
CTA = CTB = » 50 nF
RSA ´ fS ´ 3
(33)
A standard capacitor needs to be chosen for the design:
CTA = 47 nF
(34)
SLUA479B – August 2008 – Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review 9
8 Programming VOUT
Resistor RA is selected to minimize the error due to VSENSE input bias current and to minimize loading on
the power line when the PFC is disabled. Construct resistor RA from two or more resistors in series to
meet high voltage requirements. Resistor RB is sized to program the converters output voltage (VOUT).
RA = 3M W
(40)
VREF
´ RA
2 3V ´ 3MΩ
RB = = » 23.3 kW
VREF 390V - 3V
VOUT -
2
(41)
A standard resistor was chosen for the design.
RB = 23.2 kW
(42)
The resistor divider formed by RA and RB from the output voltage to the VSENSE pin also sets the over
voltage protection threshold (VOVP).
R A + RB 3MW + 23.2 kW
VOVP = 3.18V = 3.18V » 414V
RB 23.2 kW
(43)
10 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B – August 2008 – Revised July 2010
SLUA479B – August 2008 – Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review 11
For the highest possible power factor the voltage loop crossover frequency (fCV) needs to be set based on
the following equation:
DVAO = 3.2 V
(49)
POUT 1
η j ´ 2p ´ COUT 1
fCV = H ´ gmV ´ ´ ´
DVAO VOUT 2 ´ p ´ CPV
(50)
300W
1 1
fCV = 0.0077 ´ 70m S ´ 0.90 ´ ´ » 11Hz
3.2V 2 ´ p ´ 200mF ´ 390V 2 ´ p ´ 150nF
(51)
Voltage compensation resistor RZV is then sized to put a pole at the converter’s voltage loop crossover
frequency:
1 1
R ZV = = » 96.4 kW
2p ´ fCV ´ CPV 2p ´ 10.6Hz ´ 150nF
(52)
Select a standard resistor for the design:
R ZV = 100 kW
(53)
Voltage compensation capacitor CZV is used to increase the dc gain of the voltage loop and gives some
added phase margin before crossover. The zero added to the voltage loop needs to be set at 1/10th the
crossover frequency.
1 1
CZV = = » 1.5 mF
fCV 11Hz
2p ´ ´ R ZV 2p ´ ´ 100 kW
10 10
(54)
12 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B – August 2008 – Revised July 2010
The following equations can be used to estimate voltage compensation network gain, voltage loop power
stage gain and voltage loop gain. These equations can also be used to graphically check loop stability.
Voltage Compensation Network Gain (GCV(f)) as function of frequency:
DVVAO j ´ 2p ´ f ´ R ZV ´ CZV +1
GCV (f ) = = H ´ gmV ´
DVOUT æ ´ CZV ´ CPV ö
(j ´ 2p ´ f ´ (CZV + CPV ))ç j ´ 2p ´ f ´C RZV +1÷
è ZV +CPV ø
(55)
Voltage Loop Power Stage Gain (GPSV(f)) as function of frequency:
POUT æ 1 ö
ç ÷
DVOUT η è j ´ 2p ´ f ´ COUT ø
GPSV (f ) = = ´
DVVAO DVAO VOUT
(56)
Voltage Loop Gain in dB (TvdB(f)) as function of frequency:
TvdB( f ) = 20log (GPSV ( f ) ´ GCV ( f ) )
(57)
Figure 4 shows the theoretical loop gain (TvdB(f)) as a function of frequency and Figure 5 shows the
theoretical loop phase (qv(f)) as a function of frequency. From these figures it can be observed that the
voltage loop crossed over at roughly 9 Hz with a phase margin of 60 degrees. Compensating the voltage
loop is not an exact science and should be checked with a network analyzer and adjusted if necessary.
90 90
90 90
60
75
30
60
TvdB ( f) 0
qv( f)45
30
30
60
- 90 15
90 3
1 10 100 1 .10 0
1 f 3 0 3
1´10 1 10 100 1 .10
1 f 3
1´10
Figure 4. Theoretical Voltage Loop Gain (TvdB(f)) Figure 5. Theoretical Voltage Loop Phase (qv(f))
SLUA479B – August 2008 – Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review 13
14 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B – August 2008 – Revised July 2010
200 180
200 180
133.33
150
66.67
120
TcdB( f) 0
qc( f) 90
66.67
60
133.33
- 200 30
200
3 4 5 6
1 10 100 1 .10 1 .10 1 .10 1 .10
6
0
1 f 1´10 0
3 4 5 6
1 10 100 1 .10 1 .10 1 .10 1 .10
1 f 6
1´10
Figure 6. Current Loop Gain (TdB(f)) Figure 7. Current Loop Phase (qc(f))
SLUA479B – August 2008 – Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review 15
12 Soft Start
To have a controlled soft start the CSS capacitor needs to be set to at least the same value as the CZV
capacitor or larger. This means the design has a minimum soft start time based on the CZV capacitor
2.25 V ´ CZV 2.25V ´ 1.5 mF
t SSMIN = = » 338 ms
10 m A 10 m A
(72)
CSS ³ CZV
(73)
The soft-start timing can be set with timing capacitor CSS once the amount of soft start time (tSS) has been
determined. Our original design requirement was to have 200 ms of soft-start time. The calculated
capacitance needed for this soft-start time is less than the minimum required capacitance.
10 m A ´ t ss 10 m A ´ 200 ms
Css = = » 0.889 mF
2.25V 2.25 V
(74)
A CSS capacitor value equal to the CZV capacitor was chosen for the design.
Css = 1.5 mF
(75)
fDR = 10kHz
(77)
6 6
937.5 ´ 10 W 937.5 ´ 10 W
RRDM = = = 31.13 kW
fDM 30 kHz
(78)
CCDR = 220 pF
(81)
16 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B – August 2008 – Revised July 2010
SLUA479B – August 2008 – Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review 17
U1
UCC27324D
+ +
18 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B – August 2008 – Revised July 2010
SLUA479B – August 2008 – Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review 19
VOUT RETURN
C5
HS1
C2
L1 L2
C6 C7
.
D5 T1 . T2
D6
C2
RT1
J1
VAR1 Q1 Q1
F1
HS3 HS2
C11
J2 SYNC
AC LINE AC NEUTRAL VCC
GND
RETURN VOUT
JP2
D1
JP2
D3
D9 D2
R19
R5
R9 R10
R18 R8
U1
C8
C12
R14 C10 D12
D11 R16
R13 R1
C4 D8
D7 R6
D13
C9 C3
R15
R3
R4
D10 D4
J1 R12 R7
R11
R17
R2
AC NEUTRAL AC LINE
20 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B – August 2008 – Revised July 2010
15 Efficiency Curves
A 300-W prototype was built based on the design information presented in this application note. The
following graphs show the performance of this EVM.
Efficiency Efficiency
100% 100%
98% 98%
96% 96%
94% 94%
% Efficiency
92% 92%
% Efficiency
90% 90%
88% 88%
86% 86%
1.41473
1.17894
0.94316
EN61000-3-2 Class D Specifications
Amplitude (A)
0.70737
0.47159
0.23580
0.00001
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Harmonic
SLUA479B – August 2008 – Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review 21
1.000 1.000
0.990 0.990
0.980 0.980
0.970 0.970
0.960 0.960
PF
0.950
PF
0.950
0.920 0.920
0.910 0.910
0.900 0.900
20% 30% 40% 50% 60% 70% 80% 90% 100% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Figure 17. Figure 18. Input Current and Output Ripple Voltage at
Maximum Output Power
Ch2 = IIN, CH2 = VOUT
22 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B – August 2008 – Revised July 2010
Figure 21. VIN = 85 V RMS, Peak of Line Figure 22. VIN = 265V RMS, Peak of Line
Figure 23. VIN = 265V RMS, Line Voltage at Half the Figure 24. VIN = 85 V, POUT = 300 W
Output Voltage
SLUA479B – August 2008 – Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review 23
24 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B – August 2008 – Revised July 2010
15.4 Recovery from Line Dropout, CH1= Rectified Line Voltage, CH2=IL1, CH3=IL2, CH4 =
VOUT
Figure 27. VIN = 85 V, POUT = 300 W Figure 28. VIN = 265 V, POUT = 300 W
SLUA479B – August 2008 – Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review 25
Figure 29. EMI Quasi Peak (QP) Measurement with out Frequency Dithering, No EMI Filter Present
Figure 30. EMI Quasi Peak (QP) Measurement with Frequency Dithering, No EMI filter Present
16 References
1. Lazlo Balogh and Richard Redi, Power Factor Correction with Interleaved Boost, APEC 1993, pp.
168-174
2. Lloyd Dixon, High Power Factor Switching Pre-regulator Design Optimization, Unitrode Power Supply
Design Seminar SEM-700, 1990, Topic 7
3. Brett Miwa, David Otten, Martin F. Schlecht, High Efficiency Power Factor Correction Using Interleaved
Techniques IEEE 1992, pp. 557 to 568
4. Michael O’Loughlin, 350W, Two Phase Interleaved PFC Pre-regulator Design Review, Texas
Instrument Literature Number SLUA369, 2006
5. Michael O’Louglin, An Interleaving PFC Pre-Regulator for High-Power Converters Unitrode/TI Power
Supply Design Seminar SEM-1700, Topic 5
6. P. Zumel, O. Garcia, J. A. Cobos, J. Uceda, EMI Reduction by Interleaving of Power Converters
Presentation, APEC 2004
7. UCC28070 Data Sheet, Texas Instruments Literature Number SLUS794,
http://focus.ti.com/lit/ds/symlink/ucc28070.pdf
26 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B – August 2008 – Revised July 2010
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