VLSI DESIGN LAB

LABORATORY MANUAL
B. TECH
(III YEAR–II SEM)
(2022-23)

Prepared by:

Mr. P.VENKANNA B.Tech, M.Tech, Assistant Professor

Mr. K BABU RAO B.Tech, M.Tech,(P.hD), Assistant Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

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 ELECTRONICS & COMMUNICATION ENGINEERING

VISION

To evolve into a center of excellence in Engineering Technology through creative and innovative practices
in teaching-learning, promoting academic achievement & research excellence to produce internationally accepted
competitive and world class professionals.

MISSION

To provide high quality academic programmes, training activities, research facilities and opportunities
supported by continuous industry institute interaction aimed at employability, entrepreneurship, leadership and
research aptitude among students.

QUALITY POLICY

 Impart up-to-date knowledge to the students in Electronics & Communication area to make them quality
engineers.
 Make the students experience the applications on quality equipment and tools.
 Provide systems, resources and training opportunities to achieve continuous improvement.
 Maintain global standards in education, training and services.

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 LABORATORY RULES
General Rules of Conduct in Laboratories:

1. You are expected to arrive on time and not depart before the end of a laboratory.
2. You must not enter a lab unless you have permission from a technician or lecturer.
3. You are expected to comply with instructions, written or oral, that the laboratory Instructor gives you during
the laboratory session.
4. You should behave in an orderly fashion always in the lab.
5. You must not stand on the stools or benches in the laboratory.
6. Keep the workbench tidy and do not place coats and bags on the benches.
7. You must ensure that at the end of the laboratory session all equipment used is stored away where you found
it.
8. You must put all rubbish such as paper outside in the corridor bins. Broken components should be returned to
the lab technician for safe disposal.
9. You must not remove test equipment, test leads or power cables from any lab without permission.
10. Eating, smoking and drinking in the laboratories are forbidden.
11. The use of mobile phones during laboratory sessions is forbidden.
12. The use of email or messaging software for personal communications during laboratory sessions is forbidden.
13. Playing computer games in laboratories is forbidden.

Specific Safety Rules for Laboratories:

1. You must not damage or tamper with the equipment or leads.

2. You should inspect laboratory equipment for visible damage before using it. If there is a problem with a piece of
equipment, report it to the technician or lecturer. DONOT return equipment to a storage area.
3. You should not work on circuits where the supply voltage exceeds 40 volts without very specific approval from
your lab supervisor. If you need to work on such circuits, you should contact your supervisor for approval and
instruction on how to do this safely before commencing the work.
4. Always use an appropriate stand for holding your soldering iron.
5. Turn off your soldering iron if it is unlikely to be used for more than 10 minutes.
6. Never leave a hot soldering iron unattended.
7. Never touch a soldering iron element or bit unless the iron has been disconnected from the mains and has had
adequate time to cool down.
8. Never strip insulation from a wire with your teeth or a knife, always use an appropriate wire stripping tool.
9. Shield wire with your hands when cutting it with a pliers to prevent bits of wire flying about the bench.

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B.Tech. VI Semester COURSE CODE: UR20PCEC612
VLSI DESIGN LAB Internal Marks: 15
External Marks: 35

COURSE OBJECTIVES:
1. Apply the concepts of basic combinational logic circuits, sequential circuit elements and programmable logic in
the laboratory setting.
2. To develop familiarity and confidence with designing. Building and testing digital circuits including the use of
CAD tools.
3. Behavioural register transfer logic and physical – level structured VLSI design using CAD tools and hardware
description language.
COURSE OUTCOMES:
At the end of the Course, Student will be able to:
1. Write HDL code for basic as well as advanced digital integrated circuits.
2. Import the logic modules into FPGA Boards.
3. Ability to design the logic circuits.
4. Synthesize, place and Route the digital IP’s.
5. Design, implement and simulate circuits using VHDL.
6. Design, simulate and extract the layouts of anlaog IC blocks using EDA tools.
E – RESOURCE: 1.
https://nptel.ac.in/courses/111/107/111107105/ 2. https://nptel.ac.in/courses/111/105/111105123/

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 LIST OF EXPERIMENTS
CYCLE-I

PAGE
S.NO. EXPERIMENTNAME NO.
1 Realization Of Logic Gates 14
2 18
4-bit ripple carry and carry look ahead adder using behavioural, dataflow
and structural modelling.
3 a.) 16:1 MUX through 4:1 MUX. 21
3:8 decoder realization through 2:4 decoder
4 8:3 encoder
31
5 8-bit parity generator and checker 33
6 35
Flip-Flops
7
8-bit synchronous up-down counter 40

8 42
4-bit sequence detector through Mealy and Moore s machines.

CYCLE-II
S.NO. EXPERIMENTNAME PAGENO.
1 Design and Implementation of Universal Gates 43
2 Design and Implementation of An Inverter 45
3 Design and Implementation of Full Adder 47
4 Design and Implementation of Full Subtractor 49
5 Design and Implementation of Decoder 51
6 Design and Implementation of D-Flip flop 52

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 Xilinx Vivado Procedure:

1. On desktop, Double Click on Xilinx Vivado 2018.1 icon. Then It opens the design suite window as
shown below

2. Click Create New Project. A new project creation wizard will pop up. Click Next and then name the
project "project_1". Select the project location (D:/Your H.T.No) and tick project directory and click
next.

3. Choose RTL project and tick the “do not specify sources at this time” and click next.
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 4. Select the default part which the program is dumped into the FPGA board (XC7A35TFTG256-1). Then
click next and then finish.

5. Now, Go to Project Manager on left pane, then Click on Add Sources and select “Add or
Create Design Sources” then click “Create File” then give a file name(EX: LogicGates) and click ok and
click finish.

6. Here, we need to define the input and output ports based on our requirement, we can define bus/vector
here itself.
7. Now the Project and Source file created, then double click on source file which we are defined, it will
display the HDL code editor window on right side, then enter the code and save it

Note: after saving the code, if any errors are exists, it will automatically detect, highlights the text in red
color, if errors can be fix it and save the HDL code.

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 SIMULATION

8. Now go to Flow Navigator tab on left side, and then click on simulation--> Run Simulation--
>Run Behavioral Simulation.

9. Here, the simulation window is automatically displayed, now go to objects tab, and then right click on
input--- >select force clock---> radix value-binary/Hexadecimal----> leading
edge value=1, Trailing edge value=0, period=10ns then click OK.

10. Now, click on RUN all (Press F3) button, then verify the waveforms.

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11. Now go to Flow Navigator---> RTL Analysis---> Open Elaborated Design ----> click on Schematic (i.e.
RTL Schematic).

SYNTHESIS

12. Now, go to Flow Navigator---> Synthesis ---> Run Synthesis.

Note: It takes some time for synthesis process; status will be displayed at the top right side of window. After
successful completion, it displays a window, select open synthesized Design then click OK.

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13. Synthesized design window automatically displayed, in that, one can observe the synthesized design on
target FPGA.

14. For Power: Synthesis --->open Synthesized Design----> report Power----> OK

For Technology Schematic: Synthesis --->open Synthesized Design----> Schematic----> OK
For Device Utilization: Synthesis --->open Synthesized Design----> Report Utilization---> OK

IMPLEMENTATION

15. Now, Go to Flow Navigator ---> Implementation ---> Click on Run Implementation.

Note: It takes some time for synthesis process; status will be displayed at the top right side of window.
After successful completion, it displays a window, select open Implemented
Design then click OK.
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16. Now, Go to Layout--->I/O Planning. Click Scalar Ports and change “Package Pin” according to FPGA
board and change I/O Standard as “LVCMOS33” and click CTRL+S
(Save the scalar ports).

After save, then save constraints will opened and give a “file name” and click ok.

17. Now Generate a bitstream file. Go to Flow Navigator ---> PROGRAM AND DEBUG---> Generate
Bitstream Click Ok.
Note: Before going to this step, make sure that pin assignment in constraints file (.XDC) is correct or not,
if any error rises during bit generation, go to constraints file and check it once. After successful generation
of Bit Stream, the message should display in Console and then automatically a window will be displayed
that process is completed.
18. Now Connect the Target FPGA Board to PC then select open Hardware manager---->
OK.

19. Now, Click on Open Target Device ----> Auto Connect, it will automatically detects the device and
shows the device name and specification in window.
20. On hardware Manager Window, Click on Program Device ----> Select Device --->
Browse for

.BIT file (in some cases it will automatically detects >BIT file)----> Click Program.
21. Now, the target FPGA is successfully programmed(DONE LED will glow), we can verify our design by
varying the switches up/down

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12
 CYCLE-I

PAGE
S.NO. EXPERIMENTNAME NO.
1 Realization Of Logic Gates 14
2 18
4-bit ripple carry and carry look ahead adder using behavioural, dataflow
and structural modelling.
3 a.) 16:1 MUX through 4:1 MUX. 21
3:8 decoder realization through 2:4 decoder
4 31
8:3 encoder
5 8-bit parity generator and checker 33
6 35
Flip-Flops
7
8-bit synchronous up-down counter 40

8 42
4-bit sequence detector through Mealy and Moore s machines.

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 EXPERIMENT NO: 1
LOGIC GATES
Aim: Verilog HDL coding, simulation, FPGA synthesis and on board verification of LOGIC GATES
EDA Tools:
Tools : Xilinx Vivado 2018.1
Artix-7 FPGA
Theory:
A logic gate is an idealized or physical device implementing a Boolean function, that is, it performs a logical
operation on one or more logic inputs and produces a single logic output. Depending on the context, the term may
refer to an ideal logic gate, one that has for instance zero rise time and unlimited fan-out, or it may refer to a non-
ideal physical device.[1] (see Ideal and real op-amps for comparison)

Logic gates are primarily implemented using diodes or transistors acting as electronic switches, but can also be
constructed using electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even
mechanical elements. With amplification, logic gates can be cascaded in the same way that Boolean functions can
be composed, allowing the construction of a physical model of all of Boolean logic, and therefore, all of the
algorithms and mathematics that can be described with Boolean logic.

AND gate

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is used to
show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB

OR gate

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15
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two inputs are
high. An encircled plus sign ( ) is used to show the EOR operation.
EXNOR gate

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if either, but not both,
of its two inputs are high. The symbol is an EXOR gate with a small circle on the output. The small circle represents
inversion.

VERILOG Program:

module LogicGates( input A,B,

output [6:0]Y );
assign Y[0]=~A; assign Y[1]=A&B;
assign Y[2]=A|B; assign Y[3]=~(A&B);
assign Y[4]=~(A|B); assign Y[5]=A^B;
assign Y[6]=~(A^B); endmodule
TEST BENCH:
module LogicGates_tb; reg A,B; wire
[6:0]Y;
LogicGates g1(.Y(Y),.A(A),.B(B));
initial
begin A=0; B=0;
#10
A=0;
B=1;
#10
A=1; B=0;
#10
A=1;
B=1;

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#10; $stop; end endmodule

Viva questions:

1. What are universal gates?

2. Which gate acts as a comparator?

3. What are the properties of xor gate?

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 EXPERIMENT NO: 2
4-BIT RIPPLE CARRY ADDER
Aim: Verilog HDL coding, simulation, FPGA synthesis and on board verification of 4-BIT RIPPLE CARRY
ADDER
EDA Tools:
Tools : Xilinx Vivado 2018.1
Artix-7 FPGA
Theory:
The n-bit adder built from n one –bit full adders is known as ripple carry adder because of the carry is
computed. The addition is not complete until n-1 the adder has computed its Sn-1 output; that results depends upon
ci input, n and so on down the line, so the critical delay path goes from the 0-bit inputs up through ci’s to the n-1
bit.(We can find the critical path through the n-bit adder without knowing the exact logic in the full adder because
the delay through the n-bit adder without knowing the exact logic in the full adder because the delay through the
n-bit carry chain is so much longer than the delay from a and b to s). The ripple-carry adder is area efficient and
easy to design but it is when n is large.It can also be called as cascaded full adder.
The simplified Boolean functions of the two outputs can be obtained as below:
Sum si = ai xor bi xor ci
Carry ci+1 = aibi +bi ci +ai ci
Where x, y & z are the two input variables.
Procedure:
1The full-adder circuit is designed and the Boolean function is found out.
2.The Verilog Module Source for the circuit is written.
3.It is implemented in Model Sim and Simulated.
4.Signals are provided and Output Waveforms are viewed.
Circuit diagram:

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 Ripple carry adder using verilog code:
// Verilog code for 4-bit Ripple Carry Adder
module ripple_carry_adder(
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] sum,
output cout
);
assign {cout, sum} = a + b + cin;
endmodule
// Testbench code for 4-bit Ripple Carry Adder
module testbench();
reg [3:0] a;
reg [3:0] b;
reg cin;
wire [3:0] sum;
wire cout;
ripple_carry_adder dut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
$dumpfile("ripple_carry_adder.vcd");
$dumpvars(0, testbench);
// Test case 1
a = 4'b0001;

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 b = 4'b0010;
cin = 1'b0;
#10 $display("a = %b, b = %b, cin = %b, sum = %b, cout = %b", a, b, cin, sum, cout);

// Test case 2
a = 4'b1111;
b = 4'b1111;
cin = 1'b1;
#10 $display("a = %b, b = %b, cin = %b, sum = %b, cout = %b", a, b, cin, sum, cout);
$finish;
end

endmodule

Result:

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 EXPERIMENT NO: 3a

16:4 mux through 4:1 mux

Aim:Verilog coding, simulation, FPGA synthesis and on board verification of 16:4 mux through 4:1 mux .
EDA Tools:
Tools : Xilinx Vivado 2018.1
Artix-7 FPGA
Theory:
16x1 Multiplexer
In this section, let us implement 16x1 Multiplexer using 5 4x1 Multiplexer. Whereas, 16x1 Multiplexer has 16
data inputs, 4 selection lines and one output.
So, we require four 4x1 Multiplexers in first stage in order to get the 16 data inputs. Since, each 4x1 Multiplexer
produces one output, we require a 4x1 Multiplexer in second stage by considering the outputs of first stage as
inputs and to produce the final output.
Let the 16x1 Multiplexer has sixteen data inputs I15 to I0, four selection lines s3 to s0 and one output Y. The Truth
table of 16x1 Multiplexer is shown below.

Selection Inputs Output

S3 S2 S1 S0 Y

0 0 0 0
I0

0 0 0 1
I1

0 0 1 0
I2

0 0 1 1
I3

0 1 0 0
I4

0 1 0 1
I5

0 1 1 0
I6

0 1 1 1
I7

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 1 0 0 0
I8

1 0 0 1
I9

1 0 1 0
I10

1 0 1 1
I11

1 1 0 0
I12

1 1 0 1
I13

1 1 1 0
I14

1 1 1 1
I15

We can implement 16x1 Multiplexer using lower order Multiplexers easily by considering the above Truth table.
The block diagram of 16x1 Multiplexer is shown in the following figure

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23
HDL Program File for 4:1 MUX [ MUX4X1.v]

module mux4to1_gate(out,in,sel); input [0:3] in; input [0:1] sel;

output out; wire a,b,c,d,n1,n2,a1,a2,a3,a4; not n(n1,sel[1]); not

nn(n2,sel[0]); and (a1,in[0],n1,n2); and (a2,in[1],n2,sel[1]); and

(a3,in[2],sel[0],n1); and (a4,in[3],sel[0],sel[1]); or

or1(out,a1,a2,a3,a4); endmodule

HDL Program File for 16:1 MUX [ MUX16X1.v

module mux16to1(out,in,sel); input [0:15] in; input [0:3] sel;

output out; wire [0:3] ma; mux4to1_gate

mux1(ma[0],in[0:3],sel[2:3]); mux4to1_gate

mux2(ma[1],in[4:7],sel[2:3]); mux4to1_gate

mux3(ma[2],in[8:11],sel[2:3]); mux4to1_gate

mux4(ma[3],in[12:15],sel[2:3]); mux4to1_gate

mux5(out,ma,sel[0:1]);

endmodule
HDL Test Bench File for 16:1 MUX [TESTMUX16.v]

module testmux_16; reg [0:15] in; reg [0:3] sel; wire out; mux16to1
mux(out,in,sel);

initial

begin

$monitor("in=%b | sel=%b | out=%b",

in,sel,out); end

initial

begin in=16'b1000000000000000; sel=4'b0000;

#30 in=16'b0100000000000000; sel=4'b0001;

#30 in=16'b0010000000000000; sel=4'b0010;

#30 in=16'b0001000000000000; sel=4'b0011;

#30 in=16'b0000100000000000; sel=4'b0100;

#30 in=16'b0000010000000000; sel=4'b0101;

#30 in=16'b0000001000000000; sel=4'b0110;

#30 in=16'b0000000100000000; sel=4'b0111;

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#30 in=16'b0000000010000000; sel=4'b1000;

#30 in=16'b0000000001000000; sel=4'b1001;

#30 in=16'b0000000000100000; sel=4'b1010;

#30 in=16'b0000000000010000; sel=4'b1011;

#30 in=16'b0000000000001000; sel=4'b1100;

#30 in=16'b0000000000000100; sel=4'b1101;

#30 in=16'b0000000000000010; sel=4'b1110; #30

in=16'b0000000000000001; sel=4'b1111; end

endmodule

OR

// Verilog code for 16:4 MUX implemented using four 4:1 MUXes
module mux16_4(
input [15:0] data_in,
input [3:0] sel,
output reg [3:0] data_out
);

wire [3:0] mux1_out;

wire [3:0] mux2_out;
wire [3:0] mux3_out;
wire [3:0] mux4_out;

mux4_to_1 mux1 (
.data_in({data_in[3:0]}),
.sel(sel[1:0]),
.data_out(mux1_out)
);

mux4_to_1 mux2 (
.data_in({data_in[7:4]}),
.sel(sel[1:0]),

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 .data_out(mux2_out)
);

mux4_to_1 mux3 (
.data_in({data_in[11:8]}),
.sel(sel[1:0]),
.data_out(mux3_out)
);

mux4_to_1 mux4 (
.data_in({data_in[15:12]}),
.sel(sel[1:0]),
.data_out(mux4_out)
);

mux4_to_1 mux5 (
.data_in({mux1_out, mux2_out, mux3_out, mux4_out}),
.sel(sel[3:2]),
.data_out(data_out)
);

endmodule

// 4:1 MUX module

module mux4_to_1(
input [3:0] data_in,
input [1:0] sel,
output reg [3:0] data_out
);
always @(*)
case (sel)
2'b00: data_out = data_in[0];
2'b01: data_out = data_in[1];
2'b10: data_out = data_in[2];
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 2'b11: data_out = data_in[3];
endcase

endmodule
// Testbench code for 16:4 MUX
module testbench();
reg [15:0] data_in;
reg [3:0] sel;
wire [3:0] data_out;

mux16_4 dut (
.data_in(data_in),
.sel(sel),
.data_out(data_out)
);
initial begin
$dumpfile("mux16_4.vcd");
$dumpvars(0, testbench);

// Test case 1
data_in = 16'b0000000011110000;
sel = 4'b0000;
#10 $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out);
// Test case 2
data_in = 16'b0101010101010101;
sel = 4'b0001;
#10 $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out);
// Add more test cases here
$finish;
end

endmodule
Result:

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 EXPERIMENT NO: 3b

3-to-8 Decoder
Aim:Verilog coding, simulation, FPGA synthesis and on board verification of 3-to-8 Decoder.
EDA Tools:
Tools : Xilinx Vivado 2018.1
Artix-7 FPGA
Theory:
Decoder:
A Decoder is a combinational logic circuit . It converts binary integer value to an associated pattern of output
bits. A decoder has ‘n’ input lines and 2n output lines.
Decoder gives output high depending on the combination of the inputs. It detects a particular code, and the
output is the min terms of ‘n’ input variable lines, when enable is high.

Decoder has a wide variety of applications which includes, address decoding for CPU memory identification,
instruction conversion from CPU to control signals, Code Converters, Logical Data Transfer, etc.

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3:8 Decoder Truth Table:

In a 3:8 decoder, 3 input lines and 8 output lines are required. The truth table of 3:8 decoder is given below (
Table 1) , where A,B,C are the input ; EN is enable line and Y7 to Y0 are the outputs of the 3:8 decoder.

Table 1 : 3:8 Decoder Truth Table

Boolean Expression for 3:8 Decoder Y0 = A’B’C’

Y1= A’B’C

Y2= A’BC’ Y3= A’BC

Y4= AB’C’

Y5= AB’C

Y6= ABC’

Y7= ABC

Verilog Code for 3:8 Decoder

The Verilog code for 3:8 Decoder is given below :
`module decoder_3to8 (input [2:0] in, output reg [7:0]
out);

always @(*) begin

case (in)
3'b000: out = 8'b00000001;
3'b001: out = 8'b00000010;
3'b010: out = 8'b00000100;
3'b011: out = 8'b00001000;
3'b100: out = 8'b00010000;
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 3'b101: out = 8'b00100000;
3'b110: out = 8'b01000000;
3'b111: out = 8'b10000000;
endcase
end

endmodule
module decoder_3to8_tb;

reg [2:0] in;

wire [7:0] out;

decoder_3to8 dut (
.in (in),
.out (out)
);

initial begin
$display("Input Output");
$monitor("%b %b", in, out);
in = 3'b000;
#10 in = 3'b001;
#10 in = 3'b010;
#10 in = 3'b011;
#10 in = 3'b100;
#10 in = 3'b101;
#10 in = 3'b110;
#10 in = 3'b111;
#10 $finish;
end

endmodule

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 EXPERIMENT NO: 4

8-to-3 Encoder
Aim:Verilog coding, simulation, FPGA synthesis and on board verification of 3-to-8 Encoder.
EDA Tools:
Tools : Xilinx Vivado 2018.1
Artix-7 FPGA
Theory:
An Encoder is a Digital Circuit that Performs the Inverse Operation of a Decoder. An encoder has 2 n(or
Fewer) Input lines and n output Lines. In Encoder the Output Lines Generate the Binary Code Corresponding to
the Input Value. The Figure Shows the General Structure of the Encoder Circuit. As Shown in the Figure, the
Decoded information is Presented as 2n inputs Producing n Possible Outputs.

The IC 74XX148 is an 8-Input Priority encoder. It accepts Data from Eight Active Low Inputs and
Provides a Binary Representation on the three Active-low Outputs. A Priority is Assigned to each input so that
when two or more inputs are simultaneously active, the input with the highest priority is Represented on the output.
Input D0 has Least Priority and Input D7 has Highest Priority.

31
32
VERILOG Program: 8-to-3 ENCODER
module Encoder8_3( input [7:0] A, input
EN, output reg[2:0] Y
);
always@(A or EN) begin if(!EN)
Y<=1'b0;
else case(A)
8'b00000001:Y<=3'b000;
8'b00000010:Y<=3'b001;
8'b00000100:Y<=3'b010;
8'b00001000:Y<=3'b011;
8'b00010000:Y<=3'b100;
8'b00100000:Y<=3'b101;
8'b01000000:Y<=3'b110;
8'b10000000:Y<=3'b111; endcase end
endmodule

TEST BENCH
module Encoder8_3_tb; reg [7:0] A; reg EN; wire [2:0] Y;
Encoder8_3 e1(.Y(Y),.A(A),.EN(EN));
initial
begin
EN=0;
#10
EN=1;
A=8'b00000001;
#10
EN=1;
A=8'b00000010;
#10
EN=1;
A=8'b00000100;
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#10
EN=1;
A=8'b00001000;
#10
EN=1;
A=8'b00010000;
#10
EN=1;
A=8'b00100000;
#10
EN=1;
A=8'b01000000;
#10
EN=1;
A=8'b10000000;
#10; $stop; end endmodule

Viva questions:
1. How many 4X2 Encoders are needed to construct 16x4 Encoder?
2. What is the difference between Decoder and Encoder?
3. What are the applications of Encoder?
4. What is the difference between Encoder and Multiplexer?
5. What is importance of enable line in Encoder?

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 EXPERIMENT NO: 6
FLIP-FLOPS

Aim:
Verilog HDL coding, simulation, FPGA synthesis and on-board verification of Flip-Flops (SR, D, JK, T)
EDA Tools:
Tools : Xilinx Vivado 2018.1
Artix-7 FPGA
Theory: -
Flip flop are basic storage elements and the soul for sequential circuit design. Based on the application &
the need we can design and use a flip flop. Few of the flip flops which are usually used for sequential
circuitsandformemorydesign. You can code for any given FF with the truth table and thereby converting them into
a logic gate configuration which is quite a simple task as far as these flip flops are concerned.

S-R Flip-Flop

Characteristic equation: Q(next) = S + R’Q, SR = 0

S R Q(next)

0 0 Q

0 1 0

1 0 1

1 1 undefined
From the truth table it’s clear that the FF has two inputs. S & R represents Set & Reset respectively. To model this
FF, we can use the CASE statement and define all the four-input combination and the related output. It’s always a
good design to have a reset for your FF so as to bring it to a defined stage at any point of time asynchronously.

-Flip-Flop

Characteristic equation: Q(next) = JQ' + K'Q

J K Q(next)

0 0 Q

0 1 0

35
 1 0 1

1 1 Q'(toggle)
This one is similar to the SR FF except that the "11" state defines a state where the output toggles between 1
& 0. The same design
for SR can be
extended with two
more nand gates to
define the JK.

Characteristic equation: Q(next) = D

D Q
0 0
1 1

This one is the simplest of all the FF and also easy to model . Though its the simplest one its the most used FF for
designs.

T-Flip-Flop

Characteristic equation: Q(next) = TQ' + T'Q

T Q
0 Q
1 Q’
This one is the next simplest FF after D. Here the output is retains the previous state when input is 0. And when
the input is 1 the output toggles i.e for every rising edge of the clock when input is 1 the output toggles from its
previous value.
36
VERILOG Program:
Verilog code for SR Flip-Flop module srff(s,r,clk,rst, q,qb);
input s,r,clk,rst; output q,qb; reg q,qb; reg [1:0]sr;
always@(posedgeclk,posedgerst) begin
sr={s,r}; //concatenate S&R to a 2 bit value if(rst==0) // when
reset is not asserted begin case (sr)
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=1'b1;
default: begin end endcase end

else // when reset is asserted

begin q=1'b0; end qb=~q; end
endmodule
Verilog code for JK Flip Flop define TICK #2 //Flip-flop time
delay 2 units
module jkflop(j,k,clk,rst,q);

input j,k,clk,rst;

output q;

reg q;

always @(posedge clk)begin

if(j==1 & k==1 &rst==0)begin

q =`TICK ~q; //Toggles

end

37
else if(j==1 & k==0 &rst==0)begin

q = `TICK 1; //Set

end

else if(j==0 & k==1)begin

q = `TICK 0; //Cleared

end

end

always @(posedge rst)begin

q = 0; //The reset normally has negligible delay and hence ignored.

end

endmodule
Verilog Code for D-Flip Flop

module Dff(input d,inputclk,output reg q);

always @(posedge clk) // note: lines whithin the always block are executed sequententialy

begin

q=d;

end

endmodule
Verilog code for T flip flop

module tff_sync_reset (

data , // Data Input

clk , // Clock Input

38
 reset , // Reset input

q // Q output
);

input data, clk, reset ;

output q;

reg q;

always @ ( posedge
clk) if (~reset)
begin

q <= 1'b0;

end else if (data) begin q

<= !q;

end
Viva questions:

1.Write Short Notes on Edge Triggered Flip-Flop.

2. Write Short Notes on Master Slave Flip-flop.

3. What is Race Around Condition? How it is Avoided?

4. List the Functions of Asynchronous Inputs.

5. Convert SR flip-flop into JK flip-flop.

6. Convert JK flip-flop into T flip-flop.

39
 EXPERIMENT NO: 7

8-BIT UP-DOWN COUNTER

Aim:Verilog coding, simulation, FPGA synthesis and on board verification of 8-bit up-down counter.
EDA Tools:
Tools : Xilinx Vivado 2018.1
Artix-7

Verilog code:
module up_down_counter (
input clk,
input reset,
input up_down,
output reg [7:0] count
);
always @(posedge clk or negedge reset) begin
if (reset == 0) begin
count <= 8'b00000000;
end else if (up_down == 1) begin
count <= count + 1;
end else begin
count <= count - 1;
end
end
endmodule
module up_down_counter_tb;

reg clk;
reg reset;
reg up_down;
wire [7:0] count;

up_down_counter uut (
.clk(clk),
40
 .reset(reset),
.up_down(up_down),
.count(count)
);
initial begin
clk = 0;
reset = 1;
up_down = 0;
#10 reset = 0;
end

always #5 clk = ~clk;

initial begin
$dumpfile("up_down_counter_tb.vcd");
$dumpvars(0, up_down_counter_tb);
end

initial begin
#100 up_down = 1;
#500 up_down = 0;
#500 up_down = 1;
#1000 up_down = 0;
#1000 $finish;
end

endmodule

41
 CYCLE-II

CONTENTS

EXP.NO EXPERIMENT NAME PAGE NO

PART-2

1 Design and Implementation of Universal Gates 43

2 Design and Implementation of An Inverter 45

3 Design and Implementation of Full Adder 47

4 Design and Implementation of Full Subtractor 49

5 Design and Implementation of Decoder 51

6 Design and Implementation of D-Flip flop 52

42
 EXPERIMENT NO: 1

UNIVERSAL GATES

AIM: To design and Implementation of a universal Gates

TOOLS: Tanner EDA software, Personal computer.
CIRCUIT DIAGRAM FOR NAND GATE:

OUTPUT WAVE FORMS:

43
CIRCUIT DIAGRAM FOR NOR GATE:

OUTPUT WAVE FORMS:

PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Tanner EDA Schematic tool
2. Enter into Simulation mode.
3. Setup the Analysis and library.
4. Setup the required analysis.
5. Enable the waveform voltage probe as True.
6. Run the simulation.
7. Observe the waveforms in WEBx64.

RESULT:

44
 EXPERIMENT NO: 2

AN INVERTER

AIM: To design and Implementation of a An Inverter

TOOLS: Tanner EDA software, Personal computer.
CIRCUIT DIAGRAM FOR INVERTER:

OUTPUT WAVE FORMS:

45
PROCEDURE:
1.Connect the Circuit as shown in the circuit diagram using Tanner EDA Schematic tool
2.Enter into Simulation mode.
3.Setup the Analysis and library.
4.Setup the required analysis.
5.Enable the waveform voltage probe as True.
6.Run the simulation.
7.Observe the waveforms in WEBx64.

RESULT:

46
 EXPERIMENT NO: 3

FULL ADDER

AIM: To design and Implementation of a Full Adder.

TOOLS: Tanner EDA software, Personal computer.
CIRCUIT DIAGRAM FOR FULL ADDER:

OUTPUT WAVE FORMS:

47
PROCEDURE:
1.Connect the Circuit as shown in the circuit diagram using Tanner EDA Schematic tool
2.Enter into Simulation mode.
3.Setup the Analysis and library.
4.Setup the required analysis.
5.Enable the waveform voltage probe as True.
6.Run the simulation.
7.Observe the waveforms in WEBx64.

RESULT:

48
 EXPERIMENT NO: 4

FULL SUBTRACTOR

AIM: To design and Implementation of a Full Subtractor.

TOOLS: Tanner EDA software, Personal computer.
CIRCUIT DIAGRAM FOR FULL SUBTRACTOR:

OUTPUT WAVE FORMS:

49
PROCEDURE:
1.Connect the Circuit as shown in the circuit diagram using Tanner EDA Schematic tool
2.Enter into Simulation mode.
3.Setup the Analysis and library.
4.Setup the required analysis.
5.Enable the waveform voltage probe as True.
6.Run the simulation.
7.Observe the waveforms in WEBx64.

RESULT:

50
 EXPERIMENT NO: 5

DECODER

AIM: To design and Implementation of a Decoder.

TOOLS: Tanner EDA software, Personal computer.
CIRCUIT DIAGRAM FOR 2:4 DECODER:

PROCEDURE:
1.Connect the Circuit as shown in the circuit diagram using Tanner EDA Schematic tool
2.Enter into Simulation mode.
3.Setup the Analysis and library.
4.Setup the required analysis.
5.Enable the waveform voltage probe as True.
6.Run the simulation.
7.Observe the waveforms in WEBx64.

RESULT:

51
 EXPERIMENT NO: 6

D-FLIP FLOP

AIM: To design and Implementation of a D-Flip Flop.

TOOLS: Tanner EDA software, Personal computer.
CIRCUIT DIAGRAM FOR D-FLIP FLOP:

PROCEDURE:
1.Connect the Circuit as shown in the circuit diagram using Tanner EDA Schematic tool
2.Enter into Simulation mode.
3.Setup the Analysis and library.
4.Setup the required analysis.
5.Enable the waveform voltage probe as True.
6.Run the simulation.
7.Observe the waveforms in WEBx64.

RESULT:

52