LORDS INSTITUTE OF ENGINEERING AND TECHNOLOGY

(Affiliated to Osmania University)

DIGITAL INTEGRATED CIRCUITS

AND APPLICATIONS

LAB MANUAL
III.BE.VII

By
NAJEEMULLA BAIG
Assistant Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Himayathsagar, Hyderabad, Telangana.

i
S. No. CONTENTS PAGE
No.
1 Vision of the Institution I
2 Mission of the Institution I
3 Vision of the Department II
4 Mission of the Department II
5 PEOs II
6 POs III
7 PSOs IV
8 Introduction to VIVADO IV
9 General Guidelines & Safety instructions XXVII
LIST OF THE EXPERIMENTS
PART-A
1. 1Write structural and dataflow Verilog HDL models for a) 4-bit ripple 1
0carry adder. b) 4-bit carry Adder – cum Subtractor. c) 2-digit BCD adder /
subtractor. d) 4-bit carry look ahead adder e) 4-bit comparator
2. 1Write a Verilog HDL program in behavioral model for a) 8:1 multiplexer 2
1b) 3:8 decoder c) 8:3 encoder d) 8 bit parity generator and checker
3. 1Write a Verilog HDL program in Hierarchical structural model for a) 16:1 3
2multiplexer realization using 4:1 multiplexer b) 3:8 decoder realization
through 2:4 decoder c) 8-bit comparator using 4-bit comparators and
additional logic
4. 1Write a Verilog HDL program in behavioral model for D,T and JK flip 4
3flops, shift registers and counters
5. 1Write a Verilog HDL program in structural and behavioral models for a) 6
48 bit asynchronous up-down counter b) 8 bit synchronous up-down
counter
6. 1Write a Verilog HDL program for 4-bit sequence detector through Moore 8
5state machines.
7. 1Write a Verilog HDL program for 4-bit sequence detector through Mealy 9
6state machines
PART-B- 10
8 Transistor Level implementation of CMOS circuits using VLSI CAD tool
9Basic Logic Gates: Inverter, NAND and NOR 11
9
9
8. Half Adder and Full Adder 13
9. 2:1 Multiplexer and 4:1 Multiplexer using 2:1 Multiplexer 22
10. one bit comparator and four-bit magnitude comparator using one bit
comparator
11. Implement the Layout of CMOS Inverter.
12. Implement the Layout of CMOS NAND.

ii
 LORDS INSTITUTE OF ENGINEERINANTECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

1.-VISION OF THE INSTITUTION

To be part of universal human quest for development and progress by contributing high
caliber, ethical and socially responsible engineers who meet the global challenge of building modern
society in harmony with nature.

2.MISSION OF THE INSTITUTION

• To attain excellence in imparting technical education from the undergraduate through

doctorate levels by adopting coherent and judiciously coordinated curricular and co- curricular
programs
• To foster partnership with industry and government agencies through collaborative research
and consultancy
• To nurture and strengthen auxiliary soft skills for overall development and improved
employability in a multi-cultural work space
• To develop scientific temper and spirit of enquiry in order to harness the latentinnovative
talents
• To develop constructive attitude in students towards the task of nation building and empower
them to become future leaders
• To nourish the entrepreneurial instincts of the students and hone their business acumen.
• To involve the students and the faculty in solving local community problems through
economical and sustainable solutions.

3
 LORDS INSTITUTE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

3. VISION OF THE DEPARTMENT

To provide State of Art facilities to impart technical education and Research in order to guide and
motivate young Engineers in Electronics and Communication Engineering

4. MISSION OF THE DEPARTMENT

• DM1: To make engineering education an enjoyable learning experience through challenging
tutorials, mini projects, assignments and laboratory experiences.

• DM2: To impart training to students for good designing skills and exposure to Research &
Development and innovations by using modern tools in frontier areas of Engineering and Project
Management

• DM3: To promote overall development of graduates by developing their competencies in order to

prepare them to be successful engineers/ entrepreneurs making them useful to society and also
improve their ethical values.

Note: DM: Department Mission

5.PROGRAM OUTCOMES

PO1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering problems.

PO2: Problem analysis: Identify, formulate, research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural sciences,
and engineering sciences.
PO3: Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate consideration
for
the public health and safety, and the cultural, societal, and environmental considerations.

PO4: Conduct investigations of complex problems: Use research-based knowledge andresearch

methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
4
PO5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.

PO6: The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.

PO7: Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.

PO8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.

PO9: Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.

PO10: Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effectivepresentations, and give and receive clear
instructions.
PO11: Project management and finance: Demonstrate knowledge and understandingof the
engineering and management principles and apply these to one‟s own work, as amember and
leader in a team, to manage projects and in multidisciplinary environments.

PO 12: Life-long learning: Recognize the need for, and have the preparation and ability to engage
in independent and life-long learning in the broadest context of technological change.

6. PROGRAM SPECIFIC OUTCOMES

PSO1: Work as Software Engineers for providing solutions to real world problems usingStructured,
Object-Oriented Programming languages and open-source software.

PSO2: Function as Systems Engineer, Software Analyst and Tester for IT and ITeS.
5
 HDL(HARDWARE DESCRIPTION LANGUAGE)
HDL -> Hardware description language allows us to specify the components that makeup
instead of having to use a pictorial representation like a block or logic diagram. Every
component is defined by its input and output part logic function. It performs and timing
characteristics such as delay and clocking. An entire digital system can described in text
format using prescribed set of roles and keywords (reserved words).

Generally, two types of HDL

(1) VHDL (VHSLC HDL):

Very high speed: Integrated circuit HDL
(2) Verilog HDL:
Mostly in VLSI design uses verilog HDL.

Verilog HDL is a relatively loose and free following language.

It uses similar procedures and constructs C- programming language.
Verilog HDL provides for description of a digital System at all of the levels in VLSI
design flow.
Verilog code use sans serif font type.
This language is case sensitive.

In VLSI we have following types of modeling

(1) Structural Gate level modeling.

(2) Switch level modeling.
(3) Hierarchal modeling (mixed level modeling Gate and Switch level modeling).
(4) Behavioral modeling.
(5) Dataflow and RTL modeling.

6
VLSI DESIGN FLOW

7
 STEPS FOR VIVADO DESIGN SUIT

1. Open VIVADO Design Suite 22.1.

2. Click on File > New Project...

3. Give a name to the project and click on [Next].

8
4. Click on [Next] again.

5. Then click on [Finish].

9
6. Right click in “Hierarchy”.

7. Click on ‘New Source...’.

10
8. Select ‘Verilog Module’.

9. Give a name to the module then click on [Next].

11
10. Give the input and output parameters. Then click on [Next].

11. Click on [Finish].

12
12. Write the Verilog code.

13. In the process pane expand ‘Synthesize – XST’.

13
14. Run ‘Check Syntax’ to check the syntax of the written verilog code.

15. Go to ‘Simulation’ in view pane. Then right click again in ‘Hierarchy’ and
select ‘NewSource...’.

14
16. Select ‘Verilog Test Fixture’ and give a name to the file. Then click on [Next].

17. Select the Verilog code module that was created before and click on [Next].

15
18. Enter the ‘Test Bench Code’.

1. Expand ‘Isim Simulator’ in processes.

16
 2. Run the ‘Behavioral Check Syntax’ and ‘Simulate Behavioral Model’.

3. Check the Output.

17
 Using Synthesis Settings
1. From the Flow Navigator click Settings, then select Synthesis, or select Flow >
Settings > Synthesis Settings. The Settings dialog box opens, as shown in the following
figure

Figure: Settings Dialog Box

2. Under the Constraints section of the Settings dialog box, select the Default Constraint Set

as the active constraint set; a set of files containing design constraints captured in Xilinx

design constraints (XDC) files that you can apply to your design. The two types of design

constraints are: °

• Physical constraints: These constraints define pin placement, and absolute, or relative,

placement of cells such as block RAMs, LUTs, Flip-Flops, and device configuration

settings.

• Timing constraints: These constraints define the frequency requirements for the design.

Without timing constraints, the Vivado Design Suite optimizes the design solely for wire

length and placement congestion.

18
• See this link to the Vivado Design Suite User Guide: Using Constraints (UG903) [Ref 12]

for more information about organizing constraints.

• New runs use the selected constraint set, and the Vivado synthesis targets this constraint

set for design changes.

3. From the Options area: Select a Strategy from the drop-down menu where you can view and

select a predefined synthesis strategy to use for the synthesis run. There are different preconfigured

strategies, as shown in the following figure.

You can also define your own strategy. When you select a synthesis strategy, available Vivado

strategy displays in the dialog box. You can override synthesis strategy settings by changing the

option values as described in Creating Run Strategies.

For a list of all the strategies and their respective settings, see the -directive option in the

following list, and see Table 1-2 to see a matrix of strategy default settings.

4. Select from the displayed options:

• -flatten hierarchy: Determines how Vivado synthesis controls hierarchy.

- none: Instructs the synthesis tool to never flatten the hierarchy. The output of synthesis has

the same hierarchy as the original RTL.

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- full: Instructs the tool to fully flatten the hierarchy leaving only the top level.

- rebuilt: When set, rebuilt allows the synthesis tool to flatten the hierarchy, perform

synthesis, and then rebuild the hierarchy based on the original RTL. This value allows the

QoR benefit of cross-boundary optimizations, with a final hierarchy that is similar to the

RTL for ease of analysis. °

• -gated_clock_conversion: Turns on and off the ability of the synthesis tool to convert the

clocked logic with enables.

• The use of gated clock conversion also requires the use of an RTL attribute to work. See

GATED_CLOCK, for more information. °

• -bufg: Controls how many BUFGs the tool infers in the design. The Vivado design tools

use this option when other BUFGs in the design netlists are not visible to the synthesis

process.

The tool infers up to the amount specified, and tracks how many BUFGs are instantiated in the

RTL. For example, if the -bufg option is set to 12 and there are three BUFGs instantiated in the

RTL, the Vivado synthesis tool infers up to nine more BUFGs.

° -directive: Replaces the -effort level option. When specified, this option runs Vivado synthesis

with different optimizations. See Table 1-2 for a list of all strategies and settings. Values are:

- Default: Default settings. See Table 1-2.

- Runtime Optimized: Performs fewer timing optimizations and eliminates some RTL optimizations

to reduce synthesis run time.

- Area Optimized high: Performs general area optimizations including forcing ternary adder

implementation, applying new thresholds for use of carry chain in comparators, and implementing

area-optimized multiplexers.

- Area Optimized medium: Performs general area optimizations including changing the threshold for

control set optimizations, forcing ternary adder implementation, lowering multiplier threshold of

20
inference into DSP blocks, moving shift register into BRAM, applying lower thresholds for use of

carry chain in comparators, and also area optimized MUX operations.

- AlternateRoutability: Set of algorithms to improve route-ability (less use of MUXFs and CARRYs)

- AreaMapLargeShiftRegToBRAM: Detects large shift registers and implements them using dedicated

block RAM.

- AreaMultThresholdDSP: Lower threshold for dedicated DSP block inference.

- FewerCarryChains: Higher operand size threshold to use LUTs instead of the carry chain.

- LogicCompaction: Arranges CARRY chains and LUTs in such a way that it makes the logic more

compact using fewer SLICES. This could have a negative effect on timing QoR.

- PerformanceOptimized: Performs general timing optimizations including logic level reduction at the

expense of area.

- PowerOptimized_high: Performs general timing optimizations including logic level increase at the

expense of area.

- PowerOptimized_medium: Performs general timing optimizations by lowering logic level reduction

at the expense of area. °

-retiming: For non-Versal devices only: For controlling retiming in Versal, please the -no_retiming

option. This Boolean option provides an option improve circuit performance for intra-clock sequential

paths by automatically moving registers (register balancing) across combinatorial gates or LUTs. It

maintains the original behavior and latency of the circuit and does not require changes to the RTL

sources. The default is off.

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 EXPERIMENT-1

1.1. Mux 4x1 using Mux 2x1

module mux4x1(
input [3:0] in,
input [1:0] sel,
output reg out);

wire mux_out1, mux_out2;

// level-1 2:1 multiplexers

mux2x1 mux1(in[0], in[1], sel[0],mux_out1);

mux2x1 mux2(in[2], in[3], sel[0],mux_out2);

// level-2 2:1 multiplexer

mux2x1 mux3(mux_out1, mux_out2, sel[1],out);

endmodule

module mux2x1 (
input wire a,
input wire b,
input wire sel,
output reg out
);
always @* begin
case (sel)
1'b0: out = a;
1'b1: out = b;
endcase
end
endmodule

//testbench

module mux4x1_tb;

// Inputs reg

22
 [3:0] in;
reg [1:0] sel;

// Outputs
wire out;

// Instantiate the module under test

mux4x1 dut (
.in(in),
.sel(sel),
.out(out)
);

// Test stimulus
initial begin
$monitor("in=%b, sel=%b, out=%b", in, sel, out);
// Initialize inputs
in = 4'b1010;
sel = 2'b00;
#10; // Wait for some time

sel = 2'b01;
#10; // Wait for some time

sel = 2'b10;
#10; // Wait for some time

sel = 2'b11;
#10; // Wait for some time

$finish;
end
endmodule

23
Output Waveforms:

Rtl Schematic :

1.2 Mux 16x1 using Mux 4x1

//Mux 16x1

module mux16x1( input [15:0] i,

input [3:0] select, output
y);

// level 1
mux4x1 dut1(i[3:0],select[1:0],y1);
mux4x1 dut2(i[7:4],select[1:0],y2);
mux4x1 dut3(i[11:8],select[1:0],y3);
mux4x1 dut4(i[15:12],select[1:0],y4);

//level 2

mux4x1 dut5({y4,y3,y2,y1},select[3:2],y);

24
endmodule

//Mux 4x1
module mux4x1(input [3:0]i,
input [1:0]select,
output reg y);

always@*
case(select)

2'b00: y=i[0];
2'b01: y=i[1];
2'b10: y=i[2];
2'b11: y=i[3];

endcase
endmodule
//Testbench
module test_mux16x1;

// Inputs
reg [15:0] data_in;
reg [3:0] select;

// Outputs
wire out;

// Instantiate the DUT

mux16x1 dut (
.i(data_in),
.select(select),
.y(out)
);
// Initialize inputs
initial begin
$monitor($time, "data_in=%b select=%0d out = %b", data_in,select,out);
data_in = 16'b1010_1010_1010_1010;
select = 4'b0000;
end
// Stimulus
always #5 select = select + 1'b1;
initial
25
 #50 $finish;

endmodule

Output Waveform:

1.3-bit adder using 1-bit full-adder(Ripple carry adder)

module full_adder(a,b,cin,sum,co);

input a,b,cin;
output sum,co;

assign sum=a^b^cin;
assign co=(a&b)|(a&cin)|(cin&b);

endmodule

//Design of 4 Bit Adder using 4 Full adder (Structural Modeling Style)

module adder_4bit (a,b,cin,sum,cout);

26
output [3:0]sum;
output cout;

input [3:0]a;
input [3:0]b;
input cin;

wire [2:0]c;

full_adder u0 (a[0],b[0],cin,sum[0],c[0]);
full_adder u1 (a[1],b[1],c[0],sum[1],c[1]);
full_adder u2 (a[2],b[2],c[1],sum[2],c[2]);
full_adder u3 (a[3],b[3],c[2],sum[3],cout);

endmodule

//Testbench Code- Ripple carry adder

`timescale 1ns / 1ps

module TestModule;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;

// Outputs
wire [3:0] sum;
wire cout;

// Instantiate the Unit Under Test (UUT)

adder_4bit dut(a,b,cin,sum,cout);

// Initialize Inputs

initial begin
$monitor("a=%0d b=%0d cin=%b sum=%0d cout=%b",a,b,cin,sum,cout);
a = 0;
b = 0;
cin = 0;
27
// Wait 100 ns for global reset to finish
#100;
a = 5;
b = 6;
cin = 1;
// Wait 100 ns for global reset to finish
#100;
end
endmodule

Output Waveform:

RTL Schematic:

28
 1.4 -to-8 decoder using 2-to-4 decoder

module decoder2x4_enable(input [1:0] sel, input enable, output reg [3:0] out);always @(sel,

enable) begin
if (enable) begincase(sel)
2'b00: out = 4'b0001;
2'b01: out = 4'b0010;
2'b10: out = 4'b0100;
2'b11: out = 4'b1000;
endcase end else
begin
out = 4'b0000;end
end endmodule

//3 to 8 decoder
module decoder3x8(input [2:0]sel, output [7:0]out);

decoder2x4_enable uut1(sel[1:0],~sel[2], out[3:0]);

decoder2x4_enable uut2(sel[1:0],sel[2], out[7:4]);

endmodule

//Testbench

module testbench();

// Declare the inputs and outputs for the testbenchreg [2:0] sel;
wire [7:0] out;

// Instantiate the DUT (device under test)decoder3x8

dut(.sel(sel), .out(out));

// Initialize the inputsinitial

begin
$monitor("sel = %d, out = %b", sel, out);

sel = 0;
#10;
sel = 1;
#10;
sel = 2;
#10;
29
 sel = 3;
#10;
sel = 4;
#10;
sel = 5;
#10;
sel = 6;
#10;
sel = 7;
#10;
$finish;end

endmodule

Output Waveform:

30
 EXPERIMENT-2

2.1-bit full-adder using case statement:

//1-bit full-adder
module full_adder (
input a,
input b,
input cin,
output reg sum,
output reg cout
);
reg [2:0] case_input;

always @* begin case_input =

{cin, a, b};case (case_input)
3'b000: begin
sum = 1'b0;
cout = 1'b0; end
3'b001: begin
sum = 1'b1; cout
= 1'b0; end
3'b010: begin
sum = 1'b1; cout
= 1'b0; end
3'b011: begin
sum = 1'b0; cout
= 1'b1; end
3'b100: begin
sum = 1'b1; cout
= 1'b0; end
3'b101: begin
sum = 1'b0; cout
= 1'b1; end
3'b110: begin
sum = 1'b0; cout
= 1'b1; end
3'b111: begin
sum = 1'b1; cout
= 1'b1; end
endcase
31
end
endmodule

//2.1-bit full-adder Testbench:

module full_adder_tb;reg a,
b, cin;
wire sum, cout;
// Instantiate the Full-Adder modulefull_adder dut(a,
b, cin, sum, cout);
// Apply stimulus
initial begin
$monitor("%b %b %b | %b %b", a, b, cin, sum, cout);
$display("A B Cin | Sum Cout");
$display(" ---------------------- ");
a = 0; b = 0; cin = 0; #10;
a = 0; b = 0; cin = 1; #10;
a = 0; b = 1; cin = 0; #10;
a = 0; b = 1; cin = 1; #10;
a = 1; b = 0; cin = 0; #10;
a = 1; b = 0; cin = 1; #10;
a = 1; b = 1; cin = 0; #10;
a = 1; b = 1; cin = 1; #10;
$finish; end
endmodule

Waveforms

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2.1 Mux 8x1 using case

statement:module mux8x1 (
input [7:0] in,
input [2:0] sel,
output reg out
);

always @* begin
case (sel)
3'b000: out = in[0];
3'b001: out = in[1];
3'b010: out = in[2];
3'b011: out = in[3];
3'b100: out = in[4];
3'b101: out = in[5];
3'b110: out = in[6];
3'b111: out = in[7];
endcase
end
endmodule

//Mux 8x1 Testbench:

module mux8x1_tb;reg
[7:0] in;
reg [2:0] sel;
wire out;
integer i;

mux8x1 dut (
.in(in),
.sel(sel),
.out(out)
);

initial begin
in=8'b1010_1010;
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 $monitor($time,"Input: in=%b, sel=%b,Output: out=%b",in,sel,out);for(i=0;i<=7;i=i+1)
begin
sel=i;
#10;
end
#10;
$stop; end
endmodule

Waveforms:

34
2.2 Encoder 8-to-3 using case statement:

//8 to 3 encoder:
module encoder8x3 ( input [7:0] in, output reg [2:0] out);

always @* begin
case (in)
8'b00000001: out = 3'b000;
8'b00000010: out = 3'b001;
8'b00000100: out = 3'b010;
8'b00001000: out = 3'b011;
8'b00010000: out = 3'b100;
8'b00100000: out = 3'b101;
8'b01000000: out = 3'b110;
8'b10000000: out = 3'b111;
default: out = 3'b000; // Default output when none of the inputs match
endcase
end
endmodule
//testbench:
module encoder8x3_tb;
reg [7:0] in;
wire [2:0] out;
integer i;
encoder8x3 dut ( .in(in), .out(out) );
initial begin
$monitor($time, "Input: in=%b, Output: out=%b",in, out);
for(i=0;i<=7;i=i+1) begin
if(i==0)
in= 8'b0000_0001;
else
in=in<<1'b1;
#10;
end
#10;
$stop;
end
endmodule

Waveforms
35
2.3 Decoder 3-to-8 using case statement:

//decoder 3 to 8
module decoder3x8 ( input [2:0] in, output reg [7:0] out);

always @* begin
case (in)
3'b000: out = 8'b00000001;
3'b001: out = 8'b00000010;
3'b010: out = 8'b00000100;
3'b011: out = 8'b00001000;
3'b100: out = 8'b00010000;
3'b101: out = 8'b00100000;
3'b110: out = 8'b01000000;
3'b111: out = 8'b10000000;
default: out = 8'b00000000; // Default output when none of the inputs match
endcase
end
endmodule

//Testbench
module decoder3x8_tb;
reg [2:0] in;
wire [7:0] out;
integer i;
36
 decoder3x8 dut ( .in(in), .out(out) );

initial begin
$monitor($time,"Input: in=%b, Output: out=%b",in, out);
for(i=0;i<=7;i=i+1) begin
in=i;
#10;
end
#10;
$stop;
end
endmodule

Waveforms

2.1 write a verilog hdl code and its testbench for half-adder:

// Half-Adder Module
module half_adder(input a, b, output sum, carry);xor(sum, a, b);
and(carry, a, b);
endmodule

// Testbench for Half-Adder

module half_adder_tb;
reg a, b;
wire sum, carry;
// Instantiate the Half-Adder module
half_adder dut(a, b, sum, carry);

37
 // Apply stimulus
initial begin
$monitor("%b %b | %b %b", a, b, sum, carry);
$display("A B | Sum Carry");
$display(" -------------------------");
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish;
end
endmodule

Output Waveforms:

RTL Schematic:

38
 2.2 write a verilog hdl code and its testbench for 1-bit full-adder:

// Full-Adder Module
module full_adder(input a, b, cin, output sum, cout);wire s1, c1, c2;
xor(s1, a, b);
xor(sum, s1, cin);
and(c1, a, b);
and(c2, s1, cin);
or(cout, c1, c2);
endmodule

// Testbench for Full-Adder

module full_adder_tb;
reg a, b, cin; wire
sum, cout;

// Instantiate the Full-Adder modulefull_adder

dut(a, b, cin, sum, cout);

// Apply stimulus
initial begin
$monitor("%b %b %b | %b %b", a, b, cin, sum, cout);
$display("A B Cin | Sum Cout");
$display(" --------------------------- ");
a = 0; b = 0; cin = 0; #10;
a = 0; b = 0; cin = 1; #10;
a = 0; b = 1; cin = 0; #10;
a = 0; b = 1; cin = 1; #10;
a = 1; b = 0; cin = 0; #10;
a = 1; b = 0; cin = 1; #10;

39
a = 1; b = 1; cin = 0; #10;
a = 1; b = 1; cin = 1; #10;
$finish;
end
endmodule

Waveforms:

RTL Schematic:

2. 3 write a verilog hdl code and its testbench for half-subtractor:

// Half-Subtractor Module
module half_subtractor(input a, b, output diff, bout);wire n1, n2;

40
 not(n1, a);
xor(diff, a, b);
and(bout, n1, b);
endmodule

// Testbench for Half-Subtractormodule

half_subtractor_tb;
reg a, b;
wire diff, bout;

// Instantiate the Half-Subtractor modulehalf_subtractor dut(a, b,

diff, bout);

// Apply stimulus
initial begin
$monitor("%b %b | %b %b", a, b, diff, bout);
$display("A B | Diff Bout");
$display(" -------------------------");
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish;
end
endmodule

41
Waveforms:

RTL Schematic:

42
 2.4 write a verilog hdl code and its testbench for 1-bit full-subtractor:

// Full-Subtractor Module
module full_subtractor(input a, b, bin, output diff, bout);xor(diff,a,b,bin);
xnor(y1,a,b);
and(y2,bin,y1);
not(y3,a);
and(y4,y3,b);
or(bout,y2,y4);
endmodule
// Testbench for Full-Subtractormodule
full_subtractor_tb;
reg a, b, bin; wire
diff, bout;

// Instantiate the Full-Subtractor modulefull_subtractor dut(a, b, bin,

diff, bout);

// Apply stimulus
initial begin
$monitor("%b %b %b | %b %b", a, b, bin, diff, bout);
$display("A B Bin | Diff Bout");
$display(" -------------------------------- ");
a = 0; b = 0; bin = 0; #10;
a = 0; b = 0; bin = 1; #10;
a = 0; b = 1; bin = 0; #10;

43
a = 0; b = 1; bin = 1; #10;
a = 1; b = 0; bin = 0; #10;
a = 1; b = 0; bin = 1; #10;
a = 1; b = 1; bin = 0; #10;
a = 1; b = 1; bin = 1; #10;
$finish;
end
endmodule
Output:

RTL Schematic:

44
 2.5 write a verilog hdl code and its testbench for MUX 2x1

// 2x1 Multiplexer (MUX) Module

module mux_2x1(input a, b, sel, output y);wire w1, w2;

and(w1, a, ~sel);
and(w2, b, sel);
or(y, w1, w2);
endmodule

// Testbench for 2x1 Multiplexermodule

mux_2x1_tb;
reg a, b, sel;
wire y;

// Instantiate the 2x1 Multiplexer modulemux_2x1

dut(a, b, sel, y);

// Apply stimulus
initial begin
$monitor("%b %b %b | %b", a, b, sel, y);
$display("A B Sel | Y");
$display(" --------------- ");
a = 0; b = 0; sel = 0; #10;
a = 0; b = 0; sel = 1; #10;
a = 0; b = 1; sel = 0; #10;
a = 0; b = 1; sel = 1; #10;
a = 1; b = 0; sel = 0; #10;
a = 1; b = 0; sel = 1; #10;

45
a = 1; b = 1; sel = 0; #10;
a = 1; b = 1; sel = 1; #10;
$finish;
end
endmodule

Output waveforms:

RTL Schematic:

46
// 4-to-2 Encoder Module
module encoder_4to2(input [3:0] data, output [1:0] y);
or(y[0],data[1],data[3]);
or(y[1],data[2],data[3]);
endmodule

//Testbench module
module encoder_4to2_tb;
reg [3:0] data;
wire [1:0] y;

// Instantiate the 4-to-2 Encoder module

encoder_4to2 dut(data, y);

// Apply stimulus
initial begin
$monitor("%b | %b", data, y);
$display("Data | Y");
$display(" ----------- ");
data = 4'b0000; #10;
data = 4'b0001; #10;
data = 4'b0010; #10;
data = 4'b0011; #10;
data = 4'b0100; #10;
data = 4'b0101; #10;
data = 4'b0110; #10;
data = 4'b0111; #10;
data = 4'b1000; #10;
data = 4'b1001; #10;
data = 4'b1010; #10;
data = 4'b1011; #10;
data = 4'b1100; #10;
data = 4'b1101; #10;
47
 data = 4'b1110; #10;
data = 4'b1111; #10;
$finish;
end
endmodule

// 2-to-4 Decoder Module

module decoder_2to4(din [1:0] data, dout [3:0] y);wire w1, w2;

not (w1, data[0]);

not (w2, data[1]);

and (y[0], w1, w2);

and (y[1], data[0], w2);
and (y[2], w1, data[1]);
and (y[3], data[0], data[1]);

endmodule

// Testbench for 2-to-4 Decoder

`timescale 1ns/1ns module
decoder_2to4_tb;reg [1:0] data;
wire [3:0] y;

48
 // Instantiate the 2-to-4 Decoder moduledecoder_2to4
dut(data, y);

// Apply stimulus
initial begin
$monitor("%b | %b", data, y);
$display("Data | Y");
$display(" -------------------- ");
data = 2'b00; #10; data =
2'b01; #10; data = 2'b10;
#10;data = 2'b11; #10;
$finish;
end
endmodule

Out Waveforms:

49
RTL Schematic

// 1x2 Demultiplexer (deMUX) Module

module demux_1x2(input a, sel, output y0, y1);wire w1;
not(w1, sel);
and(y0, a, w1);
and(y1, a, sel);
endmodule

// Testbench
for 1x2 Demultiplexermodule demux_1x2_tb;
reg a, sel;
wire y0, y1;

// Instantiate the 1x2 Demultiplexer moduledemux_1x2 dut(a, sel,

y0, y1);

// Apply stimulus
initial begin
$monitor("%b %b | %b %b", a, sel, y0, y1);
50
$display("A Sel | Y0 Y1");
$display(" ---------------------- ");
a = 0; sel = 0; #10;
a = 0; sel = 1; #10;
a = 1; sel = 0; #10;
a = 1; sel = 1; #10;
$finish;
end
endmodule

// 1-bit Comparator Module

module comparator_1bit(input a, input b, output equal, output greater, output less);
xnor(equal, a, b);
not(bbar,b);
and(greater,a,bbar);
not(abar,a);
and(less,abar,b);
endmodule

// Testbench for 1-bit Comparator

module comparator_1bit_tb;
reg a, b;
wire equal, greater, less;

// Instantiate the 1-bit Comparator module

comparator_1bit dut(a, b, equal, greater, less);

// Apply stimulus
initial begin
$monitor("%b %b | %b %b %b", a, b, equal, greater, less);
$display("A B | Equal Greater Less");
51
 $display(" ----------------------- ");
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish;
end
endmodule

// Half-Adder module
module half_adder(input a, b, output sum, carry);assign sum = a ^ b;
assign carry = a & b;
endmodule

// Testbench for Half-Adder

module half_adder_tb;
reg a, b;
wire sum, carry;

// Instantiate the Half-Adder module

half_adder dut(a, b, sum, carry);

// Apply stimulus
initial begin
$monitor("%b %b | %b %b", a, b, sum, carry);
$display("A B | Sum Carry");
$display(" -------------------------");
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;

52
a = 1; b = 1; #10;
$finish;
end
endmodule

//1-bit full-adder module

module full_adder(input a, b, cin, output sum, cout);assign sum = a ^
b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule

// Testbench for Full-Adder

module full_adder_tb;
reg a, b, cin; wire
sum, cout;
// Instantiate the Full-Adder modulefull_adder
dut(a, b, cin, sum, cout);

// Apply stimulus
initial begin
$monitor("%b %b %b | %b %b", a, b, cin, sum, cout);
$display("A B Cin | Sum Cout");
$display(" --------------------------- ");
a = 0; b = 0; cin = 0; #10;
a = 0; b = 0; cin = 1; #10;
a = 0; b = 1; cin = 0; #10;
a = 0; b = 1; cin = 1; #10;
a = 1; b = 0; cin = 0; #10;
a = 1; b = 0; cin = 1; #10;
a = 1; b = 1; cin = 0; #10;

53
a = 1; b = 1; cin = 1; #10;
$finish;
end
endmodule

//Half_subtractor module
module half_subtractor(input a, b, output diff, borrow);assign diff = a ^ b;
assign borrow = (~a) & b;
endmodule

// Testbench for Half-Subtractormodule

half_subtractor_tb;
reg a, b;
wire diff, bout;

// Instantiate the Half-Subtractor modulehalf_subtractor dut(a, b,

diff, bout);

// Apply stimulus
initial begin
$monitor("%b %b | %b %b", a, b, diff, bout);
$display("A B | Diff Bout");
$display(" -------------------------");
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish;
end
endmodule

54
//1-bit full-subtractor module

module full_subtractor(input a, b, bin, output diff, bout);

assign diff = a ^ b ^ bin;
assign bout = (~a & b) | (~a & bin) | (b & bin);
endmodule

// Testbench for Full-Subtractor

module full_subtractor_tb;
reg a, b, bin;
wire diff, bout;

// Instantiate the Full-Subtractor module

full_subtractor dut(a, b, bin, diff, bout);

// Apply stimulus
initial begin
$monitor("%b %b %b | %b %b", a, b, bin, diff, bout);
$display("A B Bin | Diff Bout");
$display(" -------------------- ");
a = 0; b = 0; bin = 0; #10;
a = 0; b = 0; bin = 1; #10;
a = 0; b = 1; bin = 0; #10;
a = 0; b = 1; bin = 1; #10;
a = 1; b = 0; bin = 0; #10;
a = 1; b = 0; bin = 1; #10;
a = 1; b = 1; bin = 0; #10;
a = 1; b = 1; bin = 1; #10;
$finish;
end
endmodule

55
//MUX 2x1 module
module mux_2x1(input d0, d1, sel, output y);
assign y = sel ? d1 : d0;
endmodule

// Testbench for 2x1 Multiplexer

module mux_2x1_tb;
reg a, b, sel;
wire y;

// Instantiate the 2x1 Multiplexer module

mux_2x1 dut(a, b, sel, y);

// Apply stimulus
initial begin
$monitor("%b %b %b | %b", a, b, sel, y);
$display("A B Sel | Y");
$display(" ---------- ");
a = 0; b = 0; sel = 0; #10;
a = 0; b = 0; sel = 1; #10;
a = 0; b = 1; sel = 0; #10;
a = 0; b = 1; sel = 1; #10;
a = 1; b = 0; sel = 0; #10;
a = 1; b = 0; sel = 1; #10;
a = 1; b = 1; sel = 0; #10;
a = 1; b = 1; sel = 1; #10;
$finish;
end
endmodule

56
 //encoder_4to2 module
module encoder_4to2(input [3:0] data, output [1:0] y);assign y[0] =
data[1] | data[3] ;
assign y[1] = data[2] | data[3] ;endmodule

//Testbench module module

encoder_4to2_tb;reg [3:0] data;
wire [1:0] y;

// Instantiate the 4-to-2 Encoder moduleencoder_4to2

dut(data, y);

// Apply stimulus
initial begin
$monitor("%b | %b", data, y);
$display("Data | Y");
$display(" --------------------- ");
data = 4'b0000; #10; data =
4'b0001; #10;data = 4'b0010;
#10;data = 4'b0011; #10;data
= 4'b0100; #10; data =
4'b0101; #10;

57
data = 4'b0110; #10;data = 4'b0111; #10;data =
4'b1000; #10; data = 4'b1001; #10; data =
4'b1010; #10; data = 4'b1011; #10; data =
4'b1100; #10; data = 4'b1101; #10; data =
4'b1110; #10;data = 4'b1111; #10;
$finish; end endmodule

//decoder_2to4 module
module decoder_2to4(input [1:0] sel, output [3:0] y);assign y[0] = (~sel[0] & ~sel[1]);
assign y[1] = (sel[0] & ~sel[1]);
assign y[2] = (~sel[0] & sel[1]) ;
assign y[3] = (sel[0] & sel[1]) ;endmodule

// Testbench for 2-to-4 Decoder

`timescale 1ns/1ns module decoder_2to4_tb;reg
[1:0] data;

wire [3:0] y;

// Instantiate the 2-to-4 Decoder moduledecoder_2to4 dut(data, y);

// Apply stimulusinitial begin

$monitor("%b | %b", data, y);
$display("Data | Y");
$display(" -------------------- ");
data = 2'b00; #10; data = 2'b01; #10; data =
2'b10; #10;data = 2'b11; #10;
$finish; end endmodule

//de-mux 1x2 module

module demux_1x2(input d, sel, output y0, y1);assign y0 = sel ? 1'b0 : d;
assign y1 = sel ? d : 1'b0;endmodule
// Testbench for 1x2 Demultiplexermodule demux_1x2_tb;
reg a, sel; wire y0, y1;

58
 // Instantiate the 1x2 Demultiplexer moduledemux_1x2 dut(a, sel, y0, y1);

// Apply stimulusinitial begin

$monitor("%b %b | %b %b", a, sel, y0, y1);
$display("A Sel | Y0 Y1");
$display(" ----------------------- ");
a = 0; sel = 0; #10;
a = 0; sel = 1; #10;
a = 1; sel = 0; #10;
a = 1; sel = 1; #10;
$finish; end endmodule

//comparator_1bit module
module comparator_1bit(input a, b, output less, equal, greater);assign less = (a < b) ? 1'b1 : 1'b0;
assign equal = (a == b) ? 1'b1 : 1'b0;assign greater = (a > b) ? 1'b1
: 1'b0; endmodule
// Testbench for 1-bit Comparatormodule comparator_1bit_tb;
reg a, b;
wire equal, greater, less;

// Instantiate the 1-bit Comparator module comparator_1bit dut(a, b, equal, greater,

less);

// Apply stimulusinitial begin

$monitor("%b %b | %b %b %b", a, b, equal, greater, less);
$display("A B | Equal Greater Less");
$display(" ------------------------------------");
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish; end endmodule

59
 EXPERIMENT-4

//4-bit up-down counter:

module counter_updown4bit(clk,rst,ud,count);input clk,rst;

input ud; // ud=1 for up count; ud=0 for down countoutput reg [3:0]count;

always@(posedge clk)begin
if(rst) count<=0; else if(ud)
count<=count+1'b1;else
count<=count-1'b1;end

endmodule

//4-bit up-down counter testbench:

`timescale 1ns/1psmodule tb;

reg clk,rst;
reg ud; // ud=1 for up count; ud=0 for down countwire [3:0]count;

counter_updown4bit dut(clk,rst,ud,count);initial
begin

clk<=0;rst<=0; end

always #5 clk<=~clk;initial
begin
$monitor("clk %b,rst %b,ud %b,count %0d",clk,rst,ud,count);@(posedge clk); rst<=1;
@(posedge clk); rst<=0;repeat(20)
begin
@(posedge clk); ud<=1;end
repeat(20)begin
@(posedge clk); ud<=0;end
$stop;end
endmodule

Waveforms:

60
 EXPERIMENT-4

SEQUENTIAL CIRCUITS
AIM:

Write a Verilog HDL program in behavioral model for D,T and JK flip flops, shift registers and
counters.

APPARATUS:
1. Computer system
2. VIVADO software tool

SR-FF:

LOGIC SYMBOL:

SR-FF q
CLK
RST
S qb
R

Truth Table:

CLK RST S R qprev q qb

1 X X X 0 1

0 0 0 0 0 1

0 0 0 1 1 0

0 0 1 X 0 1

0 1 0 X 1 0

0 1 1 X Indeterminate
state

Behavioral Description:

`timescale 1ns / 1ps

module srff( input clk, input rst, input s, input r, output reg q, output regqb );
reg[1:0] sr;
61
 always@(posedge clk)
begin
if(rst==1'b1) q=1'b0;
else
begin
sr={s,r};

end

case (sr) 2'b00: q=q; 2'b01:

q=1'b0;
2'b10: q=1'b1;
2'b11: q=1'bZ;
default: q=1'bx;endcase
qb=~q; end endmodule

Test Bench Program:

`timescale 1ns / 1ps

module srff_test; reg
clk;
reg rst;
reg s; reg
r; wire q;
wire qb;
srff uut (.clk(clk), .rst(rst), .s(s), .r(r), .q(q), .qb(qb));initial
begin
end always
#10 clk=~clk;
Endmodule

Output Waveform:

Verilog code for JK-Flip Flop

Behavioral Description:

`timescale 1ns / 1ps

module jkff( input clk, input rst, input j, input k, output reg q, output regqb );
62
reg[1:0] jk;
always@(posedge clk)
begin
if(rst==1'b1)
q=1'b0;
else
begin
jk={j,k};
case (jk)
2'b00: q=q;
2'b01: q=1'b0;
2'b10: q=1'b1;
2'b11: q=~q;
default: q=1'bx;
endcase
end
qb=~q;
end
endmodule

Test Bench Program:

`timescale 1ns / 1ps

module jkff_test;
reg clk;
reg rst;
reg j;
reg k;
wire q;
wire qb;
jkff uut (.clk(clk), .rst(rst), .j(j), .k(k), .q(q), .qb(qb));initial
begin
clk = 0;
rst = 1;
j = 0;
k = 0;
#30 j=0 ;k=0;rst=0;
#30j=0;k=1;
#30 j=1;k=0;
#30 j=1;k=1;
#200 $finish;
end
always
#10 clk=~clk;
Endmodule
63
Output Waveform:

64
 Verilog code for D-Flip Flop

`timescale 1ns / 1ps module dff(clk,rst,d, q,qb);input clk,rst,d;

output q,qb;reg q,qb;
always@(posedge clk)begin
if(rst==1'b1) q=1'b0;
else
q=d; qb=~q; end endmodule

Test Bench Program:

`timescale 1ns / 1psmodule dFF_test; reg clk;

reg rst; reg d; wire q; wire qb;
dFF uut (.clk(clk),.rst(rst),.d(d),.q(q),.qb(qb));initial
begin clk = 0;
rst = 1;
d = 0;
#30 d=1;
#30 rst=0;
#30 d=0;
#30 d=1;
#100 $finish;end
always
#10 clk=~clk;
endmodule

Verilog code for JK-Flip Flop

65
 Truth Table

Behavioral Description:
`timescale 1ns / 1ps
module jkff( input clk, input rst, input j, input k,
output reg q, output reg qb );
reg[1:0] jk;
always@(posedge clk)
begin if(rst==1'b1)
q=1'b0;
else begin jk={j,k};
case (jk)
2'b00: q=q;
2'b01: q=1'b0;
2'b10: q=1'b1;
2'b11:
q=~q;
default: q=1'bx;
endcase
end
qb=~q;
end
66
endmodule

Test Bench Program:

`timescale 1ns / 1ps
module jkff_test;
reg clk; reg rst; reg j; reg k;
wire q; wire qb;
jkff uut (.clk(clk), .rst(rst), .j(j), .k(k), .q(q), .qb(qb));
initial begin
clk = 0; rst = 1;
j = 0; k = 0; #30
j=0 ;k=0;rst=0; #30
j=0;k=1; #30
j=1;k=0; #30
j=1;k=1; #200
$finish;
end always #10 clk=~clk;

67
 Verilog code for D-Flip Flop

Verilog Code

`timescale 1ns / 1ps

module dff(clk,rst,d, q,qb);
input clk,rst,d;
output q,qb; reg q,qb;
always@(posedge clk)
begin if(rst==1'b1) q=1'b0;
else
q=d;
qb=~q;
end
endmodule
Test Bench Program: `timescale 1ns / 1ps module
dFF_test;
reg clk; reg rst; reg d;
wire q; wire qb;
dFF uut (.clk(clk),.rst(rst),.d(d),.q(q),.qb(qb));
initial begin clk = 0;
68
rst = 1; d = 0;
#30 d=1;
#30 rst=0;
#30 d=0;
#30 d=1;
#100 $finish; end always #10 clk=~clk;
endmodule

69
 EXPERIMENT-5
Verilog HDL program in structural and behavioral models for a) 8 bit asynchronous up-
down counter

module async_up_down_counter_structural(
input wire clk,
input wire rst,
input wire up,
input wire down,
output reg [7:0] out
);

reg [7:0] temp;

always @ (posedge clk or posedge rst) begin

if (rst) begin
temp <= 8'b00000000;
end else begin
if (up) begin
temp <= temp + 1;
end else if (down) begin
temp <= temp - 1;
end
end
end

assign out = temp;

endmodule

Behavioral

module async_up_down_counter_behavioral(
input wire clk,
input wire rst,
input wire up,
input wire down,
output reg [7:0] out
);

reg [7:0] temp;

always @ (posedge clk or posedge rst) begin

if (rst) begin
temp <= 8'b00000000;
end else begin
70
 if (up) begin
temp <= temp + 1;
end else if (down) begin
temp <= temp - 1;
end
end
end

assign out = temp;

endmodule

8 bit synchronous up-down counter

module sync_up_down_counter_structural(
input wire clk,
input wire rst,
input wire up,
input wire down,
output reg [7:0] out
);

reg [7:0] temp;

always @ (posedge clk or posedge rst) begin

if (rst) begin
temp <= 8'b00000000;
end else begin
if (up) begin
temp <= temp + 1;
end else if (down) begin
temp <= temp - 1;
end
end
end

assign out = temp;

endmodule

module sync_up_down_counter_behavioral(
input wire clk,
input wire rst,
input wire up,
input wire down,
output reg [7:0] out
71
 );

reg [7:0] temp;

always @ (posedge clk or posedge rst) begin

if (rst) begin
temp <= 8'b00000000;
end else begin
if (up) begin
temp <= temp + 1;
end else if (down) begin
temp <= temp - 1;
end
end
end

assign out = temp;

endmodule

Wave forms

72
 EXPERIMENT-6

Mealy state machines

AIM:

To write the Verilog code for 4-bit sequence detector through Mealy state
machines and obtain the simulation, synthesis results using Xilinx ISE tool.

APPARATUS:
3. Computer system
4. VIVADO software tool

BLOCK DIAGRAM

Verilog code

module FSM_Mealy( y, x, clock, reset);

input x, clock, reset;
output y;

reg y;
reg [1:0] Prstate, Next_state;

parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11;

always @(posedge clock)

begin
if (reset)
Prstate = s0;
else
73
 Prstate = Next_state;
end

always @(Prstate or x)
begin
case (Prstate)
s0: if (x)
begin
Next_state = s1;
y = 1'b0;
end
else
begin
Next_state = s0;
y = 1'b0;
end
s1: if (x)
begin
Next_state = s3;
y = 1'b0;
end
else
begin
Next_state = s0;
y = 1'b1;
end
s2: if (~x)
begin
Next_state = s0;
y = 1'b1;
end
else
begin
Next_state = s2;
y = 1'b0;
end
s3: if (x)
begin
Next_state = s2;
y = 1'b0;
end
else
begin
Next_state = s0;
y = 1'b1;
end
endcase
end
endmodule

TEST BENCH:
74
module FSM_Mealy_tb_v;

reg x;
reg clock;
reg reset;

wire y;

FSM_Mealy uut(
.y(y),
.x(x),
.clock(clock),
.reset(reset)
);

initial begin

x = 0; clock = 0; reset = 1;
#10 x = 0; reset = 0;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 0; #100;

end
always #5 clock = ~clock;

endmodule

Waveform:

75
 EXPERIMENT-7
Moore state machines

AIM:

To write the Verilog code for 4-bit sequence detector through Moore state
machines and obtain thesimulation, synthesis results using VIVADO tool.
APPARATUS:
1. Computer system
2. VIVADO software tool

BLOCK DIAGRAM

A Moore state machine in Verilog differs from a Mealy state machine in that its outputs depend

only on the current state. Here's an example of a Moore state machine that detects the '1011'

sequence.

Verilog Code:

module moore_sequence_detector (

input wire clk,

input wire reset,

input wire data_in,

output reg sequence_detected

76
);

// State enumeration

typedef enum logic [1:0] {

S0, // Initial state

S1,

S2,

S3,

S4 // Final state where sequence is detected

} state_t;

// Define the state register

reg [1:0] state, next_state;

// Define the output register

reg [1:0] output_reg;

// Moore state transition and output logic

always @(posedge clk or posedge reset) begin

if (reset) begin

state <= S0;

sequence_detected <= 0;

end else begin

state <= next_state;

sequence_detected <= output_reg[state];

end

end

always @* begin

77
next_state = state;

case (state)

S0: begin

if (data_in) begin

next_state = S1;

end else begin

next_state = S0;

end

end

S1: begin

if (data_in) begin

next_state = S2;

end else begin

next_state = S0;

end

end

S2: begin

if (data_in) begin

next_state = S3;

end else begin

next_state = S0;

end

end

78
S3: begin

if (!data_in) begin

next_state = S0;

end else begin

next_state = S4;

end

end

S4: begin

79