1.

Perform logic synthesis using chiptop design

2. Use following timing constraints

set PERIOD 3.0

set INPUT_DELAY 1.0

set OUTPUT_DELAY 1.0

set CLOCK_LATENCY 1.0

set SOURCE_LATENCY 1.0

set UNCERTAINTY 0.15

set MAX_TRANSITION 0.5

set MIN_CLOCK_LATENCY 0.5

set MIN_SOURCE_LATENCY 0.5

set MIN_IO_DELAY 0.5

every output drive 10 Inverters in next stage

every input driven by least drive strength Inverter, except clk and reset.

3. Reports for Timing, Area, Power and QoR.

Design: chiptop

14nm
Technology: Frequency 150 Mhz
EDK

ff0p88v25c
Corners tt0p8v125c Jitter 150 ps

Wire Load 35000 Skew 350 ps

Power
Worst negative slack

Total negative slack

Number of violating

Dynamic Power Leakage Power

Cell
paths

Name ns ns -
Design: chiptop

14nm
Technology: Frequency 150 Mhz
EDK

ff0p88v25c
Corners tt0p8v125c Jitter 150 ps

Wire Load 35000 Skew 350 ps

Power
Worst negative slack

Total negative slack

Number of violating
Dynamic Power Leakage Power

Cell

paths
Max 0 0 0 0 0 0 0