‫مجموعة من أسئلة الخيارات المرشحة لالمتحان النهائي للمرحلة الرابعة‬

‫الكترونيك‬

Chapter 1: Timing Circuits

1. A one-shot is a type of
a) Monostable multivibrator
b) Astable multivibrator
c) Bistable multivibrator
d) none of above
2. A 𝟏 𝝁𝒔 pulse can be converted into a 𝟏 𝒎𝒔 pulse by using a:
a) Astable multivibrator
b) Monostable multivibrator
c) Bistable multivibrator
d) Schmitt trigger

3. What is the function of the Threshold pin?

a) To charge the capacitor "C".

b) To discharge the capacitor "C".
c) To detect when the capacitor is "HIGH".
d) To detect when the capacitor is "LOW".
4. The monostable multivibrator circuit is not an oscillator because
a) Its output switches between two states
b) It requires a sine wave input signal
c) The circuit does not require a dc power supply
d) It requires a trigger to obtain an output signal
5. An astable multivibrator has
a) One stable state
b) One quasi-stable state
c) Two quasi-stable states
d) None of the above
6. The gate width of a monostable multivibrator is given by
a) 𝑇 = 1.1𝑅𝐶
b) 𝑇 = 0.693𝑅𝐶
c) 𝑇 = 0.963𝑅𝐶
d) 𝑇 = 0.369𝑅𝐶
7. What is the function of the comparators in the 555 timer circuit?
a) to compare the input voltages to the internal voltage divider
b) to compare the output voltages to the internal voltage divider
c) to compare the output voltages to the external voltage divider
d) to compare the input voltages to the external voltage divider
8. A monostable 555 timer has the following number of stable states:
a) 0
b) 1
c) 2
d) 3
9. An astable multivibrator
a) has no stable state
b) is an oscillator
c) produces a periodic pulse output
d) all of the above
10. A monostable multivibrator has
a) No stable state
b) One stable state
c) Two stable states
d) None of the above

11. A multivibrator circuit is in its stable state. When it is triggered by a pulse it

goes to another state for some time and comes back to its original state. It is:
a) An astable multivibrator
b) A bistable multivibrator
c) A monostable multivibrator
d) A latch
12. What does the discharge transistor do in the 555 timer circuit?
a) charge the external capacitor to stop the timing
b) charge the external capacitor to start the timing over again
c) discharge the external capacitor to stop the timing
d) discharge the external capacitor to start the timing over again
13. What is the difference between an astable multivibrator and a monostable
multivibrator?
a) The astable is free running
b) The astable needs to be clocked
c) The monostable is free running
d) None of the above
14. The pulse width of a monostable multivibrator can be controlled by
a) The amplitude of the trigger pulse
b) The width of the trigger pulse
c) The timing resistor and capacitor
d) Any of the above
15. To obtain a 50% duty cycle in an astable 555 timer circuit
a) 𝑅𝐴 = 𝑅𝐵 and short 𝑅𝐵 with a diode during the capacitor charging cycle
b) Capacitor voltage must rise above 1/3 VCC
c) 𝑡𝐿𝑂 = 𝑡𝐻𝐼 , 𝑅𝐴 = 𝑅𝐵 , and short 𝑅𝐵 with a diode during the capacitor charging cycle
d) 𝑡𝐿𝑂 = 𝑡𝐻𝐼
16. A 𝟏 𝝁𝒔 pulse can be converted into a 1 ms pulse by using
a) Monostable multivibrator
b) Bistable multivibrator
c) Astable multivibrator
d) J-K flip-flop
17. The pulse-width of a monostable multivibrator can be controlled by
a) The amplitude of the trigger pulse.
b) The timing resistor and capacitor.
c) The width of the trigger pulse.
d) None of the above
18. Pulse stretching, time-delay, and pulse generation are all easily accomplished
with which type of multivibrator circuit?

a) Astable.
b) Monostable.
c) Multi-stable.
d) Bi-stable

19. Bistable multivibrator is also known as

a) binary
b) flip-flop
c) Ecless Jordan circuit
d) All of above
20. A monostable multivibrator circuit can be made using
a) Logic gates
b) OP AMPs
c) 555 timer
d) Any of the above
21. A 555 timer can be used as
a) An astable multivibrator only
b) A monostable multivibrator only
c) A frequency divider only
d) Any of the above
22. The ________ is defined as the time the output is active divided by the total
period of the output signal.
a) on time
b) off time
c) duty cycle
d) active ratio
23. An astable multivibrator requires
a) balanced time constants
b) a pair of matched transistors
c) no input signal
d) dual J-K flip-flops
24. The output of the astable circuit ________.
a) constantly switches between two states
b) is LOW until a trigger is received
c) is HIGH until a trigger is received
d) floats until triggered

Chapter 2: Integrated Circuits Technology

25. When the frequency of the input signal to a CMOS gate is increased, the
average power dissipation
a) Decreases
b) Increases
c) Does not change
d) Decreases exponentially
26. If two unused inputs of a LS TTL gate are connected to an input being driven
by another LS TTL gate, the total number of remaining unit loads that can be
driven by this gate is
a) 7
b) 8
c) 17
d) Unlimited
27. An open TTL NOR gate input
a) acts as a HIGH
b) acts as a LOW
c) should be connected to VCC through a resistor
d) all the above
28. In a TTL circuit, if an excessive number of load gate inputs are connected,
then:
a) 𝑉𝑂𝐻(min) drops below 𝑉𝑂𝐻
b) 𝑉𝑂𝐻 exceeds 𝑉𝑂𝐻(min)
c) 𝑉𝑂𝐻 drops below 𝑉𝑂𝐻(min)
d) 𝑉𝑂𝐻 and 𝑉𝑂𝐻(min) are unaffected
29. The input transistor in a TTL circuit is unusual in that it has:?
a) Multiple emitters.
b) Multiple bases.
c) No base.
d) No collector.
30. Totem-pole outputs ………….. be connected …………… because …………..
a) Can, in parallel, sometimes higher current is required.
b) Cannot, together, if the outputs are in opposite states excessively high currents can
damage one or both devices.
c) Should, in series, certain applications may require higher output voltage.
d) Can, together, together they can handle larger load currents and higher output
voltages.
31. Which of the following summarizes the important features of emitter-coupled
logic (ECL)?
a) Slow propagation time, high frequency response, low power consumption, and high
output voltage swings.
b) Good noise immunity, negative logic, high frequency capability, low power
dissipation, and short propagation time.
c) Poor noise immunity, positive supply voltage operation, good low-frequency
operation, and low power.
d) Negative voltage operation, high speed, and high power consumption.
32. Why are the maximum value of 𝑽𝑶𝑳 and the minimum value of 𝑽𝑶𝑯 used to
determine the noise margin rather than the typical values for these
parameters?
a) These are normal conditions.
b) These are best-case conditions.
c) These are worst-case conditions.
d) It doesn't matter what values are used.
33. CMOS operates more reliably than TTL in a high-noise environment because
of its
a) lower noise margin
b) input capacitance
c) higher noise margin
d) smaller power dissipation
34. The basic mechanism for storing a data bit in an 𝑬𝟐 CMOS cell is
a) Control gate
b) Floating drain
c) Floating gate
d) Cell current
35. Which of the following operating conditions will probably result in the lowest
average 𝑷𝑫 for a CMOS logic system?
a) 𝑉𝐷𝐷 = 5 𝑉, switching frequency 𝑓𝑚𝑎𝑥 = 1 𝑀𝐻𝑧.
b) 𝑉𝐷𝐷 = 10 𝑉, switching frequency 𝑓𝑚𝑎𝑥 = 1 𝑀𝐻𝑧.
c) 𝑉𝐷𝐷 = 10 𝑉, switching frequency 𝑓𝑚𝑎𝑥 = 10 𝑘𝐻𝑧.
d) 𝑉𝐷𝐷 = 5 𝑉, switching frequency 𝑓𝑚𝑎𝑥 = 10 𝑘𝐻𝑧.

36. What is the range of invalid TTL output voltage?

a) 0.0 – 0.4 V.
b) 0.4 – 2.4 V.
c) 2.4 – 5.0 V.
d) 0.0 – 5.0 V.
37. An open input terminal of a TTL gate
a) Will assume a very high voltage
b) Will behave as if it is connected to logic 0 level
c) Will behave as if it is connected to logic 1 level
d) Will assume some voltage between logic 0 and 1 levels
38. A TTL totem pole circuit is designed so that the output transistors are:
a) Always ON together.
b) Never ON together.
c) Providing phase splitting.
d) Providing voltage regulation
39. It is best not to leave unused TTL inputs unconnected (open) because of TTL's:
a) Noise sensitivity.
b) Low-current requirement.
c) Open-collector outputs.
d) Tristate construction
40. The most important parameter in comparing between a CMOS gate and a
TTL gate is:
a) Power dissipation.
b) Propagation delay.
c) Output drive.
d) Speed-power product
41. Proper handling of a CMOS device is necessary because of its
a) fragile construction
b) high-noise immunity
c) susceptibility to electrostatic discharge
d) low power dissipation
42. The main advantage of ECL over TTL or CMOS is
a) ECL is less expensive
b) ECL consumes less power
c) ECL is available in a greater variety of circuit types
d) ECL is faster
43. ECL cannot be used in
a) high-noise environments
b) damp environments
c) high-frequency applications
d) high-temperature environments
44. An LS TTL gate can drive a maximum of
a) 20 unit loads.
b) 10 unit loads.
c) 40 unit loads.
d) Unlimited unit loads.
45. The switching speed of ECL is very high because
a) The transistors are switched between cut-off and saturation regions
b) The transistors are switched between active and saturation regions
c) The transistors are switched between active and cut-off regions

d) The transistors may operate in any of the three regions

46. Which of the following would be most likely to destroy a TTL totem-pole
output while it is trying to switch from HIGH to LOW?
a) Tying the output to ground.
b) Applying an input of 7 V.
c) Tying the output to another TTL totem-pole output.
d) Tying the output to +5 𝑉

47. An open collector output can ………… current, but it cannot …………
a) Sink, source current.
b) Source, sink current.
c) Sink, source voltage.
d) Source, sink voltage
48. Which statement is correct about 𝑬𝟐 𝑴𝑶𝑺:
a) 𝐸 2 𝑀𝑂𝑆 technology is based on a combination of PMOS and NMOS technologies.
b) When the floating gate is charging to a negative potential by placing electrons on
it, the sense transistor is turned on, storing a binary 1.
c) To start programming of the cell, it must first be selected by a voltage in the word
line.
d) All the above

Chapter 3: Signal Conversion and Processing

49. Aliasing results in

a) oversampling
b) undersampling
c) guard-band formation
d) perfect sampling
50. Generally, an analog signal can be reconstructed more accurately with
a) more quantization levels
b) fewer quantization levels
c) a lower sampling frequency
d) none of the above
51. A digital voltmeter uses a
a) flash ADC
b) successive approximation ADC
c) sigma-delta ADC
d) dual-slope ADC
52. Which is not an A/D conversion errors?
a) Incorrect code
b) Differential nonlinearity
c) Missing code
d) Offset
53. Which type of ADC quantizes the analog signal into a stream of bits whose
amount corresponds to the signal level?
a) Successive-approximation ADC.
b) Sigma-delta ADC.
c) Dual-slope ADC.
d) None of the above.
54. In a flash ADC, the output of each comparator is connected to an input of a:
a) Decoder.
b) Buffer.
c) Multiplexer.
d) Priority encoder.
55. The percentage resolution of a 10-bit ADC is nearly:
a) 1%
b) 0.01%
c) 0.1%
d) 10%
56. Sample-and-hold circuits in analog-to digital converters (ADCs) are designed
to:
a) sample and hold the output of the binary counter during the conversion process
b) stabilize the comparator's threshold voltage during the conversion process
c) stabilize the input analog signal during the conversion process
d) sample and hold the D/A converter staircase waveform during the conversion
process
57. According to the sampling theorem, the sampling frequency should be
a) less than half the highest signal frequency
b) greater than twice the highest signal frequency
c) less than half the lowest signal frequency
d) greater than the lowest signal frequency
58. The quantization process
a) converts the sample-and-hold output to binary code
b) converts a sample impulse to a level
c) converts a sequence of binary codes to a reconstructed analog signal
d) filters out unwanted frequencies before sampling takes place
59. The most common ADC seen in telecommunications based on audio signals is
a) flash ADC
b) successive approximation ADC
c) sigma-delta ADC
d) dual-slope ADC
60. A certain eight-bit successive-approximation converter has 𝟐. 𝟓𝟓 𝑽 full scale.
The conversion time for 𝑽𝑨 = 𝟏 𝑽 is 𝟖𝟎 𝝁𝒔. What will be the conversion time
for 𝑽𝑨 = 𝟏. 𝟓 𝑽?
a) 60 𝜇𝑠.
b) 80 𝜇𝑠.
c) 120 𝜇𝑠.
d) 160 𝜇𝑠

61. Which is not an A/D conversion error?

a) Missing code.
b) Incorrect code.
c) Differential nonlinearity.
d) Offset
62. Which A/D conversion method has a fixed conversion time?
a) Successive-approximation ADC.
b) Sigma-delta ADC.
c) Dual-slope ADC.
d) All the above
63. In a flash analog-to-digital converter, the output of each comparator is
connected to an input of a:
a) decoder
b) priority encoder
c) multiplexer
d) demultiplexer
64. The primary disadvantage of the flash analog-to digital converter (ADC) is
that:
a) it requires the input voltage to be applied to the inputs simultaneously
b) a long conversion time is required
c) a large number of output lines is required to simultaneously decode the input
voltage
d) a large number of comparators is required to represent a reasonable sized binary
number
65. The throughput of a flash ADC is measured in
a) displacement per second
b) distance per second
c) samples per minute
d) samples per second
66. Which of the following best defines Nyquist frequency?
a) The frequency of resonance for the filtering circuit.
b) The second harmonic.
c) The lower frequency limit of sampling.
d) The highest frequency component of a given analog signal
67. Which is not an A/D conversion errors?
a) Incorrect code
b) Differential nonlinearity
c) Missing code
d) Offset

68. The most common ADC seen in telecommunications based on audio signals is
a) flash ADC
b) successive approximation ADC
c) sigma-delta ADC
d) dual-slope ADC
69. In a flash ADC, the output of each comparator is connected to an input of a:
a) Decoder.
b) Buffer.
c) Multiplexer.
d) Priority encoder
70. Sample-and-hold circuits in analog-to digital converters (ADCs) are designed
to:
a) sample and hold the output of the binary counter during the conversion process
b) stabilize the comparator's threshold voltage during the conversion process
c) stabilize the input analog signal during the conversion process
d) sample and hold the D/A converter staircase waveform during the conversion
process
71. A certain eight-bit successive-approximation converter has 𝟐. 𝟓𝟓 𝑽 full scale.
The conversion time for 𝑽𝑨 = 𝟏 𝑽 is 𝟖𝟎 𝝁𝒔. What will be the conversion time
for 𝑽𝑨 = 𝟏. 𝟓 𝑽?
a) 60 𝜇𝑠.
b) 80 𝜇𝑠.
c) 120 𝜇𝑠.
d) 160 𝜇𝑠.

72. Which A/D conversion method has a fixed conversion time?

a) Successive-approximation ADC.
b) Sigma-delta ADC.
c) Dual-slope ADC.
d) All the above
73. A DAC is a
a) digital-to-analog computer
b) digital analysis calculator
c) data accumulation converter
d) digital-to-analog converter
74. Assume that in a certain 4-bit binary-weighted DAC, the input representing
the most significant bit is applied to a 20 kΩ resistor. What is the size of the
resistor that represents the least significant bit?
a) 20 kΩ.
b) 80 kΩ.
c) 160 kΩ.
d) 320 kΩ.
75. Filtering is important to DAC operation:
a) Because it returns the DAC output to a smooth continuous signal.

b) Because it selects one frequency to pass on from the output.

c) Because it acts as a very high-frequency high-pass filter.
d) Because it adds noise to the output signal.
76. The equivalent weight of the LSB in a 4-bit variable binary-weighted DAC is:
a) 1/4
b) 1/16
c) 1/15
d) 1/32
77. For a 5-bit binary-weighted DAC the weight assigned to MSB is:
a) 1/31
b) 1/32
c) 8/31
d) 16/32
78. A binary-weighted digital-to-analog converter has an input resistor of 100 kΩ.
If the resistor is connected to a 5 V source, the current through the resistor is:
a) 50 𝜇𝐴
b) 5 𝑚𝐴
c) 500 𝜇𝐴
d) 50 𝑚𝐴
79. The practical use of binary-weighted DACs is limited to:
a) R/2R ladder D/A converters
b) 4-bit D/A converters
c) 8-bit D/A converters
d) op-amp comparators
80. The resolution of a 0–5 V 6-bit digital-to-analog converter (DAC) is:
a) 63%
b) 64%
c) 1.56%
d) 15.6%
81. In a binary weighted DAC, the lowest-value resistor corresponds to
a) the highest binary weighted input
b) the lowest binary weighted input
c) the first input
d) the last input
82. A monotonicity error in a DAC will show up as an incorrect analog output
a) Only for lower value inputs
b) Only for higher value inputs
c) Only for certain inputs
d) For all inputs
83. What should the accuracy be for an 12-bit DAC?
a) No worse than ±0.01% .
b) No worse than ±0.02% .
c) No worse than ±0.03% .
d) No worse than ±0.04%
84. In a R/2R ladder DAC, the input resistance for each input is
a) R
b) 2R
c) 3R
d) 4R
85. A 4-bit R/2R digital-to-analog (DAC) converter has a reference of 5 volts.
What is the analog output for the input code 0101.
a) 0.3125 V
b) 3.125 V
c) 0.78125 V
d) –3.125 V
86. What is the resolution of a digital-to-analog converter (DAC)?
a) It is the comparison between the actual output of the converter and its expected
output.
b) It is the deviation between the ideal straight-line output and the actual output of the
converter.
c) It is the smallest analog output change that can occur as a result of an increment in
the digital input.
d) It is its ability to resolve between forward and reverse steps when sequenced over
its entire range.
87. What is the major advantage of the R/2R ladder digital-to-analog (DAC), as
compared to a binary-weighted digital-to-analog DAC converter?
a) It only uses two different resistor values.
b) It has fewer parts for the same number of inputs.
c) Its operation is much easier to analyze.
d) The virtual ground is eliminated and the circuit is therefore easier to understand and
troubleshoot.
88. Which of the following is a type of error associated with digital-to-analog
converters (DACs)?
a) nonmonotonic error
b) incorrect output codes
c) offset error
d) nonmonotonic and offset error
89. A 4-bit binary weighted DAC uses 80 kΩ resistor for MSB. The resistor value
for LSB is
a) 160 kΩ
b) 40 kΩ
c) 20 kΩ
d) 10 kΩ
90. Filtering is important to DAC operation:
a) Because it selects one frequency to pass on from the output.
b) Because it acts as a very high-frequency high-pass filter.
c) Because it returns the DAC output to a smooth continuous signal.
d) Because it adds noise to the output signal
91. In a binary weighted DAC, the lowest-value resistor corresponds to
a) the highest binary weighted input
b) the lowest binary weighted input
c) the first input
d) the last input
 ‫اختيارات مصدر‬
92. The resolution of a 0–5 V 6-bit digital-to-analog converter (DAC) is:
a) 63%
b) 64%
c) 1.56%
d) 15.6%
93. A monotonicity error in a DAC will show up as an incorrect analog output
a) Only for certain inputs

‫مهمة للفصل رابع‬

b) Only for higher value inputs
c) Only for lower value inputs
d) For all inputs
94. The practical use of binary-weighted digital-to-analog converters is limited to:
a) R/2R ladder D/A converters
b) 4-bit D/A converters
c) 8-bit D/A converters
d) op-amp comparators

‫ومكررة باسئلة‬
95. A binary-weighted digital-to-analog converter has an input resistor of 100 k.
If the resistor is connected to a 5 V source, the current through the resistor is:
a) 50 𝜇𝐴
b) 5 𝑚𝐴
c) 500 𝜇𝐴
d) 50 𝑚𝐴
96. Assume that in a certain 4-bit binary-weighted DAC, the input representing

‫السنوات‬
the most significant bit is applied to a 𝟐𝟎 𝒌𝞨 resistor. What is the size of the
resistor that represents the least significant bit?
a) 20 𝑘𝛺.
b) 80 𝑘𝛺.
c) 160 𝑘𝛺.
d) 320 𝑘𝛺.

Chapter 4: Digital Storage Devices

97. The bit capacity of a memory that has 512 addresses and can store 8 bits at
each address is
a) 512
b) 1024
c) 2048
d) 4096
98. Data are stored in a random-access memory (RAM) during the
a) read operation
b) enable operation
c) write operation
d) addressing operation
99. A ROM is a
a) nonvolatile memory
b) volatile memory
c) read/write memory
d) byte-organized memory
100. What is the capacity of a memory that has 16 address inputs, four data
inputs, and four data outputs?
a) 16K×4.
b) 16K×8.
c) 64K×4.
d) 64K×8.
101. 4K × 1 RAM requires …………. address bits to access all locations.
a) 4096
b) 8
c) 10
d) 12
102. Flow-through and pipelined output are two types of:
a) SDRAM.
b) Asynchronous SRAM.
c) Synchronous SRAM.
d) FDM DRAM.
103. Which type of memories has no in-system writability feature?
a) SRAM.
b) DRAM.
c) EEPROM.
d) UV EPROM.
104. RAM is also known as
a) RWM
b) PROM
c) EPROM
d) EAROM
105. A 16-bit word consists of
a) 3 bytes
b) 4 nibbles
c) 4 bytes
d) 3 bytes and 1 nibble
106. Data that are stored at a given address in a random-access memory
(RAM) are lost when
a) power goes off
b) the data are read from the address
c) new data are written at the address
d) answers (a) and (c)
107. The storage element of a DRAM is a
a) Resistor
b) transistor
c) capacitor
d) diode
108. A certain memory has a capacity of 𝟏𝟔𝑲 × 𝟑𝟐. How many words does
it store?
a) 1024.
b) 512.
c) 16384.
d) 524288

109. A …………….. is user-programmable memory that cannot be erased

and reprogrammed.
a) ROM
b) EPROM
c) EEPROM
d) PROM
110. Which of the following RAM timing parameters determine its
operation speed?
a) Write Pulse Width
b) 𝑡𝑅𝐶 and 𝑡𝑊𝐶
c) 𝑡𝐺𝑄
d) 𝑡𝑠(𝐴)
111. The type of memory that uses address multiplexing feature to reduce
the number of address lines is:
a) PROM.
b) DRAM.
c) SRAM.
d) Flash memory
112. Relatively small, high-speed memory that stores the most recently used
instructions or data from the larger but slower main memory is:
a) SRAM.
b) DRAM.
c) Flash memory.
d) SDRAM
113. A memory with 512 addresses has
a) 512 address lines
b) 12 address lines
c) 1 address line
d) 9 address lines
114. A byte-organized memory has
a) 1 data output line
b) 4 data output lines
c) 8 data output lines
d) 16 data output lines

115. ADDRESS-BURST is a feature of

a) synchronous SRAM
b) asynchronous SRAM
c) fast page mode DRAM
d) synchronous DRAM
116. In a computer, the BIOS programs are stored in the
a) ROM.
b) RAM.
c) SRAM.
d) DRAM.

117. SRAM, DRAM, flash, and EEPROM are all

a) magneto-optical storage devices
b) semiconductor storage devices
c) magnetic storage devices
d) optical storage devices
118. ROM access time is defined as:
a) How long it takes to program the ROM chip.
b) Being the difference between the READ and WRITE times.
c) The time it takes to get valid output data after a valid address is applied.
d) The time required to activate the address lines after the ENABLE line is at a valid
level
119. Typically, computer uses a …………… as a main memory.
a) ROM.
b) SRAM.
c) DRAM.
d) BIOS.
120. The feature that the ̅̅̅̅̅̅
𝑪𝑨𝑺 signal does not disable the output data when
it goes to its nonasserted state were found in:
a) DRAM.
b) SDRAM.
c) FDM DRAM.
d) EDO DRAM
 Chapter 5: Programmable Logic Devices

121. Two types of SPLDs are

a) CPLD and PAL
b) PAL and FPGA
c) PAL and GAL
d) GAL and SRAM
122. The factor that determines the adequacy of a GAL for a logic design is
a) the number of inputs and outputs
b) the number of equivalent gates or density
c) the number of inverters involved
d) both (a) and (b)
123. The term LAB stands for
a) logic AND block
b) logic array block
c) last asserted bit
d) logic assembly block
124. The basic elements of an FPGA are
a) configurable logic blocks
b) I/O blocks
c) PAL arrays
d) (d) both (a) and (b)
125. The factor that can be useful to help determine whether a certain PAL
or GAL is adequate for a given logic design is:
a) Fusing and anti-fusing technology.
b) Number of inputs and outputs.
c) Reprograming ability.
d) All of above.
126. Fine-grained FPGA is:
a) Soft core FPGA.
b) Platform FPGA.
c) CLBs are relatively large.
d) CLBs are relatively small.
127. A PLA consists of
a) AND matrix
b) OR matrix
c) Invert/non-invert matrix
d) All of the above
128. PALs tend to execute ________ logic.
a) SAP
b) SOP
c) PLA
d) SPD
129. A PAL is a logic device which is
a) a one-time programmable
b) an erasable programmable
c) electronically erasable and programmable
d) both (a) and (b)
130. The LUT, used in the LUT-CPLD architecture, is basically a memory
that can be programmed
using
a) POS functions
b) SOP functions
c) product of complements
d) all of the above
131. The flip-flop used in a CPLD macrocell can be programmed as a
a) D flip-flop
b) J-K flip-flop
c) both (a) and (b)
d) neither (a) nor (b)
132. When the configurable logic blocks in an FPGA are relatively simple,
the FPGA architecture is
a) fine grained
b) coarse grained
c) hard core
d) soft core
133. One of the following is not a FPGA component:
a) CLB.
b) PIA.
c) IOB.
d) LAB

134. The difference between a PLA and a PAL is:

a) The PLA has a programmable OR plane and a programmable AND plane, while
the PAL only has a programmable AND plane.
b) The PAL has a programmable OR plane and a programmable AND plane, while
the PLA only has a programmable AND plane.
c) The PAL has more possible product terms than the PLA.
d) PALs and PLAs are the same thing
135. A PLA consists of
a) AND matrix
b) OR matrix
c) Invert/non-invert matrix
d) All of the above
136. PALs tend to execute ________ logic.
a) SAP
b) SOP
c) PLA
d) SPD
137. A macrocell is part of a
a) PAL
b) GAL
c) CPLD
d) All of the above
138. Two modes of macrocell operation are
a) input and output
b) registered and sequential
c) combinational and registered
d) parallel and shared
139. A typical macrocell consists of
a) gates, multiplexers, and a flip-flop
b) gates and a shift register
c) a Gray code counter
d) a fixed logic array
140. Nonvolatile FPGAs are generally based on
a) fuse technology
b) anti-fuse technology
c) EEPROM technology
d) SRAM technology
141. Which type of PLD should be used to program basic logic functions?
a) PLA.
b) PAL.
c) CPLD.
d) SPLD

142. The capacity or size of a PLA is specified by

a) Number of inputs.
b) Number of product terms.
c) Number of outputs.
d) All of the above.
143. PALs tend to execute ________ logic.
a) SAP
b) SOP
c) PLA
d) SPD
144. A GAL is essentially a ________.
a) non-reprogrammable PAL
b) PAL that is programmed only by the manufacturer
c) very large PAL
d) reprogrammable PAL
 ANSWERS

1. A
B 33.C 65.D
2. B 34.C 66.D
3. C 35.D 67.B
4. D 36.B 68.C
5. C 37.C 69.D
6. B 38.B 70.C
7. A 39.A 71.B
8. B 40.D 72.A
9. D 41.C 73.D
10.B 42.D 74.C
11.C 43.A 75.A
12.D 44.A 76.C
13.A 45.C 77.D
14.C 46.D 78.A
15.D 47.A 79.B
16.A 48.C 80.C
17.B 49.B 81.A
18.B 50.A 82.C
19.B 51.D 83.A
20.D 52.B 84.B
21.D 53.B 85.B
22.C 54.D 86.C
23.C 55.C 87.A
24.A 56.C 88.D
25.B 57.B 89.D
26.C 58.A 90.C
27.A 59.C 91.A
28.C 60.B 92.C
29.A 61.C 93.A
30.B 62.A 94.B
31.D 63.B 95.A
32.C 64.D 96.C
97.D 113. D 129. A
98.C 114. C 130. B
99.A 115. A 131. C
100. C 116. A 132. A
101. D 117. B 133. D
102. C 118. C 134. A
103. D 119. C 135. D
104. A 120. D 136. B
105. B 121. C 137. D
106. D 122. D 138. C
107. C 123. B 139. B
108. C 124. D 140. B
109. D 125. B 141. B
110. B 126. D 142. D
111. B 127. D 143. B
112. A 128. B 144. D