International Journal of Innovations & Advancement in Computer Science

IJIACS
ISSN 2347 – 8616
Volume 4, Issue2
February 2015

Minimization Of Lock Time And Analysis Of Ripple Voltage

Of Digital Phase Locked Loop(DPLL)

Prashant Ranjan Yadav Ranjit Pathak Rajiv Bisen

M.Tech Student ,United Institute Asst.Prof.,United Intitute Of M.Tech Student ,United Institute
Of Technology Technology Of Technology
Allahabad, Uttar Pradesh Allahabad, Uttar Pradesh Allahabad, Uttar Pradesh
India India India

ABSTRACT transmission[1].there are different techniques

In this paper, we describe how a DPLL can be used for short lock time[2].
lock in minimum time for a particular loop
Following are some important applications of
filter resistance and we show here the tread-off
between lock time and ripple voltage by DPLL :
varying the secondary capacitance of the loop
1. FSK Demodulation
filter. In this paper we have taken a Digital
Phase Lock Loop (DPLL) having fixed 2. FM Demodulation
characteristic of input digital signal with 3. Frequency Synthesizer
frequency 500 MHz and voltage 1 volt.The 4. Frequency Multiplication And
model is made on MATLAB simulink. Division
Keywords 5. Signal Reconstruction
Phase Detector,Charge Pump, Loop
Filter,VCO, Lock Time Ripple voltage One more problem occur after lock is achieved
, there are ripples present with each rising
1. INTRODUCTION
edge of input data at the output of loop filter (
A Phase lock loop (PLL) is a self correcting at the input of VCO), it makes fluctuation in
circuit in sense of phase and frequency , if the output frequency of VCO which is
there is change in input frequency or phase
undesired. To study lock time variation by
then the output will follow that change of
frequency and phase up to a certain limit varying the resistor of loop filter and study of
called LOCK-IN RANGE.To lock that trade-off between lock time and ripple voltage
particular frequency it takes some time and at the input of VCO which causes time jitter is
some number of laps of feedback path.In presented in this paper.
present scenario of fast data
transmission,clock recovery should be To study this parameters variation we
fast,means very short duration of time required have chosen simulink model of DPLL[3]
to track the change in clock frequency. For
this purpose the lock time should be as small 2. PROPOSED SIMULINK DPLL
as can be possible for fast data MODEL FOR STUDY OF LOCK TIME
AND RIPPLE VOLTAGE

7 Prashant Ranjan Yadav, Ranjit Pathak, Rajiv Bisen

 International Journal of Innovations & Advancement in Computer Science
Figure1:Simulink Model Of DPLL
3.THIS PAPER PRESENTS THE SIMULINK
MODEL HAVING FOLLOWING BLOCK
3.1 PFD (Phase Frequency Detector) :
This phase frequency detector is made with
the help of positive edge triggered D flip flop
[7] . It is a tri-state PFD having states up down
and clear with NANDgate[4].This PFD
preferred over EXOR and JK flip-flop based
phase detector[9],because it eliminates the
problem of dependency of phase error on the
duty cycle and a static phase difference
between the input (reference) signal and
feedback signal when locked using E-XOR
phase detector, and static phase deference
when lock using JK flip-flop based phase
detector[8].
Figure2- PFD(Phase Frequency Detector)
8 Prashant Ranjan Yadav, Ranjit Pathak, Rajiv Bisen
IJIACS
ISSN 2347 – 8616
Volume 4, Issue2
February 2015
The up and down terminals of PFD are always
high when the reference and feedback signals
are in same phase and frequency, this will ON
both of the switches of charge pump due to
which there will be no current sink/source in
the loop filter, and when the frequency of
reference signal is greater than feedback signal
then the up will high for more time than down
terminal and over all average voltage will be
high,which force the VCO to run at higher
frequency than it is running. Similarly VCO
will run at lower frequency when the
frequency of reference goes lower than the
frequency of feedback.Thus VCO will track
frequency which is equal to the input are
reference frequency with in lock in range.
From here we can understand how PLL Track
the frequency in lock-in-range.
3.2 Charge Pump
It is used to provide charge to the loop filter
according to switch position[5]. In this model
we have two resistances of values 112 kilo-
ohm used as switching resistances.There must
be current matching in charge pump[3].
Figure3- Charge Pump
3.3.Loop Filter
 International Journal of Innovations & Advancement in Computer Science
IJIACS
ISSN 2347 – 8616
Volume 4, Issue2
February 2015

The loop filter is low pass filter which is

used to integrate the current output of
charge pump and provide voltage to the
VCO.

Figure5- Control voltage ripple at C2=0.50pf

Figure4-Loop Filter

Loop filter is the most important part of

DPLL. Loop filter is responsible for
bandwidth, stability, lock time variation of
DPLL.In loop filter we have one more
capacitor called secondary capacitor is used to
minimize the voltage ripple at the input of
VCO.
Figure6- Control voltage ripple at C2=7.0pf
We have done our first work by changing the
resistance of loop filter and keeping constant 3.4. VCO
all parameters as follows :
VCO is a oscillator which is controlled by
Input frequency = 500 MHz voltage. As we increase the voltage the output
frequency will increase and decreasing of
Primary capacitance (C1) = 22 pf voltage will decrease the output frequency.
Following are the CO parameters we have
Secondary capacitance (C2)= 4pf
chosen in our paper:
Our second work is to constant the other
 Quotient frequency = 400 MHz
parameters except changing the secondary
capacitor and by this study of ripple voltage  VCO sensitivity = 1000 MHz/volt
and lock time. For this we have chosen  voltage amplitude = 5V
resistance value of loop filter i.e. The sensitivity of VCO is determined by :
Loop filter resistance R = 2.2kilo-Ω Fmax-fmin. / Vmax-Vmin.
MHz/Volt
Following simulated figure explain the effect
of secondary capacitor C2.

9 Prashant Ranjan Yadav, Ranjit Pathak, Rajiv Bisen

 International Journal of Innovations & Advancement in Computer Science
IJIACS
ISSN 2347 – 8616
Volume 4, Issue2
February 2015

4.SIMULATION RESULTS Capacitance Control ripple Lock Time

C2 voltage
(i)Keeping constant all parameters as follows : (in ns)
(in pf) (in
Input frequency = 500 MHz
mV)
Primary capacitance (C1) = 22 pf
0.25 115.75 650
Secondary capacitance (C2)= 4pf
0.50 65.80 656
By changing the loop resistance we get
following changes in lock time : 1.00 38.50 660

Resistance (in kΩ) Lock Time (in ns) 2.00 18.50 665

1.4 680 3.00 11.25 665

1.6 590 4.00 8.50 666

1.8 550 5.0 6.70 676

2.0 450 6.0 5.70 678

2.2 350 7.00 4.90 680

2.4 450

2.6 640 From above table we can see that as we

increase the capacitance value of C2 the lock
2.8 680
time increases but ripple voltage (which
causes timing jitter) decreases. So we have to
We have minimum value of lock time i.e. 350 go for Trade OFF. For Trade OFF we have
ns at R =2.2KΩ. chosen these two values :

(1) at C2 =0.50 pf the control ripple

(ii)Keeping constant all parameters as follows voltage = 65.8 mV and lock time =
: 656 ns
(2) at C2= 5.00 pf control ripple voltage =
Input frequency = 500 MHz 6.7 mV and lock time = 676.01 ns
Primary capacitance (C1) = 22 pf at the end of trade off we can say that when
Loop resistance(R)=2.2KΩ our focus on minimum lock time then we will
Changing secondary capacitance we have select the value of C2=.50 p and when our
following results focus on minimization on time jitter then we
will select value of C2= 5.00 pf
10 Prashant Ranjan Yadav, Ranjit Pathak, Rajiv Bisen
 International Journal of Innovations & Advancement in Computer Science
5.CONCLUSION
From above work we can conclude,for a
particular input frequency there will be a
particular resistance of loop filter for which
we will get minimum lock time and for
particular frequency there will be trade off
between time jitter and control ripple voltage
with the variation of secondary capacitor C2
of loop filter.
REFRENCES
[1]Wagdy Mahmoud Fawzy ,Vaishnava
Srishti,2006"A Fast Locking Digital Phase
Lock Loop".Proceedings of the Third
International Conference on Information
Technology: New Generations (ITNG'06) IEE
[2]Dr. Wagdy Mahmoud Fawzy,2011 "A
Novel Flash Fast-Locking Digital PLL:
VHDL-AMS and Matlab/Simulink Modeling
and Simulation”2011 Eighth International
Conference on Information Technology: New
Generations IEEE
[3]Patra Jyoti P. and Pati Umesh C.
2012,"Behavioural Modelling and Simulation
of PLL Based Integer N Frequency
Synthesizer using Simulink"International
Journal of Electronics and Communication
Engineering.ISSN 0974-2166 Volume 5,
Number 3 (2012), pp. 351-362
[4]Nandini Raj , SinghHimadri Raghav,
Singh B.P."Comparison of Phase Frequency
Detectors by Different Logic
Gates"International Journal of Innovative
Technology and Exploring Engineering
(IJITEE) ISSN: 2278-3075, Volume-2, Issue-
5, April 2013
11 Prashant Ranjan Yadav, Ranjit Pathak, Rajiv Bisen
IJIACS
ISSN 2347 – 8616
Volume 4, Issue2
February 2015
[5]Patel K.. Kashyap,, Patel Nilesh D."Phase
Frequency Detector And Charge Pump For
DPLL Using 0.18μm CMOS
technology"IOSR Journal of VLSI and Signal
Processing (IOSR-JVSP) Volume 2, Issue 4
(May. – Jun. 2013),
[6]Razavi,B.2003 “ Design of Integrated
Circuits for Optical Communications”,
McGraw-Hill,
[7]Prof.Talwekar R .H. , Prof. (Dr.)
Limaye,S.S 2012."A High-Speed, Low Power
Consumption Positive Edge Triggered D Flip-
Flop for High Speed Phase Frequency
Detector in 180 nm CMOS
Technology",International Journal of VLSI
design & Communication Systems (VLSICS)
Vol.3, No.5, October 2012
[8]Curtin,Mike and O’Brien Paul "Phase
Locked Loops for High-Frequency Receivers
and Transmitters-3" provides information why
D Flip-Flop is used for PFD,Analog Dialogue
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[9]Perrott M. , High Speed Communication
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Course ware